VSC8541 Gigabit Ethernet PHY

Microsemi ENT's VSC8541 provides low-power, small form-factor Cu PHY with IEEE 802.3az energy efficient Ethernet (EEE), wake-on-LAN (WoL), synchronous Ethernet (SyncE), start of frame (SOF), and fast link failure 2.0 (FLF2) indication, with widest I/O LVCMOS support. The VSC8541 device, offered in a small 8 mm x 8 mm single-row QFN package, is designed for space-constrained 10/100/1000BASE-T applications. It features integrated line-side termination to conserve board space, lower EMI, and improve system performance. Additionally, integrated RGMII version 2.0 standard timing compliant compensation eliminates the need for on-board delay lines. The device supports the industry’s widest range of LVCMOS levels for a parallel MAC interface including: 1.5 V, 1.8 V, 2.5 V, and 3.3 V, as well as 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V support on the MDIO/MDC interface. It includes Microsemi’s EcoEthernet 2.0 technology with energy efficient Ethernet and power saving features to reduce power based on link state and cable reach. It optimizes power consumption at all link operating speeds, and features wake-on-LAN power management using magic packets. The device has a recovered clock output for synchronous Ethernet applications. Programmable clock squelch control is included to inhibit undesirable clocks from propagating and to help prevent timing loops. Microsemi's patented Ring Resiliency™ allows a PHY port to switch between master and slave timing references with no link drop while in 1000BASE-T mode. VSC8541 also includes Fast Link Failure (FLF) indication for high availability networks. FLF indication identifies the onset of a link failure in less than 1 ms typical, which goes beyond the IEEE 802.3 standard requirement of 750 ms ±10 ms (link master). In addition, the device adds a programmable threshold for applications where indication of even a potential link drop must be known at the microsecond level (<10 μs).