Programmable SoCs Help Manufacturers Find the Right Balance Between Configurability and Performance
Contributed By Digi-Key's European Editors
Although semiconductor technology is the basis for all electronic products, it is software that really enables our modern world. Compared to hardware, software offers an almost limitless level of flexibility, and when running on a high-performance microprocessor it can deliver staggering results. The advancement of artificial intelligence, for example, would be impossible without the combination of software running on the latest processors.
Over the last several decades there has been a shift in the balance between hardware and software. It is generally accepted that around 70% of a product’s functionality is now defined at the embedded software level, due almost entirely to its flexibility.
As applications push the boundaries of performance, however, this imbalance becomes a limiting factor. Software is ultimately the implementation of a function in an abstracted form, which comes with unavoidable overheads in terms of execution time. The same function implemented in dedicated hardware, at the transistor level, will invariably execute faster. That performance gain normally comes at the cost of flexibility, but getting the balance right between performance and flexibility is made easier thanks to devices that integrate three key technologies: processing cores; fixed functions; and reconfigurable hardware.
High performance optimized solutions
Devices that integrate all three technologies are commonly referred to as a system-on-chip, or SoC. By their nature they offer greater flexibility than a fixed function device, increased configurability over a microcontroller, and more functional diversity than an FPGA, by bringing the best of all these features together in a single platform.
There are several reasons why this is a good mix for an application. Performance is the predominant one, which could be interpreted as either throughput or real-time response. Low power and optimized design may be another. The more functions that can be integrated on a single device, the fewer external components needed. These scenarios cover the two ‘corner points’ of SoCs, those that deliver pure performance and those that provide an optimized design.
If throughput is the ultimate goal, then it is hard to beat the performance offered by full custom design in the form of an ASIC. However, while NRE costs are coming down, the cost of developing an ASIC still needs to be weighed against the price per unit, and often, that figure only works commercially in high volumes. For a long time, FPGA technology has provided the industry with ASIC-like performance in a platform that can be configured after the device has left the foundry. The underlying technology uses look-up tables to mimic full-custom logic, but there has always been some integration of hardwired functionality, especially if it involves a function that can’t easily be emulated in logic. More recently this has evolved to include processor subsystems, which puts these devices firmly in the SoC category. The industry leaders in FPGAs offer devices that combine the three key elements of a SoC. This includes the Zynq® UltraScale+ family from Xilinx, which features devices with dual or quad ARM® Cortex®-A53 cores coupled with ARM Cortex-R5 cores.
While these devices target applications demanding high performance, SoCs that fall into the second category include the SmartFusion2 SoC FPGA family from Microsemi and the PSoC 5LP family from Cypress Semiconductor. Both devices integrate an ARM Cortex-M3 core with hardwired functions and configurable hardware. All the devices mentioned are supported by platforms that provide comprehensive support for application development, at both the hardware and software level.
The ZCU102 evaluation board from Xilinx features the Zynq UltraScale+ XCZU9EG multiprocessor SoC, which offers an incredibly high level of integration. Its multicore processing capabilities comprise the Cortex-A53 64-bit quad-core processor and the Cortex-R5 dual-core real-time processor, closely coupled to FPGA logic, connectivity interfaces and a graphical processing unit (Figure 1).
Figure 1: A block diagram of the highly-integrated Xilinx Zynq UltraScale+ EG.
The evaluation board (Figure 2) features 4 Gbit of DDR4 SODIMM connected to the processing subsystem and a further 512 Mbit of DDR4 memory connected to the programmable logic. It also includes two FPGA mezzanine card (FMC) interfaces for further expansion, as well as advanced interfaces (PCIe Gen2x4, USB3, display port, SATA) to provide the perfect evaluation platform for a range of applications in the automotive, industrial, video and communications sectors.
Figure 2: The main features of the ZCU102 evaluation board.
The EG family scales from around 100,000 system logic cells to well over one million, with configurable logic block (CLB) look-up tables (LUTs) ranging from around 50,000 to over 500,000. This level of configurability, coupled with hardened multimedia blocks and integrated high-speed peripherals, allows the Zynq UltraScale+ family to target a wide range of demanding applications. The ZCU102 evaluation board is the perfect platform for developers, delivering up to five times the performance per watt over the Zynq-7000 family.
Demand for performance constantly increases, most apparently within the communications sector. The majority of internet activity involves information stored in a database, the most common being SQL. One technique for accelerating SQL databases is to use a cache memory, normally implemented using a standard processor with integrated DRAM.
Although this works, it too is bound by the limitations of the processor’s architecture, which wasn’t designed for this kind of application. Using a device like the Zynq UltraScale+ provides an optimized solution for streaming data, without stressing the processor by using all of its advanced features to act like a standalone server on the network. This can result in four times better performance at 20x less power when measured using a standard x86 processor.
In the automotive industry, ADAS will see further increases in the use of cameras in cars. This will create demand for SoCs able to handle as many as six 2 megapixel camera feeds at 30 fps. Thanks to its high level of integration, the Zynq UltraScale+ is perfectly suited to this challenging application.
The ZCU102 comes with all of the tools and IP needed to start developing this and many more applications. It also includes a Vivado Design Suite: Design Edition voucher code that is node-locked and device-locked to the XCZU9EG on the board.
SoCs in the IoT
The IoT is often portrayed as a network of devices with limited resources and functionality, but it will also involve the connection and automation of many existing applications. With their high level of integration, SoCs that offer the right level of functionality and low power can provide the ideal platform for a connected device.
As an example, the SmartFusion2 from Microsemi is aimed at motor control and industrial automation applications, but can easily form the basis for a secure connected device. It integrates a Flash-based FPGA fabric with an ARM Cortex-M3 core and high performance communication interfaces including CAN, Gigabit Ethernet, HS-USB and PCIe, along with DDR2/DDR3 memory controllers. To support application development using the SmartFusion2, Microsemi has developed the SmartFusion2 advanced development kit. The major features of the board are shown in Figures 3 and 4.
Figure 3: A block diagram of the SmartFusion2 advanced evaluation kit.
Figure 4: Microsemi’s SmartFusion2 advanced development kit.
Using this kit, Microsemi has created a demonstration application that provides all the software and support needed to create a secure web server that supports TLS/SSL security protocol for sending and receiving encrypted data; exactly the kind of application now being deployed in the IoT.
As shown in Figure 5, the application layer receives requests from a client browser and responds with static web pages, while the server application runs on the SmartFusion2. The TLS/SSL protocol is implemented using an open source library, PolarSSL. The transport layer (TCP/IP) is enabled by more open source software which can be used with or without an operating system. In this example, the FreeRTOS open source real-time operating system is used to prioritize and schedule tasks. The advanced development kit can also be configured to run uClinux, an operating system based on the Linux kernel that has been modified by Microsemi for the SmartFusion2 SoC.
Figure 5: Overview of a secure web server application as implemented on the SmartFusion2.
Having 150,000 logic elements, a 166 MHz Cortex-M3 core and dedicated DSP blocks, coupled with embedded NVM (Non-Volatile Memory) and SRAM, the SmartFusion2 provides a powerful balance between configurability and hardwired functionality. The advanced development kit harnesses this potential with the support of PCIe edge connectors, FMC connectors, two Gigabit Ethernet ports, SPI and UART. The addition of a high performance operational amplifier allows the device’s power consumption to be measured during development, helping developers to design the optimal solution within a given power budget.
Single-chip solutions can be applied to a wide range of applications, where the right mix of digital, analog, and memory can be integrated to provide an optimized and customized device. It invariably results in a smaller PCB area, fewer external components and a lower BOM cost.
Programmable analog devices are far less common than their digital counterparts, and are arguably dominated by the PSoC family from Cypress Semiconductor. PSoC devices, or programmable SoCs, feature a microcontroller core, hardwired blocks and programmable logic, but are differentiated by their configurable analog peripherals, enabled using switch capacitor technology as well as op amps, comparators, ADCs and DACs, and digital filter blocks. Together, these features enable the configuration of complex analog signal paths to be created that are closely coupled to the digital functions on the chip.
The CY8CKIT-050 development kit can be used in conjunction with the PSoC Creator integrated development environment (IDE) to develop a range of applications based on the PSoC 5LP. The major elements of the development kit are shown in Figure 6.
Figure 6: The PSoC 5LP development kit.
PSoC Creator is an IDE with a difference; it can be used for the concurrent development of embedded software (in this case, running on the PSoC 5’s ARM Cortex-M3 core) and hardware features implemented in the device’s configurable analog blocks. Using a drag and drop approach, analog functions can be added to the design, with APIs dynamically generated, allowing the functions to be accessed through software. The IDE comes with a large number of amplifiers and filters pre-defined, but also allows developers to create their own functions.
To demonstrate the PSoC 5’s capabilities Cypress has created a number of application examples, including the implementation of a solar micro-inverter controller. Figure 7 shows an architectural overview of the application. The micro-inverter involves several conversion stages, including ripple cancel boost control, output current control, phased-locked loop control and the maximum power point tracking algorithm. It is an application that aptly demonstrates the capabilities of the platform.
Figure 7: The Solar micro-inverter controller implemented using the PSoC 5LP.
While software provides an abstract way of implementing almost any task or function, dedicated hardware can rarely be beaten in terms of performance. As demand increases for both higher throughput and greater configurability, platforms that combine the hardware, software, digital and analog domains are becoming increasingly viable as single-chip solutions.
These SoCs meet a need, but as with any implementation there are compromises involved. Not all SoCs offer the right hardwired functions. Inevitably, no single application is likely to utilize all of the available features, and in some cases the financial cost of a more flexible platform may be too high to bear.
However, as the technology evolves, these compromises become less apparent and the flexibility they offer will likely provide justification for their use in a wider range of applications.
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