ECP2(M) Family Datasheet by Lattice Semiconductor Corporation

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:.'-' LATTICE SEMICONDUCTOR.
LatticeECP2/M Family Data Sheet
DS1006 Version 04.1, September 2013
:'_.'_.' LATTICE CCCCCCCCCCCCC
www.latticesemi.com 1-1 DS1006 Introduction_02.0
July 2012 Data Sheet DS1006
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Features
High Logic Density for System Integration
6K to 95K LUTs
90 to 583 I/Os
Embedded SERDES (LatticeECP2M Only)
Data Rates 250 Mbps to 3.125 Gbps
Up to 16 channels per device
PCI Express, Ethernet (1GbE, SGMII), OBSAI,
CPRI and Serial RapidIO.
sysDSP™ Block
3 to 42 blocks for high performance multiply and
accumulate
Each block supports
One 36x36, four 18x18 or eight 9x9 multipliers
Flexible Memory Resources
55Kbits to 5308Kbits sysMEM™ Embedded
Block RAM (EBR)
18Kbit block
Single, pseudo dual and true dual port
Byte Enable Mode support
12K to 202Kbits distributed RAM
Single port and pseudo dual port
sysCLOCK Analog PLLs and DLLs
Two GPLLs and up to six SPLLs per device
Clock multiply, divide, phase & delay adjust
Dynamic PLL adjustment
Two general purpose DLLs per device
Pre-Engineered Source Synchronous I/O
DDR registers in I/O cells
Dedicated gearing logic
Source synchronous standards support
SPI4.2, SFI4 (DDR Mode), XGMII
High Speed ADC/DAC devices
Dedicated DDR and DDR2 memory support
DDR1: 400 (200MHz) / DDR2: 533 (266MHz)
Dedicated DQS support
Programmable sysI/O™ Buffer Supports
Wide Range Of Interfaces
LVTTL and LVCMOS 33/25/18/15/12
SSTL 3/2/18 I, II
HSTL15 I and HSTL18 I, II
PCI and Differential HSTL, SSTL
LVDS, RSDS, Bus-LVDS, MLVDS, LVPECL
Flexible Device Configuration
1149.1 Boundary Scan compliant
Dedicated bank for configuration I/Os
SPI boot flash interface
Dual boot images supported
TransFR™ I/O for simple field updates
Soft Error Detect macro embedded
Optional Bitstream Encryption
(LatticeECP2/M “S” Versions Only)
System Level Support
ispTRACY™ internal logic analyzer capability
On-chip oscillator for initialization & general use
•1.2V power supply
Table 1-1. LatticeECP2 (Including “S-Series”) Family Selection
Device ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70
LUTs (K) 6 12 21 32 48 68
Distributed RAM (Kbits) 1224426496136
EBR SRAM (Kbits) 55 221 276 332 387 1032
EBR SRAM Blocks 3 12 15 18 21 60
sysDSP Blocks 3 6 7 8 18 22
18x18 Multipliers 122428327288
GPLL + SPLL + DLL 2+0+2 2+0+2 2+0+2 2+0+2 2+2+2 2+4+2
Maximum Available I/O 190 297 402 450 500 583
Packages and I/O Combinations
144-pin TQFP (20 x 20 mm) 90 93
208-pin PQFP (28 x 28 mm) 131 131
256-ball fpBGA (17 x 17 mm) 190 193 193
484-ball fpBGA (23 x 23 mm) 297 331 331 339
672-ball fpBGA (27 x 27 mm) 402 450 500 500
900-ball fpBGA (31 x 31 mm) 583
LatticeECP2/M Family Data Sheet
Introduction
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1-2
Introduction
LatticeECP2/M Family Data Sheet
Table 1-2. LatticeECP2M (Including “S-Series”) Family Selection
Introduction
The LatticeECP2/M family of FPGA devices is optimized to deliver high performance features such as advanced
DSP blocks, high speed SERDES (LatticeECP2M family only) and high speed source synchronous interfaces in an
economical FPGA fabric. This combination was achieved through advances in device architecture and the use of
90nm technology.
The LatticeECP2/M FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP2/M
devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked
Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP blocks and advanced configu-
ration support, including encryption (“S” versions only) and dual boot capabilities.
The LatticeECP2M device family features high speed SERDES with PCS. These high jitter tolerance and low trans-
mission jitter SERDES with PCS blocks can be configured to support an array of popular data protocols including
PCI Express, Ethernet (1GbE and SGMII), OBSAI and CPRI. Transmit Pre-emphasis and Receive Equalization
settings make SERDES suitable for chip to chip and small form factor backplane applications.
Lattice Diamond® design software allows large complex designs to be efficiently implemented using the
LatticeECP2/M FPGA family. Synthesis library support for LatticeECP2/M is available for popular logic synthesis
tools. The Diamond software uses the synthesis tool output along with the constraints from its floor planning tools
to place and route the design in the LatticeECP2/M device. The Diamond design tool extracts the timing from the
routing and back-annotates it into the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Property) modules for the LatticeECP2/M family. By using
these IP cores as standardized blocks, designers are free to concentrate on the unique aspects of their design,
increasing their productivity.
Device ECP2M20 ECP2M35 ECP2M50 ECP2M70 ECP2M100
LUTs (K) 1934486795
sysMEM Blocks (18kb) 66 114 225 246 288
Embedded Memory (Kbits) 1217 2101 4147 4534 5308
Distributed Memory (Kbits) 41 71 101 145 202
sysDSP Blocks 6 8 22 24 42
18x18 Multipliers 24 32 88 96 168
GPLL+SPLL+DLL 2+6+2 2+6+2 2+6+2 2+6+2 2+6+2
Maximum Available I/O 304 410 410 436 520
Packages and SERDES / I/O Combinations
256-ball fpBGA (17 x 17 mm) 4 / 140 4 / 140
484-ball fpBGA (23 x 23 mm) 4 / 304 4 / 303 4 / 270
672-ball fpBGA (27 x 27 mm) 4 / 410 8 / 372
900-ball fpBGA (31 x 31 mm) 8 / 410 16 / 416 16 / 416
1152-ball fpBGA (35 x 35 mm) 16 / 436 16 / 520
_.'_.'_.' LATTICE CCCCCCCCCCCCC
www.latticesemi.com 2-1 DS1006 Architecture_02.3
September 2013 Data Sheet DS1006
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Architecture Overview
Each LatticeECP2/M device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-
spersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and rows of sys-
DSP™ Digital Signal Processing blocks, as shown in Figure 2-1. In addition, the LatticeECP2M family contains
SERDES Quads in one or more of the corners. Figure 2-2 shows the block diagram of ECP2M20 with one quad.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional Unit
without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFF
block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for
flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-
dimensional array. Only one type of block is used per row.
The LatticeECP2/M devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large dedicated
18K fast memory blocks. Each sysMEM block can be configured in a variety of depths and widths of RAM or ROM.
In addition, LatticeECP2/M devices contain up to two rows of DSP Blocks. Each DSP block has multipliers and
adder/accumulators, which are the building blocks for complex signal processing capabilities.
The LatticeECP2M devices feature up to 16 embedded 3.125Gbps SERDES (Serializer / Deserializer) channels.
Each SERDES channel contains independent 8b/10b encoding / decoding, polarity adjust and elastic buffer logic.
Each group of four SERDES channels along with its Physical Coding Sub-layer (PCS) block, creates a quad. The
functionality of the SERDES/PCS Quads can be controlled by memory cells set during device configuration or by
registers that are addressable during device operation. The registers in every quad can be programmed by a soft
IP interface, referred to as the SERDES Client Interface (SCI). These quads (up to four) are located at the corners
of the devices.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the
LatticeECP2/M devices are arranged in eight banks, allowing the implementation of a wide variety of I/O standards.
In addition, a separate I/O bank is provided for the programming interfaces. PIO pairs on the left and right edges of
the device can be configured as LVDS transmit/receive pairs. The PIC logic also includes pre-engineered support
to aid in the implementation of high speed source synchronous standards such as SPI4.2, along with memory
interfaces including DDR2.
The LatticeECP2/M registers in PFU and sysI/O can be configured to be SET or RESET. After power up and the
device is configured, it enters into user mode with these registers SET/RESET according to the configuration set-
ting, allowing the device entering to a known state for predictable system function.
Other blocks provided include PLLs, DLLs and configuration functions. The LatticeECP2/M architecture provides
two General PLLs (GPLL) and up to six Standard PLLs (SPLL) per device. In addition, each LatticeECP2/M family
member provides two DLLs per device. The GPLLs and DLLs blocks are located in pairs at the end of the bottom-
most EBR row; the DLL block is located towards the edge of the device. The SPLL blocks are located at the end of
the other EBR/DSP rows.
The configuration block that supports features such as configuration bit-stream decryption, transparent updates
and dual boot support is located toward the center of this EBR row. The Ball Grid Array (BGA) package devices in
the LatticeECP2/M family supports a sysCONFIG™ port located in the corner between banks four and five, which
allows for serial or parallel device configuration.
In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator. The
LatticeECP2/M devices use 1.2V as their core voltage.
LatticeECP2/M Family Data Sheet
Architecture
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2-2
Architecture
LatticeECP2/M Family Data Sheet
Figure 2-1. Simplified Block Diagram, ECP2-6 Device (Top Level)
Figure 2-2. Simplified Block Diagram, ECP2M20 Device (Top Level)
Programmable
Function Units
(PFUs)
Flexible sysIO Buffers:
LVCMOS, HSTL, SSTL,
LVDS, and other standards
sysDSP Blocks
Multiply and
Accumulate Support
sysMEM Block RAM
18kbit Dual Port
sysCLOCK PLLs and DLLs
Frequency Synthesis and
Clock Alignment
Flexible routing optimized
for speed, cost and routability
Configuration logic, including
dual boot and encryption.
On-chip oscillator and
soft-error detection.
Configuration port
Pre-engineered source
synchronous support
• DDR1/2
• SPI4.2
• ADC/DAC devices
Flexible sysIO
Buffers:
LVCMOS, HSTL
SSTL, LVDS
Pre-Engineered
Source Synchronous
Support
• DDR1/2
• SPI4.2
• ADC/DAC devices
SERDES
DSP Blocks
Multiply & Accumulate
Support
On-Chip
Oscillator
Programmable
Function Units
(PFUs)
Channel
3
Channel
2
Channel
1
Channel
0
sysMEM Block
RAM 18kbit Dual Port
Configuration
Logic, Including
dual boot and encryption,
and soft-error detection
Flexible Routing
optimized for speed,
cost & routability
sysCLOCK GPLLs
& GDLLs
Frequency Synthesis
& Clock Alignment
Configuration Port
sysCLOCK SPLLs
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2-3
Architecture
LatticeECP2/M Family Data Sheet
PFU Blocks
The core of the LatticeECP2/M device consists of PFU blocks, which are provided in two forms, the PFU and PFF.
The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF
blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remain-
der of this data sheet will use the term PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-3. All the interconnec-
tions to and from PFU blocks are from routing. There are 50 inputs and 23 outputs associated with each PFU block.
Figure 2-3. PFU Diagram
Slice
Slice 0 through Slice 2 contain two LUT4s feeding two registers, whereas Slice 3 contains two LUT4s only. For
PFUs, Slice 0 and Slice 2 can also be configured as distributed memory, a capability not available in the PFF.
Table 2-1 shows the capability of the slices in both PFF and PFU blocks along with the operation modes they
enable. In addition, each PFU contains some logic that allows the LUTs to be combined to perform functions such
as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchro-
nous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 2-4 shows an overview of the
internal logic of the slice. The registers in the slice can be configured for positive/negative and edge triggered or
level sensitive clocks.
Table 2-1. Resources and Modes Available per Slice
Slices 0, 1 and 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent
slice or PFU). There are seven outputs: six to routing and one to carry-chain (to the adjacent PFU). Slice 3 has 13
input signals from routing and four signals to routing. Table 2-2 lists the signals associated with Slice 0 to Slice 2.
Slice
PFU BLock PFF Block
Resources Modes Resources Modes
Slice 0 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM
Slice 1 2 LUT4s and 2 Registers Logic, Ripple, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM
Slice 2 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM
Slice 3 2 LUT4s Logic, ROM 2 LUT4s Logic, ROM
Slice 0
LUT4 &
CARRY
LUT4 &
CARRY
D D
Slice 1
LUT4 &
CARRY
LUT4 &
CARRY
Slice 2
LUT4 &
CARRY
LUT4 &
CARRY
From
Routing
To
Routing
Slice 3
LUT4 LUT4
D D D D
FF FF FF FF FF FF
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2-4
Architecture
LatticeECP2/M Family Data Sheet
Figure 2-4. Slice Diagram
Table 2-2. Slice Signal Descriptions
Function Type Signal Names Description
Input Data signal A0, B0, C0, D0 Inputs to LUT4
Input Data signal A1, B1, C1, D1 Inputs to LUT4
Input Multi-purpose M0 Multipurpose Input
Input Multi-purpose M1 Multipurpose Input
Input Control signal CE Clock Enable
Input Control signal LSR Local Set/Reset
Input Control signal CLK System Clock
Input Inter-PFU signal FC Fast Carry-in1
Input Inter-slice signal FXA Intermediate signal to generate LUT6 and LUT7
Input Inter-slice signal FXB Intermediate signal to generate LUT6 and LUT7
Output Data signals F0, F1 LUT4 output register bypass signals
Output Data signals Q0, Q1 Register outputs
Output Data signals OFX0 Output of a LUT5 MUX
Output Data signals OFX1 Output of a LUT6, LUT7, LUT82 MUX depending on the slice
Output Inter-PFU signal FCO Slice 2 of each PFU is the fast carry chain output1
1. See Figure 2-4 for connection details.
2. Requires two PFUs.
LUT4 &
CARRY*
LUT4 &
CARRY*
SLICE
A0
C0
D0
FF*
OFX0
F0
Q0
A1
B1
C1
D1
CI
CI
CO
CO
CE
CLK
LSR
FF*
OFX1
F1
Q1
F/SUM
F/SUM D
D
M1
FCI From Different Slice/PFU
FCO To Different Slice/PFU
LUT5
Mux
M0
From
Routing
To
Routing
FXB
FXA
B0
For Slices 0 and 2, memory control signals are generated from Slice 1 as follows:
WCK is CLK
WRE is from LSR
DI[3:2] for Slice 2 and DI[1:0] for Slice 0 data
WAD [A:D] is a 4bit address from slice 1 LUT input
* Not in Slice 3
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2-5
Architecture
LatticeECP2/M Family Data Sheet
Modes of Operation
Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM.
Logic Mode
In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16
possible input combinations. Any four input logic functions can be generated by programming this lookup table.
Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as
LUT6, LUT7 and LUT8 can be constructed by concatenating other slices. Note LUT8 requires more than four
slices.
Ripple Mode
Ripple mode supports the efficient implementation of small arithmetic functions. In ripple mode, the following func-
tions can be implemented by each slice:
Addition 2-bit
Subtraction 2-bit
Add/Subtract 2-bit using dynamic control
Up counter 2-bit
Down counter 2-bit
Up/Down counter with Async clear
Up/Down counter with preload (sync)
Ripple mode multiplier building block
Multiplier support
Comparator functions of A and B inputs
A greater-than-or-equal-to B
A not-equal-to B
A less-than-or-equal-to B
Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this con-
figuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are gener-
ated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices.
RAM Mode
In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed using each LUT block in Slice 0 and
Slice 2 as a 16x1-bit memory. Slice 1 is used to provide memory address and control signals. A 16x2-bit pseudo
dual port RAM (PDPR) memory is created by using one Slice as the read-write port and the other companion slice
as the read-only port.
The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-
ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3
shows the number of slices required to implement different distributed RAM primitives. For more information about
using RAM in LatticeECP2/M devices, please see the list of additional technical documentation at the end of this
data sheet.
Table 2-3. Number of Slices Required to Implement Distributed RAM
SPR 16X4 PDPR 16X4
Number of slices 3 3
Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM
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2-6
Architecture
LatticeECP2/M Family Data Sheet
ROM Mode
ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in ROM mode. Preloading is accomplished
through the programming interface during PFU configuration.
Routing
There are many resources provided in the LatticeECP2/M devices to route signals individually or as buses with
related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing)
segments.
The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU).
The x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions. The x2 and
x6 resources are buffered, allowing the routing of both short and long connections between PFUs.
The LatticeECP2/M family has an enhanced routing architecture that produces a compact design. The Diamond
design software takes the output of the synthesis tool and places and routes the design. Generally, the place and
route tool is completely automatic, although an interactive routing editor is available to optimize the design.
sysCLOCK Phase Locked Loops (GPLL/SPLL)
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. All the devices in the LatticeECP2/M fam-
ily support two General Purpose PLLs (GPLLs) which are full-featured PLLs. In addition, some of the larger devices
have two to six Standard PLLs (SPLLs) that have a subset of GPLL functionality.
General Purpose PLL (GPLL)
The architecture of the GPLL is shown in Figure 2-5. A description of the GPLL functionality follows.
CLKI is the reference frequency (generated either from the pin or from routing) for the PLL. CLKI feeds into the
Input Clock Divider block. The CLKFB is the feedback signal (generated from CLKOP or from a user clock PIN/
logic). This signal feeds into the Feedback Divider. The Feedback Divider is used to multiply the reference fre-
quency.
The Delay Adjust Block adjusts either the delays of the reference or feedback signals. The Delay Adjust Block can
either be programmed during configuration or can be adjusted dynamically. The setup, hold or clock-to-out times of
the device can be improved by programming a delay in the feedback or input path of the PLL, which will advance or
delay the output clock with reference to the input clock.
Following the Delay Adjust Block, both the input path and feedback signals enter the Voltage Controlled Oscillator
(VCO) block. In this block the difference between the input path and feedback signals is used to control the fre-
quency and phase of the oscillator. A LOCK signal is generated by the VCO to indicate that the VCO has locked
onto the input clock signal. In dynamic mode, the PLL may lose lock after a dynamic delay adjustment and not
relock until the tLOCK parameter has been satisfied. LatticeECP2/M devices have two dedicated pins on the left and
right edges of the device for connecting optional external capacitors to the VCO. This allows the PLLs to operate at
a lower frequency. This is a shared resource that can only be used by one PLL (GPLL or SPLL) per side.
The output of the VCO then enters the post-scalar divider. The post-scalar divider allows the VCO to operate at
higher frequencies than the clock output (CLKOP), thereby increasing the frequency range. A secondary divider
takes the CLKOP signal and uses it to derive lower frequency outputs (CLKOK). The Phase/Duty Select block
adjusts the phase and duty cycle of the CLKOP signal and generates the CLKOS signal. The phase/duty cycle set-
ting can be pre-programmed or dynamically adjusted.
The primary output from the post scalar divider CLKOP along with the outputs from the secondary divider (CLKOK)
and Phase/Duty select (CLKOS) are fed to the clock distribution network.
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2-7
Architecture
LatticeECP2/M Family Data Sheet
Figure 2-5. General Purpose PLL (GPLL) Diagram
Standard PLL (SPLL)
Some of the larger devices have two to six Standard PLLs (SPLLs). SPLLs have the same features as GPLLs but
without delay adjustment capability. SPLLs also provide different parametric specifications. For more information,
please see the list of additional technical documentation at the end of this data sheet.
Table 2-4 provides a description of the signals in the GPLL and SPLL blocks.
Table 2-4. GPLL and SPLL Blocks Signal Descriptions
Signal I/O Description
CLKI I Clock input from external pin or routing
CLKFB I
PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock
(PIN or logic)
RST I “1” to reset PLL counters, VCO, charge pumps and M-dividers
RSTK I “1” to reset K-divider
CLKOS O PLL output clock to clock tree (phase shifted/duty cycle changed)
CLKOP O PLL output clock to clock tree (no phase shift)
CLKOK O PLL output to clock tree through secondary clock divider
LOCK O “1” indicates PLL LOCK to CLKI
DDAMODE1I Dynamic Delay Enable. “1”: Pin control (dynamic), “0”: Fuse Control (static)
DDAIZR1I Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on
DDAILAG1I Dynamic Delay Lag/Lead. “1”: Lead, “0”: Lag
DDAIDEL[2:0]1I Dynamic Delay Input
DPA MODES I DPA (Dynamic Phase Adjust/Duty Cycle Select) mode
DPHASE [3:0] I DPA Phase Adjust inputs
DDDUTY [3:0] DPA Duty Cycle Select inputs
1. These signals are not available in SPLL.
Input Clock
Divider
(CLKI)
Feedback
Divider
(CLKFB)
Delay
Adjust
Voltage
Controlled
Oscillator
Post Scalar
Divider
(CLKOP)
Phase/Duty
Select
Secondary
Divider
(CLKOK)
CLKOS
CLKOK
CLKOP
LOCK
CLKFB
CLKI
RST
Dynamic Delay Adjustment
(from routing or external pin)
from CLKOP (PLL internal),
from clock net(CLKOP) or from
a user clock (pin or logic)
Dynamic Adjustment
PLLCAP External Pin
(Optional External Capacitor)
RSTK
fl: LATTICE .- lsstoNnucrap
2-8
Architecture
LatticeECP2/M Family Data Sheet
Delay Locked Loops (DLL)
In addition to PLLs, the LatticeECP2/M family of devices has two DLLs per device.
CLKI is the input frequency (generated either from the pin or routing) for the DLL. CLKI feeds into the output muxes
block to bypass the DLL, directly to the DELAY CHAIN block and (directly or through divider circuit) to the reference
input of the Phase Frequency Detector (PFD) input mux. The reference signal for the PFD can also be generated
from the Delay Chain and CLKFB signals. The feedback input to the PFD is generated from the CLKFB pin, CLKI
or from tapped signal from the Delay chain.
The PFD produces a binary number proportional to the phase and frequency difference between the reference and
feedback signals. This binary output of the PFD is fed into a Arithmetic Logic Unit (ALU). Based on these inputs,
the ALU determines the correct digital control codes to send to the delay chain in order to better match the refer-
ence and feedback signals. This digital code from the ALU is also transmitted via the Digital Control bus (DCNTL)
bus to its associated DLLDELA delay block. The ALUHOLD input allows the user to suspend the ALU output at its
current value. The UDDCNTL signal allows the user to latch the current value on the DCNTL bus.
The DLL has two independent clock outputs, CLKOP and CLKOS. These outputs can individually select one of the
outputs from the tapped delay line. The CLKOS has optional fine phase shift and divider blocks to allow this output
to be further modified, if required. The fine phase shift block allows the CLKOS output to phase shifted a further 45,
22.5 or 11.25 degrees relative to its normal position. Both the CLKOS and CLKOP outputs are available with
optional duty cycle correction. Divide by two and divide by four frequencies are available at CLKOS. The LOCK out-
put signal is asserted when the DLL is locked. Figure 2-6 shows the DLL block diagram and Table 2-5 provides a
description of the DLL inputs and outputs.
The user can configure the DLL for many common functions such as time reference delay mode and clock injection
removal mode. Lattice provides primitives in its design tools for these functions. For more information about the
DLL, please see the list of additional technical documentation at the end of this data sheet.
Figure 2-6. Delay Locked Loop Diagram (DLL)
CLKOP
CLKOS
LOCK
CLKFB
CLKI
ALUHOLD
DCNTL
UDDCNTL
Phase
Frequency
Detector
Delay3
Delay2
Delay1
Delay0
Delay4
Reference
Feedback
9
÷4
÷2
÷4
÷2
RSTN
(from routing
or external pin)
from CLKOP (DLL
internal), from clock net
(CLKOP) or from a user
clock (pin or logic)
Arithmetic
Logic Unit
Lock
Detect Digital
Control
Output
Delay Chain
Output
Muxes
Duty
Cycle
50%
Duty
Cycle
50%
fl: LATTICE Illssumomzucrok
2-9
Architecture
LatticeECP2/M Family Data Sheet
Table 2-5. DLL Signals
DLLDELA Delay Block
Closely associated with each DLL is a DLLDELA block. This is a delay block consisting of a delay line with taps and
a selection scheme that selects one of the taps. The DCNTL[8:0] bus controls the delay of the CLKO signal. Typi-
cally this is the delay setting that the DLL uses to achieve phase alignment. This results in the delay providing a cal-
ibrated 90° phase shift that is useful in centering a clock in the middle of a data cycle for source synchronous data.
The CLKO signal feeds the edge clock network. Figure 2-7 shows the connections between the DLL block and the
DLLDELA delay block. For more information, please see the list of additional technical documentation at the end of
this data sheet.
Figure 2-7. DLLDELA Delay Block
PLL/DLL Cascading
LatticeECP2/M devices have been designed to allow certain combinations of PLL (GPLL and SPLL) and DLL cas-
cading. The allowable combinations are:
PLL to PLL supported
PLL to DLL supported
Signal I/O Description
CLKI I Clock input from external pin or routing
CLKFB I DLL feed input from DLL output, clock net, routing or external pin
RSTN I Active low synchronous reset
ALUHOLD I Active high freezes the ALU
UDDCNTL I Synchronous enable signal (hold high for two cycles) from routing
DCNTL[8:0] O Encoded digital control signals for PIC INDEL and slave delay calibration
CLKOP O The primary clock output
CLKOS O The secondary clock output with fine phase shift and/or division by 2 or by 4
LOCK O Active high phase lock indicator
DLL Block
CLKOP
CLKOS
LOCK
CLKO
CLKI
CLKFB
CLKI
DLLDELA Delay Block
PLL_PIO
DLL_PIO
Routing
Routing
CLKFB_CK
ECLK1
CLKOP
GDLLFB_PIO
DCNTL[8:0]
*
*
*
* Software selectable
fl: LATTICE Illssumomzucrok
2-10
Architecture
LatticeECP2/M Family Data Sheet
The DLLs in the LatticeECP2/M are used to shift the clock in relation to the data for source synchronous inputs.
PLLs are used for frequency synthesis and clock generation for source synchronous interfaces. Cascading PLL
and DLL blocks allows applications to utilize the unique benefits of both DLLs and PLLs.
For further information about the DLL, please see the list of additional technical documentation at the end of this
data sheet.
GPLL/SPLL/GDLL PIO Input Pin Connections (LatticeECP2M Family Only)
All LatticeECP2M devices contain two GDLLs, two GPLLs and six SPLLs, arranged in quadrants as shown in
Figure 2-8. In the LatticeECP2M devices GPLLs, SPLLs and GDLLs share their input pins. Figure 2-8 shows the
sharing of SPLLs input pin connections in the upper two quadrants and the sharing of GDLL, GPLL and SPLL input
pin connections in the lower two quadrants.
Figure 2-8. Sharing of PIO Pins by GPLL, SPLL and GDLL in LatticeECP2M Devices
Clock Dividers
LatticeECP2/M devices have two clock dividers, one on the left side and one on the right side of the device. These
are intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2,
÷4 or ÷8 mode and maintains a known phase relationship between the divided down clock and the high-speed
clock based on the release of its reset signal. The clock dividers can be fed from selected PLL/DLL outputs, DLL-
DELA delay blocks, routing or from an external clock input. The clock divider outputs serve as primary clock
sources and feed into the clock distribution network. The Reset (RST) control signal resets input and synchro-
nously forces all outputs to low. The RELEASE signal releases outputs synchronously to the input clock. For further
information about clock dividers, please see the list of additional technical documentation at the end of this data
sheet. Figure 2-9 shows the clock divider connections.
LATTICE sstoNnucram iiiilii
2-11
Architecture
LatticeECP2/M Family Data Sheet
Figure 2-9. Clock Divider Connections
Clock Distribution Network
LatticeECP2/M devices have eight quadrant-based primary clocks and eight flexible region-based secondary
clocks/control signals. Two high performance edge clocks are available on each edge of the device to support high
speed interfaces. These clock inputs are selected from external I/Os, the sysCLOCK PLLs, DLLs or routing. These
clock inputs are fed throughout the chip via a clock distribution system.
Primary Clock Sources
LatticeECP2/M devices derive clocks from five primary sources: PLL (GPLL and SPLL) outputs, DLL outputs, CLK-
DIV outputs, dedicated clock inputs and routing. LatticeECP2/M devices have two to eight sysCLOCK PLLs and
two DLLs, located on the left and right sides of the device. There are eight dedicated clock inputs, two on each side
of the device, with the exception of the LatticeECP2M 256-fpBGA package devices which have six dedicated clock
inputs on the device. Figure 2-10 shows the primary clock sources.
RST
RELEASE
÷1
÷2
÷4
÷8
CLKO
CLKOP (GPLL)
CLKOP (DLL)
Routing
PLL PAD
CLKOS (GPLL)
CLKOS (DLL)
CLKDIV
lllllllllllllllll
2-12
Architecture
LatticeECP2/M Family Data Sheet
Figure 2-10. Primary Clock Sources for ECP2-50
Primary Clock Sources
to Eight Quadrant Clock Selection
From Routing
From Routing
SPLL
GPLL
DLL
PLL Input
PLL Input
DLL Input
Note: This diagram shows sources for the ECP2-50 device. Smaller LatticeECP2 devices have fewer SPLLs. All LatticeECP2M devices
have six SPLLs.
CLK
DIV
Clock
Input
Clock
Input
PLL Input
PLL Input
DLL Input
Clock
Input
Clock
Input
Clock Input
Clock Input
Clock Input
Clock Input
SPLL
GPLL
DLL
CLK
DIV
lllllllllllllllll ii %% ii
2-13
Architecture
LatticeECP2/M Family Data Sheet
Secondary Clock/Control Sources
LatticeECP2/M devices derive secondary clocks (SC0 through SC7) from eight dedicated clock input pads and the
rest from routing. Figure 2-11 shows the secondary clock sources.
Figure 2-11. Secondary Clock Sources
Secondary Clock Sources
From Routing
From
Routing
From
Routing
From
Routing
From
Routing
From
Routing
From
Routing
From
Routing
From
Routing
From Routing
Clock Input
Clock
Input
Clock
Input
Clock
Input
Clock
Input
Clock Input
From Routing
From Routing
From Routing
From Routing
Clock Input
Clock Input
From Routing
From Routing
lllllllllllllllll W ~
2-14
Architecture
LatticeECP2/M Family Data Sheet
Edge Clock Sources
Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be
driven from adjacent edge clock PIOs, primary clock PIOs, PLLs/DLLs and clock dividers as shown in Figure 2-12.
Figure 2-12. Edge Clock Sources
Eight Edge Clocks (ECLK)
Two Clocks per Edge
Sources for
bottom edge
clocks
Sources for right edge clocks
Clock
Input
Clock
Input
From Routing
From
Routing
From
Routing
From
Routing
From
Routing
Clock Input Clock Input
Clock Input Clock Input
From Routing
From Routing
Clock
Input
Clock
Input
From Routing
Sources for left edge clocks
Sources for top
edge clocks
DLL
Input
PLL
Input
DLL
Input
PLL
Input
DLLDELA
DLL
GPLL
DLL
GPLL
DLLDELA
fl: LATTICE lllllllllllllllll
2-15
Architecture
LatticeECP2/M Family Data Sheet
Primary Clock Routing
The clock routing structure in LatticeECP2/M devices consists of a network of eight primary clock lines (CLK0
through CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center
of the device. All the clock sources are connected to these muxes. Figure 2-13 shows the clock routing for one
quadrant. Each quadrant mux is identical. If desired, any clock can be routed globally
Figure 2-13. Per Quadrant Primary Clock Selection
Dynamic Clock Select (DCS)
The DCS is a smart multiplexer function available in the primary clock routing. It switches between two independent
input clock sources without any glitches or runt pulses. This is achieved regardless of when the select signal is tog-
gled. There are two DCS blocks per quadrant; in total, there are eight DCS blocks per device. The inputs to the
DCS block come from the center muxes. The output of the DCS is connected to primary clocks CLK6 and CLK7
(see Figure 2-13).
Figure 2-14 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed
to other modes. For more information about the DCS, please see the list of additional technical documentation at
the end of this data sheet.
Figure 2-14. DCS Waveforms
Secondary Clock/Control Routing
Secondary clocks in the LatticeECP2 devices are region-based resources. The benefit of region-based resources
is the relatively low injection delay and skew within the region, as compared to primary clocks. EBR/DSP rows and
a special vertical routing channel bound the secondary clock regions. This special vertical routing channel aligns
with either the left edge of the center DSP block in the DSP row or the center of the DSP row. Figure 2-15 shows
CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7
35:1 35:1 35:1 35:1 32:1 32:1 32:1 32:135:1 35:1
8 Primary Clocks (CLK0 to CLK7) per Quadrant
DCS DCS
Primary Clock Sources: PLLs + DLLs + CLKDIVs + PIOs + Routing
CLK0
SEL
DCSOUT
CLK1
LATTICE sstoNnucram Secondary Clock Region 5 Secondary Clock z nines ON EX“
2-16
Architecture
LatticeECP2/M Family Data Sheet
this special vertical routing channel and the eight secondary clock regions for the ECP2-50. LatticeECP2 devices
have four secondary clocks (SC0 to SC3) which are distrubed to every region.
The secondary clock muxes are located in the center of the device. Figure 2-16 shows the mux structure of the
secondary clock routing. Secondary clocks SC0 to SC3 are used for clock and control and SC4 to SC7 are used for
high fan-out signals.
Figure 2-15. Secondary Clock Regions ECP2-50
I/O Bank 0 I/O Bank 1
I/O Bank 6 I/O Bank 7
I/O Bank 2 I/O Bank 3
I/O Bank 5 I/O Bank 4
Secondary Clock
Region 1
Secondary Clock
Region 2
Secondary Clock
Region 3
Secondary Clock
Region 4
Secondary Clock
Region 5
Secondary Clock
Region 6
Secondary Clock
Region 7
Secondary Clock
Region 8
Vertical Routing
Channel Regional
Boundary
EBR Row
Regional
Boundary
DSP Row
Regional
Boundary
DSP Row
Regional
Boundary
Bank 8
_:,-_: LATTICE 55555555555555
2-17
Architecture
LatticeECP2/M Family Data Sheet
Figure 2-16. Secondary Clock Selection
Slice Clock Selection
Figure 2-17 shows the clock selections and Figure 2-18 shows the control selections for Slice0 through Slice2. All
the primary clocks and the four secondary clocks are routed to this clock selection mux. Other signals can be used
as a clock input to the slices via routing. Slice controls are generated from the secondary clocks or other signals
connected via routing.
If none of the signals are selected for both clock and control then the default value of the mux output is 1. Slice 3
does not have any registers; therefore it does not have the clock or control muxes.
Figure 2-17. Slice0 through Slice2 Clock Selection
SC0 SC1 SC2 SC3 SC4 SC5
24:1 24:1 24:1
SC6 SC7
24:1 24:1 24:1 24:1 24:1
4 Secondary Clocks/CE/LSR (SC0 to SC3) per Region
Clock/Control
Secondary Clock Feedlines: 8 PIOs + 16 Routing
High Fan-out Data
4 High Fan-out Data Signals (SC4 to SC7) per Region
Clock to Slice
Primary Clock
Secondary Clock
Routing
Vcc
8
4
12
1
25:1
LATTICE sstoNnucram l i M M M M
2-18
Architecture
LatticeECP2/M Family Data Sheet
Figure 2-18. Slice0 through Slice2 Control Selection
Edge Clock Routing
LatticeECP2/M devices have a number of high-speed edge clocks that are intended for use with the PIOs in the
implementation of high-speed interfaces. There are eight edge clocks per device: two edge clocks per edge. Differ-
ent PLL and DLL outputs are routed to the two muxes on the left and right sides of the device. In addition, the
CLKO signal (generated from the DLLDELA block) is routed to all the edge clock muxes on the left and right sides
of the device. Figure 2-19 shows the selection muxes for these clocks.
Figure 2-19. Edge Clock Mux Connections
Slice Control
Secondary Clock
Routing
Vcc
3
12
1
16:1
Left and Right
Edge Clocks
ECLK1
Top and Bottom
Edge Clocks
ECLK1/ ECLK2
Clock Input Pad
Routing
Routing
Input Pad
GPLL Input Pad
DLL Output CLKOP
GPLL Output CLKOP
CLKO
Left and Right
Edge Clocks
ECLK2
Routing
Input Pad
GPLL Input Pad
DLL Output CLKOS
GPLL Output CLKOS
CLKO
(Both Mux)
_:,-_: LATTICE 55555555555555
2-19
Architecture
LatticeECP2/M Family Data Sheet
sysMEM Memory
LatticeECP2/M devices contains a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18-
Kbit RAM with dedicated input and output registers.
sysMEM Memory Block
The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in
a variety of depths and widths as shown in Table 2-6. FIFOs can be implemented in sysMEM EBR blocks by imple-
menting support logic with PFUs. The EBR block facilitates parity checking by supporting an optional parity bit for
each data byte. EBR blocks provide byte-enable support for configurations with18-bit and 36-bit data widths.
Table 2-6. sysMEM Block Configurations
Bus Size Matching
All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB
word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for
each port varies, this mapping scheme applies to each port.
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block
during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a
ROM.
Memory Cascading
Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
cascade memory transparently, based on specific design inputs.
Single, Dual and Pseudo-Dual Port Modes
In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory
array. The output data of the memory is optionally registered at the output.
EBR memory supports two forms of write behavior for single port or dual port operation:
1. Normal – Data on the output appears only during a read cycle. During a write cycle, the data (at the current
address) does not appear on the output. This mode is supported for all data widths.
Memory Mode Configurations
Single Port
16,384 x 1
8,192 x 2
4,096 x 4
2,048 x 9
1,024 x 18
512 x 36
True Dual Port
16,384 x 1
8,192 x 2
4,096 x 4
2,048 x 9
1,024 x 18
Pseudo Dual Port
16,384 x 1
8,192 x 2
4,096 x 4
2,048 x 9
1,024 x 18
512 x 36
_:,-_: LATTICE 55555555555555
2-20
Architecture
LatticeECP2/M Family Data Sheet
2. Write Through – A copy of the input data appears at the output of the same port during a write cycle. This
mode is supported for all data widths.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A
and Port B, respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associ-
ated resets for both ports are as shown in Figure 2-20.
Figure 2-20. Memory Core Reset
For further information about the sysMEM EBR block, please see the the list of additional technical documentation
at the end of this data sheet.
EBR Asynchronous Reset
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the
reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-21. The GSR input to the
EBR is always asynchronous.
Figure 2-21. EBR Asynchronous Reset (Including GSR) Timing Diagram
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after
the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset
release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
Q
SET
D
L
CLR
Output Data
Latches
Memory Core
Port A[17:0]
Q
SET
DPort B[17:0]
RSTB
GSRN
Pro
g
rammable Disable
RSTA
L
CLR
Reset
Clock
Clock
Enable
_:,-_: LATTICE 55555555555555
2-21
Architecture
LatticeECP2/M Family Data Sheet
If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during
device Wake Up must occur before the release of the device I/Os becomes active.
These instructions apply to all EBR RAM and ROM implementations.
Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.
sysDSP™ Block
The LatticeECP2/M family provides a sysDSP block, making it ideally suited for low cost, high performance Digital
Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response
(FIR) filters, Fast Fourier Transforms (FFT) functions, Correlators, Reed-Solomon/Turbo/Convolution encoders and
decoders. These complex signal processing functions use similar building blocks such as multiply-adders and mul-
tiply-accumulators.
sysDSP Block Approach Compared to General DSP
Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with
fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by
higher clock speeds. The LatticeECP2/M, on the other hand, has many DSP blocks that support different data-
widths. This allows the designer to use highly parallel implementations of DSP functions. The designer can opti-
mize the DSP performance vs. area by choosing an appropriate level of parallelism. Figure 2-22 compares the fully
serial and the mixed parallel and serial implementations.
Figure 2-22. Comparison of General DSP and LatticeECP2/M Approaches
sysDSP Block Capabilities
The sysDSP block in the LatticeECP2/M family supports four functional elements in three 9, 18 and 36 data path
widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned)
of its operands. The operands in the LatticeECP2/M family sysDSP Blocks can be either signed or unsigned but not
mixed within a function element. Similarly, the operand widths cannot be mixed within a block. In the LatticeECP2/
M family the DSP elements can be concatenated.
The resources in each sysDSP block can be configured to support the following elements:
Multiplier 0
x
Operand
A
Operand
B
x
Operand
A
Operand
B
x
Operand
A
Operand
B
Multiplier 1 Multiplier k
(k adds)
Output
m/k
loops
Single
Multiplier x
Operand
A
Accumulator
Operand
B
M loops
Function implemented in
General purpose DSP
Function implemented
in LatticeECP2/M
m/k
accumulate
++
_:,-_: LATTICE 55555555555555
2-22
Architecture
LatticeECP2/M Family Data Sheet
MULT (Multiply)
MAC (Multiply, Accumulate)
MULTADDSUB (Multiply, Addition/Subtraction)
MULTADDSUBSUM (Multiply, Addition/Subtraction, Accumulate)
The number of elements available on each block depends in the width selected from the three available options x9,
x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions.
Table 2-7 shows the capabilities of the block.
Table 2-7. Maximum Number of Elements in a Block
Some options are available in four elements. The input register in all the elements can be directly loaded or can be
loaded as a shift register from previous operand registers. By selecting “dynamic operation” the following opera-
tions are possible:
In the ‘Signed/Unsigned’ options the operands can be switched between signed and unsigned on every cycle.
In the ‘Add/Sub’ option the Accumulator can be switched between addition and subtraction on every cycle.
The loading of operands can switch between parallel and serial operations.
Width of Multiply x9 x18 x36
MULT 841
MAC 2 2
MULTADDSUB 4 2
MULTADDSUBSUM 2 1
fl: LATTICE lllllllllllllllll
2-23
Architecture
LatticeECP2/M Family Data Sheet
MULT sysDSP Element
This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B,
are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers.
Figure 2-23 shows the MULT sysDSP element.
Figure 2-23. MULT sysDSP Element
Multiplier
x
n
m
m
n
m
n
m
n
n
m
m+n
m+n
(default)
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Pipeline
Register
Input
Register
Multiplier
Multiplicand
Signed A
Shift Register A InShift Register B In
Shift Register A OutShift Register B Out
Output
Input Data
Register A
Input Data
Register B
Output
Register
To
Multiplier
Input
Register
Signed B To
Multiplier
LATTICE 55555555555555
2-24
Architecture
LatticeECP2/M Family Data Sheet
MAC sysDSP Element
In this case, the two operands, A and B, are multiplied and the result is added with the previous accumulated value.
This accumulated value is available at the output. The user can enable the input and pipeline registers, but the out-
put register is always enabled. The output register is used to store the accumulated value. The Accumulators in the
DSP blocks in the LatticeECP2/M family can be initialized dynamically. A registered overflow signal is also avail-
able. The overflow conditions are provided later in this document. Figure 2-24 shows the MAC sysDSP element.
Figure 2-24. MAC sysDSP
Multiplier
x
Input Data
Register A
n
m
Input Data
Register B
m
n
n
n
m
n
n
m
Output
Register
Output
Register
Accumulator
Multiplier
Multiplicand
Signed A
Serial Register B in Serial Register A in
SROB SROA
Output
Addn
Accumsload
Pipeline
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Input
Pipeline
Register
Input
Register
Pipeline
Register
Input
Register
Pipeline
Register
To Accumulator
Signed B Pipeline
Input To Accumulator
To Accumulator
To Accumulator
Overflow
signal
m+n
(default)
m+n+16
(default)
m+n+16
(default)
Preload
Register
Register
Register
Register
fl: LATTICE lllllllllllllllll [ii [Ml
2-25
Architecture
LatticeECP2/M Family Data Sheet
MULTADDSUB sysDSP Element
In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands A1 and A2. The user can enable the input, output and pipeline registers. Figure 2-25
shows the MULTADDSUB sysDSP element.
Figure 2-25. MULTADDSUB
Multiplier
Multiplier
Add/Sub
Pipe
Reg
Pipe
Reg
n
m
m
n
m
n
m
n
n
m
m+n
(default)
m+n+1
(default)
m+n+1
(default)
m+n
(default)
x
x
n
m
m
n
m
n
n
m
Multiplier B0
Multiplicand A0
Multiplier B1
Multiplicand A1
Signed A
Shift Register A InShift Register B In
Shift Register A OutShift Register B Out
Output
Addn
Pipeline
Register
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Input
Register
Pipeline
Register
Input
Register
Pipeline
Register
Pipeline
Register
Pipe
Reg
Signed B Pipeline
Register
Input
Register
Input Data
Register A
Input Data
Register A
Input Data
Register B
Input Data
Register B
Output
Register
To Add/Sub
To Add/Sub
To Add/Sub
_::'_: LATTICE 55555555555555
2-26
Architecture
LatticeECP2/M Family Data Sheet
MULTADDSUBSUM sysDSP Element
In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/
subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction
are added in a summation block. The user can enable the input, output and pipeline registers. Figure 2-26 shows
the MULTADDSUBSUM sysDSP element.
Figure 2-26. MULTADDSUBSUM
Clock, Clock Enable and Reset Resources
Global Clock, Clock Enable and Reset signals from routing are available to every DSP block. Four Clock, Reset
and Clock Enable signals are selected for the sysDSP block. From four clock sources (CLK0, CLK1, CLK2, CLK3)
Multiplier
Add/Sub0
x
n
mm+n
(default)
m+n
(default)
m+n+1
m+n+2 m+n+2
m+n+1
m+n
(default)
m+n
(default)
m
n
m
n
m
n
n
m
x
n
n
m
n
n
m
Multiplier
Multiplier
Multiplier
Add/Sub1
x
n
m
m
n
m
n
m
n
n
m
x
n
m
m
n
m
n
n
m
SUM
Multiplier B0
Multiplicand A0
Multiplier B1
Multiplicand A1
Multiplier B2
Multiplicand A2
Multiplier B3
Multiplicand A3
Signed A
Shift Register B In
Output
Addn0
Pipeline
Register
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Input
Register
Pipeline
Register
Input
Register
To Add/Sub0
To Add/Sub0, Add/Sub1
Pipeline
Register
Signed B Pipeline
Register
Input
Register To Add/Sub0, Add/Sub1
Pipeline
Register
Input
Register
To Add/Sub1
Addn1
Pipeline
Register
Pipeline
Register
Pipeline
Register
Shift Register A In
Shift Register B Out Shift Register A Out
Input Data
Register A
Input Data
Register A
Input Data
Register A
Input Data
Register A
Input Data
Register B
Input Data
Register B
Input Data
Register B
Input Data
Register B
Output
Register
fl: LATTICE lllllllllllllllll
2-27
Architecture
LatticeECP2/M Family Data Sheet
one clock is selected for each input register, pipeline register and output register. Similarly Clock enable (CE) and
Reset (RST) are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3)
at each input register, pipeline register and output register.
Signed and Unsigned with Different Widths
The DSP block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. For
unsigned operands, unused upper data bits should be filled to create a valid x9, x18 or x36 operand. For signed
two’s complement operands, sign extension of the most significant bit should be performed until x9, x18 or x36
width is reached. Table 2-8 provides an example of this.
Table 2-8. Sign Extension Example
OVERFLOW Flag from MAC
The sysDSP block provides an overflow output to indicate that the accumulator has overflowed. When two
unsigned numbers are added and the result is a smaller number than the accumulator, “roll-over” is said to have
occurred and an overflow signal is indicated. When two positive numbers are added with a negative sum and when
two negative numbers are added with a positive sum, then the accumulator “roll-over” is said to have occurred and
an overflow signal is indicated. Note that when overflow occurs the overflow flag is present for only one cycle. By
counting these overflow pulses in FPGA logic, larger accumulators can be constructed. The conditions overflow
signals for signed and unsigned operands are listed in Figure 2-27.
Figure 2-27. Accumulator Overflow/Underflow
Number Unsigned
Unsigned
9-bit
Unsigned
18-bit Signed
Two’s Complement
Signed 9 Bits
Two’s Complement
Signed 18 Bits
+5 0101 000000101 000000000000000101 0101 000000101 000000000000000101
-6 N/A N/A N/A 1010 111111010 111111111111111010
000000000
000000001
000000010
000000011
111111101
111111110
111111111
Overflow signal is generated
for one cycle when this
boundary is crossed
0
+1
+2
+3
-3
-2
-1
Unsigned Operation
Signed Operation
0101111111
0101111110
0101111101
0101111100
1010000010
1010000001
1010000000
255
254
253
252
-254
-255
-256
000000000
000000001
000000010
000000011
111111101
111111110
111111111
Carry signal is generated for
one cycle when this
boundary is crossed
0
1
2
3
509
510
511
0101111111
0101111110
0101111101
0101111100
1010000010
1010000001
1010000000
255
254
253
252
258
257
256
_:_:_: LATTICE 55555555555555
2-28
Architecture
LatticeECP2/M Family Data Sheet
IPexpress™
The user can access the sysDSP block via the IPexpress tool, which provides the option to configure each DSP
module (or group of modules) or by direct HDL instantiation. In addition, Lattice has partnered with The Math-
Works® to support instantiation in the Simulink® tool, a graphical simulation environment. Simulink works with Dia-
mond to dramatically shorten the DSP design cycle in Lattice FPGAs.
Optimized DSP Functions
Lattice provides a library of optimized DSP IP functions. Some of the IP cores planned for the LatticeECP2/M DSP
include the Bit Correlator, Fast Fourier Transform, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/
Decoder, Turbo Encoder/Decoder and Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest
list of available DSP IP cores.
Resources Available in the LatticeECP2/M Family
Table 2-9 shows the maximum number of multipliers for each member of the LatticeECP2/M family. Table 2-10
shows the maximum available EBR RAM Blocks in each LatticeECP2/M device. EBR blocks, together with Distrib-
uted RAM can be used to store variables locally for fast DSP operations.
Table 2-9. Maximum Number of DSP Blocks in the LatticeECP2/M Family
Table 2-10. Embedded SRAM in the LatticeECP2/M Family
Device DSP Block 9x9 Multiplier 18x18 Multiplier 36x36 Multiplier
ECP2-6 3 24 12 3
ECP2-12 6 48 24 6
ECP2-20 7 56 28 7
ECP2-35 8 64 32 8
ECP2-50 18 144 72 18
ECP2-70 22 176 88 22
ECP2M20 6 48 24 6
ECP2M35 8 64 32 8
ECP2M50 22 176 88 22
ECP2M70 24 192 96 24
ECP2M100 42 336 168 42
Device EBR SRAM Block
Total EBR SRAM
(Kbits)
ECP2-6 3 55
ECP2-12 12 221
ECP2-20 15 277
ECP2-35 18 332
ECP2-50 21 387
ECP2-70 60 1106
ECP2M20 66 1217
ECP2M35 114 2101
ECP2M50 225 4147
ECP2M70 246 4534
ECP2M100 288 5308
_:,-_: LATTICE 55555555555555
2-29
Architecture
LatticeECP2/M Family Data Sheet
LatticeECP2/M DSP Performance
Table 2-11 lists the maximum performance in millions of MAC operations per second (MMAC) for each member of
the LatticeECP2/M family.
Table 2-11. DSP Performance
For further information about the sysDSP block, please see the list of additional technical information at the end of
this data sheet.
Programmable I/O Cells (PIC)
Each PIC contains two PIOs connected to their respective sysI/O buffers as shown in Figure 2-28. The PIO Block
supplies the output data (DO) and the tri-state control signal (TO) to the sysI/O buffer and receives input from the
buffer. Table 2-12 provides the PIO signal list.
Device DSP Block
DSP Performance
GMAC
ECP2-6 3 3.9
ECP2-12 6 7.8
ECP2-20 7 9.1
ECP2-35 8 10.4
ECP2-50 18 23.4
ECP2-70 22 28.6
ECP2M20 6 7.8
ECP2M35 8 10.4
ECP2M50 22 28.6
ECP2M70 24 31.2
ECP2M100 42 54.6
_:,-_: LATTICE 55555555555555
2-30
Architecture
LatticeECP2/M Family Data Sheet
Figure 2-28. PIC Diagram
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-28.
The PAD Labels “T” and “C” distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right
edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as inputs.
OPOS1
ONEG1
TD
INCK**
INDD
INFF
IPOS0
IPOS1
CLK
CE
LSR
GSRN
CLK1
CLK0
CEO
CEI
sysIO
Buffer
PADA
“T”
PADB
“C”
LSR
GSR
ECLK1
DDRCLKPOL*
*Signals are available on left/right/bottom edges only.
** Selected blocks.
IOLD0
DI
Tristate
Register
Block
Output
Register
Block
Input
Register
Block
Control
Muxes
PIOB
PIOA
OPOS0
OPOS2*
ONEG0
ONEG2*
DQSXFER*
QPOS1*
QNEG1*
QNEG0*
QPOS0*
IOLT0
ECLK2
_:_:_: LATTICE 55555555555555
2-31
Architecture
LatticeECP2/M Family Data Sheet
Table 2-12. PIO Signals List
PIO
The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic
block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selec-
tion logic.
Input Register Block
The input register blocks for PIOs in left, right and bottom edges contain delay elements and registers that can be
used to condition high-speed interface signals, such as DDR memory interfaces and source synchronous inter-
faces, before they are passed to the device core. Figure 2-29 shows the diagram of the input register block for left,
right and bottom edges. The input register block for the top edge contains one memory element to register the input
signal as shown in Figure 2-30. The following description applies to the input register block for PIOs in the left, right
and bottom edges of the device.
Input signals are fed from the sysI/O buffer to the input register block (as signal DI). If desired, the input signal can
bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and,
in selected blocks, the input to the DQS delay block. If an input delay is desired, designers can select either a fixed
delay or a dynamic delay DEL[3:0]. The delay, if selected, reduces input register hold time requirements when
using a global clock.
The input block allows three modes of operation. In the single data rate (SDR) the data is registered, by one of the
registers in the single data rate sync register block, with the system clock. In DDR Mode, two registers are used to
sample the data on the positive and negative edges of the DQS signal, creating two data streams, D0 and D1.
These two data streams are synchronized with the system clock before entering the core. Further discussion on
this topic is in the DDR Memory section of this data sheet.
Name Type Description
CE0, CE1 Control from the core Clock enables for input and output block flip-flops
CLK0, CLK1 Control from the core System clocks for input and output blocks
ECLK1, ECLK2 Control from the core Fast edge clocks
LSR Control from the core Local Set/Reset
GSRN Control from routing Global Set/Reset (active low)
INCK2 Input to the core Input to Primary Clock Network or PLL reference inputs
DQS Input to PIO DQS signal from logic (routing) to PIO
INDD Input to the core Unregistered data input to core
INFF Input to the core Registered input on positive edge of the clock (CLK0)
IPOS0, IPOS1 Input to the core Double data rate registered inputs to the core
QPOS01, QPOS11 Input to the core Gearbox pipelined inputs to the core
QNEG01, QNEG11Input to the core Gearbox pipelined inputs to the core
OPOS0, ONEG0,
OPOS2, ONEG2 Output data from the core Output signals from the core for SDR and DDR operation
OPOS1 ONEG1 Tristate control from the core Signals to Tristate Register block for DDR operation
DEL[3:0] Control from the core Dynamic input delay control bits
TD Tristate control from the core Tristate signal from the core used in SDR operation
DDRCLKPOL Control from clock polarity bus Controls the polarity of the clock (CLK0) that feed the DDR input block
DQSXFER Control from core Controls signal to the Output block
1. Signals available on left/right/bottom only.
2. Selected I/O.
_::'_: LATTICE 55555555555555 ","rfifirfiflwrrwrfl ”777777777": ,,,,,,,,,,,,,,,,,, + 43W; % a f ’ h?
2-32
Architecture
LatticeECP2/M Family Data Sheet
By combining input blocks of the complementary PIOs and sharing some registers from output blocks, a gearbox
function can be implemented, which takes a double data rate signal applied to PIOA and converts it as four data
streams, IPOS0A, IPOS1A, IPOS0B and IPOS1B. Figure 2-29 shows the diagram using this gearbox function. For
more information about this topic, please see information regarding additional documentation at the end of this
data sheet.
The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-
quate timing when data is transferred from the DQS to the system clock domain. For further information about this
topic, see the DDR Memory section of this data sheet.
Figure 2-29. Input Register Block for Left, Right and Bottom Edges
Clock Transfer Registers
Clock Transfer Registers
SDR & Sync
Registers
D1
D2
D0
DDR Registers
DQ
D-Type
DQ
D-Type
DQ
D-Type
DQ
D-Type
/LATCH
DQ
D-Type
0
1
DQ
DQ
0
1
Fixed Delay
Dynamic Delay
DI
(From sysIO
Buffer)
DI
(From sysIO
Buffer)
INCK**
INDD
IPOS0A
QPOS0A
IPOS1A
QPOS1A
DEL [3:0]
CLK0 (of PIO A)
Delayed
DQS 0
1
CLKA
DQ
DQ
DQ
0
1
0
1
DQ
DQ
0
1
DQ
DQ
0
1
Fixed Delay
Dynamic Delay
INCK**
INDD
IPOS0B
QPOS0B
IPOS1B
QPOS1B
DEL [3:0]
CLK0 (of PIO B)
Delayed
DQS
CLKB
/LATCH
True PIO (A) in LVDS I/O Pair
Comp PIO (B) in LVDS I/O Pair
D-Type*
D-Type*
D-Type
/LATCH
D-Type
/LATCH
D-Type*
D-Type*
From
Routing
To
Routing
D1 D2
D0
DDR Registers SDR & Sync
Registers
0
1
DDRSRC
Gearbox Configuration Bit
DDRCLKPOL
DDRCLKPOL
*Shared with output register
**Selected PIO.
Note: Simplified version does not
show CE and SET/RESET details
From
Routing
To
Routing
To DQS Delay Block**
To DQS Delay Block**
D-TypeD-Type
D-Type
_:,-_: LATTICE 55555555555555
2-33
Architecture
LatticeECP2/M Family Data Sheet
Figure 2-30. Input Register Block Top Edge
Output Register Block
The output register block provides the ability to register signals from the core of the device before they are passed
to the sysI/O buffers. The blocks on the PIOs on the left, right and bottom contain a register for SDR operation that
is combined with an additional latch for DDR operation. Figure 2-31 shows the diagram of the Output Register
Block for PIOs on the left, right and the bottom edges. Figure 2-32 shows the diagram of the Output Register Block
for PIOs on the top edge of the device.
In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-
type or latch. In DDR mode, ONEG0 and OPOS0 are fed into registers on the positive edge of the clock. Then at
the next clock cycle this registered OPOS0 is latched. A multiplexer running off the same clock selects the correct
register for feeding to the output (D0).
By combining the output blocks of the complementary PIOs and sharing some registers from input blocks, a gear-
box function can be implemented, that takes four data streams: ONEG0A, ONEG1A, ONEG1B and ONEG1B.
Figure 2-32 shows the diagram using this gearbox function. For more information about this topic, please see infor-
mation regarding additional documentation at the end of this data sheet.
Fixed Delay
Dynamic Delay
Note: Simplified version does not show CE and SET/RESET details.
*On selected blocks.
To Routing
DI
(from sysIO
buffer)
CLK0
(from
routing)
DEL[3:0]
INCK*
INDD
D-Type
IPOS0
/LATCH
DQ
_::'_: LATTICE 55555555555555
2-34
Architecture
LatticeECP2/M Family Data Sheet
Figure 2-31. Output and Tristate Block for Left, Right and Bottom Edges
Clock Transfer
Registers
ONEG1
CLKA
TO
OPOS1
From Routing
TD
DQ
DQDQ
0
1
0
1
0
1
DQ
DQDQ
0
1
0
1
DQ
D-Type
*
DQ
Latch
DQ
0
1
0
1
0
1
0
1
ONEG0
OPOS0
DO
Programmable
Control
Programmable
Control
0
1
ECLK1
ECLK2
CLK1
Tristate Logic
Tristate Logic
Output Logic
True PIO (A) in LVDS I/O Pair
To sysIO Buffer
ONEG1
CLKB
TO
OPOS1
From Routing
TD
DQ
DQ
DQ
0
1
0
1
0
1
DQ
D-Type
/LATCH
D-Type
/LATCH
D-Type
/LATCH
D-Type
/LATCH
DQDQ
0
1
0
1
DQ
DQ
Latch D-Type
D-Type Latch
Latch
D-Type Latch
D-Type Latch
DQ
ONEG0
OPOS0
DO
ECLK1
ECLK2
CLK1
Output Logic
To sysIO Buffer
Comp PIO (B) in LVDS I/O Pair
(CLKB)
(CLKA)
D-Type
*
D-Type*
D-Type*
Clock Transfer
Registers
DDR Output
Registers
DDR Output
Registers
* Shared with input register Note: Simplified version does not show CE and SET/RESET details
0
1
DQSXFER
DQSXFER
0
10
1
fl: LATTICE lllllllllllllllll
2-35
Architecture
LatticeECP2/M Family Data Sheet
Figure 2-32. Output and Tristate Block, Top Edge
Tristate Register Block
The tristate register block provides the ability to register tri-state control signals from the core of the device before
they are passed to the sysI/O buffers. The block contains a register for SDR operation and an additional latch for
DDR operation. Figure 2-31 shows the diagram of the Tristate Register Block with the Output Block for the left, right
and bottom edges and Figure 2-32 shows the diagram of the Tristate Register Block with the Output Block for the
top edge.
In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D-
type or latch. In DDR mode, ONEG1 and OPOS1 are fed into registers on the positive edge of the clock. Then in
the next clock the registered OPOS1 is latched. A multiplexer running off the same clock cycle selects the correct
register for feeding to the output (D0).
Control Logic Block
The control logic block allows the selection and modification of control signals for use in the PIO block. A clock is
selected from one of the clock signals provided from the general purpose routing, one of the edge clocks (ECLK1/
ECLK2) and a DQS signal provided from the programmable DQS pin and provided to the input register block. The
clock can optionally be inverted.
DDR Memory Support
Certain PICs have additional circuitry to allow the implementation of high speed source synchronous and DDR
memory interfaces. The support varies by the edge of the device as detailed below.
Left and Right Edges
PICs on these edges have registered elements that support DDR memory interfaces. One of every 16 PIOs con-
tains a delay element to facilitate the generation of DQS signals. The DQS signal feeds the DQS bus that spans the
set of 16 PIOs. Figure 2-33 shows the assignment of DQS pins in each set of 16 PIOs.
Bottom Edge
PICs on the bottom edge have registered elements that support DDR memory interfaces. One of every 18 PIOs
contains a delay element to facilitate the generation of DQS signals. The DQS signal feeds the DQS bus that spans
the set of 18 PIOs. Figure 2-34 shows the assignment of DQS pins in each set of 18 PIOs.
TO
ONEG1
Note: Simplified version does not show CE and SET/RESET details.
From Routing
TD
DQ
D-Type
0
1
0
1
DQ
D-Type
/LATCH
0
1
ONEG0
DO
ECLK1
ECLK2
CLK1
Tristate Logic
Output Logic
To sysIO Buffer
(CLKA)
0
1
/LATCH
_:,-_: LATTICE 55555555555555 Hm l’fll‘l’l
2-36
Architecture
LatticeECP2/M Family Data Sheet
Top Edge
The PICs on the top edge are different from PIOs on the left, right and bottom edges. PIOs on this edge do not
have DDR registers or DQS signals.
The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Addi-
tional detail is provided in the Signal Descriptions table. The DQS signal from the bus is used to strobe the DDR
data from the memory into input register blocks. Interfaces on the left and right edges are designed for DDR mem-
ories that support 16 bits of data, whereas interfaces on the bottom are designed for memories that support 18 bits
of data.
Figure 2-33. DQS Input Routing for the Left and Right Edges of the Device
PIO B
PIO A
PIO B
PIO A
Assigned
DQS Pin
DQS Delay
sysIO
Buffer PADA "T"
PADB "C"
LVDS Pair
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
llllllllllllllllllllllllllllllllllllllllllll fl: LATTICE Illssumomzucrok
2-37
Architecture
LatticeECP2/M Family Data Sheet
Figure 2-34. DQS Input Routing for the Bottom Edge of the Device
DLL Calibrated DQS Delay Block
Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at
the input register. For most interfaces a PLL is used for this adjustment. However, in DDR memories the clock
(referred to as DQS) is not free-running so this approach cannot be used. The DQS Delay block provides the
required clock alignment for DDR memory interfaces.
The DQS signal (selected PIOs only, as shown in Figure 2-35) feeds from the PAD through a DQS delay element to
a dedicated DQS routing resource. The DQS signal also feeds polarity control logic, which controls the polarity of
the clock to the sync registers in the input register blocks. Figure 2-35 and Figure 2-36 show how the DQS transi-
tion signals are routed to the PIOs.
The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration
(6-bit bus) signals from two dedicated DLLs (DDR_DLL) on opposite sides of the device. Each DLL compensates
DQS delays in its half of the device as shown in Figure 2-35. The DLL loop is compensated for temperature, volt-
age and process variations by the system clock and feedback loop.
PIO B
PIO A
PIO B
PIO A
Assigned
DQS Pin
DQS Delay
sysIO
Buffer PADA " T"
PADB "C"
LVDS Pair
PA DA "T "
PADB "C"
LVDS Pair
PIO A
PIO B
PA DA "T "
PADB "C"
LVDS Pair
PIO A
PIO B
PA DA "T "
PADB "C"
LVDS Pair
PIO A
PIO B
PA DA "T "
PADB "C"
LVDS Pair
PIO A
PIO B
PA DA "T "
PADB "C"
LVDS Pair
PIO A
PIO B
PA DA "T "
PADB "C"
LVDS Pair
PIO B
PIO A PA DA "T "
PADB "C"
LVDS Pair
PIO A
PIO B
PA DA "T "
PADB "C"
LVDS Pair
LATTICE 55555555555555 II VI [k |
2-38
Architecture
LatticeECP2/M Family Data Sheet
Figure 2-35. Edge Clock, DLL Calibration and DQS Local Bus Distribution
I/O Bank 5
Note: Bank 8 is not shown.
I/O Bank 4
I/O
B
a
n
k
6
I/O
B
a
n
k
3
I/O
B
a
n
k
2
I/O Bank 0 I/O Bank 1
DDR_DLL
(Right)
I/O
B
a
n
k
7
DDR_DLL
(Left)
ECLK1
ECLK2
Delayed
DQS
Polarity Control
DQSXFER
DQS Delay
Control Bus
DQS Input
Spans 18 PIOs
Spans 16 PIOs
_:,-_: LATTICE 55555555555555
2-39
Architecture
LatticeECP2/M Family Data Sheet
Figure 2-36. DQS Local Bus
Polarity Control Logic
In a typical DDR Memory interface design, the phase relationship between the incoming delayed DQS strobe and
the internal system clock (during the READ cycle) is unknown.
The LatticeECP2/M family contains dedicated circuits to transfer data between these domains. To prevent set-up
and hold violations, at the domain transfer between DQS (delayed) and the system clock, a clock polarity selector
is used. This changes the edge on which the data is registered in the synchronizing registers in the input register
block. This requires evaluation at the start of each READ cycle for the correct clock polarity.
Prior to the READ operation in DDR memories, DQS is in tristate (pulled by termination). The DDR memory device
drives DQS low at the start of the preamble state. A dedicated circuit detects the first DQS rising edge after the pre-
amble state. This signal is used to control the polarity of the clock to the synchronizing registers.
sysIO
Buffer
DDR
Datain
PAD
DI
CLK1
CEI
PIO
sysIO
Buffer
GSR
DQS
To Sync
Reg.
DQS To DDR
Reg.
DQS
Strobe
PAD
PIO
DQSDEL
Polarity Control
Logic
DQS
Calibration bus
from DLL
DQSXFER
Output
Register Block
Input
Register Block
DQSXFER
DCNTL[6:0]
Polarity control
DQS
DI
DQSXFERDEL*
DQSXFER
DCNTL[6:0]
*DQSXFERDEL shifts ECLK1 by 90% and is not associated with a particular PIO.
DCNTL[6:0]
ECLK1
CLK1
ECLK2
ECLK1
_:,-_: LATTICE 55555555555555
2-40
Architecture
LatticeECP2/M Family Data Sheet
DQSXFER
LatticeECP2/M devices provide a DQSXFER signal to the output buffer to assist it in data transfer to DDR memo-
ries that require DQS strobe be shifted 90o. This shifted DQS strobe is generated by the DQSDEL block. The
DQSXFER signal runs the span of the data bus.
sysI/O Buffer
Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement the wide variety
of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.
sysI/O Buffer Banks
LatticeECP2/M devices have nine sysI/O buffer banks: eight banks for user I/Os arranged two per side. The ninth
sysI/O buffer bank (Bank 8) is located adjacent to Bank 3 and has dedicated/shared I/Os for configuration. When a
shared pin is not used for configuration it is available as a user I/O. Each bank is capable of supporting multiple I/O
standards. Each sysI/O bank has its own I/O supply voltage (VCCIO). In addition, each bank, except Bank 8, has
voltage references, VREF1 and VREF2, which allow it to be completely independent from the others. Bank 8 shares
two voltage references, VREF1 and VREF2, with Bank 3. Figure 2-37 shows the nine banks and their associated
supplies.
In LatticeECP2/M devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are
powered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold inputs
independent of VCCIO.
Each bank can support up to two separate VREF voltages, VREF1 and VREF2, that set the threshold for the refer-
enced input buffers. Some dedicated I/O pins in a bank can be configured to be a reference voltage supply pin.
Each I/O is individually configurable based on the bank’s supply and reference voltages.
LATTICE lsstoNnucTok
2-41
Architecture
LatticeECP2/M Family Data Sheet
Figure 2-37. LatticeECP2 Banks
VREF1(2)
GND
Bank 2
VCCIO2
VREF2(2)
VREF1(3)
GND
Bank 3
VCCIO3
VREF2(3)
VREF1(7)
GND
Bank 7
VCCIO7
VREF2(7)
VREF1(6)
GND
Bank 6
VCCIO6
VREF2(6)
Bank 5 Bank 4
V
REF1(0)
GND
Bank 0
V
CCIO0
VREF2(0)
VREF1(1)
GND
Bank 1
V
CCIO1
V
REF2(1)
GND
Bank 8
VCCIO8
LEFT
RIGHT
TOP
VREF1(5)
GND
V
CCIO5
VREF2(5)
V
REF1(4)
GND
V
CCIO4
VREF2(4)
BOTTOM
LATTICE lsstoNnucTok 4 \ \ \ \ 7,4 7‘ \ 4
2-42
Architecture
LatticeECP2/M Family Data Sheet
Figure 2-38. LatticeECP2M Banks
LatticeECP2/M devices contain two types of sysI/O buffer pairs.
1. Top (Bank 0 and Bank 1) sysI/O Buffer Pairs (Single-Ended Outputs Only)
The sysI/O buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of
single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be con-
figured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
2. Bottom (Bank 4 and Bank 5) sysI/O Buffer Pairs (Single-Ended Outputs Only)
The sysI/O buffer pairs in the bottom banks of the device consist of two single-ended output drivers and two
VREF1(5)
GND
V
CCIO5
VREF2(5)
V
REF1(4)
GND
V
CCIO4
VREF2(4)
V
REF1(0)
GND
V
CCIO0
VREF2(0)
VREF1(1)
GND
V
CCIO1
V
REF2(1)
VREF1(7)
GND
VCCIO7
VREF2(7)
VREF1(6)
GND
VCCIO6
VREF2(6)
VREF1(2)
GND
VCCIO2
VREF2(2)
VREF1(3)
GND
VCCIO3
VREF2(3)
GND
VCCIO8
RIGHT
Bank 2 Bank 3
Bank 7
Bank 6
Bank 5 Bank 4
Bank 0 Bank 1
Bank 8
BOTTOM
SERDES
Quad
SERDES
Quad
SERDES
Quad
SERDES
Quad
LEFT
TOP
_:,-_: LATTICE 55555555555555
2-43
Architecture
LatticeECP2/M Family Data Sheet
sets of single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also
be configured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
3. Left and Right (Banks 2, 3, 6 and 7) sysI/O Buffer Pairs (50% Differential and 100% Single-Ended Out-
puts)
The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two
sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. One of the ref-
erenced input buffers can also be configured as a differential input. In these banks the two pads in the pair are
described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O, and
the comp (complementary) pad is associated with the negative side of the differential I/O.
LVDS differential output drivers are available on 50% of the buffer pairs on the left and right banks.
4. Bank 8 sysI/O Buffer Pairs (Single-Ended Outputs, Only on Shared Pins When Not Used by Configura-
tion)
The sysI/O buffers in Bank 8 consist of single-ended output drivers and single-ended input buffers (both ratioed
and referenced). The referenced input buffer can also be configured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the
differential input buffer.
In LatticeECP2 devices, only the I/Os on the bottom banks have programmable PCI clamps. In LatticeECP2M
devices, the I/Os on the left and bottom banks have programmable PCI clamps.
Typical sysI/O I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when VCC, VCCIO8 and VCCAUX have reached satisfactory
levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to
ensure that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of
all the I/O banks that are critical to the application. For more information about controlling the output logic state with
valid input logic levels during power-up in LatticeECP2/M devices, see the list of additional technical documentation
at the end of this data sheet.
The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buf-
fers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended
that the I/O buffers be powered-up prior to the FPGA core fabric. VCCIO supplies should be powered-up before or
together with the VCC and VCCAUX supplies.
Prior to and throughout programming of the FPGA, the I/O of the device have a weak-pullup resistor to VCCIO on
the input buffer and the output buffer is tri-stated. A pullup to VCCIO is present on the input until the user programs
the input differently in the FPGA design. See the DC Electrical Characteristics table of this data sheet. The pullup
value will be between 20-30K ohms based on the VCCIO voltage supplied on the board. This pullup will also remain
active if the design does not use a particular I/O.
Supported sysI/O Standards
The LatticeECP2/M sysI/O buffer supports both single-ended and differential standards. Single-ended standards
can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS
1.2V, 1.5V, 1.8V, 2.5V and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individual configura-
tion options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open
drain. Other single-ended standards supported include SSTL and HSTL. Differential standards supported include
LVDS, MLVDS, BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-13 and 2-14 show the I/
_:_:_: LATTICE 55555555555555
2-44
Architecture
LatticeECP2/M Family Data Sheet
O standards (together with their supply and reference voltages) supported by LatticeECP2/M devices. For further
information about utilizing the sysI/O buffer to support a variety of standards please see the the list of additional
technical information at the end of this data sheet.
Table 2-13. Supported Input Standards
Input Standard VREF (Nom.) VCCIO1 (Nom.)
Single Ended Interfaces
LVT TL
LVC MOS 33 — —
LVC MOS 25 — —
LVC MOS 18 1. 8
LVC MOS 15 1. 5
LVC MOS 12 — —
PCI 33 3.3
HSTL18 Class I, II 0.9
HSTL15 Class I 0.75
SSTL3 Class I, II 1.5
SSTL2 Class I, II 1.25
SSTL18 Class I, II 0.9
Differential Interfaces
Differential SSTL18 Class I, II
Differential SSTL2 Class I, II
Differential SSTL3 Class I, II
Differential HSTL15 Class I
Differential HSTL18 Class I, II
LVDS, MLVDS, LVPECL, BLVDS, RSDS
1When not specified, VCCIO can be set anywhere in the valid operating range (page 3-1).
_:_:_: LATTICE 55555555555555
2-45
Architecture
LatticeECP2/M Family Data Sheet
Table 2-14. Supported Output Standards
Hot Socketing
LatticeECP2/M devices have been carefully designed to ensure predictable behavior during power-up and power-
down. During power-up and power-down sequences, the I/Os remain in tri-state until the power supply voltage is
high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified limits. This
allows for easy integration with the rest of the system. These capabilities make the LatticeECP2/M ideal for many
multiple power supply and hot-swap applications.
Output Standard Drive VCCIO (Nom.)
Single-ended Interfaces
LVTTL 4mA, 8mA, 12mA, 16mA, 20mA 3.3
LVCMOS33 4mA, 8mA, 12mA 16mA, 20mA 3.3
LVCMOS25 4mA, 8mA, 12mA, 16mA, 20mA 2.5
LVCMOS18 4mA, 8mA, 12mA, 16mA 1.8
LVCMOS15 4mA, 8mA 1.5
LVCMOS12 2mA, 6mA 1.2
LVCMOS33, Open Drain 4mA, 8mA, 12mA 16mA, 20mA
LVCMOS25, Open Drain 4mA, 8mA, 12mA 16mA, 20mA
LVCMOS18, Open Drain 4mA, 8mA, 12mA 16mA
LVCMOS15, Open Drain 4mA, 8mA
LVCMOS12, Open Drain 2mA, 6mA
PCI33 N/A 3.3
HSTL18 Class I, II N/A 1.8
HSTL15 Class I N/A 1.5
SSTL3 Class I, II N/A 3.3
SSTL2 Class I, II N/A 2.5
SSTL18 Class I, II N/A 1.8
Differential Interfaces
Differential SSTL3, Class I, II N/A 3.3
Differential SSTL2, Class I, II N/A 2.5
Differential SSTL18, Class I, II N/A 1.8
Differential HSTL18, Class I, II N/A 1.8
Differential HSTL15, Class I N/A 1.5
LVDS N/A 2.5
MLVDS1 N/A 2.5
BLVDS1N/A 2.5
LVPECL1N/A 3.3
RSDS1N/A 2.5
LVCMOS33D14mA, 8mA, 12mA, 16mA, 20mA 3.3
1. Emulated with external resistors. For more detail, please see information regarding additional technical documentation at
the end of this data sheet.
LATTICE JMDMM \_H_H_H_l |:| |:| |:| I—VW—H—W I—Vl—WW—W
2-46
Architecture
LatticeECP2/M Family Data Sheet
SERDES and PCS (Physical Coding Sublayer)
LatticeECP2M devices feature up to 16 channels of embedded SERDES arranged in quads at the corners of the
devices. Figure 2-39 shows the position of the quad blocks in relation to the PFU array for LatticeECP2M70 and
LatticeECP2M100 devices. Table 2-15 shows the location of Quads for all the devices.
Each quad contains four dedicated SERDES (Ch0 to Ch3) for high-speed, full-duplex serial data transfer. Each
quad also has a PCS block that interfaces to the SERDES channels and contains digital logic to support an array of
popular data protocols. PCS also contains logic to the interface to FPGA core.
Figure 2-39. SERDES Quads (LatticeECP2M70/LatticeECP2M100)
Table 2-15. Available SERDES Quads per LatticeECP2M Devices
SERDES Block
A differential receiver receives the serial encoded data stream, equalizes the signal, extracts the buried clock and
de-serializes the data-stream before passing the 8- or 10-bit data to the PCS logic. The transmit channel receives
the parallel (8- or 10-bit) encoded data, serializes the data and transmits the serial bit stream through the differen-
tial buffers. There is a single transmit clock per quad. Figure 2-40 shows a single channel SERDES and its inter-
face to the PCS logic. Each SERDES receiver channel provides a recovered clock to the PCS block and to the
FPGA core logic.
Device URC Quad ULC Quad LRC Quad LLC Quad
ECP2M20 Available — — —
ECP2M35 Available — — —
ECP2M50 Available — Available —
ECP2M70 Available Available Available Available
ECP2M100 Available Available Available Available
ULC SERDES Quad URC SERDES Quad
LRC SERDES QuadLLC SERDES Quad
Ch 3
PCS Digital Logic
Ch 2 Ch 1 Ch 0
Ch 3
PCS Digital Logic
Ch 2 Ch 1 Ch 0
Ch 3
PCS Digital Logic
Ch 2 Ch 1 Ch 0Ch 3
PCS Digital Logic
Ch 2 Ch 1 Ch 0
_::'_: LATTICE 55555555555555 r“ H WL‘PHWT: 54' a; 6? ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
2-47
Architecture
LatticeECP2/M Family Data Sheet
Each Transmit and Receive channel has its independent power supplies. The Output and Input buffers of each
channel also have their own independent power supplies. In addition, there are separate power supplies for PLL,
terminating resistor per quad.
Figure 2-40. Simplified Channel Block Diagram for SERDES and PCS
PCS
As shown in Figure 2-40, the PCS receives the parallel digital data from the deserializer receivers and adjusts the
polarity, detects, byte boundary, decodes (8b/10b) and provides Clock Tolerance Compensation (CTC) FIFO for
changing the clock domain from receiver clock to the FPGA Clock.
For the transmit channel, the PCS block receives the parallel data from the FPGA core, encodes it with 8b/10b,
adjusts the polarity and passes the 8/10 bit data to the transmit SERDES channel.
The PCS also provides bypass modes that allow a direct 8-bit or 10-bit interface from the SERDES to the FPGA
logic. The PCS interface to FPGA can also be programmed to run at 1/2 speed for a 16-bit or 20-bit interface to the
FPGA logic.
SCI (SERDES Client Interface) Bus
The SERDES Client Interface (SCI) is a soft IP interface that allow the SERDES/PCS Quad block to be controlled
by registers as opposed to the configuration memory cells. It is a simple register configuration interface.
The Diamond design tools support all modes of the PCS. Most modes are dedicated to applications associated
with a specific industry standard data protocol. Other more general purpose modes allow users to define their own
operation. With Diamond, the user can define the mode for each quad in a design.
Popular standards such as 10Gb Ethernet and x4 PCI-Express and 4x Serial RapidIO can be implemented using
IP (provided by Lattice), a single quad (Four SERDES channels and PCS) and some additional logic from the core.
For further information about SERDES, please see the list of additional technical documentation at the end of this
data sheet.
Deserializer
1:8/1:10
Polarity
Adjust
Equalizer
Byte Boundary
Detect, 8b/10b
Decoder
CTC
FIFO
Down
Sample
FIFO
Up
Sample
FIFO
8b/10b
Encoder
Polarity
Adjust
Serializer
TX PLL FPGA Transmit Clock
Recovered Clock
RX REFCLK
FPGA Receive Clock
To FPGA Core
Transmit
Receiver
8/10 bits or
16/20 bits
Transmit Data
Elastic Buffer
Read Clock
16/20 bits
Receive Data
From Transmit PLL
(In Common Block)
SERDES (Analog)PCS (Digital)
8:1/10:1
TX REFCLK
LATTICE lsstoNnucrap LamceECPZ/M sysCONFIG Usage Guide Minimizing Sysiem Interrugiion During Configuraiion Using TransFR Technology
2-48
Architecture
LatticeECP2/M Family Data Sheet
IEEE 1149.1-Compliant Boundary Scan Testability
All LatticeECP2/M devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test
Access Port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a
serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to
be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test
access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage
VCCJ and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.
For more details on boundary scan test, please see information regarding additional technical documentation at
the end of this data sheet.
Device Configuration
All LatticeECP2/M devices contain two ports that can be used for device configuration. The Test Access Port (TAP),
which supports bit-wide configuration, and the sysCONFIG port, support both byte-wide and serial configuration,
including the standard SPI Flash interface. The TAP supports both the IEEE Standard 1149.1 Boundary Scan
specification and the IEEE Standard 1532 In- System Configuration specification. The sysCONFIG port is a 20-pin
interface with six I/Os used as dedicated pins with the remainder used as dual-use pins. See TN1108,
LatticeECP2/M sysCONFIG Usage Guide for more information about using the dual-use pins as general purpose I/
Os.
On power-up, the FPGA SRAM is ready to be configured using the selected sysCONFIG port. Once a configuration
port is selected, it will remain active throughout that configuration cycle. The IEEE 1149.1 port can be activated any
time after power-up by sending the appropriate command through the TAP port.
Enhanced Configuration Option
LatticeECP2/M devices have enhanced configuration features such as: decryption support, TransFR™ I/O and
dual boot image support.
1. Decryption Support
LatticeECP2/M devices provide on-chip, One Time Programmable (OTP) non-volatile key storage to support
decryption of a 128-bit AES encrypted bitstream, securing designs and deterring design piracy.
2. TransFR (Transparent Field Reconfiguration)
TransFR I/O (TFR) is a unique Lattice technology that allows users to update their logic in the field without
interrupting system operation using a single ispVM® command. TransFR I/O allows I/O states to be frozen dur-
ing device configuration. This allows the device to be field updated with a minimum of system disruption and
downtime. See TN1087, Minimizing System Interruption During Configuration Using TransFR Technology, for
details.
3. Dual Boot Image Support
Dual boot images are supported for applications requiring reliable remote updates of configuration data for the
system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded
remotely and stored in a separate location in the configuration storage device. Any time after the update the
LatticeECP2/M can be re-booted from this new configuration file. If there is a problem, such as corrupt data
during download or incorrect version number with this new boot image, the LatticeECP2/M device can revert
back to the original backup configuration and try again. This all can be done without power cycling the system.
For more information about device configuration, please see the list of additional technical documentation at the
end of this data sheet.
Soft Error Detect (SED) Support
LatticeECP2/M devices have dedicated logic to perform CRC checks. During configuration, the configuration data
bitstream can be checked with the CRC logic block. In addition, the LatticeECP2 device can also be programmed
_:,-_: LATTICE 55555555555555
2-49
Architecture
LatticeECP2/M Family Data Sheet
for checking soft errors (SED) in SRAM. SED can be run on a programmed device when the user logic is not active.
If a soft error occurs, during user mode (normal operation) the device can be programmed to either reload from a
known good boot image or generate an error signal.
For further information about Soft Error Detect (SED) support, please see the list of additional technical documen-
tation at the end of this data sheet.
External Resistor
LatticeECP2/M devices require a single external, 10K ohm ±1% value between the XRES pin and ground. Device
configuration will not be completed if this resistor is missing. There is no boundary scan register on the external
resistor pad.
On-Chip Oscillator
Every LatticeECP2/M device has an internal CMOS oscillator which is used to derive a Master Clock for configura-
tion. The oscillator and the Master Clock run continuously and are available to user logic after configuration is com-
pleted. The software default value of the Master Clock is 2.5MHz. Table 2-16 lists all the available Master
Configuration Clock frequencies for normal non-encrypted mode and encrypted mode. When a different Master
Clock is selected during the design process, the following sequence takes place:
1. Device powers up with a Master Clock frequency of 3.1MHz.
2. During configuration, users select a different master clock frequency.
3. The Master Clock frequency changes to the selected frequency once the clock configuration bits are received.
4. If the user does not select a master clock frequency, then the configuration bitstream defaults to the Master
Clock frequency of 2.5MHz.
This internal CMOS oscillator is available to the user by routing it as an input clock to the clock tree. For further
information about the use of this oscillator for configuration or user mode, please see the list of additional technical
documentation at the end of this data sheet.
Table 2-16. Selectable Master Clock (CCLK) Frequencies During Configuration
Density Shifting
The LatticeECP2/M family is designed to ensure that different density devices in the same family and in the same
package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design
migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower uti-
lization design targeted for a high-density device to a lower density device. However, the exact details of the final
resource utilization will impact the likelihood of success in each case. Design migration between LatticeECP2 and
LatticeECP2M families is not possible. For specific requirements relating to sysCONFIG pins of the ECP2M50,
M70 and M100, see the Logic Signal Connections tables.
Non-Encrypted Mode CCLK (MHz) Encrypted Mode CCLK (MHz)
2.5113.0 45.0 2.51
4.3 15.0 55.0 5.4
5.4 20.0 60.0 10.0
6.9 26.0
8.1 30.0
9.2 34.0
10.0 41.0 130.0
1. Software default frequency.
' LATTICE SEMICONDUCTOR. Therma‘ Management
www.latticesemi.com 3-1 DS1006 DC and Switching_02.4
September 2013 Data Sheet DS1006
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Recommended Operating Conditions7
Absolute Maximum Ratings1, 2, 3
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V
Supply Voltage VCCAUX . . . . . . . . . . . . . . . . -0.5 to 3.75V
Supply Voltage VCCJ . . . . . . . . . . . . . . . . . . -0.5 to 3.75V
Output Supply Voltage VCCIO . . . . . . . . . . . -0.5 to 3.75V
Input or I/O Tristate Voltage Applied4. . . . . . -0.5 to 3.75V
Storage Temperature (Ambient) . . . . . . . . . -65 to 150°C
Junction Temperature (Tj) . . . . . . . . . . . . . . . . . . +125°C
4. Overshoot and undershoot of -2V to (VIHMAX + 2) volts is permitted for a duration of <20ns.
Symbol Parameter Min. Max. Units
VCC1, 4, 5 Core Supply Voltage 1.14 1.26 V
VCCAUX1, 3, 4, 5 Auxiliary Supply Voltage 3.135 3.465 V
VCCPLL PLL Supply Voltage 1.14 1.26 V
VCCIO1, 2, 4 I/O Driver Supply Voltage 1.14 3.465 V
VCCJ1Supply Voltage for IEEE 1149.1 Test Access Port 1.14 3.465 V
tJCOM Junction Temperature, Commercial Operation 0 85 °C
tJIND Junction Temperature, Industrial Operation -40 100 °C
SERDES External Power Supply (For LatticeECP2M Family Only)
VCCIB
Input Buffer Power Supply (1.2V) 1.14 1.26 V
Input Buffer Power Supply (1.5V) 1.425 1.575 V
VCCOB
Output Buffer Power Supply (1.2V) 1.14 1.26 V
Output Buffer Power Supply (1.5V) 1.425 1.575 V
VCCAUX33 Termination Resistor Switching Power Supply 3.135 3.465 V
VCCRX6Receive Power Supply 1.14 1.26 V
VCCTX6Transmit Power Supply 1.14 1.26 V
LatticeECP2/M Family Data Sheet
DC and Switching Characteristics
LATTICE sstoNnucram E‘ecmca‘ Recommendahons for Lamce SERDES m m LaniceECPz/M Producx Family Qua‘ilicalion Summary
3-2
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
ESD Performance
Please refer to LatticeECP2/M Product Family Qualification Summary for complete qualification data, including
ESD performance.
VCCP6PLL and Reference Clock Buffer Power 1.14 1.26 V
1. If VCCIO or VCCJ is set to 1.2V, they must be connected to the same power supply as VCC. If VCCIO or VCCJ is set to 3.3V, they must be con-
nected to the same power supply as VCCAUX. VCCPLL must be connected to the same power supply as VCC through careful filtering and
decoupling.
2. See recommended voltages by I/O standard in subsequent table.
3. VCCAUX ramp rate must not exceed 30mV/µs during power-up when transitioning between 0V and 3.3V.
4. For proper power-up configuration, users must ensure that the configuration control signals such as the CFGx, INITN, PROGRAMN and
DONE pins are driven to the proper logic levels when the device powers up. The device power-up is triggered by the last of VCC, VCCAUX or
VCCIO8 supplies that reaches its minimum valid levels. Alternatively, if the configuration control signals are pulled up by VCCIO8, the VCCIO8
(configuration I/O bank) voltage must be powered up prior to or at the same time as the last of VCC or VCCAUX reaches its minimum lev-
els.
5. For power-up, VCC must reach its valid minimum value before powering up VCCAUX (LatticeECP2/M “S” version devices only).
6. VCCRX,VCCTX and VCCP must be tied together in each quad and all quads need to be powered up.
7. For more power supply design recommendations, refer to TN1114 Electrical Recommendations for Lattice SERDES.
Hot Socketing Specifications1, 2, 3, 4
Symbol Parameter Condition Min. Typ. Max. Units
IDK Input or I/O leakage current 0 VIN VIH (MAX.) +/-1000 µA
IHDIN5
SERDES average input current when
device is powered down and inputs
are driven
—— 4mA
1. VCC, VCCAUX and VCCIO should rise/fall monotonically. VCC and VCCPLL must be connected to the same power supply (applies to ECP2-6,
ECP2-12 and ECP2-20 only).
2. 0 VCC VCC (MAX), 0 VCCIO VCCIO (MAX) or 0 VCCAUX VCCAUX (MAX).
3. IDK is additive to IPU, IPW or IBH.
4. LVCMOS and LVTTL only.
5. Assumes that the device is powered down with all supplies grounded, both P and N inputs driven by a CML driver with maximum allowed
VCCIB of 1.575V, 8b10b data and internal AC coupling.
Symbol Parameter Min. Max. Units
3-3
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol Parameter Condition Min. Typ. Max. Units
IIL, IIH1, 2 Input or I/O Low Leakage 0 VIN (VCCIO - 0.2V) 10 µA
IIH1, 3 Input or I/O High Leakage (VCCIO - 0.2V) < VIN 3.6V 150 µA
IPU I/O Active Pull-up Current 0 VIN 0.7 VCCIO -30 -210 µA
IPD I/O Active Pull-down Current VIL (MAX) VIN VIH (MAX) 30 210 µA
IBHLS Bus Hold Low Sustaining Current VIN = VIL (MAX) 30 µA
IBHHS Bus Hold High Sustaining Current VIN = 0.7 VCCIO -30 µA
IBHLO Bus Hold Low Overdrive Current 0 VIN VCCIO ——210µA
IBHHO Bus Hold High Overdrive Current 0 VIN VCCIO ——-210µA
VBHT Bus Hold Trip Points 0 VIN VIH (MAX) VIL (MAX) VIH (MIN) V
C14I/O Capacitance VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,
VCC = 1.2V, VIO = 0 to VIH (MAX)
—58pf
C24 Dedicated Input Capacitance VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,
VCC = 1.2V, VIO = 0 to VIH (MAX)
—56pf
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured
with the output driver active. Bus maintenance circuits are disabled.
2. When used as VREF
, maximum leakage = 25uA
3. Applicable to general purpose I/Os in top and bottom banks.
4. TA 25oC, f = 1.0MHz.
_:_:_: LATTICE 55555555555555
3-4
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
LatticeECP2 Supply Current (Standby)1, 2, 3, 4
Over Recommended Operating Conditions
Symbol Parameter Device Typ.5Units
ICC Core Power Supply Current
ECP2-6 10 mA
ECP2-12 20 mA
ECP2-20 30 mA
ECP2-35 50 mA
ECP2-50 70 mA
ECP2-70 100 mA
ICCAUX Auxiliary Power Supply Current
ECP2-6 24 mA
ECP2-12 24 mA
ECP2-20 24 mA
ECP2-35 24 mA
ECP2-50 24 mA
ECP2-70 24 mA
ICCGPLL GPLL Power Supply Current (per GPLL) ECP2-35, -50, -70 Only 0.5 mA
ICCSPLL GPLL Power Supply Current (per SPLL) ECP2-35, -50, -70 Only 0.5 mA
ICCIO Bank Power Supply Current (Per Bank)
ECP2-6 2 mA
ECP2-12 2 mA
ECP2-20 2 mA
ECP2-35 2 mA
ECP2-50 2 mA
ECP2-70 2 mA
ICCJ VCCJ Power Supply Current All Devices 3 mA
1. For further information about supply current, please see the list of additional technical documentation at the end of this data sheet.
2. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND.
3. Frequency 0MHz.
4. Pattern represents a “blank” configuration data file.
5. TJ = 25°C, power supplies at normal voltage.
_:_:_: LATTICE 55555555555555
3-5
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
LatticeECP2M Supply Current (Standby)1, 2, 3, 4
Over Recommended Operating Conditions
Symbol Parameter Device Typ.5Units
ICC Core Power Supply Current
ECP2M20 25 mA
ECP2M35 50 mA
ECP2M50 85 mA
ECP2M70 100 mA
ECP2M100 100 mA
ICCAUX Auxiliary Power Supply Current
ECP2M20 24 mA
ECP2M35 24 mA
ECP2M50 24 mA
ECP2M70 24 mA
ECP2M100 24 mA
ICCGPLL GPLL Power Supply Current (per GPLL) All Devices 0.5 mA
ICCSPLL GPLL Power Supply Current (per SPLL) All Devices 0.5 mA
ICCIO Bank Power Supply Current (Per Bank)
ECP2M20 2 mA
ECP2M35 2 mA
ECP2M50 2 mA
ECP2M70 2 mA
ECP2M100 2 mA
ICCJ VCCJ Power Supply Current All Devices 3 mA
1. For further information about supply current, please see the list of additional technical documentation at the end of this data sheet.
2. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND.
3. Frequency 0MHz.
4. Pattern represents a “blank” configuration data file.
5. TJ = 25°C, power supplies at normal voltage.
_:_:_: LATTICE 55555555555555
3-6
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
LatticeECP2 Initialization Supply Current1, 2, 3, 4
Over Recommended Operating Conditions
Symbol Parameter Device Typ.5, 6, 7 Units
ICC Core Power Supply Current
ECP2-6 34 mA
ECP2-12 54 mA
ECP2-20 82 mA
ECP2-35 135 mA
ECP2-50 187 mA
ECP2-70 267 mA
ICCAUX Auxiliary Power Supply Current
ECP2-6 30 mA
ECP2-12 30 mA
ECP2-20 30 mA
ECP2-35 30 mA
ECP2-50 30 mA
ECP2-70 30 mA
ICCGPLL GPLL Power Supply Current (per GPLL) ECP2-35, -50, -70 Only 0.5 mA
ICCSPLL SPLL Power Supply Current (per SPLL) ECP2-35, -50, -70 Only 0.5 mA
ICCIO Bank Power Supply Current (per Bank) All Devices 3 mA
ICCJ VCCJ Power Supply Current All Devices 4 mA
1. Until DONE signal is active.
2. For further information about supply current, please see the list of additional technical documentation at the end of this data sheet.
3. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND.
4. Frequency 0MHz.
5. TJ = 25oC, power supplies at nominal voltage.
6. A specific configuration pattern is used that scales with the size of the device; consists of 75% PFU utilization, 50% EBR, and 25% I/O con-
figuration.
7. Values shown in this column are the typical average DC current during configuration. Use the Power Calculator tool to find the peak startup
current.
_:_:_: LATTICE 55555555555555
3-7
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
LatticeECP2M Initialization Supply Current1, 2, 3, 4
Over Recommended Operating Conditions
Symbol Parameter Device Typ.5, 6, 7 Units
ICC Core Power Supply Current
ECP2M20 41 mA
ECP2M35 107 mA
ECP2M50 169 mA
ECP2M70 254 mA
ECP2M100 378 mA
ICCAUX Auxiliary Power Supply Current
ECP2M20 30 mA
ECP2M35 30 mA
ECP2M50 30 mA
ECP2M70 30 mA
ECP2M100 30 mA
ICCGPLL GPLL Power Supply Current (per GPLL) All Devices 0.5 mA
ICCSPLL SPLL Power Supply Current (per SPLL) All Devices 0.5 mA
ICCIO Bank Power Supply Current (per Bank) All Devices 3 mA
ICCJ VCCJ Power Supply Current All Devices 4 mA
1. Until DONE signal is active.
2. For further information about supply current, please see the list of additional technical documentation at the end of this data sheet.
3. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND.
4. Frequency 0MHz.
5. TJ = 25oC, power supplies at nominal voltage.
6. A specific configuration pattern is used that scales with the size of the device; consists of 75% PFU utilization, 50% EBR, and 25% I/O con-
figuration.
7. Values shown in this column are the typical average DC current during configuration. Use the Power Calculator tool to find the peak startup
current.
_:_:_: LATTICE 55555555555555
3-8
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
SERDES Power Supply Requirements (LatticeECP2M Family Only)1
Over Recommended Operating Conditions
SERDES Power (LatticeECP2M Family Only)
Table 3-1 presents the SERDES power for one channel.
Table 3-1. SERDES Power1
Symbol Description Typ.2Units
Standby (Power Down)
ICCTX-SB VCCTX current (per channel) 10 µA
ICCRX-SB VCCRX current (per channel) 75 µA
ICCIB-SB Input buffer current (per channel) 0 µA
ICCOB-SB Output buffer current (per channel) 0 µA
ICCP-SB SERDES PLL current (per quad) 30 µA
ICCAX33-SB SERDES termination current (per quad) 10 µA
Operating (Data Rate = 3.125 Gbps)
ICCTX-OP VCCTX current (per channel) 19 mA
ICCRX-OP VCCRX current (per channel) 34 mA
ICCIB-OP Input buffer current (per channel) 4 mA
ICCOB-OP Output buffer current (per channel) 13 mA
ICCP-OP SERDES PLL current (per quad) 26 mA
ICCAX33-OP SERDES termination current (per quad) 0.01 mA
1. Equalization enabled, pre-emphasis disabled.
2. TJ = 25°C, power supplies at nominal voltage.
Symbol Description Typ.2Units
PS-1CH-31 SERDES power (one channel @ 3.125 Gbps) 90 mW
PS-1CH-25 SERDES power (one channel @ 2.5 Gbps) 87 mW
PS-1CH-12 SERDES power (one channel @ 1.25 Gbps) 86 mW
PS-1CH-02 SERDES power (one channel @ 250 Mbps) 76 mW
1. One quarter of the total quad power (includes contribution from common circuits, all channels in the quad operating, pre-emphasis dis-
abled, equalization enabled).
2. Typical values measured at 25oC and 1.2V.
_:_:_: LATTICE 55555555555555
3-9
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
sysI/O Recommended Operating Conditions
Standard
VCCIO VREF (V)
Min. Typ. Max. Min. Typ. Max.
LVC MOS 3. 32 3.135 3.3 3.465
LVC MOS 2. 52 2.375 2.5 2.625
LVCMOS 1.8 1.71 1.8 1.89
LVCMOS 1.5 1.425 1.5 1.575
LVC MOS 1. 22 1.14 1.2 1.26
LVT TL2 3.135 3.3 3.465
PCI 3.135 3.3 3.465 — — —
SSTL182 Class I, II 1.71 1.8 1.89 0.833 0.9 0.969
SSTL22 Class I, II 2.375 2.5 2.625 1.15 1.25 1.35
SSTL32 Class I, II 3.135 3.3 3.465 1.3 1.5 1.7
HSTL2 15 Class I 1.425 1.5 1.575 0.68 0.75 0.9
HSTL2 18 Class I, II 1.71 1.8 1.89 0.816 0.9 1.08
LVD S2 2.375 2.5 2.625
MLVDS251 2.375 2.5 2.625 — — —
LVPECL331, 2 3.135 3.3 3.465 — — —
BLVDS251, 2 2.375 2.5 2.625 — — —
RSDS1, 2 2.375 2.5 2.625 — — —
SSTL18D_I2, II21.71 1.8 1.89 — — —
SSTL25D_ I2, II22.375 2.5 2.625 — — —
SSTL33D_ I2, II23.135 3.3 3.465 — — —
HSTL15D_ I21.425 1.5 1.575 — — —
HSTL18D_ I2, II21.71 1.8 1.89 — — —
1. Inputs on chip. Outputs are implemented with the addition of external resistors.
2. Input on this standard does not depend on the value of VCCIO.
_:_:_: LATTICE 55555555555555
3-10
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
sysI/O Single-Ended DC Electrical Characteristics
Input/Output
Standard
VIL VIH VOL
Max. (V)
VOH
Min. (V) IOL1 (mA) IOH1 (mA)Min. (V) Max. (V) Min. (V) Max. (V)
LVCMOS 3.3 -0.3 0.8 2.0 3.6 0.4 VCCIO - 0.4 20, 16,
12, 8, 4
-20, -16,
-12, -8, -4
0.2 VCCIO - 0.2 0.1 -0.1
LVTTL -0.3 0.8 2.0 3.6 0.4 VCCIO - 0.4 20, 16,
12, 8, 4
-20, -16,
-12, -8, -4
0.2 VCCIO - 0.2 0.1 -0.1
LVCMOS 2.5 -0.3 0.7 1.7 3.6 0.4 VCCIO - 0.4 20, 16,
12, 8, 4
-20, -16,
-12, -8, -4
0.2 VCCIO - 0.2 0.1 -0.1
LVCMOS 1.8 -0.3 0.35 VCCIO 0.65 VCCIO 3.6 0.4 VCCIO - 0.4 16, 12,
8, 4
-16, -12,
-8, -4
0.2 VCCIO - 0.2 0.1 -0.1
LVCMOS 1.5 -0.3 0.35 VCCIO 0.65 VCCIO 3.6 0.4 VCCIO - 0.4 8, 4 -8, -4
0.2 VCCIO - 0.2 0.1 -0.1
LVCMOS 1.2 -0.3 0.35 VCC 0.65 VCC 3.6 0.4 VCCIO - 0.4 6, 2 -6, -2
0.2 VCCIO - 0.2 0.1 -0.1
PCI -0.3 0.3 VCCIO 0.5 VCCIO 3.6 0.1 VCCIO 0.9 VCCIO 1.5 -0.5
SSTL3 Class I -0.3 VREF - 0.2 VREF + 0.2 3.6 0.7 VCCIO - 1.1 8 -8
SSTL3 Class II -0.3 VREF - 0.2 VREF + 0.2 3.6 0.5 VCCIO - 0.9 16 -16
SSTL2 Class I -0.3 VREF - 0.18 VREF + 0.18 3.6 0.54 VCCIO - 0.62 7.6 -7.6
12 -12
SSTL2 Class II -0.3 VREF - 0.18 VREF + 0.18 3.6 0.35 VCCIO - 0.43 15.2 -15.2
20 -20
SSTL18 Class I -0.3 VREF - 0.125 VREF + 0.125 3.6 0.4 VCCIO - 0.4 6.7 -6.7
SSTL18 Class II -0.3 VREF - 0.125 VREF + 0.125 3.6 0.28 VCCIO - 0.28 8-8
11 -11
HSTL Class I -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCIO - 0.4 4-4
8-8
HSTL18 Class I -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCIO - 0.4 8-8
12 -12
HSTL18 Class II -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCIO - 0.4 16 -16
1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as
shown in the logic signal connections table shall not exceed n * 8mA, where n is the number of I/Os between bank GND connections or
between the last GND in a bank and the end of a bank.
_:_:_: LATTICE 55555555555555
3-11
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
sysI/O Differential Electrical Characteristics
LVD S
Over Recommended Operating Conditions
Differential HSTL and SSTL
Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow-
able single-ended output classes (class I and class II) are supported in this mode.
For further information about LVPECL, RSDS, MLVDS, BLVDS and other differential interfaces please see the list
of additional technical information at the end of this data sheet.
Parameter Description Test Conditions Min. Typ. Max. Units
VINP
, VINM Input Voltage 0 2.4 V
VCM Input Common Mode Voltage Half the Sum of the Two Inputs 0.05 2.35 V
VTHD Differential Input Threshold Difference Between the Two Inputs +/-100 mV
IIN Input Current Power On or Power Off +/-10 µA
VOH Output High Voltage for VOP or VOM RT = 100 Ohm 1.38 1.60 V
VOL Output Low Voltage for VOP or VOM RT = 100 Ohm 0.9V 1.03 V
VOD Output Voltage Differential (VOP - VOM), RT = 100 Ohm 250 350 450 mV
ýVOD Change in VOD Between High and
Low ——50mV
VOS Output Voltage Offset (VOP + VOM)/2, RT = 100 Ohm 1.125 1.20 1.375 V
ýVOS Change in VOS Between H and L 50 mV
ISA Output Short Circuit Current VOD = 0V Driver Outputs Shorted to
Ground ——24mA
ISAB Output Short Circuit Current VOD = 0V Driver Outputs Shorted to
Each Other ——12mA
!—AZ'7.,'!CE
3-12
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
LVDS25E
The top and bottom sides of LatticeECP2/M devices support LVDS outputs via emulated complementary LVCMOS
outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one
possible solution for point-to-point signals.
Figure 3-1. LVDS25E Output Termination Example
Table 3-2. LVDS25E DC Conditions
LVCMOS33D
All I/O banks support emulated differential I/O using the LVCMOS33D I/O type. This option, along with the external
resistor network, provides the system designer the flexibility to place differential outputs on an I/O bank with 3.3V
VCCIO. The default drive current for LVCMOS33D output is 12mA with the option to change the device strength to
4mA, 8mA, 16mA or 20mA. Follow the LVCMOS33 specifications for the DC characteristics of the LVCMOS33D.
Parameter Description Typical Units
VCCIO Output Driver Supply (+/-5%) 2.50 V
ZOUT Driver Impedance 20
RSDriver Series Resistor (+/-1%) 158
RPDriver Parallel Resistor (+/-1%) 140
RTReceiver Termination (+/-1%) 100
VOH Output High Voltage 1.43 V
VOL Output Low Voltage 1.07 V
VOD Output Differential Voltage 0.35 V
VCM Output Common Mode Voltage 1.25 V
ZBACK Back Impedance 100.5
IDC DC Output Current 6.03 mA
+
-
RS=158 ohms
(±1%)
RS=158 ohms
(±1%)
RP = 140 ohms
(±1%)
RT = 100 ohms
(±1%)
OFF-chip
Transmission line, Zo = 100 ohm differential
VCCIO = 2.5V (±5%)
8 mA
VCCIO = 2.5V (±5%)
ON-chip OFF-chip ON-chip
8 mA
_::'_: LATTICE 55555555555555 45$} 90$}
3-13
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
BLVDS
The LatticeECP2/M devices support the BLVDS standard. This standard is emulated using complementary LVC-
MOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use
when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is
one possible solution for bi-directional multi-point differential signals.
Figure 3-2. BLVDS Multi-point Output Example
Table 3-3. BLVDS DC Conditions1
Over Recommended Operating Conditions
Parameter Description
Typical
UnitsZo = 45Zo = 90
VCCIO Output Driver Supply (+/- 5%) 2.50 2.50 V
ZOUT Driver Impedance 10.00 10.00
RSDriver Series Resistor (+/- 1%) 90.00 90.00
RTL Driver Parallel Resistor (+/- 1%) 45.00 90.00
RTR Receiver Termination (+/- 1%) 45.00 90.00
VOH Output High Voltage 1.38 1.48 V
VOL Output Low Voltage 1.12 1.02 V
VOD Output Differential Voltage 0.25 0.46 V
VCM Output Common Mode Voltage 1.25 1.25 V
IDC DC Output Current 11.24 10.20 mA
1. For input buffer, see LVDS table.
Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential
2.5V
RTL RTR
RS = 90 ohms
RS = 90 ohms RS =
90 ohms
RS =
90 ohms RS =
90 ohms
RS =
90 ohms
RS =
90 ohms
RS =
90 ohms
45-90
ohms
45-90
ohms
2.5V
2.5V
2.5V 2.5V 2.5V 2.5V
2.5V
+
-
. . .
+
-
. . .
+
-
+
-
16mA
16mA
16mA 16mA 16mA 16mA
16mA
16mA
!—AZ'7.,'!CE
3-14
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
LVPECL
The LatticeECP2/M devices support the differential LVPECL standard. This standard is emulated using comple-
mentary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input stan-
dard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for
point-to-point signals.
Figure 3-3. Differential LVPECL
Table 3-4. LVPECL DC Conditions1
Over Recommended Operating Conditions
Parameter Description Typical Units
VCCIO Output Driver Supply (+/-5%) 3.30 V
ZOUT Driver Impedance 10
RSDriver Series Resistor (+/-1%) 93
RPDriver Parallel Resistor (+/-1%) 196
RTReceiver Termination (+/-1%) 100
VOH Output High Voltage 2.05 V
VOL Output Low Voltage 1.25 V
VOD Output Differential Voltage 0.80 V
VCM Output Common Mode Voltage 1.65 V
ZBACK Back Impedance 100.5
IDC DC Output Current 12.11 mA
1. For input buffer, see LVDS table.
Transmission line,
Zo = 100 ohm differential
Off-chipOn-chip
VCCIO = 3.3V
(+/-5%)
VCCIO = 3.3V
(+/-5%)
RP = 196 ohms
(+/-1%) RT = 100 ohms
(+/-1%)
RS = 93.1 ohms
(+/-1%)
RS = 93.1 ohms
(+/-1%)
16mA
16mA
+
-
Off-chip On-chip
!—AZ'7.,'!CE
3-15
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
RSDS
The LatticeECP2/M devices support differential RSDS standard. This standard is emulated using complementary
LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup-
ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS
standard implementation. Resistor values in Figure 3-4 are industry standard values for 1% resistors.
Figure 3-4. RSDS (Reduced Swing Differential Signaling)
Table 3-5. RSDS DC Conditions1
Over Recommended Operating Conditions
Parameter Description Typical Units
VCCIO Output Driver Supply (+/-5%) 2.50 V
ZOUT Driver Impedance 20
RSDriver Series Resistor (+/-1%) 294
RPDriver Parallel Resistor (+/-1%) 121
RTReceiver Termination (+/-1%) 100
VOH Output High Voltage 1.35 V
VOL Output Low Voltage 1.15 V
VOD Output Differential Voltage 0.20 V
VCM Output Common Mode Voltage 1.25 V
ZBACK Back Impedance 101.5
IDC DC Output Current 3.66 mA
1. For input buffer, see LVDS table.
R
S
= 294 ohms
(+/-1%)
R
S
= 294 ohms
(+/-1%)
R
P
= 121 ohms
(+/-1%)
R
T
= 100 ohms
(+/-1%)
On-chip On-chip
8mA
8mA
VCCIO = 2.5V
(+/-5%)
VCCIO = 2.5V
(+/-5%)
Transmission line,
Zo = 100 ohm differential
+
-
Off-chipOff-chip
:':'.:!-AZ'Z'!CE 15$? fiéfif
3-16
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
MLVDS
The LatticeECP2/M devices support the differential MLVDS standard. This standard is emulated using complemen-
tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is
supported by the LVDS differential input buffer. The scheme shown in Figure 3-5 is one possible solution for
MLVDS standard implementation. Resistor values in Figure 3-5 are industry standard values for 1% resistors.
Figure 3-5. MLVDS (Multipoint Low Voltage Differential Signaling)
Table 3-6. MLVDS DC Conditions1
For further information about LVPECL, RSDS, MLVDS, BLVDS and other differential interfaces please see the list
of additional technical information at the end of this data sheet.
Parameter Description
Typical
UnitsZo=50Zo=70
VCCIO Output Driver Supply (+/-5%) 2.50 2.50 V
ZOUT Driver Impedance 10.00 10.00
RSDriver Series Resistor (+/-1%) 35.00 35.00
RTL Driver Parallel Resistor (+/-1%) 50.00 70.00
RTR Receiver Termination (+/-1%) 50.00 70.00
VOH Output High Voltage 1.52 1.60 V
VOL Output Low Voltage 0.98 0.90 V
VOD Output Differential Voltage 0.54 0.70 V
VCM Output Common Mode Voltage 1.25 1.25 V
IDC DC Output Current 21.74 20.00 mA
1. For input buffer, see LVDS table.
16mA
2.5V
+
-
2.5V
2.5V
+
-
2.5V
2.5V
+
-
Am61
Heavily loaded backplace, effective Zo~50 to 70 ohms differential
50 to 70 ohms +/-1%
RS =
35ohms
RS =
35ohms
RS =
35ohms
RS =
35ohms
RS =
35ohms
RS =
35ohms
RS =
35ohms
RTR
RTL
16mA
2.5V
Am61
2.5V
+
-
Am61
2.5V 2.5V
RS =
50 to 70 ohms +/-1%
35ohms
Am61
16mA
+
-
16mA
OE
OE
OE OE OE OE
OE
OE
_:_:_: LATTICE 55555555555555
3-17
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Typical Building Block Function Performance1
Pin-to-Pin Performance (LVCMOS25 12mA Drive)
Function -7 Timing Units
Basic Functions
16-bit Decoder 3.8 ns
32-bit Decoder 4.5 ns
64-bit Decoder 5.0 ns
4:1 MUX 3.2 ns
8:1 MUX 3.4 ns
16:1 MUX 3.5 ns
32:1 MUX 4.0 ns
1. These timing numbers were generated using the ispLEVER 8.0 design tool. Exact performance may vary with device and tool version. The
tool uses internal parameters that have been characterized but are not tested on every device.
Register-to-Register Performance
Function -7 Timing Units
Basic Functions
16-bit Decoder 599 MHz
32-bit Decoder 542 MHz
64-bit Decoder 417 MHz
4:1 MUX 847 MHz
8:1 MUX 803 MHz
16:1 MUX 660 MHz
32:1 MUX 577 MHz
8-bit Adder 591 MHz
16-bit Adder 500 MHz
64-bit Adder 306 MHz
16-bit Counter 488 MHz
32-bit Counter 378 MHz
64-bit Counter 260 MHz
64-bit Accumulator 253 MHz
Embedded Memory Functions
512x36 Single Port RAM, EBR Output
Registers 370 MHz
1024x18 True-Dual Port RAM (Write
Through or Normal, EBR Output Regis-
ters)
370 MHz
1024x18 True-Dual Port RAM (Write
Through or Normal, PLC Output
Registers)
280 MHz
Distributed Memory Functions
16x4 Pseudo-Dual Port RAM (One PFU) 819 MHz
32x4 Pseudo-Dual Port RAM 521 MHz
64x8 Pseudo-Dual Port RAM 435 MHz
DSP Functions
18x18 Multiplier (All Registers) 420 MHz
9x9 Multiplier (All Registers) 420 MHz
_:,-_: LATTICE 55555555555555
3-18
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Derating Timing Tables
Logic timing provided in the following sections of this data sheet and the Diamond design tool are worst case num-
bers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be much
better than the values given in the tables. The Diamond design tool can provide logic timing numbers at a particular
temperature and voltage.
36x36 Multiplier
(All Registers) 372 MHz
18x18 Multiplier/Accumulate (Input and
Output Registers) 295 MHz
18x18 Multiplier-Add/Sub-Sum (All Reg-
isters) 420 MHz
DSP IP Functions
16-Tap Fully-Parallel FIR Filter 304 MHz
1024-pt, Radix 4, Decimation in
Frequency FFT 227 MHz
8x8 Matrix Multiplier 223 MHz
Register-to-Register Performance (Continued)
Function -7 Timing Units
_:_:_: LATTICE 55555555555555
3-19
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
LatticeECP2/M External Switching Characteristics9
Over Recommended Operating Conditions
Parameter Description Device
-7 -6 -5
UnitsMin. Max. Min. Max. Min. Max.
General I/O Pin Parameters (using Primary Clock without PLL)1
tCO Clock to Output - PIO Output
Register
LFE2-6 — 3.50 — 3.90 — 4.20 ns
LFE2-12 — 3.50 — 3.90 — 4.20 ns
LFE2-20 — 3.50 — 3.90 — 4.20 ns
LFE2-35 — 3.50 — 3.90 — 4.20 ns
LFE2-50 — 3.50 — 3.90 — 4.20 ns
LFE2-70 — 3.70 — 4.10 — 4.40 ns
LFE2M20 — 3.90 — 4.30 — 4.70 ns
LFE2M35 — 3.90 — 4.30 — 4.70 ns
LFE2M50 — 4.50 — 5.00 — 5.40 ns
LFE2M70 — 4.50 — 5.00 — 5.40 ns
LFE2M100 — 4.50 — 5.00 — 5.40 ns
tSU Clock to Data Setup - PIO Input
Register
LFE2-6 0.00 — 0.00 — 0.00 — ns
LFE2-12 0.00 — 0.00 — 0.00 — ns
LFE2-20 0.00 — 0.00 — 0.00 — ns
LFE2-35 0.00 — 0.00 — 0.00 — ns
LFE2-50 0.00 — 0.00 — 0.00 — ns
LFE2-70 0.00 — 0.00 — 0.00 — ns
LFE2M20 0.00 — 0.00 — 0.00 — ns
LFE2M35 0.00 — 0.00 — 0.00 — ns
LFE2M50 0.00 — 0.00 — 0.00 — ns
LFE2M70 0.00 — 0.00 — 0.00 — ns
LFE2M100 0.00 — 0.00 — 0.00 — ns
tHClock to Data Hold - PIO Input
Register
LFE2-6 1.40 — 1.70 — 1.90 — ns
LFE2-12 1.40 — 1.70 — 1.90 — ns
LFE2-20 1.40 — 1.70 — 1.90 — ns
LFE2-35 1.40 — 1.70 — 1.90 — ns
LFE2-50 1.40 — 1.70 — 1.90 — ns
LFE2-70 1.40 — 1.70 — 1.90 — ns
LFE2M20 1.40 — 1.70 — 1.90 — ns
LFE2M35 1.40 — 1.70 — 1.90 — ns
LFE2M50 1.80 — 2.10 — 2.30 — ns
LFE2M70 1.80 — 2.10 — 2.30 — ns
LFE2M100 1.80 — 2.10 — 2.30 — ns
_:_:_: LATTICE 55555555555555
3-20
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
tSU_DEL Clock to Data Setup - PIO Input
Register with Data Input Delay
LFE2-6 1.40 — 1.70 — 1.90 — ns
LFE2-12 1.40 — 1.70 — 1.90 — ns
LFE2-20 1.40 — 1.70 — 1.90 — ns
LFE2-35 1.40 — 1.70 — 1.90 — ns
LFE2-50 1.40 — 1.70 — 1.90 — ns
LFE2-70 1.40 — 1.70 — 1.90 — ns
LFE2M20 1.40 — 1.70 — 1.90 — ns
LFE2M35 1.40 — 1.70 — 1.90 — ns
LFE2M50 1.40 — 1.70 — 1.90 — ns
LFE2M70 1.40 — 1.70 — 1.90 — ns
LFE2M100 1.40 — 1.70 — 1.90 — ns
tH_DEL Clock to Data Hold - PIO Input Reg-
ister with Input Data Delay
LFE2-6 0.00 — 0.00 — 0.00 — ns
LFE2-12 0.00 — 0.00 — 0.00 — ns
LFE2-20 0.00 — 0.00 — 0.00 — ns
LFE2-35 0.00 — 0.00 — 0.00 — ns
LFE2-50 0.00 — 0.00 — 0.00 — ns
LFE2-70 0.00 — 0.00 — 0.00 — ns
LFE2M20 0.00 — 0.00 — 0.00 — ns
LFE2M35 0.00 — 0.00 — 0.00 — ns
LFE2M50 0.00 — 0.00 — 0.00 — ns
LFE2M70 0.00 — 0.00 — 0.00 — ns
LFE2M100 0.00 — 0.00 — 0.00 — ns
fMAX_IO Clock Frequency of I/O Register and
PFU Register ECP2/M —420—357—311MHz
General I/O Pin Parameters (using Edge Clock without PLL)1
tCOE Clock to Output - PIO Output
Register
LFE2-6 — 2.60 — 2.90 — 3.20 ns
LFE2-12 — 2.60 — 2.90 — 3.20 ns
LFE2-20 — 2.60 — 2.90 — 3.20 ns
LFE2-35 — 2.60 — 2.90 — 3.20 ns
LFE2-50 — 2.60 — 2.90 — 3.20 ns
LFE2-70 — 2.60 — 2.90 — 3.20 ns
LFE2M20 — 2.60 — 2.90 — 3.20 ns
LFE2M35 — 2.60 — 2.90 — 3.20 ns
LFE2M50 — 3.10 — 3.40 — 3.70 ns
LFE2M70 — 3.10 — 3.40 — 3.70 ns
LFE2M100 — 3.10 — 3.40 — 3.70 ns
LatticeECP2/M External Switching Characteristics9 (Continued)
Over Recommended Operating Conditions
Parameter Description Device
-7 -6 -5
UnitsMin. Max. Min. Max. Min. Max.
_:_:_: LATTICE 55555555555555
3-21
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
tSUE Clock to Data Setup - PIO Input
Register
LFE2-6 0.00 — 0.00 — 0.00 — ns
LFE2-12 0.00 — 0.00 — 0.00 — ns
LFE2-20 0.00 — 0.00 — 0.00 — ns
LFE2-35 0.00 — 0.00 — 0.00 — ns
LFE2-50 0.00 — 0.00 — 0.00 — ns
LFE2-70 0.00 — 0.00 — 0.00 — ns
LFE2M20 0.00 — 0.00 — 0.00 — ns
LFE2M35 0.00 — 0.00 — 0.00 — ns
LFE2M50 0.00 — 0.00 — 0.00 — ns
LFE2M70 0.00 — 0.00 — 0.00 — ns
LFE2M100 0.00 — 0.00 — 0.00 — ns
tHE Clock to Data Hold - PIO Input
Register
LFE2-6 0.90 — 1.10 — 1.30 — ns
LFE2-12 0.90 — 1.10 — 1.30 — ns
LFE2-20 0.90 — 1.10 — 1.30 — ns
LFE2-35 0.90 — 1.10 — 1.30 — ns
LFE2-50 0.90 — 1.10 — 1.30 — ns
LFE2-70 0.90 — 1.10 — 1.30 — ns
LFE2M20 0.90 — 1.10 — 1.30 — ns
LFE2M35 0.90 — 1.10 — 1.30 — ns
LFE2M50 1.20 — 1.40 — 1.60 — ns
LFE2M70 1.20 — 1.40 — 1.60 — ns
LFE2M100 1.20 — 1.40 — 1.60 — ns
tSU_DELE Clock to Data Setup - PIO Input
Register with Data Input Delay
LFE2-6 1.00 — 1.30 — 1.60 — ns
LFE2-12 1.00 — 1.30 — 1.60 — ns
LFE2-20 1.00 — 1.30 — 1.60 — ns
LFE2-35 1.00 — 1.30 — 1.60 — ns
LFE2-50 1.00 — 1.30 — 1.60 — ns
LFE2-70 1.00 — 1.30 — 1.60 — ns
LFE2M20 1.20 — 1.60 — 1.90 — ns
LFE2M35 1.20 — 1.60 — 1.90 — ns
LFE2M50 1.20 — 1.60 — 1.90 — ns
LFE2M70 1.20 — 1.60 — 1.90 — ns
LFE2M100 1.20 — 1.60 — 1.90 — ns
LatticeECP2/M External Switching Characteristics9 (Continued)
Over Recommended Operating Conditions
Parameter Description Device
-7 -6 -5
UnitsMin. Max. Min. Max. Min. Max.
_:_:_: LATTICE 55555555555555
3-22
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
tH_DELE Clock to Data Hold - PIO Input
Register with Input Data Delay
LFE2-6 0.00 — 0.00 — 0.00 — ns
LFE2-12 0.00 — 0.00 — 0.00 — ns
LFE2-20 0.00 — 0.00 — 0.00 — ns
LFE2-35 0.00 — 0.00 — 0.00 — ns
LFE2-50 0.00 — 0.00 — 0.00 — ns
LFE2-70 0.00 — 0.00 — 0.00 — ns
LFE2M20 0.00 — 0.00 — 0.00 — ns
LFE2M35 0.00 — 0.00 — 0.00 — ns
LFE2M50 0.00 — 0.00 — 0.00 — ns
LFE2M70 0.00 — 0.00 — 0.00 — ns
LFE2M100 0.00 — 0.00 — 0.00 — ns
fMAX_IOE Clock Frequency of I/O and PFU
Register ECP2/M —420—357—311MHz
General I/O Pin Parameters (using Primary Clock with PLL)1
tCOPLL10 Clock to Output - PIO Output
Register
LFE2-6 — 2.30 — 2.60 — 2.80 ns
LFE2-12 — 2.30 — 2.60 — 2.80 ns
LFE2-20 — 2.30 — 2.60 — 2.80 ns
LFE2-35 — 2.30 — 2.60 — 2.80 ns
LFE2-50 — 2.30 — 2.60 — 2.80 ns
LFE2-70 — 2.30 — 2.60 — 2.80 ns
LFE2M20 — 2.30 — 2.60 — 2.80 ns
LFE2M35 — 2.30 — 2.60 — 2.80 ns
LFE2M50 — 2.60 — 2.90 — 3.10 ns
LFE2M70 — 2.60 — 2.90 — 3.10 ns
LFE2M100 — 2.70 — 3.00 — 3.20 ns
tSUPLL Clock to Data Setup - PIO Input
Register
LFE2-6 0.70 — 0.80 — 0.90 — ns
LFE2-12 0.70 — 0.80 — 0.90 — ns
LFE2-20 0.70 — 0.80 — 0.90 — ns
LFE2-35 0.70 — 0.80 — 0.90 — ns
LFE2-50 0.70 — 0.80 — 0.90 — ns
LFE2-70 0.70 — 0.80 — 0.90 — ns
LFE2M20 0.70 — 0.80 — 0.90 — ns
LFE2M35 0.70 — 0.80 — 0.90 — ns
LFE2M50 0.70 — 0.80 — 0.90 — ns
LFE2M70 0.70 — 0.80 — 0.90 — ns
LFE2M100 0.80 — 0.90 — 1.00 — ns
LatticeECP2/M External Switching Characteristics9 (Continued)
Over Recommended Operating Conditions
Parameter Description Device
-7 -6 -5
UnitsMin. Max. Min. Max. Min. Max.
_:_:_: LATTICE 55555555555555
3-23
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
tHPLL Clock to Data Hold - PIO Input
Register
LFE2-6 1.00 — 1.20 — 1.40 — ns
LFE2-12 1.00 — 1.20 — 1.40 — ns
LFE2-20 1.00 — 1.20 — 1.40 — ns
LFE2-35 1.00 — 1.20 — 1.40 — ns
LFE2-50 1.00 — 1.20 — 1.40 — ns
LFE2-70 1.00 — 1.20 — 1.40 — ns
LFE2M20 1.00 — 1.20 — 1.40 — ns
LFE2M35 1.00 — 1.20 — 1.40 — ns
LFE2M50 1.00 — 1.20 — 1.40 — ns
LFE2M70 1.00 — 1.20 — 1.40 — ns
LFE2M100 1.00 — 1.20 — 1.40 — ns
tSU_DELPLL Clock to Data Setup - PIO Input
Register with Data Input Delay
LFE2-6 1.80 — 2.00 — 2.20 — ns
LFE2-12 1.80 — 2.00 — 2.20 — ns
LFE2-20 1.80 — 2.00 — 2.20 — ns
LFE2-35 1.80 — 2.00 — 2.20 — ns
LFE2-50 1.80 — 2.00 — 2.20 — ns
LFE2-70 1.80 — 2.00 — 2.20 — ns
LFE2M20 1.80 — 2.00 — 2.20 — ns
LFE2M35 1.80 — 2.00 — 2.20 — ns
LFE2M50 1.90 — 2.10 — 2.30 — ns
LFE2M70 1.90 — 2.10 — 2.30 — ns
LFE2M100 2.00 — 2.20 — 2.40 — ns
tH_DELPLL Clock to Data Hold - PIO Input
Register with Input Data Delay
LFE2-6 0.00 — 0.00 — 0.00 — ns
LFE2-12 0.00 — 0.00 — 0.00 — ns
LFE2-20 0.00 — 0.00 — 0.00 — ns
LFE2-35 0.00 — 0.00 — 0.00 — ns
LFE2-50 0.00 — 0.00 — 0.00 — ns
LFE2-70 0.00 — 0.00 — 0.00 — ns
LFE2M20 0.00 — 0.00 — 0.00 — ns
LFE2M35 0.00 — 0.00 — 0.00 — ns
LFE2M50 0.00 — 0.00 — 0.00 — ns
LFE2M70 0.00 — 0.00 — 0.00 — ns
LFE2M100 0.00 — 0.00 — 0.00 — ns
DDR I/O Pin Parameters2
tDVADQ Data Valid After DQS (DDR Read) ECP2/M 0.225 0.225 0.225 UI
tDVEDQ Data Hold After DQS (DDR Read) ECP2/M 0.640 0.640 0.640 UI
tDQVBS Data Valid Before DQS (DDR Write) ECP2/M 0.250 — 0.250 — 0.250 — UI
tDQVAS Data Valid After DQS (DDR Write) ECP2/M 0.250 — 0.250 — 0.250 — UI
fMAX_DDR DDR Clock Frequency6ECP2/M 95 200 95 166 95 133 MHz
DDR2 I/O Pin Parameters3
tDVADQ Data Valid After DQS (DDR Read) ECP2/M 0.225 0.225 0.225 UI
tDVEDQ Data Hold After DQS (DDR Read) ECP2/M 0.640 0.640 0.640 UI
LatticeECP2/M External Switching Characteristics9 (Continued)
Over Recommended Operating Conditions
Parameter Description Device
-7 -6 -5
UnitsMin. Max. Min. Max. Min. Max.
_:_:_: LATTICE 55555555555555
3-24
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
tDQVBS Data Valid Before DQS (DDR Write) ECP2/M 0.250 — 0.250 — 0.250 — UI
tDQVAS Data Valid After DQS (DDR Write) ECP2/M 0.250 — 0.250 — 0.250 — UI
fMAX_DDR2 DDR Clock Frequency ECP2/M 133 266 133 200 133 166 MHz
SPI4.2 I/O Pin Parameters Static Alignment4, 8, 11
Maximum Data Rate
ECP2-20 — 750 — 622 — 622 Mbps
ECP2-35 — 750 — 622 — 622 Mbps
ECP2-50 — 750 — 622 — 622 Mbps
ECP2-70 — 750 — 622 — 622 Mbps
ECP2M20 — 622 — 622 — 622 Mbps
ECP2M35 — 622 — 622 — 622 Mbps
ECP2M50 — 622 — 622 — 622 Mbps
ECP2M70 — 622 — 622 — 622 Mbps
ECP2M100 — 622 — 622 — 622 Mbps
tDVACLKSPI Data Valid After CLK (Receive)
ECP2-20 — 0.25 — 0.25 — 0.25 UI
ECP2-35 — 0.25 — 0.25 — 0.25 UI
ECP2-50 — 0.25 — 0.25 — 0.25 UI
ECP2-70 — 0.25 — 0.25 — 0.25 UI
ECP2M20 — 0.21 — 0.21 — 0.21 UI
ECP2M35 — 0.21 — 0.21 — 0.21 UI
ECP2M50 — 0.21 — 0.21 — 0.21 UI
ECP2M70 — 0.21 — 0.21 — 0.21 UI
ECP2M100 — 0.21 — 0.21 — 0.21 UI
tDVECLKSPI Data Hold After CLK (Receive)
ECP2-20 0.75 — 0.75 — 0.75 — UI
ECP2-35 0.75 — 0.75 — 0.75 — UI
ECP2-50 0.75 — 0.75 — 0.75 — UI
ECP2-70 0.75 — 0.75 — 0.75 — UI
ECP2M20 0.79 — 0.79 — 0.79 — UI
ECP2M35 0.79 — 0.79 — 0.79 — UI
ECP2M50 0.79 — 0.79 — 0.79 — UI
ECP2M70 0.79 — 0.79 — 0.79 — UI
ECP2M100 0.79 — 0.79 — 0.79 — UI
tDIASPI Data Invalid After Clock (Transmit)
ECP2-20 — 280 — 280 — 280 ps
ECP2-35 — 280 — 280 — 280 ps
ECP2-50 — 280 — 280 — 280 ps
ECP2-70 — 280 — 280 — 280 ps
ECP2M20 — 230 — 230 — 230 ps
ECP2M35 — 230 — 230 — 230 ps
ECP2M50 — 230 — 230 — 230 ps
ECP2M70 — 230 — 230 — 230 ps
ECP2M100 — 230 — 230 — 230 ps
LatticeECP2/M External Switching Characteristics9 (Continued)
Over Recommended Operating Conditions
Parameter Description Device
-7 -6 -5
UnitsMin. Max. Min. Max. Min. Max.
ATTIC E ssumownucrom LamceECPz/M Pm Assxgnmenl Recommendamns
3-25
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
tDIBSPI Data Invalid Before Clock (Transmit)
ECP2-20 — 280 — 280 — 280 ps
ECP2-35 — 280 — 280 — 280 ps
ECP2-50 — 280 — 280 — 280 ps
ECP2-70 — 280 — 280 — 280 ps
ECP2M20 — 230 — 230 — 230 ps
ECP2M35 — 230 — 230 — 230 ps
ECP2M50 — 230 — 230 — 230 ps
ECP2M70 — 230 — 230 — 230 ps
ECP2M100 — 230 — 230 — 230 ps
XGMII I/O Pin Parameters (312 Mbps)5
tSUXGMII Data Setup Before Read Clock ECP2/M 480 480 480 ps
tHXGMII Data Hold After Read Clock ECP2/M 480 480 480 ps
tDVBCKXGMII Data Valid Before Clock ECP2/M 960 960 960 ps
tDVACKXGMII Data Valid After Clock ECP2/M 960 960 960 ps
Primary
fMAX_PRI7Frequency for Primary Clock Tree ECP2/M 420 357 311 MHz
tW_PRI Clock Pulse Width for Primary Clock ECP2/M 0.95 1.19 2.00 ns
tSKEW_PRI Primary Clock Skew Within a Bank ECP2/M 300 360 420 ps
Edge Clock
fMAX_EDGE7Frequency for Edge Clock ECP2/M 420 357 311 MHz
tW_EDGE Clock Pulse Width for Edge Clock ECP2/M 0.95 1.19 2.00 ns
tSKEW_EDGE Edge Clock Skew Within an Edge of
the Device ECP2/M —300—360—420ps
1. General timing numbers based on LVCMOS 2.5, 12mA, 0pf load.
2. DDR timing numbers based on SSTL25 for BGA packages only.
3. DDR2 timing numbers based on SSTL18 for BGA packages only.
4. SPI4.2 and SFI4 timing numbers based on LVDS25 for BGA packages only.
5. XGMII timing numbers based on HSTL class I. A corresponding left/right dedicated clock buffer is used when using the SPI4.2 interface to
the left or right edge of the device. For SPI4.2 mode, the software tool will help in selecting the appropriate clock buffer.
6. IP will be used to support DDR and DDR2 memory data rates down to 95MHz. This approach uses a free-running clock and PFU register to
sample the data instead of the hardwired DDR memory interface.
7. Using the LVDS I/O standard.
8. ECP2-6 and ECP2-12 do not support SPI4.2
9. The AC numbers do not apply to PCLK6 and PCLK7.
10. Applies to CLKOP only.
11. Please refer to TN1159, LatticeECP2/M Pin Assignment Recommendations for best performance.
LatticeECP2/M External Switching Characteristics9 (Continued)
Over Recommended Operating Conditions
Parameter Description Device
-7 -6 -5
UnitsMin. Max. Min. Max. Min. Max.
fl: LATTICE Illssumamzucram WWWW III 4: ||| FAF WW I I m
3-26
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Figure 3-6. SPI4.2 Parameters
Transmit Parameters
Receiver Parameters
tDVACLKSPI
tDVECLKSPI
tDIASPI
tDIBSPI tDIASPI
tDIBSPI
Data (RDAT,RCTL)
RDTCLK
tDVECLKSPI
tDVACLKSPI
CLK
Data (TDAT, TCTL)
fl: LATTICE Illssumamzucram WW WW WW I I W WWW
3-27
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Figure 3-7. DDR and DDR2 Parameters
Figure 3-8. XGMII Parameters
Transmit Parameters
Receiver Parameters
tDQVBS
tDQVAS tDQVBS
tDQVAS
DQS
DQ
DQS
DQ
tDVADQ
tDVEDQ tDVEDQ
tDVADQ
Transmit Parameters
Receiver Parameters
t
tt
t
CLOCK
DATA
CLOCK
DATA
tSUXGMII
tHXGMII
tSUXGMII
tHXGMII
DVBCKXGMII DVACKXGMII
DVACKXGMII DVBCKXGMII
_:_:_: LATTICE 55555555555555
3-28
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
LatticeECP2/M Internal Switching Characteristics1
Over Recommended Operating Conditions
Parameter Description
-7 -6 -5
UnitsMin. Max. Min. Max. Min. Max.
PFU/PFF Logic Mode Timing
tLUT4_PFU LUT4 delay (A to D inputs to F output) 0.180 0.198 0.216 ns
tLUT6_PFU LUT6 delay (A to D inputs to OFX output) 0.304 0.331 0.358 ns
tLSR_PFU Set/Reset to output of PFU (Asynchro-
nous) — 0.600 — 0.655 — 0.711 ns
tSUM_PFU Clock to Mux (M0,M1) Input Setup Time 0.128 0.129 0.129 ns
tHM_PFU Clock to Mux (M0,M1) Input Hold Time -0.051 -0.049 -0.046 ns
tSUD_PFU Clock to D input setup time 0.061 0.071 0.081 ns
tHD_PFU Clock to D input hold time 0.002 0.003 0.003 ns
tCK2Q_PFU Clock to Q delay, (D-type Register Configu-
ration) — 0.285 — 0.309 — 0.333 ns
PFU Dual Port Memory Mode Timing
tCORAM_PFU Clock to Output (F Port) 0.902 1.083 1.263 ns
tSUDATA_PFU Data Setup Time -0.172 -0.205 -0.238 ns
tHDATA_PFU Data Hold Time 0.199 0.235 0.271 ns
tSUADDR_PFU Address Setup Time -0.245 -0.284 -0.323 ns
tHADDR_PFU Address Hold Time 0.246 0.285 0.324 ns
tSUWREN_PFU Write/Read Enable Setup Time -0.122 -0.145 -0.168 ns
tHWREN_PFU Write/Read Enable Hold Time 0.132 0.156 0.180 ns
PIC Timing
PIO Input/Output Buffer Timing
tIN_PIO Input Buffer Delay (LVCMOS25) 0.613 0.681 0.749 ns
tOUT_PIO Output Buffer Delay (LVCMOS25) 1.115 1.115 1.343 ns
IOLOGIC Input/Output Timing
tSUI_PIO Input Register Setup Time (Data Before
Clock) 0.596 — 0.645 — 0.694 — ns
tHI_PIO Input Register Hold Time (Data after
Clock) -0.570 — -0.614 — -0.658 — ns
tCOO_PIO Output Register Clock to Output Delay 0.61 0.66 0.72 ns
tSUCE_PIO Input Register Clock Enable Setup Time 0.032 0.037 0.041 ns
tHCE_PIO Input Register Clock Enable Hold Time -0.022 -0.025 -0.028 ns
tSULSR_PIO Set/Reset Setup Time 0.184 0.201 0.217 ns
tHLSR_PIO Set/Reset Hold Time -0.080 -0.086 -0.093 ns
EBR Timing
tCO_EBR Clock (Read) to output from Address or
Data — 2.51 — 2.75 — 2.99 ns
tCOO_EBR Clock (Write) to output from EBR output
Register — 0.33 — 0.36 — 0.39 ns
tSUDATA_EBR Setup Data to EBR Memory -0.157 -0.181 -0.205 ns
tHDATA_EBR Hold Data to EBR Memory 0.173 0.195 0.217 ns
tSUADDR_EBR Setup Address to EBR Memory -0.115 -0.130 -0.145 ns
tHADDR_EBR Hold Address to EBR Memory 0.138 0.155 0.172 ns
tSUWREN_EBR Setup Write/Read Enable to PFU Memory -0.128 -0.149 -0.170 ns
_:_:_: LATTICE 55555555555555
3-29
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
tHWREN_EBR Hold Write/Read Enable to PFU Memory 0.139 0.156 0.173 ns
tSUCE_EBR Clock Enable Setup Time to EBR Output
Register 0.123 — 0.134 — 0.145 — ns
tHCE_EBR Clock Enable Hold Time to EBR Output
Register -0.081 — -0.090 — -0.100 — ns
tRSTO_EBR Reset To Output Delay Time from EBR
Output Register — 1.03 — 1.15 — 1.26 ns
tSUBE_EBR Byte Enable Set-Up Time to EBR Output
Register -0.115 — -0.130 — -0.145 — ns
tHBE_EBR Byte Enable Hold Time to EBR Output
Register 0.138 — 0.155 — 0.172 — ns
GPLL Parameters
tRSTREC_GPLL Reset Recovery to Rising Clock 1.00 1.00 1.00 ns
SPLL Parameters
tRSTREC_SPLL Reset Recovery to Rising Clock 1.00 1.00 1.00 ns
DSP Block Timing2,3
tSUI_DSP Input Register Setup Time 0.12 0.13 0.14 ns
tHI_DSP Input Register Hold Time 0.02 -0.01 -0.03 ns
tSUP_DSP Pipeline Register Setup Time 2.18 2.42 2.66 ns
ttHP_DSP Pipeline Register Hold Time -0.68 -0.77 -0.86 ns
tSUO_DSP Output Register Setup Time 4.26 4.71 5.16 ns
tHO_DSP Output Register Hold Time -1.25 — -1.40 — -1.54 — ns
tCOI_DSP Input Register Clock to Output Time 3.92 4.30 4.68 ns
tCOP_DSP Pipeline Register Clock to Output Time 1.87 1.98 2.08 ns
tCOO_DSP Output Register Clock to Output Time 0.50 0.52 0.55 ns
tSUADDSUB AddSub Input Register Setup Time -0.24 -0.26 -0.28 ns
tHADDSUB AddSub Input Register Hold Time 0.27 0.29 0.32 ns
1. Internal parameters are characterized but not tested on every device.
2. These parameters apply to LatticeECP devices only.
3. DSP Block is configured in Multiply Add/Sub 18x18 Mode.
LatticeECP2/M Internal Switching Characteristics1 (Continued)
Over Recommended Operating Conditions
Parameter Description
-7 -6 -5
UnitsMin. Max. Min. Max. Min. Max.
fl: LATTICE lllllllllllllllll ._.m—n M M M M M Xi‘x XD‘1X 1 1 1 H—u m—u 11
3-30
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Timing Diagrams
Figure 3-9. Read/Write Mode (Normal)
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.
Figure 3-10. Read/Write Mode with Input and Output Registers
A0 A1 A0 A1
D0 D1
DOA
A0
t
CO_EBR
t
CO_EBR
t
CO_EBR
t
SU
t
H
D0 D1 D0
DIA
ADA
WEA
CSA
CLKA
A0 A1 A0 A0
D0 D1
output is only updated during a read cycle
A1
D0 D1
Mem(n) data from previous read
DIA
ADA
WEA
CSA
CLKA
DOA (Regs)
tSU tH
tCOO_EBR tCOO_EBR
fl: LATTICE lllllllllllllllll X 1 3 3 éx‘m‘m W‘ Wer x W:
3-31
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Figure 3-11. Write Through (SP Read/Write on Port A, Input Registers Only)
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.
A0 A1 A0
D0 D1
D4
tSU
tACCESS tACCESS tACCESS
tH
D2 D3 D4
D0 D1 D2
Data from Prev Read
or Write
Three consecutive writes to A0
D3
DOA
DIA
ADA
WEA
CSA
CLKA
tACCESS
_:_:_: LATTICE 55555555555555
3-32
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
LatticeECP2/M Family Timing Adders1, 2, 3
Over Recommended Operating Conditions
Buffer Type Description -7-6-5Units
Input Adjusters
LVDS25 LVDS -0.04 -0.02 0.00 ns
BLVDS25 BLVDS -0.04 -0.09 -0.15 ns
MLVDS LVDS -0.15 -0.15 -0.15 ns
RSDS RSDS -0.15 -0.15 -0.15 ns
LVPECL33 LVPECL 0.16 0.15 0.13 ns
HSTL18_I HSTL_18 class I 0.01 -0.01 -0.04 ns
HSTL18_II HSTL_18 class II 0.01 -0.01 -0.04 ns
HSTL18D_I Differential HSTL 18 class I 0.01 -0.01 -0.04 ns
HSTL18D_II Differential HSTL 18 class II 0.01 -0.01 -0.04 ns
HSTL15_I HSTL_15 class I 0.01 -0.01 -0.04 ns
HSTL15D_I Differential HSTL 15 class I 0.01 -0.01 -0.04 ns
SSTL33_I SSTL_3 class I -0.03 -0.07 -0.10 ns
SSTL33_II SSTL_3 class II -0.03 -0.07 -0.10 ns
SSTL33D_I Differential SSTL_3 class I -0.03 -0.07 -0.10 ns
SSTL33D_II Differential SSTL_3 class II -0.03 -0.07 -0.10 ns
SSTL25_I SSTL_2 class I -0.04 -0.07 -0.10 ns
SSTL25_II SSTL_2 class II -0.04 -0.07 -0.10 ns
SSTL25D_I Differential SSTL_2 class I -0.04 -0.07 -0.10 ns
SSTL25D_II Differential SSTL_2 class II -0.04 -0.07 -0.10 ns
SSTL18_I SSTL_18 class I -0.01 -0.04 -0.07 ns
SSTL18_II SSTL_18 class II -0.01 -0.04 -0.07 ns
SSTL18D_I Differential SSTL_18 class I -0.01 -0.04 -0.07 ns
SSTL18D_II Differential SSTL_18 class II -0.01 -0.04 -0.07 ns
LVTTL33 LVTTL -0.16 -0.16 -0.16 ns
LVCMOS33 LVCMOS 3.3 -0.08 -0.12 -0.16 ns
LVCMOS25 LVCMOS 2.5 0.00 0.00 0.00 ns
LVCMOS18 LVCMOS 1.8 -0.16 -0.17 -0.17 ns
LVCMOS15 LVCMOS 1.5 -0.14 -0.14 -0.14 ns
LVCMOS12 LVCMOS 1.2 -0.04 -0.01 0.01 ns
PCI33 PCI -0.08 -0.12 -0.16 ns
Output Adjusters
LVDS25E LVDS 2.5 E40.25 0.19 0.13 ns
LVDS25 LVDS 2.5 0.10 0.13 0.17 ns
BLVDS25 BLVDS 2.5 0.00 -0.01 -0.03 ns
MLVDS MLVDS 2.540.00 -0.01 -0.03 ns
RSDS RSDS 2.540.25 0.19 0.13 ns
LVPECL33 LVPECL 3.34-0.02 -0.04 -0.06 ns
HSTL18_I HSTL_18 class I 8mA drive -0.19 -0.22 -0.25 ns
HSTL18_II HSTL_18 class II -0.30 -0.34 -0.37 ns
HSTL18D_I Differential HSTL 18 class I 8mA drive -0.19 -0.22 -0.25 ns
HSTL18D_II Differential HSTL 18 class II -0.30 -0.34 -0.37 ns
_:_:_: LATTICE 55555555555555
3-33
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
HSTL15_I HSTL_15 class I 4mA drive -0.22 -0.25 -0.27 ns
HSTL15D_I Differential HSTL 15 class I 4mA drive -0.22 -0.25 -0.27 ns
SSTL33_I SSTL_3 class I -0.12 -0.15 -0.18 ns
SSTL33_II SSTL_3 class II -0.20 -0.23 -0.27 ns
SSTL33D_I Differential SSTL_3 class I -0.12 -0.15 -0.18 ns
SSTL33D_II Differential SSTL_3 class II -0.20 -0.23 -0.27 ns
SSTL25_I SSTL_2 class I 8mA drive -0.16 -0.19 -0.22 ns
SSTL25_II SSTL_2 class II 16mA drive -0.19 -0.22 -0.25 ns
SSTL25D_I Differential SSTL_2 class I 8mA drive -0.16 -0.19 -0.22 ns
SSTL25D_II Differential SSTL_2 class II 16mA drive -0.19 -0.22 -0.25 ns
SSTL18_I SSTL_1.8 class I -0.14 -0.17 -0.20 ns
SSTL18_II SSTL_1.8 class II 8mA drive -0.20 -0.23 -0.25 ns
SSTL18D_I Differential SSTL_1.8 class I -0.14 -0.17 -0.20 ns
SSTL18D_II Differential SSTL_1.8 class II 8mA drive -0.20 -0.23 -0.25 ns
LVTTL33_4mA LVTTL 4mA drive 0.52 0.60 0.68 ns
LVTTL33_8mA LVTTL 8mA drive 0.06 0.08 0.09 ns
LVTTL33_12mA LVTTL 12mA drive 0.04 0.04 0.05 ns
LVTTL33_16mA LVTTL 16mA drive 0.03 0.02 0.02 ns
LVTTL33_20mA LVTTL 20mA drive -0.09 -0.09 -0.10 ns
LVCMOS33_4mA LVCMOS 3.3 4mA drive, fast slew rate 0.52 0.60 0.68 ns
LVCMOS33_8mA LVCMOS 3.3 8mA drive, fast slew rate 0.06 0.08 0.09 ns
LVCMOS33_12mA LVCMOS 3.3 12mA drive, fast slew rate 0.04 0.04 0.05 ns
LVCMOS33_16mA LVCMOS 3.3 16mA drive, fast slew rate 0.03 0.02 0.02 ns
LVCMOS33_20mA LVCMOS 3.3 20mA drive, fast slew rate -0.09 -0.09 -0.10 ns
LVCMOS25_4mA LVCMOS 2.5 4mA drive, fast slew rate 0.41 0.47 0.53 ns
LVCMOS25_8mA LVCMOS 2.5 8mA drive, fast slew rate 0.01 0.01 0.00 ns
LVCMOS25_12mA LVCMOS 2.5 12mA drive, fast slew rate 0.00 0.00 0.00 ns
LVCMOS25_16mA LVCMOS 2.5 16mA drive, fast slew rate 0.04 0.04 0.04 ns
LVCMOS25_20mA LVCMOS 2.5 20mA drive, fast slew rate -0.09 -0.10 -0.11 ns
LVCMOS18_4mA LVCMOS 1.8 4mA drive, fast slew rate 0.37 0.40 0.43 ns
LVCMOS18_8mA LVCMOS 1.8 8mA drive, fast slew rate 0.10 0.12 0.13 ns
LVCMOS18_12mA LVCMOS 1.8 12mA drive, fast slew rate -0.02 -0.02 -0.02 ns
LVCMOS18_16mA LVCMOS 1.8 16mA drive, fast slew rate -0.02 -0.03 -0.03 ns
LVCMOS15_4mA LVCMOS 1.5 4mA drive, fast slew rate 0.29 0.31 0.32 ns
LVCMOS15_8mA LVCMOS 1.5 8mA drive, fast slew rate 0.05 0.05 0.06 ns
LVCMOS12_2mA LVCMOS 1.2 2mA drive, fast slew rate 0.58 0.69 0.79 ns
LVCMOS12_6mA LVCMOS 1.2 6mA drive, fast slew rate 0.13 0.19 0.26 ns
LVCMOS33_4mA LVCMOS 3.3 4mA drive, slow slew rate 2.17 2.44 2.71 ns
LVCMOS33_8mA LVCMOS 3.3 8mA drive, slow slew rate 2.50 2.67 2.83 ns
LVCMOS33_12mA LVCMOS 3.3 12mA drive, slow slew rate 1.72 1.88 2.05 ns
LVCMOS33_16mA LVCMOS 3.3 16mA drive, slow slew rate 1.64 1.63 1.62 ns
LVCMOS33_20mA LVCMOS 3.3 20mA drive, slow slew rate 1.33 1.36 1.39 ns
LatticeECP2/M Family Timing Adders1, 2, 3 (Continued)
Over Recommended Operating Conditions
Buffer Type Description -7-6-5Units
_:_:_: LATTICE 55555555555555
3-34
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
LVCMOS25_4mA LVCMOS 2.5 4mA drive, slow slew rate 2.18 2.26 2.33 ns
LVCMOS25_8mA LVCMOS 2.5 8mA drive, slow slew rate 2.19 2.35 2.51 ns
LVCMOS25_12mA LVCMOS 2.5 12mA drive, slow slew rate 1.50 1.66 1.82 ns
LVCMOS25_16mA LVCMOS 2.5 16mA drive, slow slew rate 1.60 1.59 1.58 ns
LVCMOS25_20mA LVCMOS 2.5 20mA drive, slow slew rate 1.43 1.39 1.34 ns
LVCMOS18_4mA LVCMOS 1.8 4mA drive, slow slew rate 2.22 2.27 2.32 ns
LVCMOS18_8mA LVCMOS 1.8 8mA drive, slow slew rate 1.93 2.08 2.23 ns
LVCMOS18_12mA LVCMOS 1.8 12mA drive, slow slew rate 1.43 1.51 1.58 ns
LVCMOS18_16mA LVCMOS 1.8 16mA drive, slow slew rate 1.47 1.46 1.45 ns
LVCMOS15_4mA LVCMOS 1.5 4mA drive, slow slew rate 2.32 2.38 2.43 ns
LVCMOS15_8mA LVCMOS 1.5 8mA drive, slow slew rate 1.84 1.98 2.12 ns
LVCMOS12_2mA LVCMOS 1.2 2mA drive, slow slew rate 2.52 2.63 2.74 ns
LVCMOS12_6mA LVCMOS 1.2 6mA drive, slow slew rate 1.69 1.83 1.96 ns
PCI33 PCI33 0.04 0.04 0.04 ns
1. Timing Adders are characterized but not tested on every device.
2. LVCMOS timing measured with the load specified in Switching Test Condition table.
3. All other standards tested according to the appropriate specifications.
4. These timing adders are measured with the recommended resistor values.
Timing v.A 0.11
LatticeECP2/M Family Timing Adders1, 2, 3 (Continued)
Over Recommended Operating Conditions
Buffer Type Description -7-6-5Units
_:_:_: LATTICE 55555555555555
3-35
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
sysCLOCK GPLL Timing
Over Recommended Operating Conditions
Parameter Description Conditions Min. Typ. Max. Units
fIN Input Clock Frequency (CLKI, CLKFB) Without external capacitor 20 420 MHz
With external capacitor5, 6 2—420MHz
fOUT Output Clock Frequency (CLKOP,
CLKOS)
Without external capacitor 20 420 MHz
With external capacitor55—50MHz
fOUT2 K-Divider Output Frequency (CLKOK) Without external capacitor 0.156 210 MHz
With external capacitor50.039 — 25 MHz
fVCO PLL VCO Frequency 640 1280 MHz
fPFD Phase Detector Input Frequency Without external capacitor 20 420 MHz
With external capacitor5, 6 2—50MHz
AC Characteristics
tDT Output Clock Duty Cycle Default duty cycle selected345 50 55 %
tPH4Output Phase Accuracy ±0.05 UI
tOPJIT1Output Clock Period Jitter
fOUT 100 MHz ±125 ps
50 fOUT < 100 MHz 0.025 UIPP
fOUT < 50 MHz 0.04 UIPP
tSK Input Clock to Output Clock Skew N/M = integer ±250 ps
tWOutput Clock Pulse Width At 90% or 10% 1 ns
tLOCK2PLL Lock-in Time Without external capacitor 150 µs
With external capacitor5——500µs
tPA Programmable Delay Unit 85 130 360 ps
tIPJIT Input Clock Period Jitter ±200 ps
tFBKDLY External Feedback Delay 10 ns
tHI Input Clock High Time 90% to 90% 0.5 ns
tLO Input Clock Low Time 10% to 10% 0.5 ns
tRST
RST Pulse Width (RESETM/RESETK) 15 ns
Reset Signal Pulse Width (CNTRST) Without external capacitor 500 ns
With external capacitor520 — µs
1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock and no additional I/O pins toggling.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Using LVDS output buffers.
4. Relative to CLKOP.
5. Value of external capacitor: 5.6 nF ±20%, NPO dielectric, ceramic chip capacitor, 1206 or smaller package, connected to PLLCAP pin.
6. fOUT (max) = fIN * 10 for fIN < 5MHz.
_:_:_: LATTICE 55555555555555
3-36
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
sysCLOCK SPLL Timing
Over Recommended Operating Conditions
Parameter Description Conditions Min. Typ. Max. Units
fIN Input Clock Frequency (CLKI, CLKFB) Without external capacitor 33 420 MHz
With external capacitor5, 6 2 420 MHz
fOUT Output Clock Frequency (CLKOP, CLKOS) Without external capacitor 33 420 MHz
With external capacitor55—50MHz
fOUT2 K-Divider Output Frequency (CLKOK) Without external capacitor 0.258 210 MHz
With external capacitor50.039 — 25 MHz
fVCO PLL VCO Frequency 640 1280 MHz
fPFD Phase Detector Input Frequency Without external capacitor 33 420 MHz
With external capacitor62—50MHz
AC Characteristics
tDT Output Clock Duty Cycle Default Duty Cycle Selected345 50 55 %
tPH4Output Phase Accuracy ±0.05 UI
tOPJIT1Output Clock Period Jitter
fOUT 100 MHz ±125 ps
50 fOUT < 100 MHz 0.025 UIPP
fOUT < 50 MHz 0.04 UIPP
tSK Input Clock to Output Clock Skew Divider Ratio = Integer ±250 ps
tWOutput Clock Pulse Width At 90% or 10% 1 ns
tLOCK2PLL Lock-in Time Without external capacitor 150 µs
With external capacitor5 500 µs
tIPJIT Input Clock Period Jitter ±200 ps
tFBKDLY External Feedback Delay 10 ns
tHI Input Clock High Time 90% to 90% 0.5 ns
tLO Input Clock Low Time 10% to 10% 0.5 ns
tRST
RST Pulse Width (RSTK) 15 ns
Reset Signal Pulse Width (RST) Without external capacitor 500 ns
With external capacitor520 — — µs
1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock and no additional I/O pins toggling.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Using LVDS output buffers.
4. Phase accuracy of CLKOS compared to CLKOP.
5. Value of external capacitor: 5.6 nF ±20%, NPO dielectric, ceramic chip capacitor, 1206 or smaller package, connected to PLLCAP pin.
6. fOUT (max) = fIN * 10 for fIN < 5MHz.
_:_:_: LATTICE 55555555555555
3-37
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
DLL Timing
Over Recommended Operating Conditions
Parameter Description Min. Typ. Max. Units
fREF Input reference clock frequency (on-chip or off-chip) 100 500 MHz
fFB Feedback clock frequency (on-chip or off-chip) 100 500 MHz
fCLKOP1Output clock frequency, CLKOP 100 500 MHz
fCLKOS2Output clock frequency, CLKOS 25 500 MHz
tPJIT Output clock period jitter (clean input) 250 ps p-p
tCYJIT Output clock cycle to cycle jitter (clean input) 250 ps p-p
tDUTY Output clock duty cycle (at 50% levels, 50% duty cycle input clock,
50% duty cycle circuit turned off, time reference delay mode) 35 65 %
tDUTYTRD Output clock duty cycle (at 50% levels, arbitrary duty cycle input
clock, 50% duty cycle circuit enabled, time reference delay mode) 40 60 %
tDUTYCIR
Output clock duty cycle (at 50% levels, arbitrary duty cycle input
clock, 50% duty cycle circuit enabled, clock injection removal
mode)
40 60 %
tSKEW3Output clock to clock skew between two outputs with the same
phase setting ——100ps
tPWHInput clock minimum pulse width high (at 80% level) 750 ps
tPWLInput clock minimum pulse width low (at 20% level) 750 ps
tINSTB Input clock period jitter +/-250 ps
tLOCK DLL lock time 18,500 — cycles
tRSWDDigital reset minimum pulse width (at 80% level) 3 ns
tPA Delay step size 16.5 42 59.4 ps
tRANGE1 Max. delay setting for single delay block (144 taps) 2.376 6 8.553 ns
tRANGE4 Max. delay setting for four chained delay blocks 9.504 24 34.214 ns
1. CLKOP runs at the same frequency as the input clock.
2. CLKOS minimum frequency is obtained with divide by 4.
3. This is intended to be a “path-matching” design guideline and is not a measurable specification.
ATTIC E ssumownucrom LamceECPzM SERDES/PCS Usage Gume
3-38
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
SERDES High-Speed Data Transmitter (LatticeECP2M Family Only)1, 2
Table 3-7. Serial Output Timing and Levels
Table 3-8. Channel Output Jitter - x10 Mode
Symbol Description Frequency Min. Typ. Max. Units
VTX-DIFF-P-P-1 Differential swing (1V setting)1, 2 0.25 to 3.125 Gbps 0.79 0.99 1.19 V, p-p
VTX-DIFF-P-P-1.25 Differential swing (1.25V setting)1, 2 0.25 to 3.125 Gbps 1.00 1.25 1.50 V, p-p
VTX-DIFF-P-P-1.3 Differential swing (1.3V setting)1, 2 0.25 to 3.125 Gbps 1.04 1.30 1.56 V, p-p
VTX-DIFF-P-P-1.35 Differential swing (1.35V setting)1, 2 0.25 to 3.125 Gbps 1.08 1.35 1.62 V, p-p
VOCM Output common mode voltage VCCOB -
0.75
VCCOB -
0.60
VCCOB -
0.45 V
TTX-R Rise time (20% to 80%) 70 ps
TTX-F Fall time (80% to 20%) 70 ps
ZTX-OI-SE Output impedance 50/75/HiZ
K Ohms (single-ended) ——
50/70
HiZ —Ohms
RTX-RL Return loss (with package) 9 dB
1. All measurements are with 50 ohm impedance.
2. See TN1124, LatticeECP2M SERDES/PCS Usage Guide for actual binary settings.
Description Frequency Min. Typ. Max. Units
Deterministic 3.125 Gbps 0.08 0.12 UI, p-p
Random 3.125 Gbps 0.22 0.38 UI, p-p
Total 3.125 Gbps 0.33 0.43 UI, p-p
Deterministic 2.5 Gbps 0.08 0.17 UI, p-p
Random 2.5 Gbps 0.20 0.25 UI, p-p
Total 2.5 Gbps 0.25 0.35 UI, p-p
Deterministic 1.25 Gbps 0.03 0.10 UI, p-p
Random 1.25 Gbps 0.14 0.19 UI, p-p
Total 1.25 Gbps 0.17 0.24 UI, p-p
Deterministic 250 Mbps 0.04 0.17 UI, p-p
Random 250 Mbps 0.12 0.13 UI, p-p
Total 250 Mbps 0.15 0.29 UI, p-p
Note: Values are measured with PRBS 27-1, all channels operating, FPGA Logic active, I/Os around SERDES pins quiet, reference clock at
x10 mode.
_:_:_: LATTICE 55555555555555
3-39
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Table 3-9. Channel Output Jitter - x20 Mode
Table 3-10. SERDES/PCS Latency Breakdown (Parallel Clock Cycle)
Description Frequency Min. Typ. Max. Units
Deterministic 3.125 Gbps 0.08 0.12 UI, p-p
Random 3.125 Gbps 0.27 0.51 UI, p-p
Total 3.125 Gbps 0.35 0.59 UI, p-p
Deterministic 2.5 Gbps 0.09 0.19 UI, p-p
Random 2.5 Gbps 0.23 0.34 UI, p-p
Total 2.5 Gbps 0.29 0.45 UI, p-p
Deterministic 1.25 Gbps 0.05 0.11 UI, p-p
Random 1.25 Gbps 0.16 0.22 UI, p-p
Total 1.25 Gbps 0.20 0.28 UI, p-p
Note: Values are measured with PRBS 27-1, all channels operating, FPGA Logic active, I/Os around SERDES pins quiet, reference clock at
x20 mode.
Item Description Min. Average Max. Fixed Bypass Units
Transmit Data Latency
T1 FPGA Bridge Transmit2135 1word clk
T2 8b10b Encoder 2 1 word clk
T3 SERDES Bridge Transmit 2 1 word clk
T43Serializer: 8-bit mode 15 + 1—UI + ps
Serializer: 10-bit mode 18 + 1—UI + ps
Receive Data Latency
R13Deserializer: 8-bit mode 10 + 2—UI + ps
Deserializer: 10-bit mode 12 + 2—UI + ps
R2 SERDES Bridge Receive 2 1 word clk
R3 Word Alignment 3.1 4 0 word clk
R4 8b10b Decoder 1 1 word clk
R5 Clock Tolerance Compensation 7 15 23 1 word clk
R6 FPGA Bridge Receive2135 1word clk
1. PCS internal parallel clock. This clock rate is the same as rxfullclk.
2. FPGA Bridge latency varies by the upsample/downsample FIFO read/write. The numbers given are for the 8b10b interface. The
depth of the downsample/upsample FIFO is 4. The earliest read can be done after the write clock cycle (one clock) in downsample
FIFO. The latest read will be done after the FIFO is full (4 + 1 = 5). For the 16b20b interface, the numbers are doubled: min. = 2, max.
= 10. This latency depends on the internal FIFO flag operation.
3. 1 = -245ps, 2 = 700ps
_:,-_: LATTICE 55555555555555
3-40
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Figure 3-12. Transmitter and Receiver Block Diagram
HDOUTPi
HDOUTNi
Deserializer
1:8/1:10
Polarity
Adjust
Elastic
Buffer
FIFO
Encoder
SERDES PCS
BYPASS
Transmitter
Receiver
Recovered Clock
FPGA
Receive Clock
FPGA
Receive Data
Transmit Data
CDR
REFCLK
HDINPi
HDINNi
EQ
Polarity
Adjust
Up
Sample
FIFO
SERDES BridgeFPGA Bridge
Serializer
8:1/10:1
WA DEC
FPGA
EBRD Clock
Transmit Clock
TX PLL
REFCLK
FPGA Core
Down
Sample
FIFO
BYPASS
BYPASS
BYPASS
BYPASS
BYPASS
BYPASS
R1 R2 R3 R4 R5 R6
T1
T2
T3
T4
Transmit Clock
_:_:_: LATTICE 55555555555555
3-41
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
SERDES High Speed Data Receiver (LatticeECP2M Family Only)
Table 3-11. Serial Input Data Specifications
Input Data Jitter Tolerance
A receiver’s ability to tolerate incoming signal jitter is very dependent on jitter type. High speed serial interface stan-
dards have recognized the dependency on jitter type and have recently modified specifications to indicate toler-
ance levels for different jitter types as they relate to specific protocols (e.g. FC, etc.). Sinusoidal jitter is considered
to be a worst case jitter type.
Table 3-12. Receiver Total Jitter Tolerance Specification1
Symbol Description Min. Typ. Max. Units
RX-CIDSStream of nontransitions1
(CID = Consecutive Identical Digits) @ 10-12 BER
7 @ 3.125 Gbps
20 @ 1.25 Gbps Bits
VRX-DIFF-S Differential input sensitivity 100 mV, p-p
VRX-IN Input levels 0 VCCRX + 0.8 V
VRX-CM-DC Input common mode range (DC coupled) 0.5 1.2 V
VRX-CM-AC Input common mode range (AC coupled)30—1.5V
TRX-RELOCK CDR re-lock time2 3000 Bits
ZRX-TERM Input termination 50/75 Ohm/High Z 50 Ohms
RLRX-RL Return loss (without package) 9 dB
1. This is the number of bits allowed without a transition on the incoming data stream when using DC coupling.
2. This is the typical number of bit times to re-lock to a new phase of frequency within +/- 300 ppm, assuming 8b10b encoded data and the
CDR is in lock state. When CDR is in un-lock state, or reset is applied, the total re-lock settling time will be approximately 4ms including ana-
log settle time, calibration time, and acquisition time.
3. AC coupling is used to interface to LVPECL and LVDS.
Description Frequency Condition Min. Typ. Max. Units
Deterministic
3.125 Gbps
600 mV differential eye 0.54 UI, p-p
Random 600 mV differential eye 0.26 UI, p-p
Total 600 mV differential eye 0.80 UI, p-p
Deterministic
2.5 Gbps
600 mV differential eye 0.61 UI, p-p
Random 600 mV differential eye 0.22 UI, p-p
Total 600 mV differential eye 0.81 UI, p-p
Deterministic
1.25 Gbps
600 mV differential eye 0.53 UI, p-p
Random 600 mV differential eye 0.22 UI, p-p
Total 600 mV differential eye 0.80 UI, p-p
Deterministic
250 Mbps2
600 mV differential eye 0.42 UI, p-p
Random 600 mV differential eye 0.10 UI, p-p
Total 600 mV differential eye 0.60 UI, p-p
1. Values are measured with PRBS 27-1, all channels operating, FPGA Logic active, I/Os around SERDES pins quiet, voltages are nominal,
room temperature.
2. Jitter specification is limited by measurement equipment capability.
_:,-_: LATTICE 55555555555555
3-42
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Table 3-13. Periodic Receiver Jitter Tolerance Specification1
Description Frequency Condition Min. Typ. Max. Units
Periodic
3.125 Gbps 600 mV differential eye 0.20 UI, p-p
2.5 Gbps 600 mV differential eye 0.22 UI, p-p
1.25 Gbps 600 mV differential eye 0.20 UI, p-p
250 Mbps2600 mV differential eye 0.08 UI, p-p
1. Values are measured with PRBS 27-1, all channels operating.
2. Jitter specification is limited by measurement equipment capability.
ATTIC E ssumownucrom
3-43
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
SERDES External Reference Clock (LatticeECP2M Family Only)
The external reference clock selection and its interface are a critical part of system applications for this product.
Table 3-14 specifies reference clock requirements, over the full range of operating conditions.
Figure 3-13. Jitter Transfer
SERDES Power-Down/Power-Up Specification
Table 3-15. Power-Down and Power-Up Specification
Table 3-14. External Reference Clock Specification (refclkp/refclkn)
Symbol Description Min. Typ. Max. Units
FREF Frequency range 25 320 MHz
FREF-PPM Frequency tolerance -300 300 ppm
VREF-IN-SE Input swing, single-ended clock1100 1200 mV, p-p
VREF-IN Input levels 0 VCCP + 0.8 V
VREF-CM-DC Input common mode range (DC coupled) 0.5 1.2 V
VREF-CM-AC Input common mode range (AC coupled)20— 1.5 V
DREF Duty cycle340 — 60 %
TREF-R Rise time (20% to 80%) 500 1000 ps
TREF-F Fall time (80% to 20%) 500 1000 ps
ZREF-IN-TERM Input termination 50/2K Ohms
CREF-IN-CAP Input capacitance4—— 1.5 pF
1. The signal swing for a single-ended input clock must be as large as the p-p differential swing of a differential input clock to get the same
gain at the input receiver. Lower swings for the clock may be possible, but will tend to increase jitter.
2. When AC coupled, the input common mode range is determined by:
(Min input level) + (Peak-to-peak input swing)/2 (Input common mode voltage) (Max input level) - (Peak-to-peak input swing)/2
3. Measured at 50% amplitude.
4. Input capacitance of 1.5pF is total capacitance, including both device and package.
Symbol Description Max. Units
tPWRDN Power-down time after all power down register bits set to ‘0’ 10 s
tPWRUP Power-up time after all power down register bits set to ‘1’ 100 s
Frequency (MHz)
dB
Note: This graph is for a nominal device.
-25.00
-20.00
-15.00
-10.00
-5.00
0.00
5.00
0.1 1 10 100
Jitter T.
Gain@25°C,1.20V,
PJ=100ps
_:_:_: LATTICE 55555555555555
3-44
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
PCI Express Electrical and Timing Characteristics
AC and DC Characteristics
Table 3-16. Transmit1, 2
Table 3-17. Receive
Symbol Description Test Conditions Min Typ Max Units
UI Unit interval 399.88 400 400.12 ps
VTX-DIFF_P-P Differential peak-to-peak output
voltage 0.8 1.0 1.2 V
VTX-DE-RATIO De-emphasis differential output
voltage ratio 0 -3.5 -7.96 dB
VTX-CM-AC_P RMS AC peak common-mode out-
put voltage —20—mV
VTX-CM-DC-LINE-DELTA Maximum Common mode voltage
delta between n and p channels ——25mV
VTX-DC-CM Tx DC common mode voltage 0 VCCOB +
5% V
ITX-SHORT Output short circuit current VTX-D+=0.0V
VTX-D-=0.0V ——90mA
ZTX-DIFF-DC Differential output impedance 80 100 120 Ohms
TTX-RISE Tx output rise time 20 to 80% 0.125 UI
TTX-FALL Tx output fall time 20 to 80% 0.125 UI
LTX-SKEW
Lane-to-lane static output skew for
all lanes in port/link ——1.3ns
TTX-EYE Transmitter eye width 0.75 UI
TTX-EYE-MEDIAN-TO-MAX-JITTER3 — 0.125 UI
CTX AC coupling capacitor 75 200 nF
1. Values are measured at 2.5 Gbps.
2. Compliant to PCI Express v1.1.
3. Measured at 60ps with plug-in board and jitter due to socket removed.
Symbol Description Test Conditions Min. Typ. Max. Units
UI Unit Interval 399.88 400 400.12 ps
VRX-DIFF_P-P Differential peak-to-peak input
voltage 0.175 — V
VRX-IDLE-DET-DIFF_P-P Idle detect threshold voltage 65 175 mV
ZRX-DIFF-DC DC differential input impedance 80 100 120 Ohms
ZRX-DC DC input impedance 40 50 60 Ohms
ZRX-HIGH-IMP-DC1Power-down DC input impedance 200K Ohms
TRX-EYE Receiver eye width 0.4 UI
TRX-EYE-MEDIAN-TO-MAX-JITTER ——0.3UI
Notes:
1. Measured with external AC-coupling on the receiver
2. Values are measured at 2.5 Gbps
_:,-_: LATTICE 55555555555555
3-45
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Table 3-18. Reference Clock
Symbol Description Test Conditions Min. Typ. Max. Units
FREFCLK Reference clock frequency 100 MHz
VCM Input common mode voltage 0.65 V
TR/TFClock input rise/fall time 1.0 ns
VSWDifferential input voltage swing 0.6 1.6 V
DCREFCLK Input clock duty cycle 40 50 60 %
PPM Reference clock tolerance -300 +300 ppm
_:_:_: LATTICE 55555555555555
3-46
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
LatticeECP2/M sysCONFIG Port Timing Specifications
Over Recommended Operating Conditions
Parameter Description Min. Max. Units
sysCONFIG Byte Data Flow
tSUCBDI Byte D[0:7] Setup Time to CCLK 7 ns
tHCBDI Byte D[0:7] Hold Time to CCLK 1 ns
tCODO CCLK to DOUT in Flowthrough Mode 12 ns
tSUCS CSN[0:1] Setup Time to CCLK 7 ns
tHCS CSN[0:1] Hold Time to CCLK 1 ns
tSUWDWrite Signal Setup Time to CCLK 7 ns
tHWDWrite Signal Hold Time to CCLK 1 ns
tDCB CCLK to BUSY Delay Time 12 ns
tCORD CCLK to Out for Read Data 12 ns
sysCONFIG Byte Slave Clocking
tBSCH Byte Slave CCLK Minimum High Pulse 6 ns
tBSCL Byte Slave CCLK Minimum Low Pulse 9 ns
tBSCYC Byte Slave CCLK Cycle Time 15 ns
sysCONFIG Serial (Bit) Data Flow
tSUSCDI DI Setup Time to CCLK Slave Mode 7 ns
tHSCDI DI Hold Time to CCLK Slave Mode 1 ns
tCODO CCLK to DOUT in Flowthrough Mode 12 ns
sysCONFIG Serial Slave Clocking
tSSCH Serial Slave CCLK Minimum High Pulse 6 ns
tSSCL Serial Slave CCLK Minimum Low Pulse 6 ns
sysCONFIG POR, Initialization and Wake-up
tICFG Minimum Vcc to INITN High 28 ms
tVMC Time from tICFG to Valid Master CCLK 2 us
tPRGMRJ PROGRAMN Pin Pulse Rejection 8 ns
tPRGM PROGRAMN Low Time to Start Configuration 25 ns
tDINIT PROGRAMN High to INITN High Delay1— 1.5ms
tDPPINIT Delay Time from PROGRAMN Low to INITN Low 37 ns
tDPPDONE Delay Time from PROGRAMN Low to DONE Low 37 ns
tIODISS User I/O Disable from PROGRAMN Low 35 ns
tIOENSS User I/O Enabled Time from CCLK Edge During Wake-up Sequence 25 ns
tMWCAdditional Wake Master Clock Signals after DONE Pin High 120 cycles
sysCONFIG SPI Port2
tCFGX INITN High to CCLK Low 1 µs
tCSSPI INITN High to CSSPIN Low 2 us
tCSCCLK CCLK Low before CSSPIN Low 0 ns
tSOCDO CCLK Low to Output Valid 15 ns
tSOE CSSPIN[0:1] Active Setup Time 300 ns
tCSPID CSSPIN[0:1] Low to First CCLK Edge Setup Time 300+3cyc 600+6cyc ns
::: LATTICE ll.55MICoNDu(ToR
3-47
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Figure 3-14. sysCONFIG Parallel Port Read Cycle
fMAXSPI
Max. CCLK Frequency - SPI Flash Read Opcode (0x03)
(SPIFASTN = 1) — 20MHz
Max. CCLK Frequency - SPI Flash Fast Read Opcode (0x0B)
(SPIFASTN = 0) —50MHz
Max. CCLK Frequency - Encrypted Bitstream 10 MHz
tSUSPI SOSPI Data Setup Time Before CCLK 7 ns
tHSPI SOSPI Data Hold Time After CCLK 2 ns
tSUMCDI DI Setup to CCLK 7 ns
tHMCDI DI Hold from CCLK 1 ns
1. Re-toggling the PROGRAMN pin is not permitted until the INITN pin is high. Avoid consecutive toggling of the PROGRAMN.
2. For SED (Soft Error Detect), the SEDCLKIN operating frequency must be at least 20MHz. SEDCLKIN is derived from Master Clock Fre-
quency that has a +/-30% variation..
Parameter Min. Max. Units
Master Clock Frequency Selected value - 30% Selected value + 30% MHz
Duty Cycle 40 60 %
LatticeECP2/M sysCONFIG Port Timing Specifications (Continued)
Over Recommended Operating Conditions
Parameter Description Min. Max. Units
CCLK
CS1N
CSN
WRITEN
BUSY
D[0:7]
tSUCS tHCS
tSUWD
tCORD
tDCB
tHWD
tBSCYC
tBSCH
tBSCL
Byte 0 Byte 1 Byte 2 Byte n*
*n = last byte of read cycle.
:':'.:!-AZ'Z'!CE f mfi « ”VF
3-48
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Figure 3-15. sysCONFIG Parallel Port Write Cycle
Figure 3-16. sysCONFIG Slave Serial Port Timing
Figure 3-17. Power-On-Reset (POR) Timing
CCLK 1
CS1N
CSN
WRITEN
BUSY
D[0:7]
tSUCS tHCS
tSUWD
tHCBDI
tDCB
tHWD
tBSCYC
tBSCH
tBSCL
tSUCBDI
Byte 0 Byte 1 Byte 2 Byte n
1. In Master Parallel Mode the FPGA provides CCLK. In Slave Parallel Mode the external device provides CCLK.
CCLK (input)
DIN
DOUT
tSUSCDI
tHSCDI
tCODO
tSSCL tSSCH
CCLK
2
DONE
VCC/VCCAUX
1
CFG[2:0]
3
tICFG
Valid
INITN
tVMC
tSUCFG tHCFG
1. Time taken from V
CC
or V
CCAUX
, whichever is the last to reach its V
MIN
.
2. Device is in a Master Mode.
3. The CFG pins are normally static (hard wired).
_:,-_: LATTICE ssssssssssssss W M j
3-49
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Figure 3-18. Configuration from PROGRAMN Timing
Figure 3-19. Wake-Up Timing
Figure 3-20. SPI/SPIm Configuration Waveforms
CCLK
DONE
PROGRAMN
CFG[2:0]
tPRGM
Valid
INITN
tSUCFG tHCFG
1. The CFG pins are normally static (hard wired)
tDPPINIT
tDINITD
tDINIT
tIODISS
USER I/O
CCLK
DONE
PROGRAMN
USER I/O
INITN
tIOENSS
Wake-Up
tMWC
VCC
t
ICFG
t
CSCCLK
t
SOE
t
SOCDO
t
CSPID
t
CSSPI
t
CFGX
t
DINIT
t
DPPINIT
PROGRAMN
DONE
INITN
CSSPI[0:1]N
CCLK
SISPI/BUSY
D7/SPID0
D7 D5 D4 D3 D2 D1 D0
D6
XXX Valid Bitstream
Clock 127 Clock 128
0 1 2 3 4 5 6 7
0
t
PRGM
Capture
CFGx
Capture
OPCODE
DPPDONE
fl: LATTICE lllllllllllllllll
3-50
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
JTAG Port Timing Specifications
Over Recommended Operating Conditions
Figure 3-21. JTAG Port Timing Waveforms
Symbol Parameter Min Max Units
fMAX TCK clock frequency 25 MHz
tBTCP TCK [BSCAN] clock pulse width 40 ns
tBTCPH TCK [BSCAN] clock pulse width high 20 ns
tBTCPL TCK [BSCAN] clock pulse width low 20 ns
tBTS TCK [BSCAN] setup time 8 ns
tBTH TCK [BSCAN] hold time 10 ns
tBTRF TCK [BSCAN] rise/fall time 50 mV/ns
tBTCO TAP controller falling edge of clock to valid output 10 ns
tBTCODIS TAP controller falling edge of clock to valid disable 10 ns
tBTCOEN TAP controller falling edge of clock to valid enable 10 ns
tBTCRS BSCAN test capture register setup time 8 ns
tBTCRH BSCAN test capture register hold time 25 ns
tBUTCO BSCAN test update register, falling edge of clock to valid output 25 ns
tBTUODIS BSCAN test update register, falling edge of clock to valid disable 25 ns
tBTUPOEN BSCAN test update register, falling edge of clock to valid enable 25 ns
Timing v.A 0.11
TMS
TDI
TCK
TDO
Data to be
captured
from I/O
Data to be
driven out
to I/O
ataD dilaVataD dilaV
ataD dilaVataD dilaV
Data Captured
t
BTCPH
t
BTCPL
t
BTCOEN
t
BTCRS
t
BTUPOEN
t
BUTCO
t
BTUODIS
t
BTCRH
t
BTCO
t
BTCODIS
t
BTS
t
BTH
t
BTCP
fl: LATTICE .- lsstoNnucrap
3-51
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Switching Test Conditions
Figure 3-22 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 3-19.
Figure 3-22. Output Test Load, LVTTL and LVCMOS Standards
Table 3-19. Test Fixture Required Components, Non-Terminated Interfaces
Test Condition R1R2CLTiming Ref. VT
LVTTL and other LVCMOS settings (L -> H, H -> L) 
0pF
LVCMOS 3.3 = 1.5V
LVCMOS 2.5 = VCCIO/2 —
LVCMOS 1.8 = VCCIO/2 —
LVCMOS 1.5 = VCCIO/2 —
LVCMOS 1.2 = VCCIO/2 —
LVCMOS 2.5 I/O (Z -> H) 1MVCCIO/2 —
LVCMOS 2.5 I/O (Z -> L) 1MVCCIO/2 VCCIO
LVCMOS 2.5 I/O (H -> Z) 100 VOH - 0.10
LVCMOS 2.5 I/O (L -> Z) 100 VOL + 0.10 VCCIO
Note: Output test conditions for all other interfaces are determined by the respective standards.
DUT
V
T
R1
R2
CL*
Test Point
*CL Includes Test Fixture and Probe Capacitance
:'_.'_.' LATTICE CCCCCCCCCCCCC
www.latticesemi.com 4-1 DS1006 Pinout Information_02.4
July 2012 Data Sheet DS1006
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Signal Descriptions
Signal Name I/O Description
General Purpose
P[Edge] [Row/Column Number*]_[A/B] I/O
[Edge] indicates the edge of the device on which the pad is located. Valid
edge designations are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on
which the PIC exists. When Edge is T (Top) or B (Bottom), only need to spec-
ify Row Number. When Edge is L (Left) or R (Right), only need to specify Col-
umn Number.
[A/B] indicates the PIO within the PIC to which the pad is connected. Some of
these user-programmable pins are shared with special function pins. These
pins, when not used as special purpose pins, can be programmed as I/Os for
user logic. During configuration the user-programmable I/Os are tri-stated
with an internal pull-up resistor enabled. If any pin is not used (or not bonded
to a package pin), it is also tri-stated with an internal pull-up resistor enabled
after configuration. See “Typical sysI/O I/O Behavior During Power-up” for
more information about I/O behavior during power-up.
GSRN I Global RESET signal (active low). Any I/O pin can be GSRN.
NC — No connect.
GND Ground. Dedicated pins.
VCC Power supply pins for core logic. Dedicated pins.
VCCAUX
Auxiliary power supply pin. This dedicated pin powers all the differential and
referenced input buffers.
VCCIOx Dedicated power supply pins for I/O bank x.
VCCPLL PLL supply pins. Should be tied to VCC even when the corresponding PLL is
unused.
VREF1_x, VREF2_x Reference supply pins for I/O bank x. Pre-determined pins in each bank are
assigned as VREF inputs. When not used, they may be used as I/O pins.
XRES4 10K ohm +/-1% resistor must be connected between this pad and ground.
PLLCAP4 External capacitor connection for PLL.
PLL, DLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)
[LOC][num]_VCCPLL Power supply pin for PLL: LUM, LLM, RUM, RLM, num = row from center.
[LOC][num]_GPLL[T, C]_IN_A I General Purpose PLL (GPLL) input pads: LUM, LLM, RUM, RLM, num = row
from center, T = true and C = complement, index A,B,C...at each side.
[LOC][num]_GPLL[T, C]_FB_A I Optional feedback GPLL input pads: LUM, LLM, RUM, RLM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
[LOC][num]_SPLL[T, C]_IN_A5 I
Secondary PLL (SPLL) input pads: LUM, LLM, RUM, RLM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
[LOC][num]_SPLL[T, C]_FB_A5 I
Optional feedback (SPLL) input pads: LUM, LLM, RUM, RLM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
[LOC][num]_DLL[T, C]_IN_A I DLL input pads: LUM, LLM, RUM, RLM, num = row from center, T = true and
C = complement, index A,B,C...at each side.
[LOC][num]_DLL[T, C]_FB_A I Optional feedback (DLL) input pads: LUM, LLM, RUM, RLM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
PCLK[T, C]_[n:0]_[3:0] I Primary Clock pads, T = true and C = complement, n per side, indexed by
bank and 0,1,2,3 within bank.
LatticeECP2/M Family Data Sheet
Pinout Information
_:_:_: LATTICE 55555555555555
4-2
Pinout Information
LatticeECP2/M Family Data Sheet
[LOC]DQS[num] I/O DQ input/output pads: T (top), R (right), B (bottom), L (left), DQS, num = ball
function number.
[LOC]DQ[num] I/O DQ input/output pads: T (top), R (right), B (bottom), L (left), DQ, associated
DQS number.
Test and Programming (Dedicated Pins)
TMS I Test Mode Select input, used to control the 1149.1 state machine. Pull-up is
enabled during configuration.
TCK I
Test Clock input pin, used to clock the 1149.1 state machine. No pull-up
enabled.
TDI I
Test Data in pin. Used to load data into device using 1149.1 state machine.
After power-up, this TAP port can be activated for configuration by sending
appropriate command. (Note: once a configuration port is selected it is
locked. Another configuration port cannot be selected until the power-up
sequence). Pull-up is enabled during configuration.
TDO O Output pin. Test Data Out pin used to shift data out of a device using 1149.1.
VCCJ Power supply pin for JTAG Test Access Port.
Configuration Pads (Used During sysCONFIG)
CFG[2:0] I
Mode pins used to specify configuration mode values latched on rising edge
of INITN. During configuration, a pull-up is enabled. These are dedicated
pins.
INITN I/O
Open Drain pin. Indicates the FPGA is ready to be configured. During config-
uration, a pull-up is enabled. It is a dedicated pin.
PROGRAMN I
Initiates configuration sequence when asserted low. This pin always has an
active pull-up. This is a dedicated pin.
DONE I/O
Open Drain pin. Indicates that the configuration sequence is complete, and
the startup sequence is in progress. This is a dedicated pin.
CCLK I/O Configuration Clock for configuring an FPGA in sysCONFIG mode.
BUSY/SISPI I/O Read control command in SPI or SPIm mode.
CSN I
sysCONFIG chip select (active low). During configuration, a pull-up is
enabled.
CS1N I
sysCONFIG chip select (active low). During configuration, a pull-up is
enabled.
WRITEN I Write Data on Parallel port (active low).
D[0]/SPIFASTN I/O
sysCONFIG Port Data I/O for Parallel mode.
sysCONFIG Port Data I/O for SPI or SPIm. When using the SPI or SPIm
mode, this pin should either be tied high or low, must not be left floating.
D[1:6] I/O sysCONFIG Port Data I/O for Parallel
D[7]/SPID0 I/O sysCONFIG Port Data I/O for Parallel, SPI, SPIm
DOUT/CSON O Output for serial configuration data (rising edge of CCLK) when using sys-
CONFIG port.
DI/CSSPI0N I/O
Input for serial configuration data (clocked with CCLK) when using sysCON-
FIG port. During configuration, a pull-up is enabled. Output when used in SPI/
SPIm modes.
Dedicated SERDES Signals1, 2, 3
[LOC]_SQ_VCCAUX33 Termination resistor switching power (3.3V). This pin must be tied to 3.3V
even if the quad is unused.
[LOC]_SQ_REFCLKN I Negative Reference Clock Input
[LOC]_SQ_REFCLKP I Positive Reference Clock Input
[LOC]_SQ_VCCP PLL and Reference clock buffer power (1.2V). This pin must be tied to 1.2V
even if the quad is unused.
Signal Descriptions (Cont.)
Signal Name I/O Description
LATTICE sstoNnucram LamceECPZM Pm Assxgnmenl Recommendamns
4-3
Pinout Information
LatticeECP2/M Family Data Sheet
[LOC]_SQ_VCCIBm Input buffer power supply, channel m (1.2V/1.5V). This pin should be left float-
ing if the channel is unused.
[LOC]_SQ_VCCOBm Output buffer power supply, channel m (1.2V/1.5V). This pin should be left
floating if the channel is unused.
[LOC]_SQ_HDOUTNm O High-speed output, negative channel m
[LOC]_SQ_HDOUTPm O High-speed output, positive channel m
[LOC]_SQ_HDINNm I High-speed input, negative channel m
[LOC]_SQ_HDINPm I High-speed input, positive channel m
[LOC]_SQ_VCCTXm4 Transmitter power supply, channel m (1.2V). This pin must be tied to 1.2V
even if the channel is unused.
[LOC]_SQ_VCCRXm4 Receiver power supply, channel m (1.2V). This pin must be tied to 1.2V even if
the channel is unused.
1. These signals are relevant for LatticeECP2M family.
2. m defines the associated channel in the Quad.
3. These signals are defined in Quads [LOC] indicates the corner SERDES Quad is located: ULC (upper left), URC (upper right), LLC (lower
left), LRC (lower right).
4. When placing switching I/Os around these critical pins that are designed to supply the device with the proper reference or supply voltage,
care must be given. For more information, refer to TN1159, LatticeECP2/M Pin Assignment Recommendations.
5. There may be SPLLs that do not have dedicated I/Os.
Signal Descriptions (Cont.)
Signal Name I/O Description
_:_:_: LATTICE 55555555555555
4-4
Pinout Information
LatticeECP2/M Family Data Sheet
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
PICs Associated with
DQS Strobe PIO Within PIC
DDR Strobe (DQS) and
Data (DQ) Pins
For Left and Right Edges of the Device
P[Edge] [n-4] ADQ
BDQ
P[Edge] [n-3] ADQ
BDQ
P[Edge] [n-2] ADQ
BDQ
P[Edge] [n-1] ADQ
BDQ
P[Edge] [n] A[Edge]DQSn
BDQ
P[Edge] [n+1] ADQ
BDQ
P[Edge] [n+2] ADQ
BDQ
P[Edge] [n+3] ADQ
BDQ
For Bottom Edge of the Device
P[Edge] [n-4] ADQ
BDQ
P[Edge] [n-3] ADQ
BDQ
P[Edge] [n-2] ADQ
BDQ
P[Edge] [n-1] ADQ
BDQ
P[Edge] [n] A [Edge]DQSn
BDQ
P[Edge] [n+1] ADQ
BDQ
P[Edge] [n+2] ADQ
BDQ
P[Edge] [n+3] ADQ
BDQ
P[Edge] [n+4] ADQ
BDQ
Notes:
1. “n” is a row PIC number.
2. The DDR interface is designed for memories that support one DQS strobe up to 15 bits
of data for the left and right edges and up to 17 bits of data for the bottom edge. In some
packages, all the potential DDR data (DQ) pins may not be available. PIC numbering
definitions are provided in the “Signal Names” column of the Signal Descriptions table.
_:_:_: LATTICE 55555555555555
4-5
Pinout Information
LatticeECP2/M Family Data Sheet
LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12
Pin Type
LFE2-6 LFE2-12
144
TQFP
256
fpBGA
144
TQFP
208
PQFP
256
fpBGA
484
fpBGA
Single Ended User I/O 90 190 93 131 193 297
Differential Pair User I/O 43 95 45 62 96 148
Configuration
TAP Pins 555555
Muxed Pins 14 14 14 14 14 14
Dedicated Pins (Non TAP)777777
Non Configuration Muxed Pins 34 54 33 40 54 57
Dedicated Pins 333333
VCC 10 7 10 14 7 16
VCCAUX 4448416
VCCPLL 000000
VCCIO
Bank0 121224
Bank1 121224
Bank2 121224
Bank3 121224
Bank4 121224
Bank5 121224
Bank6 121224
Bank7 121224
Bank8 111212
GND, GND0 to GND7 12 20 12 22 20 60
NC 4310044
Single Ended/ Differential I/O
Pairs per Bank (including
emulated with resistors)
Bank0 8/4 18/6 8/4 18/9 18/9 50/25
Bank1 17/8 34/17 18/9 18/9 34/17 46/23
Bank2 4/2 20/10 4/2 11/5 20/10 24/12
Bank3 8/4 12/6 8/4 11/5 12/6 16/8
Bank4 18/9 32/16 18/9 19/9 32/16 46/23
Bank5 8/4 14/7 10/5 18/9 17/8 46/23
Bank6 9/4 26/13 9/4 18/8 26/13 32/16
Bank7 12/6 20/10 12/6 12/6 20/10 23/11
Bank8 6/2 14/7 6/2 6/2 14/7 14/7
True LVDS I/O Pairs per Bank
Bank0 (Top Edge) 000000
Bank1 (Top Edge) 000000
Bank2 (Right Edge) 151456
Bank3 (Right Edge) 333334
Bank4 (Bottom Edge) 0 00000
Bank5 (Bottom Edge) 0 00000
Bank6 (Left Edge) 272678
Bank7 (Left Edge) 555555
Bank8 (Right Edge) 000000
_:_:_: LATTICE 55555555555555
4-6
Pinout Information
LatticeECP2/M Family Data Sheet
Available DDR-Interfaces per I/O
Bank1
Bank0 000000
Bank1 000000
Bank2 010011
Bank3 000000
Bank4 020023
Bank5 010013
Bank6 010011
Bank7 010011
Bank8 000000
PCI Capable I/Os per Bank
Bank0 000000
Bank1 000000
Bank2 000000
Bank3 000000
Bank4 183218193246
Bank5 8 14 10 18 17 46
Bank6 000000
Bank7 000000
Bank8 000000
1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1
DQSB + 8 DQs + 1 DM + Bank VREF1).
LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12 (Cont.)
Pin Type
LFE2-6 LFE2-12
144
TQFP
256
fpBGA
144
TQFP
208
PQFP
256
fpBGA
484
fpBGA
_:_:_: LATTICE 55555555555555
4-7
Pinout Information
LatticeECP2/M Family Data Sheet
LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35
Pin Type
LFE2-20 LFE2-35
208
PQFP
256
fpBGA
484
fpBGA
672
fpBGA
484
fpBGA
672
fpBGA
Single Ended User I/O 131 193 331 402 331 450
Differential Pair User I/O 62 96 165 200 165 224
Configuration
TAP Pins 555555
Muxed Pins 14 14 14 14 14 14
Dedicated Pins (Non TAP)777777
Non Configuration Muxed Pins 42 54 60 64 60 68
Dedicated Pins 333333
VCC 14 7 18 24 16 22
VCCAUX 8 4 16 16 16 16
VCCPLL 000022
VCCIO
Bank0 224545
Bank1 224545
Bank2 224545
Bank3 224545
Bank4 224545
Bank5 224545
Bank6 224545
Bank7 224545
Bank8 212222
GND, GND0 to GND7 22 20 60 72 60 72
NC 0 1 81018102
Single Ended/ Differential I/O
Pairs per Bank (including
emulated with resistors)
Bank0 18/9 18/9 50/25 67/33 50/25 67/33
Bank1 18/9 34/17 46/23 52/26 46/23 52/26
Bank2 11/5 20/10 34/17 36/18 34/17 48/24
Bank3 11/5 12/6 22/11 32/16 22/11 42/21
Bank4 19/9 32/16 46/23 50/25 46/23 54/27
Bank5 18/9 17/8 46/23 68/34 46/23 68/34
Bank6 18/8 26/13 40/20 48/24 40/20 58/29
Bank7 12/6 20/10 33/16 35/17 33/16 47/23
Bank8 6/2 14/7 14/7 14/7 14/7 14/7
True LVDS I/O Pairs per Bank
Bank0 (Top Edge) 000000
Bank1 (Top Edge) 000000
Bank2 (Right Edge) 4599912
Bank3 (Right Edge) 335859
Bank4 (Bottom Edge) 0 00000
Bank5 (Bottom Edge) 0 00000
Bank6 (Left Edge) 6 7 10 12 10 13
Bank7 (Left Edge) 5588811
Bank8 (Right Edge) 000000
_:_:_: LATTICE 55555555555555
4-8
Pinout Information
LatticeECP2/M Family Data Sheet
Available DDR-Interfaces per I/O
Bank1
Bank0 000000
Bank1 000000
Bank2 012223
Bank3 000202
Bank4 023333
Bank5 013434
Bank6 012313
Bank7 012223
Bank8 000000
PCI Capable I/Os per Bank
Bank0 000000
Bank1 000000
Bank2 000000
Bank3 000000
Bank4 193246504654
Bank5 181746684668
Bank6 000000
Bank7 000000
Bank8 000000
1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1
DQSB + 8 DQs + 1 DM + Bank VREF1).
LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35 (Cont.)
Pin Type
LFE2-20 LFE2-35
208
PQFP
256
fpBGA
484
fpBGA
672
fpBGA
484
fpBGA
672
fpBGA
_:_:_: LATTICE 55555555555555
4-9
Pinout Information
LatticeECP2/M Family Data Sheet
LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70
Pin Type
LFE2-50 LFE2-70
484 fpBGA 672 fpBGA 672 fpBGA 900 fpBGA
Single Ended User I/O 339 500 500 583
Differential Pair User I/O 169 249 249 290
Configuration
TAP Pins 5 5 5 5
Muxed Pins 14 14 14 14
Dedicated Pins (Non TAP) 7 7 7 7
Non Configuration Muxed Pins 68 79 79 89
Dedicated Pins 3 3 3 3
VCC 16202026
VCCAUX 16 16 16 17
VCCPLL 4 4 2 4
VCCIO
Bank0 4556
Bank1 4556
Bank2 4556
Bank3 4556
Bank4 4556
Bank5 4556
Bank6 4556
Bank7 4556
Bank8 2222
GND, GND0 to GND7 60 72 72 104
NC 0 3 5 101
Single Ended/ Differential I/O
Pairs per Bank (including
emulated with resistors)
Bank0 50/25 67/33 67/33 84/42
Bank1 46/23 66/33 66/33 76/38
Bank2 38/19 56/28 56/28 74/37
Bank3 22/11 48/24 48/24 48/24
Bank4 46/23 62/31 62/31 72/35
Bank5 46/23 68/34 68/34 80/40
Bank6 40/20 64/32 64/32 64/32
Bank7 37/18 55/27 55/27 71/35
Bank8 14/7 14/7 14/7 14/7
True LVDS I/O Pairs per Bank
Bank0 (Top Edge) 0 0 0 0
Bank1 (Top Edge) 0 0 0 0
Bank2 (Right Edge) 9 13 13 18
Bank3 (Right Edge) 5 12 12 12
Bank4 (Bottom Edge) 0 0 0 0
Bank5 (Bottom Edge) 0 0 0 0
Bank6 (Left Edge) 10 16 16 16
Bank7 (Left Edge) 8 12 12 16
Bank8 (Right Edge) 0 0 0 0
_:_:_: LATTICE 55555555555555
4-10
Pinout Information
LatticeECP2/M Family Data Sheet
Available DDR-Interfaces per I/O
Bank1
Bank0 0000
Bank1 0000
Bank2 2334
Bank3 0333
Bank4 3444
Bank5 3445
Bank6 1444
Bank7 2334
Bank8 0000
PCI Capable I/Os per Bank
Bank0 0000
Bank1 0000
Bank2 0000
Bank3 0000
Bank4 46626272
Bank5 46686880
Bank6 0000
Bank7 0000
Bank8 0000
1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1
DQSB + 8 DQs + 1 DM + Bank VREF1).
LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70 (Cont.)
Pin Type
LFE2-50 LFE2-70
484 fpBGA 672 fpBGA 672 fpBGA 900 fpBGA
_:_:_: LATTICE 55555555555555
4-11
Pinout Information
LatticeECP2/M Family Data Sheet
LatticeECP2M Pin Information Summary, LFE2M20 and LFE2M35
Pin Type
LFE2M20 LFE2M35
256 fpBGA 484 fpBGA 256 fpBGA 484 fpBGA 672 fpBGA
Single Ended User I/O 140 304 140 303 410
Differential Pair User I/O 70 152 70 151 199
Configuration
TAP Pins 55555
Muxed Pins 14 14 14 14 14
Dedicated Pins (Non TAP)77777
Non Configuration Muxed Pins 64 84 60 84 89
Dedicated Pins 33333
VCC 6 16 6 16 29
VCCAUX 484817
VCCPLL 14148
VCCIO
Bank0 14145
Bank1 13134
Bank2 24245
Bank3 24245
Bank4 24244
Bank5 24245
Bank6 24245
Bank7 24245
Bank8 12122
GND, GND0 to GND7 22 57 22 57 80
NC 17 11 17 12 37
Single Ended/ Differential I/O
Pairs per Bank (including
emulated with resistors)
Bank0 0/0 36/18 0/0 36/18 63/31
Bank1 0/0 18/9 0/0 18/9 18/9
Bank2 14/7 30/15 14/7 30/15 50/25
Bank3 16/8 36/18 16/8 36/18 43/21
Bank4 32/16 62/31 32/16 62/31 50/21
Bank5 20/10 28/14 20/10 28/14 60/30
Bank6 16/8 40/20 16/8 39/19 52/25
Bank7 28/14 40/20 28/14 40/20 60/30
Bank8 14/7 14/7 14/7 14/7 14/7
True LVDS I/O Pairs per Bank
Bank0 (Top Edge) 00000
Bank1 (Top Edge) 00000
Bank2 (Right Edge) 373712
Bank3 (Right Edge) 494911
Bank4 (Bottom Edge) 00000
Bank5 (Bottom Edge) 00000
Bank6 (Left Edge) 4 10 4 10 14
Bank7 (Left Edge) 7 10 7 10 15
Bank8 (Right Edge) 00000
_:_:_: LATTICE 55555555555555
4-12
Pinout Information
LatticeECP2/M Family Data Sheet
Available DDR-Interfaces per
I/O Bank1
Bank0 00000
Bank1 00000
Bank2 01013
Bank3 01012
Bank4 24243
Bank5 12123
Bank6 03012
Bank7 12123
Bank8 00000
PCI Capable I/Os per Bank
Bank0 00000
B