AD5251/52 Datasheet by Analog Devices Inc.

View All Related Products | Download PDF Datasheet
ANALOG 64-l256-Position I23 Nonvolatile DEVICES Memory Digital Potentiometers Documenl Feedback
Dual 64-/256-Position I2C Nonvolatile
Memory Digital Potentiometers
Data Sheet AD5251/AD5252
Rev. E Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©20042017 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
AD5251: Dual 64-position resolution
AD5252: Dual 256-position resolution
AD5251: 50 k
AD5252: 1 k, 10 k, 50 k, 100 k
Nonvolatile memory1 stores wiper setting w/write protection
Power-on refreshed with EEMEM settings in 300 µs typ
EEMEM rewrite time = 540 µs typ
Resistance tolerance stored in nonvolatile memory
12 extra bytes in EEMEM for user-defined information
I2C-compatible serial interface
Direct read/write access of RDAC2 and EEMEM registers
Predefined linear increment/decrement commands
Predefined ±6 dB step change commands
Synchronous or asynchronous dual-channel update
Wiper setting readback
4 MHz bandwidth1 kversion
Single supply 2.7 V to 5.5 V
Dual supply ±2.25 V to ±2.75 V
2 slave address decoding bits allow operation of 4 devices
100-year typical data retention, TA = 55°C
Operating temperature: 40°C to +105°C
APPLICATIONS
Mechanical potentiometer replacement
General-purpose DAC replacement
LCD panel VCOM adjustment
White LED brightness adjustment
RF base station power amp bias control
Programmable gain and offset control
Programmable voltage-to-current conversion
Programmable power supply
Sensor calibrations
GENERAL DESCRIPTION
The AD5251/AD5252 are dual-channel, I2, nonvolatile mem-
ory, digitally controlled potentiometers with 64/256 positions,
respectively. These devices perform the same electronic adjust-
ment functions as mechanical potentiometers, trimmers, and
variable resistors. The parts’ versatile programmability allows
multiple modes of operation, including read/write access in the
RDAC and EEMEM registers, increment/decrement of resistance,
resistance changes in ±6 dB scales, wiper setting readback,
FUNCTIONAL BLOCK DIAGRAM
RDAC1
REGIS-
TER
RDAC3
REGIS-
TER
RDAC1
RDAC3
DATA
CONTROL
COMMAND
DECODE LOGIC
ADDRESS
DECODE LOGIC
CONTROL LOGIC
AD5251/
AD5252
I
2
C
SERIAL
INTERFACE
POWER-
ON RESET
V
DD
A1
W1
B1
A3
W3
B3
V
SS
DGND
SCL
SDA
AD0
AD1
WP
RDAC EEMEM
RAB
TOL
03823-0-001
EEMEM
POWER-ON
REFRESH
Figure 1.
and extra EEMEM for storing user-defined information, such as
memory data for other components, look-up table, or system
identification information.
The AD5251/AD5252 allow the host I2C controllers to write
any of the 64-/256-step wiper settings in the RDAC registers
and store them in the EEMEM. Once the settings are stored,
they are restored automatically to the RDAC registers at system
power-on; the settings can also be restored dynamically.
The AD5251/AD5252 provide additional increment,
decrement, +6 dB step change, and 6 dB step change in
synchronous or asynchronous channel update mode. The
increment and decrement functions allow stepwise linear
adjustments, with a ± 6 dB step change equivalent to doubling
or halving the RDAC wiper setting. These functions are useful
for steep-slope, nonlinear adjustments, such as white LED
brightness and audio volume control.
The AD5251/AD5252 have a patented resistance-tolerance
storing function that allows the user to access the EEMEM and
obtain the absolute end-to-end resistance values of the RDACs
for precision applications.
The AD5251/AD5252 are available in TSSOP-14 packages.
AD5251 has only 50 kresistance options and AD5252 is
available in 1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ options. All parts
are guaranteed to operate over the 40°C to +105°C extended
industrial temperature range.
1 The terms nonvolatile memory and EEMEM are used interchangeably.
2 The terms digital potentiometer and RDAC are used interchangeably.
('lhm \’\’P W
AD5251/AD5252 Data Sheet
Rev. E | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Electrical Characteristics ................................................................. 3
1 kΩ Version .................................................................................. 3
10 kΩ, 50 kΩ, 100 kΩ Versions .................................................. 5
Interface Timing Characteristics ................................................ 7
Absolute Maximum Ratings ............................................................ 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 10
I2C Interface ..................................................................................... 14
I2C Interface General Description ............................................ 14
I2C Interface Detail Description ............................................... 15
I2C-Compatible 2-Wire Serial Bus ........................................... 20
Theory of Operation ...................................................................... 21
Linear Increment/Decrement Commands ............................. 21
±6 dB Adjustments (Doubling/Halving Wiper Setting) ....... 21
Digital Input/Output Configuration........................................ 21
Multiple Devices on One Bus ................................................... 22
Terminal Voltage Operation Range ......................................... 22
Power-Up and Power-Down Sequences .................................. 22
Layout and Power Supply Biasing ............................................ 23
Digital Potentiometer Operation ............................................. 23
Programmable Rheostat Operation ......................................... 23
Programmable Potentiometer Operation ............................... 24
Applications Information .............................................................. 25
LCD Panel VCOM Adjustment .................................................... 25
Current-Sensing Amplifier ....................................................... 25
Adjustable High Power LED Driver ........................................ 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 27
REVISION HISTORY
11/2017—Rev. D to Rev. E
Changes to Features Section and General Description Section ........ 1
Changes to Theory of Operation Section .................................... 21
Changes to Ordering Guide .......................................................... 27
9/2012Rev. C to Rev. D
Changed Temperature Range from 40°C to +85°C to 40°C to
+105°C (Throughout) ...................................................................... 1
Changed EE
AA Leakage Current from 5 µA to 8 µA, Table 1 ........ 4
WP
Changed AA WPEE
AA Leakage Current from 5 µA to 8 µA, Table 2 ........ 5
Changes to Figure 11 and Figure 12 ............................................. 11
12/2011Rev. B to Rev. C
Changes to Theory of Operation Section .................................... 21
Changes to Ordering Guide .......................................................... 27
10/2009Rev. A to Rev. B
Changes to Figure 15 ...................................................................... 12
Changes to Figure 27 ...................................................................... 15
9/2005Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Change to Figure 6 ......................................................................... 10
Changes to Figure 28 ...................................................................... 15
Changes to Figure 29 ...................................................................... 17
Changes to RDAC/EEMEM Quick Commands Section .......... 18
Changes to EEMEM Write Protection Section .......................... 18
Changes to Figure 37 ...................................................................... 22
Deleted Table 13 and Table 14 ...................................................... 23
Change to Figure 42 ....................................................................... 24
Change to Figure 46 ....................................................................... 25
Changes to Ordering Guide .......................................................... 27
6/2004Revision 0: Initial Version
Table L
Data Sheet AD5251/AD5252
Rev. E | Page 3 of 28
ELECTRICAL CHARACTERISTICS
1 kΩ VERSION
VDD = 3 V ± 10% or 5 V ± 10%, VSS = 0 V or VDD/VSS = ±2.5 V ± 10%, VA = VDD, VB = 0 V, 40°C < TA < +105°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ2F2F
1 Max Unit
DC CHARACTERISTICS
RHEOSTAT MODE
Resolution N AD5251 6 Bits
AD5252 8 Bits
Resistor Differential Nonlinearity3F3F
2 R-DNL RWB, RWA = NC, VDD = 5.5 V, AD5251 0.5 ±0.2 +0.5 LSB
RWB, RWA = NC, VDD = 5.5 V, AD5252 1.00 ±0.25 +1.00 LSB
RWB, RWA = NC, VDD = 2.7 V, AD5251 0.75 ±0.30 +0.75 LSB
RWB, RWA = NC, VDD = 2.7 V, AD5252 1.5 ±0.3 +1.5 LSB
Resistor Nonlinearity
2
R-INL
R
WB
, R
WA
= NC, V
DD
= 5.5 V, AD5251
0.5
±0.2
LSB
RWB, RWA = NC, VDD = 5.5 V, AD5252 2.0 ±0.5 +2.0 LSB
RWB, RWA = NC, VDD = 2.7 V, AD5251 1.0 +2.5 +4.0 LSB
RWB, RWA = NC, VDD = 2.7 V, AD5252 –2 +9 +14 LSB
Nominal Resistor Tolerance ΔRAB/RAB TA = 25°C 30 +30 %
Resistance Temperature
Coefficient
(ΔRAB/RAB) × 106/ΔT 650 ppm/°C
Wiper Resistance RW IW = 1 V/R, VDD = 5 V 75 130
IW = 1 V/R, VDD = 3 V 200 300
Channel-Resistance Matching ΔRAB1/ΔRAB3 0.15 %
DC CHARACTERISTICS
POTENTIOMETER DIVIDER MODE
Differential Nonlinearity4F
3 DNL AD5251 0.5 ±0.1 +0.5 LSB
AD5252 1.00 ±0.25 +1.00 LSB
Integral Nonlinearity3 INL AD5251 0.5 ±0.2 +0.5 LSB
AD5252 2.0 ±0.5 +2.0 LSB
Voltage Divider Tempco (ΔVW/VW) × 106/ΔT Code = half scale 25 ppm/°C
Full-Scale Error VWFSE Code = full scale, VDD = 5.5 V,
AD5251
–5 –3 0 LSB
Code = full scale, VDD = 5.5 V,
AD5252
16 11 0 LSB
Code = full scale, VDD = 2.7 V,
AD5251
−6 –4 0 LSB
Code = full scale, VDD = 2.7 V,
AD5252
23 16 0 LSB
Zero-Scale Error VWZSE Code = zero scale, VDD = 5.5 V,
AD5251
0 3 5 LSB
Code = zero scale, VDD = 5.5 V,
AD5252
0 11 16 LSB
Code = zero scale, VDD = 2.7 V,
AD5251
0 4 6 LSB
Code = zero scale, V
DD
= 2.7 V,
AD5252
0
15
LSB
RESISTOR TERMINALS
Voltage Range5F
4 VA, VB, VW VSS VDD V
Capacitance6F
5 A, B CA, CB f = 1 kHz, measured to GND,
code = half scale
85 pF
Capacitance5 W CW f = 1 kHz, measured to GND,
code = half scale
95 pF
Common-Mode Leakage Current ICM VA = VB = VDD/2 0.01 1 µA
<_ur wp="">
AD5251/AD5252 Data Sheet
Rev. E | Page 4 of 28
Parameter Symbol Conditions Min Typ2F2F
1 Max Unit
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH VDD = 5 V, VSS = 0 V 2.4 V
VDD/VSS = 2.7 V/0 V or VDD/VSS = ± 2.5
V
2.1 V
Input Logic Low VIL VDD = 5 V, VSS = 0 V 0.8 V
Output Logic High (SDA) VOH RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0
V
4.9 V
Output Logic Low (SDA) VOL RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0
V
0.4 V
AAWPEE AALeakage Current IWP AAWPEE AA= VDD 8 µA
A0 Leakage Current
I
A0
A0 = GND
µA
Input Leakage Current
(Other than AAWPEE
AA and A0)
II VIN = 0 V or VDD ±1 µA
Input Capacitance5 CI 5 pF
POWER SUPPLIES
Single-Supply Power Range VDD VSS = 0 V 2.7 5.5 V
Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V
Positive Supply Current IDD VIH = VDD or VIL = GND 5 15 µA
Negative Supply Current
I
SS
V
IH
= V
DD
or V
IL
= GND, V
DD
= 2.5 V,
VSS = 2.5 V
–5
µA
EEMEM Data Storing Mode
Current
IDD_STORE VIH = VDD or VIL = GND 35 mA
EEMEM Data Restoring Mode
Current7F
6
IDD_RESTORE VIH = VDD or VIL = GND 2.5 mA
Power Dissipation8F
7 PDISS VIH = VDD = 5 V or VIL = GND 0.075 mW
Power Supply Sensitivity PSS ΔVDD = 5 V ± 10% −0.025 +0.010 +0.025 %/%
ΔVDD = 3 V ± 10% 0.04 +0.02 +0.04 %/%
DYNAMIC CHARACTERISTICS5,
9F
8
Bandwidth 3 dB BW RAB = 1 kΩ 4 MHz
Total Harmonic Distortion THD VA = 1 V rms, VB = 0 V, f = 1 kHz 0.05 %
VW Settling Time tS VA = VDD, VB = 0 V 0.2 µs
Resistor Noise Voltage eN_WB RWB = 500 Ω, f = 1 kHz
(thermal noise only)
3 nV/AAHzEE
Digital Crosstalk CT VA = VDD, VB = 0 V, measure VW with
adjacent RDAC making full-scale
change
80 dB
Analog Coupling CAT Signal input at A1 and measure
the output at W3, f = 1 kHz
72 dB
1 Typical values represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the
relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ version at VDD =
2.7 V, IW = VDD/R for both VDD = 3 V and VDD = 5 V.
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
4 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.
5 Guaranteed by design and not subject to production test.
6 Command 0 NOP should be activated after Command 1 to minimize IDD_READ current consumption.
7 PDISS is calculated from IDD × VDD = 5 V.
8 All dynamic characteristics use VDD = 5 V.
Table 2‘ <_ur wp="">
Data Sheet AD5251/AD5252
Rev. E | Page 5 of 28
10 kΩ, 50 kΩ, 100 kΩ VERSIONS
VDD = +3 V ± 10% or +5 V ± 10%, VSS = 0 V or VDD/VSS = ± 2.5 V ± 10%, VA = VDD, VB = 0 V, 40°C < TA < +105°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ10F
1 Max Unit
DC CHARACTERISTICS
RHEOSTAT MODE
Resolution N AD5251 6 Bits
AD5252 8 Bits
Resistor Differential Nonlinearity11F
2 R-DNL RWB, RWA = NC, AD5251 0.75 ±0.10 +0.75 LSB
R
WB
, R
WA
= NC, AD5252
−1.00
±0.25
LSB
Resistor Nonlinearity2 R-INL RWB, RWA = NC, AD5251 0.75 ±0.25 +0.75 LSB
RWB, RWA = NC, AD5252 2.5 ±1.0 +2.5 LSB
Nominal Resistor Tolerance ΔRAB/RAB TA = 25°C 20 +20 %
Resistance Temperature
Coefficient
(ΔRAB/RAB) × 106/ΔT 650 ppm/°C
Wiper Resistance RW IW = 1 V/R, VDD = 5 V 75 130
IW = 1 V/R, VDD = 3 V 200 300
Channel-Resistance Matching ΔRAB1/ΔRAB2 RAB = 10 kΩ, 50 kΩ 0.15 %
RAB = 100 kΩ 0.05 %
DC CHARACTERISTICS
POTENTIOMETER DIVIDER MODE
Differential Nonlinearity12F
3 DNL AD5251 0.5 ±0.1 +0.5 LSB
AD5252 −1.0 ±0.3 +1.0 LSB
Integral Nonlinearity3 INL AD5251 0.50 ±0.15 +0.50 LSB
AD5252 −1.5 ±0.5 +1.5 LSB
Voltage Divider
Temperature Coefficient
(ΔVW/VW) × 106T Code = half scale 15 ppm/°C
Full-Scale Error VWFSE Code = full scale, AD5251 −1.0 −0.3 0 LSB
Code = full scale, AD5252
−3
−1
LSB
Zero-Scale Error VWZSE Code = zero scale, AD5251 0 0.3 1.0 LSB
Code = zero scale, AD5252 0 1.2 3.0 LSB
RESISTOR TERMINALS
Voltage Range13F
4 VA, VB, VW VSS VDD V
Capacitance14F
5 A, B CA, CB f = 1 kHz, measured to GND,
code = half scale
85 pF
Capacitance5 W CW f = 1 kHz, measured to GND,
code = half scale
95 pF
Common-Mode Leakage Current ICM VA = VB = VDD/2 0.01 1.00 µA
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH VDD = 5 V, VSS = 0 V 2.4 V
V
DD
/V
SS
= +2.7 V/0 V or V
DD
/V
SS
= ±2.5 V
2.1
V
Input Logic Low VIL VDD = 5 V, VSS = 0 V 0.8 V
VDD/VSS = +2.7 V/0 V or VDD/VSS = ±2.5 V 0.6 V
Output Logic High (SDA) VOH RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V 4.9 V
Output Logic Low (SDA) VOL RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V 0.4 V
AAWPEE AALeakage Current IWP AAWPEE
AA = VDD 8 µA
A0 Leakage Current IA0 A0 = GND 3 µA
Input Leakage Current
(Other than AAWPEE
AA and A0)
II VIN = 0 V or VDD ±1 µA
Input Capacitance5 CI 5 pF
AD5251/AD5252 Data Sheet
Rev. E | Page 6 of 28
Parameter Symbol Conditions Min Typ10F
1 Max Unit
POWER SUPPLIES
Single-Supply Power Range VDD VSS = 0 V 2.7 5.5 V
Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V
Positive Supply Current IDD VIH = VDD or VIL = GND 5 15 µA
Negative Supply Current
I
SS
V
IH
= V
DD
or V
IL
= GND, V
DD
= 2.5 V,
VSS = −2.5 V
−5
µA
EEMEM Data Storing Mode
Current
IDD_STORE VIH = VDD or VIL = GND, TA = 0°C to 105°C 35 mA
EEMEM Data Restoring Mode
Current15F
6
IDD_RESTORE VIH = VDD or VIL = GND, TA = 0°C to 105°C 2.5 mA
Power Dissipation16F
7 PDISS VIH = VDD = 5 V or VIL = GND 0.075 mW
Power Supply Sensitivity PSS ΔVDD = 5 V ± 10% −0.005 +0.002 +0.005 %/%
ΔVDD = 3 V ± 10% −0.010 +0.002 +0.010 %/%
DYNAMIC CHARACTERISTICS
5,
17F
8
3 dB Bandwidth BW RAB = 10 kΩ/50 kΩ/100 kΩ 400/80/40 kHz
Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz 0.05 %
VW Settling Time tS VA = VDD, VB = 0 V,
RAB = 10 kΩ/50 kΩ/100 kΩ
1.5/7/14 µs
Resistor Noise Voltage eN_WB RAB = 10 kΩ/50 kΩ/100 kΩ,
code = midscale, f = 1 kHz
(thermal noise only)
9/20/29 nV/AAHzEE
Digital Crosstalk CT VA = VDD, VB = 0 V, measure VW with
adjacent RDAC making full-scale
change
−80 dB
Analog Coupling CAT Signal input at A1 and measure
output at W3, f = 1 kHz
−72 dB
1 Typical values represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the
relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ version at VDD = 2.7 V,
IW = VDD/R for both VDD = 3 V and VDD = 5 V.
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
4 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.
5 Guaranteed by design and not subject to production test.
6 Command 0 NOP should be activated after Command 1 to minimize IDD_READ current consumption.
7 PDISS is calculated from IDD × VDD = 5 V.
8 All dynamic characteristics use VDD = 5 V.
Table 3‘ Interface Timing and EEMEM Reliability Characteristics (All Pans)'
Data Sheet AD5251/AD5252
Rev. E | Page 7 of 28
INTERFACE TIMING CHARACTERISTICS
All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching
characteristics are measured using both VDD = 3 V and 5 V.
Table 3. Interface Timing and EEMEM Reliability Characteristics (All Parts)18F
1
Parameter Symbol Conditions Min Typ Max Unit
INTERFACE TIMING
SCL Clock Frequency fSCL
400 kHz
tBUF Bus-Free Time Between Stop and Start t1 1.3 µs
tHD;STA Hold Time (Repeated Start) t2 After this period, the first clock pulse is
generated.
0.6 µs
tLOW Low Period of SCL Clock t3 1.3 µs
tHIGH High Period of SCL Clock t4 0.6 µs
tSU;STA Set-up Time for Start Condition t5 0.6 µs
tHD;DAT Data Hold Time t6 0 0.9 µs
tSU ;DAT Data Set-up Time t7 100 ns
tF Fall Time of Both SDA and SCL Signals t8 300 ns
t
R
Rise Time of Both SDA and SCL Signals
t
9
300
ns
t
SU;STO
Set-up Time for Stop Condition
t
10
0.6
µs
EEMEM Data Storing Time tEEMEM_STORE 26 ms
EEMEM Data Restoring Time at Power-On19F
2 tEEMEM_RESTORE1 VDD rise time dependent. Measure
without decoupling capacitors at VDD
and VSS.
300 µs
EEMEM Data Restoring Time upon Restore
Command or Reset Operation2
tEEMEM_RESTORE2 VDD = 5 V. 300 µs
EEMEM Data Rewritable Time (Delay Time
After Power-On or Reset Before EEMEM
Can Be Written)
tEEMEM_REWRITE 540 µs
FLASH/EE MEMORY RELIABILITY
Endurance20F
3 100 k cycles
Data Retention21F
4 100 Years
1 Guaranteed by design; not subject to production test. See Figure 23 for location of measured values.
2 During power-up, all outputs are preset to midscale before restoring the EEMEM contents. RDAC0 has the shortest EEMEM data restoring time, whereas RDAC3 has the longest.
3 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117, and measured at 40°C, +25°C, and +10C; typical endurance at +25°C is 700,000
cycles.
4 Retention lifetime equivalent at junction temperature TJ = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates
with junction temperature in Flash/EE memory.
ESD CAUTION A M ESD (alemosmic charge) sensi‘ive devke. Chavged deers and (Mun board; (an dwschavge wwhom daemon Mmaugh m; plodud feawve; paremed m pvopnemy pvmemon (ivzumy, damage may mum on dams summed m hwgh EnEvgy ESD Thevefove, pvopev ESD pvezaufions mama be (aken w avmd pevfovmance degudamm av loss or funmonalmy
AD5251/AD5252 Data Sheet
Rev. E | Page 8 of 28
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to GND −0.3 V, +7 V
VSS to GND +0.3 V, −7 V
VDD to VSS 7 V
VA, VB, VW to GND VSS, VDD
Maximum Current
IWB, IWA Pulsed ±20 mA
I
WB
Continuous (R
WB
≤ 1 kΩ, A Open)
0F0F
1
±5 mA
IWA Continuous (RWA ≤ 1 kΩ, B Open)1 ±5 mA
IAB Continuous
(RAB = 1 kΩ/10 kΩ/50 kΩ/100 kΩ)1
±5 mA/±500 µA/
±100 µA/±50 µA
Digital Inputs and Output Voltage to GND 0 V, 7 V
Operating Temperature Range −40°C to +105°C
Maximum Junction Temperature (TJMAX) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
TSSOP-14 Thermal Resistance1F1F
2 θJA 136°C/W
1 Maximum terminal current is bound by the maximum applied voltage across
any two of the A, B, and W terminals at a given resistance, the maximum
current handling of the switches, and the maximum power dissipation of the
package. VDD = 5 V.
2 Package power dissipation = (TJMAX − TA)/θJA.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Data Sheet AD5251/AD5252
Rev. E | Page 9 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
AD0
WP
W1
SDA
A1
B1
V
DD 14
13
12
11
10
9
8
B3
A3
AD1
V
SS
SCL
DGND
W3
03823-0-002
AD5251/
AD5252
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or ±2.7 V for dual supply, where
VDDVSS5.5 V. VDD must be able to source 35 mA for 26 ms when storing data to EEMEM.
2 AD0 I2C Device Address 0. AD0 and AD1 allow four AD5251/AD5252 devices to be addressed.
3 AAWPEE Write Protect, Active Low. VWPVDD + 0.3 V.
4 W1 Wiper Terminal of RDAC1. VSSVW1VDD.22F
1
5
B1
B Terminal of RDAC1. V
SS
V
B1
V
DD
.
1
6 A1 A Terminal of RDAC1. VSS ≤ VA1VDD.1
7 SDA Serial Data Input/Output Pin. Shifts in one bit at a time upon positive clock edges. MSB loaded first.
Open-drain MOSFET requires pull-up resistor.
8 VSS Negative Supply. Connect to 0 V for single supply or 2.7 V for dual supply, where VDDVSS ≤ +5.5 V. If
VSS is used in dual supply, VSS must be able to sink 35 mA for 26 ms when storing data to EEMEM.
9 SCL Serial Input Register Clock Pin. Shifts in one bit at a time upon positive clock edges. VSCL ≤ (VDD + 0.3 V).
Pull-up resistor is recommended for SCL to ensure minimum power.
10 DGND Digital Ground. Connect to system analog ground at a single point.
11 AD1 I2C Device Address 1. AD0 and AD1 allow four AD5251/AD5252 devices to be addressed.
12 A3 A Terminal of RDAC3. VSS ≤ VA3VDD.1
13 B3 B Terminal of RDAC3. VSSVB3VDD.1
14 W3 Wiper Terminal of RDAC3. VSS VW3 VDD.1
1 For quad-channel device software compatibility, the dual potentiometers in the parts are designated as RDAC1 and RDAC3.
AD5251/AD5252 Data Sheet
Rev. E | Page 10 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
R-INL (LSB)
CODE (Decimal)
03823-0-015
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0 32 64 96 128 160 192 224 256
T
A
= –40°C, +25°C, +85°C, +125°C
Figure 3. R-INL vs. Code
R-DNL (LSB)
CODE (Decimal)
03823-0-016
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
032 64 96 128 160 192 224 256
T
A
= –40°C, +25°C, +85°C, +125°C
Figure 4. R-DNL vs. Code
INL (LSB)
CODE (Decimal)
03823-0-017
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0 32 64 96 128 160 192 224 256
T
A
= –40°C, +25°C, +85°C, +125°C
Figure 5. INL vs. Code
DNL (LSB)
CODE (Decimal)
03823-0-018
1.0
0.8
0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
032 64 96 128 160 192 224 256
T
A
= –40°C, +25°C, +85°C, +125°C
Figure 6. DNL vs. Code
I
DD
(µA)
TEMPERATURE (°C)
03823-0-019
–10
–8
–6
–4
–2
0
2
4
6
8
10
–40 –20 0 20 40 60 80 100 120
I
DD
@ V
DD
= 5.5V
I
DD
@ V
DD
= 2.7V
I
SS
@ V
DD
= 2.7V, V
SS
= –2.7V
Figure 7. Supply Current vs. Temperature
DIGITAL INPUT VOLTAGE (V)
03823-0-020
0.0001
0.01
0.001
0.1
1
10
0 1 2 3 4 5 6
V
DD
= 5.5V
V
DD
= 2.7V
I
DD (mA)
Figure 8. Supply Current vs. Digital Input Voltage, TA = 25°C
Data Sheet AD5251/AD5252
Rev. E | Page 11 of 28
R
WB
()
V
BIAS
(V)
03823-0-021
20
0
40
60
80
100
120
140
160
200
240
180
220
1
0 2 3 4 56
V
DD
= 2.7V
T
A
= 25°C
V
DD
= 5.5V
T
A
= 25°C
DATA = 0x00
Figure 9. Wiper Resistance vs. VBIAS
TEMPERATURE (°C)
03823-0-022
–6
–4
–2
0
2
4
6
–40 –20 0 20 40 60 80 100 120
R
WB
(%)
Figure 10. Change of RWB vs. Temperature
03823-0-023
CODE (Decimal)
0 32 64 96 128160
10k
100k
50k
192224256
RHEOSTAT MODE TEMPCO (ppm/°C)
V
DD
= 5V
T
A
=–40°C TO +85°C
V
A
= V
DD
V
B
= 0V
500
550
600
650
700
750
800
850
900
950
1000
Figure 11. AD5252 Rheostat Mode Tempco ∆RWB/∆T vs. Code
03823-0-024
CODE (Decimal)
0
20
25
10
5
15
30
35
40
45
50
032 64 96 128 160 192 224 256
POTENTIOMETER MODE TEMPCO (ppm/°C)
100k
50kΩ
10kΩ
V
DD
= 5V
T
A
= –40°C TO +85°C
V
A
= V
DD
V
B
= 0V
Figure 12. AD5252 Potentiometer Mode Tempco ∆VWB/∆T vs. Code
60
48
24
–12
0
–36
–54
30
18
6
–42
GAIN (dB)
1k 10k
10 100 100k 1M 10M
FREQUENCY (Hz)
03823-0-025
0xFF
0x80
0x40
0x20
0x10
0x08 0x04 0x02 0x01 0x00
Figure 13. AD5252 Gain vs. Frequency vs. Code, RAB = 1 kΩ, TA = 25°C
–60
–48
–24
–12
0
–36
–54
–30
–18
6
–42
GAIN (dB)
1k 10k10 100 100k 1M 10M
FREQUENCY (Hz)
03823-0-026
0xFF
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
0x00
Figure 14. AD5252 Gain vs. Frequency vs. Code, RAB = 10 kΩ , TA = 25°C
3 an v (Hqiwumv \ \ : aim 2nnv m2 2nm‘ Mmflus A Cm! mnv (M 2am mum
AD5251/AD5252 Data Sheet
Rev. E | Page 12 of 28
–60
–48
–24
–12
0
–36
–54
–30
–18
–6
–42
GAIN (dB)
1k 10k10 100 100k 1M 10M
FREQUENCY (Hz)
03823-0-027
0xFF
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
0x00
Figure 15. AD5252 Gain vs. Frequency vs. Code, RAB = 50 kΩ , TA = 25°C
–60
–48
–24
–12
0
–36
–54
–30
–18
–6
–42
GAIN (dB)
1k 10k10 100 100k 1M 10M
FREQUENCY (Hz)
03823-0-028
0xFF
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
0x00
Figure 16. AD5252 Gain vs. Frequency vs. Code, RAB = 100 kΩ , TA = 25°C
R
AB
()
CODE (Decimal)
03823-0-029
–100
–80
–60
–40
–20
0
20
40
60
80
100
0 32 64 96 128 160 192 224 256
100k
1k
10k
V
DD
= 5.5V
50k
Figure 17. AD5252 ΔRAB vs. Code, TA = 25°C
CLOCK FREQUENCY (Hz)
03823-0-030
0
0.6
0.4
0.2
0.8
1.0
1.2
1 10010 1k 10k 100k 1M 10M
V
DD
= 2.7V
T
A
= 25°C
V
DD
= 5.5V
I
DD
(mA)
Figure 18. Supply Current vs. Digital Input Clock Frequency
03823-0-031
DIGITAL FEEDTHROUGH
CLK
V
DD
= 5V
V
W
400ns/DIV
Figure 19. Clock Feedthrough and Midscale Transition Glitch
03823-0-032
V
WB1
(0x3F
STORED
IN EEMEM)
V
WB3
(0x3F
STORED
IN EEMEM)
V
DD
= VA1 = VA3 = 3.3V
GND = VB1 = VB3
MIDSCALE
PRESET
RESTORE RDAC1
SETTING TO 0x3F
RESTORE RDAC3
SETTING TO 0x3F
V
DD
(NO DE-
COUPLING
CAPS)
MIDSCALE
PRESET
Figure 20. tEEMEM_RESTORE of RDAC0 and RDAC3
Data Sheet AD5251/AD5252
Rev. E | Page 13 of 28
CODE (Decimal)
03823-0-033
0
3
2
1
4
5
6
0 8 16 24 32 40 48 56 64
THEORETICAL I
WB_MAX
(mA)
R
AB
= 1k
V
A
= V
B
= OPEN
T
A
= 25°C
R
AB
= 10k
R
AB
= 50k
R
AB
= 100k
Figure 21. AD5251 IWB_MAX vs. Code
CODE (Decimal)
03823-0-034
0
3
2
1
4
5
6
032 64 96 128 160 192 224 256
THEORETICAL I
WB_MAX
(mA)
R
AB
= 1k
V
A
= V
B
=OPEN
T
A
= 25°C
R
AB
= 10k
R
AB
= 50k
R
AB
= 100k
Figure 22. AD5252 IWB_MAX vs. Code
AD5251/AD5252 Data Sheet
Rev. E | Page 14 of 28
I2C INTERFACE
03823-0-003
t
1
t
2
t
3
t
8
t
8
t
9
t
9
t
6
t
4
t
7
t
5
t
2
t
10
PS S
SCL
SD
A
P
Figure 23. I2C Interface Timing Diagram
I2C INTERFACE GENERAL DESCRIPTION
R/W A/AS SLAVE ADDRESS
(7-BIT) A
0 WRITE
A
INSTRUCTIONS
(8-BIT)
DATA TRANSFERRED
(N BYTES + ACKNOWLEDGE)
DATA
(8-BIT) P
03823-0-004
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
S = START CONDITION
P = STOP CONDITION
A = ACKNOWLEDGE (SDA LOW)
A = NOT ACKNOWLEDGE (SDA HIGH)
R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW
Figure 24. I2C—Master Writing Data to Slave
R/W AS SLAVE ADDRESS
(7-BIT)
1 READ DATA TRANSFERRED
(N BYTES + ACKNOWLEDGE)
DATA
(8-BIT)
DATA
(8-BIT) P
03823-0-005
AA
Figure 25. I2C—Master Reading Data from Slave
R/W R/WS SLAVE ADDRESS
(7-BIT)
READ OR WRITE (N BYTES +
ACKNOWLEDGE)
SLAVE ADDRESS
DATA A
S
03823-0-006
REPEATED START READ
OR WRITE
DIRECTION OF TRANSFER MAY
CHANGE AT THIS POINT
AA/A
(N BYTES +
ACKNOWLEDGE)
DATA P
A/A
Figure 26. I2C—Combined Write/Read
\<—(\>
Data Sheet AD5251/AD5252
Rev. E | Page 15 of 28
I2C INTERFACE DETAIL DESCRIPTION
0 WRITE
03823-0-007
S 0 1 0 1 1 A
D
1
A
D
0
0 A A
4A
3A
2A
1A
0A PDATA0
(1 BYTE +
ACKNOWLEDGE)
SLAVE ADDRESS INSTRUCTIONS
AND ADDRESS
CMD/
REG
EE/
RDAC
0 REG
A/
A
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
S = START CONDITION
P = STOP CONDITION
A = ACKNOWLEDGE (SDA LOW)
A = NOT ACKNOWLEDGE (SDA HIGH)
R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW
CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTERACCESS BIT, LOGIC LOW
EE/RDAC = EEMEM REGISTER, LOGIC HIGH/RDAC REGISTER, LOGIC LOW
A4, A3, A2, A1, A0 = RDAC/EEMEM REGISTER ADDRESSES
Figure 27. Single Write Mode
0 WRITE
03823-0-008
S 0 1 0 1 1 A
D
1
A
D
0
0 A A
4A
3A
2A
1A
0PA ARDAC1
DATA RDAC3
DATA
0
(N BYTES +
ACKNOWLEDGE)
RDAC SLAVE ADDRESS RDAC INSTRUCTIONS
AND ADDRESS
CMD/
REG
EE/
RDAC
0 REG
A/
A
AX
DATA
Figure 28. Consecutive Write Mode
Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/AWE
A = 0, CMD/AREGE
A = 0, EE/ARDACE
A = 0)
A4 A3 A2 A1 A0 RDAC Data Byte Description
0 0 0 0 0 Reserved
0 0 0 0 1 RDAC1 6-/8-bit wiper setting (2 MSB of AD5251 are X)
0 0 0 1 0 Reserved
0 0 0 1 1 RDAC3 6-/8-bit wiper setting (2 MSB of AD5251 are X)
0 0 1 0 0 Reserved
: : : : : :
: : : : : :
0 1 1 1 1 Reserved
and Us Defined Dal EMEM R R/W MD/REG (RDAC huwn m F RDAC and U Data from E M R/W MD/REG (RDAC
AD5251/AD5252 Data Sheet
Rev. E | Page 16 of 28
RDAC/EEMEM Write
Setting the wiper position requires an RDAC write operation.
The single write operation is shown in Figure 27, and the
consecutive write operation is shown in Figure 28. In the
consecutive write operation, if the AARDACEE
AA is selected and the
address starts at 00001, the first data byte goes to RDAC1 and
the second data byte goes to RDAC3. The RDAC address is
shown in Table 6.
While the RDAC wiper setting is controlled by a specific RDAC
register, each RDAC register corresponds to a specific EEMEM
location, which provides nonvolatile wiper storage functionality.
The addresses are shown in Table 7. The single and consecutive
write operations also apply to EEMEM write operations.
There are 12 nonvolatile memory locations: EEMEM4 to
EEMEM15. Users can store a total of 12 bytes of information,
such as memory data for other components, look-up tables, or
system identification information.
In a write operation to the EEMEM registers, the device disables
the I2C interface during the internal write cycle. Acknowledge
polling is required to determine the completion of the write
cycle. See the EEMEM Write-Acknowledge Polling section.
RDAC/EEMEM Read
The AD5251/AD5252 provide two different RDAC or EEMEM
read operations. For example, Figure 29 shows the method of
reading the RDAC0 to RDAC3 contents without specifying the
address, assuming Address RDAC0 was already selected in the
previous operation. If an RDAC_N address other than RDAC0
was previously selected, readback starts with Address N, followed
by N + 1, and so on.
Figure 30 illustrates a random RDAC or EEMEM read
operation. This operation allows users to specify which RDAC
or EEMEM register is read by issuing a dummy write command
to change the RDAC address pointer and then proceeding with
the RDAC read operation at the new address location.
Table 7. Addresses for Writing (Storing) RDAC Settings
and User-Defined Data to EEMEM Registers
(R/ EE
AA = 0, CMD/AAREGEE
AA = 0, EE/AARDACEE
AA = 1)
W
A4 A3 A2 A1 A0 Data Byte Description
0
0
0
0
0
Reserved
0 0 0 0 1 Store RDAC1 setting to EEMEM123F
1
0 0 0 1 0 Reserved
0 0 0 1 1 Store RDAC3 setting to EEMEM31
0 0 1 0 0 Store user data to EEMEM4
0 0 1 0 1 Store user data to EEMEM5
0 0 1 1 0 Store user data to EEMEM6
0 0 1 1 1 Store user data to EEMEM7
0 1 0 0 0 Store user data to EEMEM8
0 1 0 0 1 Store user data to EEMEM9
0 1 0 1 0 Store user data to EEMEM10
0 1 0 1 1 Store user data to EEMEM11
0 1 1 0 0 Store user data to EEMEM12
0 1 1 0 1 Store user data to EEMEM13
0 1 1 1 0 Store user data to EEMEM14
0 1 1 1 1 Store user data to EEMEM15
Users can store any of the 64 RDAC settings directly to the EEMEM for AD5251,
or any of the 256 RDAC settings directly to the EEMEM for the AD5252. This is
not limited to current RDAC wiper setting.
Table 8. Addresses for Reading (Restoring) RDAC Settings
and User Data from EEMEM
(R/AAWEE
AA = 1, CMD/AAREGEE
AA = 0, EE/AARDACEE
AA = 1)
A4 A3 A2 A1 A0 Data Byte Description
0 0 0 0 0 Reserved
0
0
0
0
1
Read RDAC1 setting from EEMEM1
0 0 0 1 0 Reserved
0 0 0 1 1 Read RDAC3 setting from EEMEM3
0 0 1 0 0 Read user data from EEMEM4
0 0 1 0 1 Read user data from EEMEM5
0 0 1 1 0 Read user data from EEMEM6
0 0 1 1 1 Read user data from EEMEM7
0 1 0 0 0 Read user data from EEMEM8
0 1 0 0 1 Read user data from EEMEM9
0 1 0 1 0 Read user data from EEMEM10
0 1 0 1 1 Read user data from EEMEM11
0 1 1 0 0 Read user data from EEMEM12
0 1 1 0 1 Read user data from EEMEM13
0 1 1 1 0 Read user data from EEMEM14
0 1 1 1 1 Read user data from EEMEM15
Data Sheet AD5251/AD5252
Rev. E | Page 17 of 28
1 READ
03823-0-009
S 0 1 0 1 1 A
D
1
A
D
0
1 A PARDAC1
EEMEM OR REGISTER DATA RDAC3
EEMEM OR REGISTER DATA
SLAVE ADDRESS (N BYTES + ACKNOWLEDGE)
A/
A
AX
DATA
Figure 29. RDAC Current Read (Restricted to Previously Selected Address Stored in the Register)
PS SLAVE ADDRESS
0 WRITE
SLAVE ADDRESSINSTRUCTION AND
ADDRESS A1S
03823-0-010
REPEATED START 1 READ
A0A
(N BYTES + ACKNOWLEDGE)
RDAC OR
EEMEM DATA A/A
Figure 30. RDAC or EEMEM Random Read
0 WRITE
03823-0-011
1 CMD
S 0 1 0 1 1 A
D
1
A
D
0
0 A C
3C
2C
1C
0A
2A
1A
0A P
RDAC SLAVE ADDRESS
CMD/
REG
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
S = START CONDITION
P = STOP CONDITION
A = ACKNOWLEDGE (SDA LOW)
A = NOT ACKNOWLEDGE (SDA HIGH)
AD1, AD0 = I
2
C DEVICE ADDRESS BITS; MUST MATCH WITH THE LOGIC STATES AT PINS AD1, AD0
R/W = READ ENABLE BIT, LOGIC HIGH/WRITE ENABLE BIT, LOGIC LOW
CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTER ACCESS BIT, LOGIC LOW
C3, C2, C1, C0 = COMMAND BITS
A2, A1, A0 = RDAC/EEMEM REGISTER ADDRESSES
Figure 31. RDAC Quick Command Write (Dummy Write)
CMD/ REG
AD5251/AD5252 Data Sheet
Rev. E | Page 18 of 28
RDAC/EEMEM Quick Commands
The AD5251/AD5252 feature 12 quick commands that facilitate
easy manipulation of RDAC wiper settings and provide RDAC-
to-EEMEM storing and restoring functions. The command
format is shown in Figure 31, and the command descriptions
are shown in Table 9.
When using a quick command, issuing a third byte is not needed,
but is allowed. The quick commands reset and store RDAC to
EEMEM require acknowledge polling to determine whether the
command has finished executing.
RAB Tolerance Stored in Read-Only Memory
The AD5251/AD5252 feature patented RAB tolerances storage in
the nonvolatile memory. The tolerance of each channel is stored
in the memory during the factory production and can be read
by users at any time. The knowledge of the stored tolerance,
which is the average of RAB over all codes (see Figure 16), allows
users to predict RAB accurately. This feature is valuable for
precision, rheostat mode, and open-loop applications in which
knowledge of absolute resistance is critical.
The stored tolerances reside in the read-only memory and are
expressed as percentages. Each tolerance is stored in two memory
locations (see Table 10 ). The tolerance data is expressed in sign
magnitude binary format stored in two bytes; an example is shown
in Figure 32. For the first byte in Register N, the MSB is designated
for the sign (0 = + and 1 = ) and the 7 LSB is designated for the
integer portion of the tolerance.
For the second byte in Register N + 1, all eight data bits are
designated for the decimal portion of tolerance. As shown in
Table 10 and Figure 32, for example, if the rated RAB is 10 kΩ
and the data readback from Address 11000 shows 0001 1100
and Address 11001 shows 0000 1111, then RDAC0 tolerance
can be calculated as
MSB: 0 = +
Next 7 MSB: 001 1100 = 28
8 LSB: 0000 1111 = 15 × 2–8 = 0.06
Tolerance = 28.06% and, therefore,
RAB_ACTUAL = 12.806 kΩ
EEMEM Write-Acknowledge Polling
After each write operation to the EEMEM registers, an
internal write cycle begins. The I2C interface of the device is
disabled. To determine if the internal write cycle is complete
and the I2C interface is enabled, interface polling can be
executed. I2C interface polling can be conducted by sending a
start condition, followed by the slave address and the write bit.
If the I2C interface responds with an ACK, the write cycle is
complete and the interface is ready to proceed with further
operations. Other-wise, I2C interface polling can be repeated
until it succeeds. Command 2 and Command 7 also require
acknowledge polling.
EEMEM Write Protection
Setting the AAWPEE
AA pin to logic low after EEMEM programming
protects the memory and RDAC registers from future write
operations. In this mode, the EEMEM and RDAC read
operations function as normal.
Table 9. RDAC-to-EEMEM Interface and RDAC Operation Quick Command Bits (CMD/AA REGEE
AA = 1, A2 = 0)
C3 C2 C1 C0 Command Description
0 0 0 0 NOP
0 0 0 1 Restore EEMEM (A1, A0) to RDAC (A1, A0)24F
1
0 0 1 0 Store RDAC (A1, A0) to EEMEM (A1, A0)
0
0
1
1
Decrement RDAC (A1, A0) 6 dB
0
1
0
0
Decrement all RDACs 6 dB
0 1 0 1 Decrement RDAC (A1, A0) one step
0 1 1 0 Decrement all RDACs one step
0 1 1 1 Reset: restore EEMEMs to all RDACs
1 0 0 0 Increment RDACs (A1, A0) 6 dB
1 0 0 1 Increment all RDACs 6 dB
1 0 1 0 Increment RDACs (A1, A0) one step
1 0 1 1 Increment all RDACs one step
1 1 0 0 Reserved
: : : : :
: : : : :
1
1
1
1
Reserved
1 This command leaves the device in the EEMEM read power state, which consumes power. Issue the NOP command to return the device to its idle state.
Data Sheet AD5251/AD5252
Rev. E | Page 19 of 28
Table 10. Address Table for Reading Tolerance (CMD/AREGE
A = 0, EE/ARDACE
A = 1, A4 = 1)
A4 A3 A2 A1 A0 Data Byte Description
0 0 0 0 0 Reserved
: : : : : :
: : : : : :
1 1 0 0 1 Reserved
1 1 0 1 0 Sign and 7-bit integer values of RDAC1 tolerance (read only)
1 1 0 1 1 8-bit decimal value of RDAC1 tolerance (read only)
1 1 1 0 0 Reserved
1 1 1 0 1 Reserved
1 1 1 1 0 Sign and 7-bit integer values of RDAC3 tolerance (read only)
1 1 1 1 1 8-bit decimal value of RDAC3 tolerance (read only)
03823-0-012
AA A
D7 D6 D5 D4 D3 D2 D1 D0
SIGN
SIGN 7 BITS FOR INTEGER NUMBER
2
6
2
5
2
4
2
3
2
2
2
1
2
0
D7 D6 D5 D4 D3 D2 D1 D0
8 BITS FOR DECIMAL NUMBER
2
–8
2
–1
2
–2
2
–3
2
–4
2
–5
2
–6
2
–7
Figure 32. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions (Unit Is Percent, Only Data Bytes Are Shown)
‘ \ \ \ W mmn w EDIE-£9-43»- \~ awb a (“i 1,- R/ W evlces WW «dam: by MD/RE
AD5251/AD5252 Data Sheet
Rev. E | Page 20 of 28
I2C-COMPATIBLE 2-WIRE SERIAL BUS
SDA
FRAME 1
SLAVE ADDRESS BYTE FRAME 2
INSTRUCTION BYTE
SCL
ACK. BY
AD525x
ACK. BY
AD525x ACK. BY
AD525x
FRAME 1
DATA BYTE
STOP BY
MASTER
03823-0-013
START BY
MASTER
0
1
1
0
1
1
AD1
AD0
R/W
X
X
X
X
X
X
X
X
D7
D6
D5
D4 D3 D2 D1 D0
9
1
9
1
9
Figure 33. General I2C Write Pattern
03823-0-014
SDA
FRAME 1
SLAVE ADDRESS BYTE FRAME 2
RDAC REGISTER
SCL
ACK. BY
AD525x NO ACK. BY
MASTER
STOP BY
MASTER
START BY
MASTER
0
1
101 1 AD1 AD0 D7 D6 D5 D4 D3 D2 D1 D0
9 1 9
R/W
Figure 34. General I2C Read Pattern
The first byte of the AD5251/AD5252 is a slave address byte
(see Figure 33 and Figure 34). It has a 7-bit slave address and an
R/AAWEE
AA bit. The 5 MSB of the slave address is 01011, and the next
2 LSB is determined by the states of the AD1 and AD0 pins.
AD1 and AD0 allow the user to place up to four
AD5251/AD5252 devices on one bus.
AD5251/AD5252 can be controlled via an I2C-compatible serial
bus and are connected to this bus as slave devices. The 2-wire
I2C serial bus protocol (see Figure 33 and Figure 34) follows:
1. The master initiates a data transfer by establishing a start
condition, such that SDA goes from high to low while SCL
is high (see Figure 33). The following byte is the slave address
byte, which consists of the 5 MSB of a slave address defined
as 01011. The next two bits are AD1 and AD0, I2C device
address bits. Depending on the states of their AD1 and
AD0 bits, four AD5251/AD5252 devices can be addressed
on the same bus. The last LSB, the R/AAWEE
AA bit, determines
whether data is read from or written to the slave device.
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is called an acknowledge bit). At
this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to or read
from its serial register.
2. In the write mode (except when restoring EEMEM to the
RDAC register), there is an instruction byte that follows
the slave address byte. The MSB of the instruction byte is
labeled CMD/AAREGEE
AA. MSB = 1 enables CMD, the command
instruction byte; MSB = 0 enables general register writing.
The third MSB in the instruction byte, labeled EE/AARDACEE
AA,
is true when MSB = 0 or when the device is in general
writing mode. EE enables the EEMEM register, and REG
enables the RDAC register. The 5 LSB, A4 to A0, designates
the addresses of the EEMEM and RDAC registers (see
Figure 27 and Figure 28). When MSB = 1 or when the device
is in CMD mode, the four bits following the MSB are C3 to
C1, which correspond to 12 predefined EEMEM controls
and quick commands; there are also four factory-reserved
commands. The 3 LSBA2, A1, and A0are addresses,
but only 001 and 011 are used for RDAC1 and RDAC3,
respectively (see Figure 31). After acknowledging the
instruction byte, the last byte in the write mode is the data
byte. Data is transmitted over the serial bus in sequences of
nine clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high period
of SCL (see Figure 33).
3. In current read mode, the RDAC0 data byte immediately
follows the acknowledgment of the slave address byte.
After an acknowledgement, RDAC1 follows, then RDAC2,
and so on. (There is a slight difference in write mode,
where the last eight data bits representing RDAC3 data are
followed by a no acknowledge bit.) Similarly, the transitions
on the SDA line must occur during the low period of SCL
and remain stable during the high period of SCL (see
Figure 34). Another reading method, random read
method, is shown in Figure 30.
4. When all data bits have been read or written, a stop
condition is established by the master. A stop condition is
defined as a low-to-high transition on the SDA line that
occurs while SCL is high. In write mode, the master pulls
the SDA line high during the 10th clock pulse to establish a
stop condition (see Figure 33). In read mode, the master
issues a no acknowledge for the ninth clock pulse, that is,
the SDA line remains high. The master brings the SDA line
low before the 10th clock pulse and then brings the SDA
line high to establish a stop condition (see Figure 34).
require: a pullrup m hand, 5 L and W
Data Sheet AD5251/AD5252
Rev. E | Page 21 of 28
THEORY OF OPERATION
The AD5251/AD5252 are dual-channel digital potentiometers
that allow 64/256 linear resistance step adjustments. The
AD5251/AD5252 employ double-gate CMOS EEPROM
technology, which allows resistance settings and user-defined
data to be stored in the EEMEM registers. The EEMEM is
nonvolatile, such that settings remain when power is removed.
The RDAC wiper settings are restored from the nonvolatile
memory settings during device power-up and can also be
restored at any time during operation.
The AD5251/AD5252 resistor wiper positions are determined
by the RDAC register contents. The RDAC register acts like a
scratch-pad register, allowing unlimited changes of resistance
settings. RDAC register contents can be changed using the
devices serial I2C interface. The format of the data-words and
the commands to program the RDAC registers are discussed in
the I2C Interface Detail Description section.
The four RDAC registers have corresponding EEMEM memory
locations that provide nonvolatile storage of resistor wiper position
settings. The AD5251/AD5252 provide commands to store the
RDAC register contents to their respective EEMEM memory
locations. During subsequent power-on sequences, the RDAC
registers are automatically loaded with the stored value.
Whenever the EEMEM write operation is enabled, the device
activates the internal charge pump and raises the EEMEM cell
gate bias voltage to a high level; this essentially erases the current
content in the EEMEM register and allows subsequent storage
of the new content. Saving data to an EEMEM register consumes
about 35 mA of current and lasts approximately 26 ms. Because
of charge-pump operation, all RDAC channels may experience
noise coupling during the EEMEM writing operation.
The EEMEM restore time in power-up or during operation is
about 300 µs. Note that the power-up EEMEM refresh time
depends on how fast VDD reaches its final value. As a result, any
supply voltage decoupling capacitors limits the EEMEM restore
time during power-up. For example, Figure 20 shows a power-
up profile of the VDD where there is no decoupling capacitor and
the applied power is a digital signal. The device initially resets
the measured RDACs to midscale before restoring the EEMEM
contents. By default, EEMEM is loaded at midscale until a new
value is loaded. The omission of the decoupling capacitors
should only be considered when the fast restoring time is
absolutely needed in the application. In addition, users should
issue a NOP Command 0 immediately after using Command 1
to restore the EEMEM setting to RDAC, thereby minimizing
supply current dissipation. Reading user data directly from
EEMEM does not require a similar NOP command execution.
In addition to the movement of data between RDAC and
EEMEM registers, the AD5251/AD5252 provide other shortcut
commands that facilitate programming, as shown in Table 11.
Table 11. Quick Commands
Command Description
0 N O P.
1
Restore EEMEM content to RDAC. Users should
issue NOP immediately after this command to
conserve power.
2 Store RDAC register setting to EEMEM.
3 Decrement RDAC 6 dB (shift data bits right).
4
Decrement all RDACs 6 dB (shift all data bits right).
5 Decrement RDAC one step.
6 Decrement all RDACs one step.
7 Reset EEMEM contents to all RDACs.
8 Increment RDAC 6 dB (shift data bits left).
9 Increment all RDACs 6 dB (shift all data bits left).
10 Increment RDAC one step.
11 Increment all RDACs one step.
12 to 15 Reserved.
LINEAR INCREMENT/DECREMENT COMMANDS
The increment and decrement commands (10, 11, 5, and 6) are
useful for linear step-adjustment applications. These commands
simplify microcontroller software coding by allowing the
controller to send just an increment or decrement command to
the AD5251/AD5252. The adjustments can be directed to a
single RDAC or to all four RDACs.
±6 dB ADJUSTMENTS
(DOUBLING/HALVING WIPER SETTING)
The AD5251/AD5252 accommodate ±6 dB adjustments of
the RDAC wiper positions by shifting the register contents to
left/right for increment/decrement operations, respectively.
Command 3, Command 4, Command 8, and Command 9
can be used to increment or decrement the wiper positions in
6 dB steps synchronously or asynchronously.
Incrementing the wiper position by +6 dB essentially doubles
the RDAC register value, whereas decrementing the wiper
position by 6 dB halves the register content. Internally, the
AD5251/AD5252 use shift registers to shift the bits left and
right to achieve a ±6 dB increment or decrement. The maximum
number of adjustments is nine and eight steps for incrementing
from zero scale and decrementing from full scale, respectively.
These functions are useful for various audio/video level
adjustments, especially for white LED brightness settings in
which human visual responses are more sensitive to large
adjustments than to small adjustments.
DIGITAL INPUT/OUTPUT CONFIGURATION
SDA is a digital input/output with an open-drain MOSFET that
requires a pull-up resistor for proper communication. On the other
hand, SCL and AA WPEE
AA are digital inputs for which pull-up resistors are
recommended to minimize the MOSFET cross-conduction current
when the driving signals are lower than VDD.
fi SCL and W and Figure Sb, W Hfi «fl
AD5251/AD5252 Data Sheet
Rev. E | Page 22 of 28
SCL and AAWPEE
AA have ESD protection diodes, as shown in Figure 35
and Figure 36. AAWPEE
AA can be permanently tied to VDD without a
pull-up resistor if the write-protect feature is not used. If AAWPEE
AA is
left floating, an internal current source pulls it low to enable
write protection. In applications in which the device is
programmed infrequently, this allows the part to default to
write-protection mode after any one-time factory programming
or field calibration without using an on-board pull-down
resistor. Because there are protection diodes on all inputs, the
signal levels must not be greater than VDD to prevent forward
biasing of the diodes.
03823-0-035
GND
SCL
V
DD
Figure 35. SCL Digital Input
03823-0-036
GND
INPUTS
WP
VDD
Figure 36. Equivalent AAWPEE
AA Digital Input
MULTIPLE DEVICES ON ONE BUS
The AD5251/AD5252 are equipped with two addressing pins,
AD1 and AD0, that allow up to four AD5251/AD5252 devices
to be operated on one I2C bus. To achieve this result, the states of
AD1 and AD0 on each device must first be defined. An example
is shown in Table 12 and Figure 37. In I2C programming, each
device is issued a different slave address01011(AD1)(AD0)
to complete the addressing.
Table 12. Multiple Devices Addressing
AD1 AD0 Device Addressed
0 0 U1
0 1 U2
1 0 U3
1 1 U4
03823-0-037
5V
R
P
R
P
5V
5V 5V
U1
AD0
AD1
SDA SCL
MASTER
U2
AD0
AD1
SDA SCL
U3
AD0
AD1
SDA SCL
U4
AD0
AD1
SDA
SDA
SCL
SCL
Figure 37. Multiple AD5251/AD5252 Devices on a Single Bus
TERMINAL VOLTAGE OPERATION RANGE
The AD5251/AD5252 are designed with internal ESD diodes
for protection; these diodes also set the boundaries for the
terminal operating voltages. Positive signals present on
Terminal A, Terminal B, or Terminal W that exceed VDD are
clamped by the forward-biased diode. Similarly, negative signals
on Terminal A, Terminal B, or Terminal W that are more
negative than VSS are also clamped (see Figure 38). In practice,
users should not operate VAB, VWA , and VWB to be higher than
the voltage across VDD to VSS, but VAB, VWA , and VWB have no
polarity constraint.
V
SS
V
DD
A
W
B
03823-0-018
Figure 38. Maximum Terminal Voltages Set by VDD and VSS
POWER-UP AND POWER-DOWN SEQUENCES
Because the ESD protection diodes limit the voltage compliance
at Terminal A, Terminal B, and Terminal W (see Figure 38), it is
important to power on VDD/VSS before applying any voltage to
these terminals. Otherwise, the diodes are forward biased such
that VDD/VSS are powered unintentionally and may affect the
user’s circuit. Similarly, VDD/VSS should be powered down last.
The ideal power-up sequence is in the following order: GND,
VDD, VSS, digital inputs, and VA/VB/VW. The order of powering
VA, VB, VW, and the digital inputs is not important, as long as
they are powered after VDD/VSS.
@IIW H15
Data Sheet AD5251/AD5252
Rev. E | Page 23 of 28
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to employ a compact, minimum
lead-length layout design. The leads to the input should be as
direct as possible, with a minimum conductor length. Ground
paths should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors. Low equivalent series resistance (ESR)
1 µF to 10 µF tantalum or electrolytic capacitors should be
applied at the supplies to minimize any transient disturbance
and filter low frequency ripple. Figure 39 illustrates the basic
supply-bypassing configuration for the AD5251/AD5252.
V
DD
V
DD
V
SS
V
SS
GND
C3
AD5251/AD5252
C4
C1
+
+C2
10µF
10µF0.1µF
0.1µF
03823-0-039
Figure 39. Power Supply-Bypassing Configuration
The ground pin of the AD5251/AD5252 is used primarily as a
digital ground reference. To minimize the digital ground
bounce, the AD5251/AD5252 ground terminal should be joined
remotely to the common ground (see Figure 39).
DIGITAL POTENTIOMETER OPERATION
The structure of the RDAC is designed to emulate the
performance of a mechanical potentiometer. The RDAC
contains a string of resistor segments with an array of analog
switches that act as the wiper connection to the resistor array.
The number of points is the resolution of the device. For
example, the AD5251/AD5252 emulate 64/256 connection
points with 64/256 equal resistance, RS, allowing them to
provide better than 1.5%/0.4% resolution.
Figure 40 provides an equivalent diagram of the connections
between the three terminals that make up one channel of the
RDAC. Switches SWA and SWB are always on, but only one of
switches SW(0) to SW(2N 1) can be on at a time (determined by
the setting decoded from the data bit). Because the switches are
nonideal, there is a 75 Ω wiper resistance, RW. Wiper resistance
is a function of supply voltage and temperature: Lower supply
voltages and higher temperatures result in higher wiper
resistances. Consideration of wiper resistance dynamics is
important in applications in which accurate prediction of
output resistance is required.
SW
B
SW(1)
SW(0)
B
X
R
S
R
S
SW
A
SW(2
N
1)
A
X
W
X
SW(2
N
– 2)
RDAC
WIPER
REGISTER
AND
DECODER
R
S
= R
AB
/2
N
R
S
DIGITAL
CIRCUITRY
OMITTED FOR
CLARITY
03823-0-040
Figure 40. Equivalent RDAC Structure
PROGRAMMABLE RHEOSTAT OPERATION
If either the W-to-B or W-to-A terminal is used as a variable
resistor, the unused terminal can be opened or shorted with W;
such operation is called rheostat mode (see Figure 41). The
resistance tolerance can range ±20%.
A
W
B
03823-0-041
A
W
B
A
W
B
Figure 41. Rheostat Mode Configuration
The nominal resistance of the AD5251/AD5252 has 64/256
contact points accessed by the wiper terminal, plus the B terminal
contact. The 6-/8-bit data-word in the RDAC register is decoded
to select one of the 64/256 settings. The wiper’s first connection
starts at the B terminal for Data 0x00. This B terminal connection
has a wiper contact resistance, RW, of 75 Ω, regardless of the
nominal resistance. The second connection (the AD5251 10 kΩ
part) is the first tap point where RWB = 231 Ω (RWB = RAB/64 +
RW = 156 Ω + 75 Ω) for Data 0x01, and so on. Each LSB data
value increase moves the wiper up the resistor ladder until the
last tap point is reached at RWB = 9893 . See Figure 40 for a
simplified diagram of the equivalent RDAC circuit.
The general equation that determines the digitally programmed
output resistance between W and B is
AD5251: RWB(D) = (D/64) × RAB + 75 Ω (1)
AD5252: RWB(D) = (D/256) × RAB + 75 Ω (2)
where:
D is the decimal equivalent of the data contained in the
RDAC latch.
RAB is the nominal end-to-end resistance.
AD5251/AD5252 Data Sheet
Rev. E | Page 24 of 28
R
AB
(%)
D (Code in Decimal)
03823-0-042
0
25
50
75
100
0
16 32 48 63
R
WA
R
WB
Figure 42. AD5251 RWA(D) and RWB(D) vs. Decimal Code
Since the digital potentiometer is not ideal, a 75 Ω finite wiper
resistance is present that can easily be seen when the device is
programmed at zero scale. Because of the fine geometric and
interconnects employed by the device, care should be taken to
limit the current conduction between W and B to no more than
±5 mA continuous for a total resistance of 1 kΩ or a pulse of
±20 mA to avoid degradation or possible destruction of the
device. The maximum dc current for AD5251 and AD5252 are
shown in Figure 21and Figure 22, respectively.
Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A also produces a
digitally controlled complementary resistance, RWA . When these
terminals are used, the B terminal can be opened. The RWA
starts at a maximum value and decreases as the data loaded into
the latch increases in value (see Figure 42). The general
equation for this operation is
AD5251: RWA (D) = [(64 – D)/64] × RAB + 75 Ω (3)
AD5252: RWA (D) = [(256 – D)/256] × RAB + 75 Ω (4)
The typical distribution of RAB from channel-to-channel
matches is about ±0.15% within a given device. On the other
hand, device-to-device matching is process-lot dependent with
a ±20% tolerance.
PROGRAMMABLE POTENTIOMETER OPERATION
If all three terminals are used, the operation is called potenti-
ometer mode (see Figure 43); the most common configuration
is the voltage divider operation.
03823-0-043
A
B
W
V
I
V
C
Figure 43. Potentiometer Mode Configuration
If the wiper resistance is ignored, the transfer function is simply
AD5251: B
AB
WVV
D
V64 (5)
AD5252: B
AB
WVV
D
V256 (6)
A more accurate calculation that includes the wiper resistance
effect is
A
W
AB
W
AB
N
WV
RR
RR
D
DV
2
2
)(
(7)
where 2N is the number of steps.
Unlike in rheostat mode operation, where the tolerance is high,
potentiometer mode operation yields an almost ratiometric
function of D/2N with a relatively small error contributed by the
RW terms. Therefore, the tolerance effect is almost cancelled.
Similarly, the ratiometric adjustment also reduces the
temperature coefficient effect to 50 ppm/°C, except at low value
codes where RW dominates.
Potentiometer mode operations include other applications, such
as op amp input, feedback-resistor networks, and other voltage-
scaling applications. The A, W, and B terminals can, in fact, be
input or output terminals, provided that |VA|, |VW|, and |VB| do
not exceed VDD to VSS.
if
Data Sheet AD5251/AD5252
Rev. E | Page 25 of 28
APPLICATIONS INFORMATION
LCD PANEL VCOM ADJUSTMENT
Large LCD panels usually require an adjustable VCOM voltage
centered around 6 V to 8 V with ±1 V swing and small steps
adjustment. This example represents common DAC appli-
cations where the window of adjustments is small and centered
at any level. High voltage and high resolution DACs can be
used, but it is far more cost-effective to use low voltage digital
potentiometers with level shifting, such as the AD5251 or
AD5252, to achieve the objective.
Assume a VCOM voltage requirement of 6 V ± 1 V with a ±20 mV
step adjustment, as shown in Figure 44. The AD5252 can be
configured in voltage divider mode with an op amp gain. With
±20% tolerance accounted for by the AD5252, this circuit can
still be adjusted from 5 V to 7 V with an 8 mV/step in the
worst case.
V
DD
U1
U2
V
COM
+5V R2
10k
R4
6k
R3
18.5k
R5
1k
R1
350k
C1
2.2pF
B
AD5252
+14.4V
+14.4V
±20%
±1%
6V ±1V
V+
V–
03823-0-044
Figure 44. Apply 5 V Digital Potentiometer AD5251 in a 6 V ± 1 V Application
CURRENT-SENSING AMPLIFIER
The dual-channel, synchronous update, and channel-to-channel
resistance matching characteristics make the AD5251/AD5252
suitable for current-sensing applications, such as LED
brightness control. In the circuit shown in Figure 45, when
RDAC1 and RDAC3 are programmed to the same settings, it
can be shown that
( )
REF
N
o
VVV
D
D
V+
=
12
2
(8)
As a result, the current through a sense resistor connected
between V1 and V2 can be determined.
The circuit can be programmed for use with systems that require
different sensitivities. If the op amp has very low offset and low
bias current, the major source of error comes from the digital
potentiometer channel-to-channel resistance mismatch, which
is typically 0.15%. The circuit accuracy is about 9 bits, which is
adequate for LED control and other general-purpose applications.
U1
V
1
R
SENSE
0.1k
RDAC1
10k
RDAC3
10k
B
B
AD5252 AD8628
U2
V
O
VREF
+5V
V+
V
03823-0-045
V
2
Figure 45. Current-Sensing Amplifier
ADJUSTABLE HIGH POWER LED DRIVER
Figure 46 shows a circuit that can drive three or four high power
LEDs. The ADP1610 is an adjustable boost regulator that provides
adequate headroom and current for the LEDs. Because its FB pin
voltage is 1.2 V, the digital potentiometer AD5252 and the op amp
form an average gain of 12 feedback networks that servo the
sensing and feedback voltages. As a result, the voltage across
RSET is regulated around 0.1 V, depending on the AD5252’s
setting. An adjustable LED current is
SET
R
LED
R
V
I
SET
=
(9)
RSET should be small enough to conserve power, but large enough
to limit the maximum LED current. R3 should be used in parallel
with the AD5252 to limit the LED current to an achievable range.
SD SW
FB
COMP
SS RT GND
IN
PWM
C
C
390pF C
SS
10nF
R
O
100k
R
SET
0.25k
10k
W
B A
C8
0.1µF
AD5252
ADP1610
V
OUT
AD8591
U3
U1
U2
U1
+5V
+5V
V+
V
03823-0-046
R3
200
R2
1.1k
R1
100
C3
10µF
C2
10µF
D1
D1
D2
D3
L1
10µF
Figure 46. High Power, Adjustable LED Driver
4 LE: 4",
AD5251/AD5252 Data Sheet
Rev. E | Page 26 of 28
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
061908-A
4.50
4.40
4.30
14 8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65 BSC
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
Figure 47. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Data Sheet AD5251/AD5252
Rev. E | Page 27 of 28
ORDERING GUIDE
Model1, 2, 3 Step RAB (kΩ) Temperature Range Package Description
Package
Option
Ordering
Quantity
AD5251BRUZ50 64 50 −40°C to +105°C 14-Lead TSSOP RU-14 96
AD5252BRUZ1 256 1 −40°C to +105°C 14-Lead TSSOP RU-14 96
AD5252BRUZ1-RL7
256
1
−40°C to +105°C
14-Lead TSSOP
RU-14
1,000
AD5252BRUZ10 256 10 −40°C to +105°C 14-Lead TSSOP RU-14 96
AD5252BRUZ10-RL7 256 10 −40°C to +105°C 14-Lead TSSOP RU-14 1,000
AD5252BRUZ50 256 50 −40°C to +105°C 14-Lead TSSOP RU-14 96
AD5252BRUZ50-RL7 256 50 −40°C to +105°C 14-Lead TSSOP RU-14 1,000
AD5252BRUZ100 256 100 −40°C to +105°C 14-Lead TSSOP RU-14 96
AD5252BRUZ100-RL7 256 100 −40°C to +105°C 14-Lead TSSOP RU-14 1,000
EVAL-AD5252SDZ 256 10 Evaluation Board 1
1 In the package marking, Line 1 shows the part number. Line 2 shows the branding information, such that B1 = 1 kΩ, B10 = 10 kΩ, and so on. There is also a “#” marking
for the Pb-free part. Line 3 shows the date code in YYWW.
2 Z = RoHS Compliant Part.
3 The EVAL-AD5252SDZ can be used to evaluate the AD5251 and the AD5252.
monnm 7 Analug nuim, Inn All my“; Itsevvedv Tvidemivks and ANALOG DEVICES www.analug.cum
AD5251/AD5252 Data Sheet
Rev. E | Page 28 of 28
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©20042017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03823-0-11/17(E)

Products related to this Datasheet

IC DGT POT 10KOHM 256TAP 14TSSOP
IC DGTL POT 1KOHM 256TAP 14TSSOP
IC DGT POT 10KOHM 256TAP 14TSSOP
IC DGT POT 10KOHM 256TAP 14TSSOP
IC DGT POT 50KOHM 256TAP 14TSSOP
IC DGT POT 100KOHM 256TP 14TSSOP
IC DGT POT 50KOHM 256TAP 14TSSOP
IC DGT POT 100KOHM 256TP 14TSSOP
BOARD EVAL FOR AD5252
IC DGTL POT 1KOHM 256TAP 14TSSOP
IC DGT POT 10KOHM 256TAP 14TSSOP
IC DGT POT 100KOHM 256TP 14TSSOP
IC DGTL POT 1KOHM 64TAP 14TSSOP
IC DGTL POT 1KOHM 64TAP 14TSSOP
IC DGTL POT 10KOHM 64TAP 14TSSOP
IC DGTL POT 10KOHM 64TAP 14TSSOP
IC DGT POT 100KOHM 64TAP 14TSSOP
IC DGTL POT 50KOHM 64TAP 14TSSOP
IC DGTL POT 1KOHM 256TAP 14TSSOP
IC DGT POT 10KOHM 256TAP 14TSSOP
IC DGT POT 100KOHM 256TP 14TSSOP
IC DGT POT 50KOHM 256TAP 14TSSOP
IC DGT POT 50KOHM 256TAP 14TSSOP
IC DGTL POT 1KOHM 256TAP 14TSSOP
IC DGT POT 100KOHM 256TP 14TSSOP
IC DGT POT 50KOHM 256TAP 14TSSOP
IC DGTL POT 50KOHM 64TAP 14TSSOP
IC DGT POT 100KOHM 64TAP 14TSSOP
IC DGTL POT 10KOHM 64TAP 14TSSOP
IC DGTL POT 1KOHM 64TAP 14TSSOP