IRFR,IRFU,SiHFR,SiHFU_320 Datasheet by Vishay Siliconix

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IRFR320, IRFU320, SiHFR320, SiHFU320
www.vishay.com Vishay Siliconix
S14-2355-Rev. E, 08-Dec-14 1Document Number: 91273
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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Power MOSFET
FEATURES
Dynamic dV/dt rating
Repetitive avalanche rated
Surface mount (IRFR320,SiHFR320)
Straight lead (IRFU320,SiHFU320)
Available in tape and reel
Fast switching
Ease of paralleling
Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
DESCRIPTION
Third generation power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The DPAK is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU, SiHFU series) is for through-hole
mounting applications. Power dissipation levels up to 1.5 W
are possible in typical surface mount applications.
Note
a. See device orientation.
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 50 V, starting TJ = 25 °C, L = 29 mH, Rg = 25 Ω, IAS = 3.1 A (see fig. 12).
c. ISD 3.1 A, dI/dt 65 A/μs, VDD VDS, TJ 150 °C.
d. 1.6 mm from case.
PRODUCT SUMMARY
VDS (V) 400
RDS(on) (Ω)V
GS = 10 V 1.8
Qg (Max.) (nC) 20
Qgs (nC) 3.3
Qgd (nC) 11
Configuration Single
N-Channel MOSFET
G
D
S
DPAK
(TO-252)
IPAK
(TO-251)
GDS
S
D
G
D
Available
ORDERING INFORMATION
Package DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) IPAK (TO-251)
Lead (Pb)-free and Halogen-free SiHFR320-GE3 SiHFR320TRL-GE3aSiHFR320TR-GE3 a - SiHFU320-GE3
Lead (Pb)-free IRFR320PbF IRFR320TRLPbFaIRFR320TRPbF aIRFR320TRRPbF a IRFU320PbF
SiHFR320-E3 SiHFR320TL-E3aSiHFR320T-E3 aSiHFR320TR-E3 a SiHFU320-E3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS 400 V
Gate-Source Voltage VGS ± 20
Continuous Drain Current VGS at 10 V TC = 25 °C ID
3.1
ATC = 100 °C 2.0
Pulsed Drain Current aIDM 12
Linear Derating Factor 0.33 W/°C
Linear Derating Factor (PCB Mount) e 0.020
Single Pulse Avalanche Energy bEAS 160 mJ
Repetitive Avalanche Current a IAR 3.1 A
Repetitive Avalanche Energy a EAR 4.2 mJ
Maximum Power Dissipation TC = 25 °C PD
42 W
Maximum Power Dissipation (PCB Mount)eTA = 25 °C 2.5
Peak Diode Recovery dV/dt cdV/dt 4.0 V/ns
Operating Junction and Storage Temperature Range TJ, Tstg -55 to +150 °C
Soldering Recommendations (Peak Temperature) d for 10 s 260
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IRFR320, IRFU320, SiHFR320, SiHFU320
www.vishay.com Vishay Siliconix
S14-2355-Rev. E, 08-Dec-14 2Document Number: 91273
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
e. When mounted on 1" square PCB (FR-4 or G-10 material).
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width 300 μs; duty cycle 2 %.
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA --110
°C/W
Maximum Junction-to-Ambient
(PCB Mount) a RthJA --50
Maximum Junction-to-Case (Drain) RthJC --3.0
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 μA 400 - - V
VDS Temperature Coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.51 - V/°C
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V
Gate-Source Leakage IGSS V
GS = ± 20 V - - ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = 400 V, VGS = 0 V - - 25 μA
VDS = 320 V, VGS = 0 V, TJ = 125 °C - - 250
Drain-Source On-State Resistance RDS(on) V
GS = 10 V ID = 1.9 A b --1.8Ω
Forward Transconductance gfs VDS = 50 V, ID = 1.9 A 1.7 - - S
Dynamic
Input Capacitance Ciss VGS = 0 V,
VDS = - 25 V,
f = 1.0 MHz, see fig. 5
- 350 -
pFOutput Capacitance Coss - 120 -
Reverse Transfer Capacitance Crss -47-
Total Gate Charge Qg
VGS = 10 V ID = 3.3 A, VDS = 320 V,
see fig. 6 and 13 b
--20
nC Gate-Source Charge Qgs --3.3
Gate-Drain Charge Qgd --11
Turn-On Delay Time td(on)
VDD = 200 V, ID = 3.3 A,
Rg = 18 Ω, RD = 56 Ω, see fig. 10 b
-10-
ns
Rise Time tr -14-
Turn-Off Delay Time td(off) -30-
Fall Time tf -13-
Internal Drain Inductance LD Between lead,
6 mm (0.25") from
package and center of
die contact
-4.5-
nH
Internal Source Inductance LS-7.5-
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current ISMOSFET symbol
showing the
integral reverse
p - n junction diode
--3.1
A
Pulsed Diode Forward Current a ISM --12
Body Diode Voltage VSD TJ = 25 °C, IS = 3.1 A, VGS = 0 V b --1.6V
Body Diode Reverse Recovery Time trr TJ = 25 °C, IF = 3.3 A, dI/dt = 100 A/μs b - 270 600 ns
Body Diode Reverse Recovery Charge Qrr -1.43.0μC
Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
D
S
G
S
D
G
VISHAY. 3 E x m" c E '5 o c E“ , D m . a a, 2m: wig wm’H V” _ V” .2 H mm“ 1 m1 V95. Dvaimosaurce Vollage (volls) m E 3 m0 E = o E S .4 a .0 ii 2w: =ULSE Mam rs , 1500!; m“ 135 10‘ v05, DrainriorSource Vo‘hage (valls) 10 Raspm, DraingmASaume On Hesxstance (Nmmahzed) m , m\' a an 40 720 a 2n 4o so an ion m m 150 T1, Junction Tempevalure (”C) hvm@wshay.com ww wshaycam/do 1000
IRFR320, IRFU320, SiHFR320, SiHFU320
www.vishay.com Vishay Siliconix
S14-2355-Rev. E, 08-Dec-14 3Document Number: 91273
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
0.01
0.1
1
10
45678910
ID, Drain-to-Source Current (A)
VGS, Gate-to-Source Voltage (V)
TJ= 150 °C
TJ= 25 °C
VDS= 26.2V
Capacxtanoe (p F) Veg, GateAwASouvce Vulxage (volts) mm g (N. r — 1MHz (2,55 _ 5““ - ”qr, Lab ”up tu CPSS ’ Lan c m . 7 um ‘ sao am: arm n m“ VHS, DIawn-Io-Source Voltage (vans) r v r c ncux‘ SEE mun: m 05, Tmar Gate Charge (nC) ‘snv Reverse Dvain Curvent (Amps) In, Drain Current (Amps) w" v55 = av o ‘ a s a 7 a n 1 a 1 2 v5.3, Souroerlchlain Voltage (volts) 1n” DPI'RAHUN m Hus Am umrtu ”V/ “Us ION) YC=P50E YUVISODC SINGLEI‘ULSE ‘251024‘0229103 v95, Drainrtanource Vo‘tage (vans) hvm@wshay.com
IRFR320, IRFU320, SiHFR320, SiHFU320
www.vishay.com Vishay Siliconix
S14-2355-Rev. E, 08-Dec-14 4Document Number: 91273
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
VISHAY. 55% \D‘ Dmin Cment(Amps) 25 an 7: ma :2: 150 T5. Case Temperature (’0) 3mm PULSE WHERNAL nsswwsa Thermal Response (2%) unrzs : am new, n-u/La 2 pm rm. x 1m: r 1,7 {0'5 :0" so" 10'? u I 1 10 n, Hananguxar Pulse Duration (seconds) hvm@wshay.com ww wshaycom/do 1000
IRFR320, IRFU320, SiHFR320, SiHFU320
www.vishay.com Vishay Siliconix
S14-2355-Rev. E, 08-Dec-14 5Document Number: 91273
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10a - Switching Time Test Circuit
Fig. 10b - Switching Time Waveforms
Fig. 10 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Pulse width 1 µs
Duty factor 0.1 %
RD
VGS
Rg
D.U.T.
10 V
+
-
VDS
VDD
VDS
90 %
10 %
VGS
td(on) trtd(off) tf
EAS, Single Pulse Energy (mJ) A30 \ I[I ‘ mu 1 n , , 7 , z m T ‘ arm“ a u ago J 7 \ ‘ £qu V m \j:\ , \\ a mu = 50v ‘ \ as 5n 7a mm ,;s «in Starlmg TJ, Junction Temperature("C) hvm@wshay.com www.v\shay.com/doc?91000
IRFR320, IRFU320, SiHFR320, SiHFU320
www.vishay.com Vishay Siliconix
S14-2355-Rev. E, 08-Dec-14 6Document Number: 91273
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit
Rg
IAS
0.01 Ω
tp
D.U.T
L
VDS
+
-VDD
10 V
Vary tp to obtain
required IAS
I
AS
V
DS
V
DD
V
DS
t
p
D.U.T.
3 mA
VGS
VDS
IGID
0.3 µF
0.2 µF
50 kΩ
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
VISHAY. (>1 WTT L33 ’5) wwwwshaz cam/Egg’91273 hvm@wshay.com www.v\shay.com/doc?91000
IRFR320, IRFU320, SiHFR320, SiHFU320
www.vishay.com Vishay Siliconix
S14-2355-Rev. E, 08-Dec-14 7Document Number: 91273
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91273.
P.W. Period
dI/dt
Diode recovery
dV/dt
Ripple 5 %
Body diode forward drop
Re-applied
voltage
Reverse
recovery
current
Body diode forward
current
VGS = 10 Va
ISD
Driver gate drive
D.U.T. lSD waveform
D.U.T. VDS waveform
Inductor current
D = P.W.
Period
+
-
+
+
+
-
-
-
Peak Diode Recovery dV/dt Test Circuit
VDD
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
D.U.T. Circuit layout considerations
Low stray inductance
Ground plane
Low leakage inductance
current transformer
Rg
Note
a. VGS = 5 V for logic level devices
VDD
— VISHAY. V L' Com/605791000
Package Information
www.vishay.com Vishay Siliconix
Revision: 16-May-16 1Document Number: 71197
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TO-252AA Case Outline
Notes
Dimension L3 is for reference only.
L3
D
L4
L5
bb2
e1
E1
D1
C
A1
gage plane height (0.5 mm)
e
b3
E
C2
A
L
H
MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX.
A 2.18 2.38 0.086 0.094
A1 - 0.127 - 0.005
b 0.64 0.88 0.025 0.035
b2 0.76 1.14 0.030 0.045
b3 4.95 5.46 0.195 0.215
C 0.46 0.61 0.018 0.024
C2 0.46 0.89 0.018 0.035
D 5.97 6.22 0.235 0.245
D1 4.10 - 0.161 -
E 6.35 6.73 0.250 0.265
E1 4.32 - 0.170 -
H 9.40 10.41 0.370 0.410
e 2.28 BSC 0.090 BSC
e1 4.56 BSC 0.180 BSC
L 1.40 1.78 0.055 0.070
L3 0.89 1.27 0.035 0.050
L4 - 1.02 - 0.040
L5 1.01 1.52 0.040 0.060
ECN: T16-0236-Rev. P, 16-May-16
DWG: 5347
— VISHAY.. '\* ’A L J L J SewanE~EandC~C Notes 1. Dimensxonmg and Iolerancmg per ASME V14.5M71994 2. Dimensxon are shewn m mches and mnhmeters. a. Dimensxon D and E as net mclude mom Hash. Mold flash shau nut exceed omermost extremes 00 me was“: body. . Thermal pad camour opnonal wnn dlmensxons b4‘ L2‘ E1 and m . Lead mmensmn uncomronea m L3 .Dlmensxon [31.173 and c1 app‘y to base metal emy, .omune conlmms Io JEDEC ouflme T07251AA. \Amw» Documem Number, 91362 Rewsmn. TSVSepVOE
Document Number: 91362 www.vishay.com
Revision: 15-Sep-08 1
Package Information
Vishay Siliconix
TO-251AA (HIGH VOLTAGE)
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension are shown in inches and millimeters.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the
outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions b4, L2, E1 and D1.
5. Lead dimension uncontrolled in L3.
6. Dimension b1, b3 and c1 apply to base metal only.
7. Outline conforms to JEDEC outline TO-251AA.
Base
metal
Plating b1, b3
(b, b2)
c1
(c)
Section B - B and C - C
D
A
c2
c
Lead tip
5
5
(Datum A)
Thermal PAD
E1
4
D1
View A - A
A1
A
A
C
Seating
plane
CC
BB
θ1
θ2
B
4
4
4
3
5
L1
L
L3
3 x b2
3 x b
3
b4
E
2 x e 0.010 C B
M
A
0.25
0.010 BA
0.25
L2
A
C
M
MILLIMETERS INCHES MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.
A 2.18 2.39 0.086 0.094 D1 5.21 - 0.205 -
A1 0.89 1.14 0.035 0.045 E 6.35 6.73 0.250 0.265
b 0.64 0.89 0.025 0.035 E1 4.32 - 0.170 -
b1 0.65 0.79 0.026 0.031 e 2.29 BSC 2.29 BSC
b2 0.76 1.14 0.030 0.045 L 8.89 9.65 0.350 0.380
b3 0.76 1.04 0.030 0.041 L1 1.91 2.29 0.075 0.090
b4 4.95 5.46 0.195 0.215 L2 0.89 1.27 0.035 0.050
c 0.46 0.61 0.018 0.024 L3 1.14 1.52 0.045 0.060
c1 0.41 0.56 0.016 0.022 θ1 0' 15' 0' 15'
c2 0.46 0.86 0.018 0.034 θ2 25' 35' 25' 35'
D 5.97 6.22 0.235 0.245
ECN: S-82111-Rev. A, 15-Sep-08
DWG: 5968
— VISHAY., Vishay Siliconix RECOMMENDED MINIMUM PADS FOR DPAK (TO-252) 0 22A (5 590} n 420 110.668) Recammended Mlmmum Pads Dimensmns m \nchesr‘(mm} rm; com 3
Application Note 826
Vishay Siliconix
Document Number: 72594 www.vishay.com
Revision: 21-Jan-08 3
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)
0.420
(10.668)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.224
(5.690)
0.180
(4.572)
0.055
(1.397)
0.243
(6.180)
0.087
(2.202)
0.090
(2.286)
Return to Index
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Revision: 08-Feb-17 1Document Number: 91000
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