MCP40D17/18/19 Datasheet by Microchip Technology

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© 2009 Microchip Technology Inc. DS22152B-page 1
MCP40D17/18/19
Features
Potentiometer or Rheostat configuration options
7-bit: Resistor Network Resolution
- 127 Resistors (128 Steps)
Zero Scale to Full Scale Wiper operation
•R
AB Resistances: 5 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ
Low Wiper Resistance: 100Ω (typical)
Low Tempco:
- Absolute (Rheostat): 50 ppm typical
(0°C to 70°C)
- Ratiometric (Potentiometer): 15 ppm typical
•I
2C Protocol
- Supports SMBus 2.0 Write Byte/Word
Protocol Formats
- Supports SMBus 2.0 Read Byte/Word
Protocol Formats
Standard I2C Device Addresses:
- All devices offered with address “0101110
- MCP40D18 also offered with address
0111110
Brown-out reset protection (1.5V typical)
Power-on Default Wiper Setting (Mid-scale)
Low-Power Operation:
- 2.5 µA Static Current (typical)
Wide Operating Voltage Range:
- 2.7V to 5.5V - Device Characteristics
Specified
- 1.8V to 5.5V - Device Operation
Wide Bandwidth (-3 dB) Operation:
- 2 MHz (typical) for 5.0 kΩ device
Extended temperature range (-40°C to +125°C)
Very small package (SC70)
Lead free (Pb-free) package
Package Types
Applications
PC Servers (I2C Protocol with Command Code)
Amplifier Gain Control and Offset Adjustment
Sensor Calibration (Pressure, Temperature,
Position, Optical and Chemical)
Set point or offset trimming
Cost-sensitive mechanical trim pot replacement
RF Amplifier Biasing
LCD Brightnes and Contract Adjustment
Device Features
MCP40D18
SC70-6
MCP40D19
SC70-5
Rheostat
4
1
2
3
5W
SDA
VDD
VSS
SCL
4
1
2
3
6A
SDA
VDD
VSS
SCL
5W
A
W
W
A
B
B
Potentiometer
MCP40D17
SC70-6
4
1
2
3
6W
SDA
VDD
VSS
SCL
5B
AW
B
Device
Control
Interface
# of Steps
Wiper
Configuration
Memory
Type
Resistance (typical) VDD
Operating
Range (1)
PackageOptions (kΩ)Wiper
(Ω)
MCP40D17 I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 75 1.8V to 5.5V SC70-6
MCP40D18 I2C 128 Potentiometer RAM 5.0, 10.0, 50.0, 100.0 75 1.8V to 5.5V SC70-6
MCP40D19 I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 75 1.8V to 5.5V SC70-5
Note 1: Analog characteristics only tested from 2.7V to 5.5V
7-Bit Single I2C™ (with Command Code) Digital POT
with Volatile Memory in SC70
MCP40D17/18/19
DS22152B-page 2 © 2009 Microchip Technology Inc.
Device Block Diagram
Comparison of Similar Microchip Devices (1)
Device
Control
Interface
# of Steps
Wiper
Configuration
Memory
Type
Resistance (typical)
VDD
Operating
Range
HV
Interface
WiperLock
Technology
PackageOptions (kΩ)
MCP40D17 (2) I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-6
MCP4017 (2,4)
I2C128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-6
MCP4012 (2) U/D 64 Rheostat RAM 2.1, 5.0, 10.0, 50.0 1.8V to 5.5V Yes No SOT-23-6
MCP4022 (2) U/D 64 Rheostat EE 2.1, 5.0, 10.0, 50.0 2.7V to 5.5V Yes Yes SOT-23-6
MCP4132 (3) SPI 129 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V Yes No PDIP-8,
SOIC-8,
MSOP-8,
DFN-8
MCP4142 (3) SPI 129 Rheostat EE 5.0, 10.0, 50.0, 100.0 2.7V to 5.5V Yes Yes
MCP4152 (3) SPI 257 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V Yes No
MCP4162 (3) SPI 257 Rheostat EE 5.0, 10.0, 50.0, 100.0 2.7V to 5.5V Yes Yes
MCP4532 (3) I2C129 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V Yes No MSOP-8,
DFN-8
MCP4542 (3) I2C129 Rheostat EE 5.0, 10.0, 50.0, 100.0 2.7V to 5.5V Yes Yes
MCP4552 (3) I2C257 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V Yes No
MCP4562 (3) I2C257 Rheostat EE 5.0, 10.0, 50.0, 100.0 2.7V to 5.5V Yes Yes
MCP40D18 (2) I2C 128 Potentiometer RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-6
MCP4018 (2,4) I2C128 Potentiometer RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-6
MCP4013 (2) U/D 64 Potentiometer RAM 2.1, 5.0, 10.0, 50.0 1.8V to 5.5V Yes No SOT-23-6
MCP4023 (2) U/D 64 Potentiometer EE 2.1, 5.0, 10.0, 50.0 2.7V to 5.5V Yes Yes SOT-23-6
MCP40D19 (2) I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-5
MCP4019 (2,4) I2C128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-5
MCP4014 (2) U/D 64 Rheostat RAM 2.1, 5.0, 10.0, 50.0 1.8V to 5.5V Yes No SOT-23-5
MCP4024 (2) U/D 64 Rheostat EE 2.1, 5.0, 10.0, 50.0 2.7V to 5.5V Yes Yes SOT-23-5
Note 1: This table is broken into three groups by a thick line (and color coding). The unshaded devices in this table
are the devices described in this data sheet, while the shaded devices offer a comparable resistor network
configuration.
2: Analog characteristics only tested from 2.7V to 5.5V.
3: Analog characteristics only tested from 3.0V to 5.5V.
4: These devices have a simplified I2C command format, which allows higher data throughput.
Power-up/
Brown-out
Control
VDD
VSS
I2C Serial
Interface
Module,
Control
Logic, &
Resistor
Network 0
(Pot 0)
SCL
SDA
A (2)
W
B (1, 2)
Note 1
Memory Note 1: Some configurations will have this
signal internally connected to
ground.
2: In some configurations, this signal
may not be connected externally
(internally floating or grounded).
© 2009 Microchip Technology Inc. DS22152B-page 3
MCP40D17/18/19
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
Voltage on VDD with respect to VSS ..... -0.6V to +7.0V
Voltage on SCL, and SDA with respect to VSS
............................................................................. -0.6V to 12.5V
Voltage on all other pins (A, W, and B)
with respect to VSS ............................ -0.3V to VDD + 0.3V
Input clamp current, IIK
(VI < 0, VI > VDD, VI > VPP ON HV pins)...........±20 mA
Output clamp current, IOK
(VO < 0 or VO > VDD) .......................................±20 mA
Maximum output current sunk by any Output pin
...........................................................................25 mA
Maximum output current sourced by any Output pin
...........................................................................25 mA
Maximum current out of VSS pin ......................100 mA
Maximum current into VDD pin ......................... 100 mA
Maximum current into A, W and B pins...........±2.5 mA
Package power dissipation (TA = +50°C, TJ = +150°C)
SC70-5............................................................302 mW
SC70-6............................................................483 mW
Storage temperature ..........................-65°C to +150°C
Ambient temperature with power applied
...........................................................-40°C to +125°C
ESD protection on all pins ........................4 kV (HBM)
........................................................................400V (MM)
Maximum Junction Temperature (TJ) .............. +150°C
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification
is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
VDD VBOR
MCP40D17/18/19
DS22152B-page 4 © 2009 Microchip Technology Inc.
AC/DC CHARACTERISTICS
DC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions
Supply Voltage VDD 2.7 5.5 V Analog Characteristics specified
1.8 5.5 V Digital Characteristics specified
VDD Start Voltage
to ensure Wiper
Reset
VBOR 1.65 V RAM retention voltage (VRAM) < VBOR
VDD Rise Rate to
ensure Power-on
Reset
VDDRR (Note 7)V/ms
Delay after device
exits the reset
state
(VDD > VBOR)
TBORD —1020µS
Supply Current
(Note 8) IDD 45 80 µA Serial Interface Active,
Write all 0’s to Volatile Wiper
VDD = 5.5V, FSCL = 400 kHz
2.5 5 µA Serial Interface Inactive,
(Stop condition, SCL = SDA = VIH),
Wiper = 0, VDD = 5.5V
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS.
3: MCP40D18 device only, includes VWZSE and VWFSE.
4: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
5: This specification by design.
6: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
7: POR/BOR is not rate dependent.
8: Supply current is independent of current through the resistor network
dewces ABMN ABMN ABMN ABMN
© 2009 Microchip Technology Inc. DS22152B-page 5
MCP40D17/18/19
Resistance
(± 20%) RAB 4.0 5 6.0 kΩ-502 devices (Note 1)
8.0 10 12.0 kΩ-103 devices (Note 1)
40.0 50 60.0 kΩ-503 devices (Note 1)
80.0 100 120.0 kΩ-104 devices (Note 1)
Resolution N 128 Taps No Missing Codes
Step Resistance RS —R
AB /
(127) ΩNote 5
Wiper Resistance RW 100 170 ΩVDD = 5.5 V, IW = 2.0 mA, code = 00h
155 325 ΩVDD = 2.7 V, IW = 2.0 mA, code = 00h
Nominal
Resistance
Tempco
ΔRAB/ΔT 50 ppm/°C TA = -20°C to +70°C
100 ppm/°C TA = -40°C to +85°C
150 ppm/°C TA = -40°C to +125°C
Ratiometeric
Tempco
ΔVWB/ΔT 15 ppm/°C Code = Midscale (3Fh)
Resistor Terminal
Input Voltage
Range (Terminals
A, B and W)
VA,VW,VBVss — VDD VNote 4, Note 5
Maximum current
through Terminal
(A, W or B)
Note 5
IT 2.5 mA Terminal A IAW, W = Full Scale (FS)
2.5 mA Terminal B IBW, W = Zero Scale (ZS)
2.5 mA Terminal W IAW or IBW, W = FS or ZS
1.38 mA
Terminal A
and
Terminal B
IAB, VB = 0V, VA = 5.5V,
RAB(MIN) = 4000
0.688 mA IAB, VB = 0V, VA = 5.5V,
RAB(MIN) = 8000
0.138 mA IAB, VB = 0V, VA = 5.5V,
RAB(MIN) = 40000
0.069 mA IAB, VB = 0V, VA = 5.5V,
RAB(MIN) = 80000
AC/DC CHARACTERISTICS (CONTINUED)
DC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS.
3: MCP40D18 device only, includes VWZSE and VWFSE.
4: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
5: This specification by design.
6: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
7: POR/BOR is not rate dependent.
8: Supply current is independent of current through the resistor network
MCP40D17/18/19
DS22152B-page 6 © 2009 Microchip Technology Inc.
Full Scale Error
(MCP40D18 only)
(code = 7Fh)
VWFSE -3.0 -0.1 LSb 5 kΩ2.7V VDD 5.5V
-2.0 -0.1 LSb 10 kΩ 2.7V VDD 5.5V
-0.5 -0.1 LSb 50 kΩ 2.7V VDD 5.5V
-0.5 -0.1 LSb 100 kΩ 2.7V VDD 5.5V
Zero Scale Error
(MCP40D18 only)
(code = 00h)
VWZSE +0.1 +3.0 LSb 5 kΩ 2.7V VDD 5.5V
+0.1 +2.0 LSb 10 kΩ2.7V VDD 5.5V
+0.1 +0.5 LSb 50 kΩ2.7V VDD 5.5V
+0.1 +0.5 LSb 100 kΩ 2.7V VDD 5.5V
Potentiometer
Integral
Non-linearity
INL -0.5 ±0.25 +0.5 LSb 2.7V VDD 5.5V
MCP40D18 device only (Note 2)
Potentiometer
Differential Non-
linearity
DNL -0.25 ±0.125 +0.25 LSb 2.7V VDD 5.5V
MCP40D18 device only (Note 2)
Bandwidth -3 dB
(See Figure 2-83,
load = 30 pF)
BW 2 MHz 5 kΩCode = 3Fh
—1MHz10kΩCode = 3Fh
260 kHz 50 kΩCode = 3Fh
100 kHz 100 kΩCode = 3Fh
AC/DC CHARACTERISTICS (CONTINUED)
DC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS.
3: MCP40D18 device only, includes VWZSE and VWFSE.
4: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
5: This specification by design.
6: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
7: POR/BOR is not rate dependent.
8: Supply current is independent of current through the resistor network
© 2009 Microchip Technology Inc. DS22152B-page 7
MCP40D17/18/19
Rheostat Integral
Non-linearity
MCP40D18
(Note 3)
MCP40D17 and
MCP40D19
devices only
(Note 3)
R-INL -2.0 ±0.5 +2.0 LSb 5 kΩ5.5V, IW = 900 µA
-5.0 +3.5 +5.0 LSb 2.7V, IW = 430 µA (Note 6)
See Section 2.0 LSb 1.8V (Note 6)
-2.0 ±0.5 +2.0 LSb 10 kΩ5.5V, IW = 450 µA
-4.0 +2.5 +4.0 LSb 2.7V, IW = 215 µA (Note 6)
See Section 2.0 LSb 1.8V (Note 6)
-1.125 ±0.5 +1.125 LSb 50 kΩ5.5V, IW = 90 µA
-1.5 +1 +1.5 LSb 2.7V, IW = 43 µA (Note 6)
See Section 2.0 LSb 1.8V (Note 6)
-0.8 ±0.5 +0.8 LSb 100 kΩ5.5V, IW = 45 µA
-1.125 +0.25 +1.125 LSb 2.7V, IW = 21.5 µA (Note 6)
See Section 2.0 LSb 1.8V (Note 6)
Rheostat
Differential
Non-linearity
MCP40D18
(Note 3)
MCP40D17 and
MCP40D19
devices only
(Note 3)
R-DNL -0.5 ±0.25 +0.5 LSb 5 kΩ5.5V, IW = 900 mA
-0.75 +0.5 +0.75 LSb 2.7V, IW = 430 µA (Note 6)
See Section 2.0 LSb 1.8V (Note 6)
-0.5 ±0.25 +0.5 LSb 10 kΩ5.5V, IW = 450 µA
-0.75 +0.5 +0.75 LSb 2.7V, IW = 215 µA (Note 6)
See Section 2.0 LSb 1.8V (Note 6)
-0.375 ±0.25 +0.375 LSb 50 kΩ5.5V, IW = 90 µA
-0.375 ±0.25 +0.375 LSb 2.7V, IW = 43 µA (Note 6)
See Section 2.0 LSb 1.8V (Note 6)
-0.375 ±0.25 +0.375 LSb 100 kΩ5.5V, IW = 45 µA
-0.375 ±0.25 +0.375 LSb 2.7V, IW = 21.5 µA (Note 6)
See Section 2.0 LSb 1.8V (Note 6)
Capacitance (PA)C
AW 75 pF f =1 MHz, Code = Full Scale
Capacitance (Pw)C
W 120 pF f =1 MHz, Code = Full Scale
Capacitance (PB)C
BW 75 pF f =1 MHz, Code = Full Scale
AC/DC CHARACTERISTICS (CONTINUED)
DC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS.
3: MCP40D18 device only, includes VWZSE and VWFSE.
4: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
5: This specification by design.
6: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
7: POR/BOR is not rate dependent.
8: Supply current is independent of current through the resistor network
MCP40D17/18/19
DS22152B-page 8 © 2009 Microchip Technology Inc.
Digital Inputs/Outputs (SDA, SCK)
Schmitt Trigger
High Input
Threshold
VIH 0.7 VDD —— V1.8V VDD 5.5V
Schmitt Trigger
Low Input
Threshold
VIL -0.5 — 0.3VDD V
Hysteresis of
Schmitt Trigger
Inputs (Note 5)
VHYS —0.1V
DD V All inputs except SDA and SCL
N.A. V SDA
and
SCL
100 kHz VDD < 2.0V
N.A. — V VDD 2.0V
0.1 VDD —— V 400 kHz VDD < 2.0V
0.05 VDD —— V V
DD 2.0V
Output Low
Voltage (SDA) VOL V
SS —0.2V
DD VV
DD < 2.0V, IOL = 1 mA
VSS —0.4 VV
DD 2.0V, IOL = 3 mA
Input Leakage
Current IIL -1 1 µA VIN = VDD and VIN = VSS
Pin Capacitance CIN, COUT —10pFf
C = 400 kHz
RAM (Wiper) Value
Value Range N 0h 7Fh hex
Wiper POR/BOR
Value NPOR/BOR 3Fh hex
Power Requirements
Power Supply
Sensitivity
(MCP40D18 only)
PSS 0.0005 0.0035 %/% VDD = 2.7V to 5.5V,
VA = 2.7V, Code = 3Fh
AC/DC CHARACTERISTICS (CONTINUED)
DC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS.
3: MCP40D18 device only, includes VWZSE and VWFSE.
4: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
5: This specification by design.
6: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
7: POR/BOR is not rate dependent.
8: Supply current is independent of current through the resistor network
# 397 7:37 777777 ,7 ”1 X7 f 7 777777
© 2009 Microchip Technology Inc. DS22152B-page 9
MCP40D17/18/19
1.1 I2C Mode Timing Waveforms and Requirements
FIGURE 1-1: I2C Bus Start/Stop Bits Timing Waveforms.
TABLE 1-1: I2C BUS START/STOP BITS REQUIREMENTS
FIGURE 1-2: I2C Bus Data Timing.
I2C AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (Extended)
Operating Voltage VDD range is described in Section 2.0 “Typical
Performance Curves
Param.
No. Symbol Characteristic Min Max Units Conditions
FSCL Standard Mode 0 100 kHz Cb = 400 pF, 1.8V - 5.5V
Fast Mode 0 400 kHz Cb = 400 pF, 2.7V - 5.5V
D102 Cb Bus capacitive
loading 100 kHz mode 400 pF
400 kHz mode 400 pF
90 TSU:STA START condition 100 kHz mode 4700 ns Only relevant for repeated
START condition
Setup time 400 kHz mode 600 ns
91 THD:STA START condition 100 kHz mode 4000 ns After this period the first
clock pulse is generated
Hold time 400 kHz mode 600 ns
92 TSU:STO STOP condition 100 kHz mode 4000 ns
Setup time 400 kHz mode 600 ns
93 THD:STO STOP condition 100 kHz mode 4000 ns
Hold time 400 kHz mode 600 ns
91 93
SCL
SDA
START
Condition STOP
Condition
90 92
Note 1: Refer to specification D102 (Cb) for load conditions.
90 91 92
100
101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
MCP40D17/18/19
DS22152B-page 10 © 2009 Microchip Technology Inc.
TABLE 1-2: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
I2C AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature 40°C TA +125°C (Extended)
Operating Voltage VDD range is described in AC/DC characteristics
Parame-
ter No. Sym Characteristic Min Max Units Conditions
100 THIGH Clock high time 100 kHz mode 4000 ns 1.8V-5.5V
400 kHz mode 600 ns 2.7V-5.5V
101 TLOW Clock low time 100 kHz mode 4700 ns 1.8V-5.5V
400 kHz mode 1300 ns 2.7V-5.5V
102A (5)
TRSCL SCL rise time 100 kHz mode 1000 ns Cb is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1Cb 300 ns
102B (5)
TRSDA SDA rise time 100 kHz mode 1000 ns Cb is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1Cb 300 ns
103A (5)
TFSCL SCL fall time 100 kHz mode 300 ns Cb is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1Cb 40 ns
103B (5)
TFSDA SDA fall time 100 kHz mode 300 ns Cb is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1Cb
(4)
300 ns
106 THD:DAT Data input hold
time 100 kHz mode 0 ns 1.8V-5.5V, Note 6
400 kHz mode 0 ns 2.7V-5.5V, Note 6
107 TSU:DAT Data input
setup time 100 kHz mode 250 ns (2)
400 kHz mode 100 ns
109 TAA Output valid
from clock 100 kHz mode 3450 ns (1)
400 kHz mode 900 ns
110 TBUF Bus free time 100 kHz mode 4700 ns Time the bus must be free
before a new transmission
can start
400 kHz mode 1300 ns
TSP Input filter spike
suppression
(SDA and SCL)
100 kHz mode 50 ns Philips Spec states N.A.
400 kHz mode 50 ns
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
requirement tsu; DAT 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
the SCL line is released.
3: The MCP40D18/MCP40D19 device must provide a data hold time to bridge the undefined part between
VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but
must be tested in order to guarantee that the output data will meet the setup and hold specifications for the
receiving device.
4: Use Cb in pF for the calculations.
5: Not Tested.
6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
© 2009 Microchip Technology Inc. DS22152B-page 11
MCP40D17/18/19
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS =GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA-40 +125 °C
Operating Temperature Range TA-40 +125 °C
Storage Temperature Range TA-65 +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SC70 θJA —331°C/WNote 1
Thermal Resistance, 6L-SC70 θJA —207°C/W
Note 1: Package Power Dissipation (PDIS) is calculated as follows:
PDIS = (TJ - TA) / θJA,
where: TJ = Junction Temperature, TA = Ambient Temperature.
MCP40D17/18/19
DS22152B-page 12 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS22152B-page 13
MCP40D17/18/19
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-1: Interface Active Current
(IDD) vs. SCL Frequency (fSCL) and Temperature
(VDD = 1.8V, 2.7V and 5.5V).
FIGURE 2-2: Interface Inactive Current
(ISHDN) vs. Temperature and VDD.
(VDD = 1.8V, 2.7V and 5.5V).
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0
10
20
30
40
50
60
-40 0 40 80 120
Temperature (°C)
IDD (µA)
100 kHz, 5.5V
400 kHz, 5.5V
100 kHz, 2.7V
400 kHz, 2.7V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-40 0 40 80 120
Temperature (°C)
IDD Interface Inactive (µA)
5.5V
2.7V
HO 0H H0 H! H} 0H H9
MCP40D17/18/19
DS22152B-page 14 © 2009 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-3: 5.0 k
Ω
: Pot Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (VDD = 5.5V). (A = VDD, B = VSS).
FIGURE 2-4: 5.0 k
Ω
: Pot Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (VDD = 2.7V). (A = VDD, B = VSS)
FIGURE 2-5: 5.0 k
Ω
: Pot Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (VDD = 1.8V). (A = VDD, B = VSS)
FIGURE 2-6:
5.0 k
Ω
: Rheo Mode – R
W
(
Ω
), INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (V
DD
= 5.5V).(I
W
= 1.4 mA, B = V
SS
)
FIGURE 2-7:
5.0 k
Ω
: Rheo Mode – R
W
(
Ω
), INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (V
DD
= 2.7V).(I
W
= 450 µA, B = V
SS
)
FIGURE 2-8:
5.0 k
Ω
: Rheo Mode – R
W
(
Ω
), INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (V
DD
= 1.8V). (I
W
=260 µA, B = V
SS
)
20
40
60
80
100
120
0 326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
-40°C
25°C
85°C 125°C
20
60
100
140
180
220
260
300
0326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL-40°C 25°C
85°
RW
125°C
Note: Refer to AN1080 for additional informa-
tion on the characteristics of the wiper
resistance (RW) with respect to device
voltage and wiper setting value.
0
500
1000
1500
2000
2500
0 326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-0.35
-0.25
-0.15
-0.05
0.05
0.15
0.25
0.35
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL DNL
RW
20
40
60
80
100
120
0 326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNLR
W
-40°C
25°C
85°C 125°C
20
60
100
140
180
220
260
300
0326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-1
0
1
2
3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
-40°C
25°C
85°C 125°C
Note: Refer to AN1080 for additional informa-
tion on the characteristics of the wiper
resistance (RW) with respect to device
voltage and wiper setting value.
0
500
1000
1500
2000
2500
0326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-1
4
9
14
19
24
29
34
39
44
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
© 2009 Microchip Technology Inc. DS22152B-page 15
MCP40D17/18/19
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-9: 5.0 k
Ω
: Full Scale Error
(FSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V).
FIGURE 2-10: 5.0 k
Ω
: Zero Scale Error
(ZSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V).
FIGURE 2-11: 5.0 k
Ω
: Nominal Resistance
(
Ω
) vs. Temperature and VDD.
FIGURE 2-12: 5.0 k
Ω
: RBW Tempco
Δ
RWB /
Δ
T vs. Code.
FIGURE 2-13: 5.0 k
Ω
: Power-Up Wiper
Response Time.
FIGURE 2-14: 5.0 k
Ω
: Digital Feedthrough
(SCL signal coupling to Wiper pin).
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
-40 0 40 80 120
Ambient Temperature (°C)
Full-Scale Error (FSE) (LSb)
2.7
5.5V
1.8V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-40 0 40 80 120
Ambient Temperature (°C)
Zero-Scale Error (ZSE) (LSb)
2.7
5.5V
1.8V
5000
5020
5040
5060
5080
5100
5120
5140
5160
5180
5200
-40 0 40 80 120
Ambient Temperature (°C)
Nominal Resistance (RAB
)
(Ohms)
2.7V
5.5V
1.8V
0
20
40
60
80
100
120
140
160
180
200
0 326496
Wiper Setting (decimal)
RBW Tempco (PPM)
2.7V
5.5V
Wiper
VDD
MCP40D17/18/19
DS22152B-page 16 © 2009 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-15: 5.0 k
Ω
: Write Wiper
(40h
3Fh) Settling Time (VDD=5.5V).
FIGURE 2-16: 5.0 k
Ω
: Write Wiper
(40h
3Fh) Settling Time (VDD=2.7V).
FIGURE 2-17: 5.0 k
Ω
: Write Wiper
(40h
3Fh) Settling Time (VDD=1.8V).
FIGURE 2-18: 5.0 k
Ω
: Write Wiper
(FFh
00h) Settling Time (VDD=5.5V).
FIGURE 2-19: 5.0 k
Ω
: Write Wiper
(FFh
00h) Settling Time (VDD=2.7V).
FIGURE 2-20: 5.0 k
Ω
: Write Wiper
(FFh
00h) Settling Time (VDD=1.8V).
~ I. I. “I‘m. :. I. W, I x :. w! \
© 2009 Microchip Technology Inc. DS22152B-page 17
MCP40D17/18/19
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-21: 10 k
Ω
Pot Mode : RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (VDD = 5.5V). (A = VDD, B = VSS).
FIGURE 2-22: 10 k
Ω
Pot Mode : RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (VDD = 2.7V). (A = VDD, B = VSS).
FIGURE 2-23: 10 k
Ω
Pot Mode : RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (VDD = 1.8V). (A = VDD, B = VSS).
FIGURE 2-24:
10 k
Ω
Rheo Mode : R
W
(
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (V
DD
= 5.5V).(I
W
= 450
µ
A, B = V
SS
).
FIGURE 2-25:
10 k
Ω
Rheo Mode : R
W
(
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (V
DD
= 2.7V).(I
W
= 210
µ
A, B = V
SS
).
FIGURE 2-26:
10 k
Ω
Rheo Mode : R
W
(
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (V
DD
= 1.8V). (I
W
=260
µ
A, B = V
SS
).
20
40
60
80
100
120
0 326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL RW
-40°C 25°C
85°C 125°C
20
60
100
140
180
220
260
300
0326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
-40°C
25°C
85°
RW
125°C
Note: Refer to AN1080 for additional informa-
tion on the characteristics of the wiper
resistance (RW) with respect to device
voltage and wiper setting value.
0
1000
2000
3000
0 326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-0.35
-0.25
-0.15
-0.05
0.05
0.15
0.25
0.35
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
20
40
60
80
100
120
0 326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
R
W
-40°C 25°C
85°C 125°C
20
60
100
140
180
220
260
300
0326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-1
0
1
2
3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
-40°C
2C
85°C 125°C
Note: Refer to AN1080 for additional informa-
tion on the characteristics of the wiper
resistance (RW) with respect to device
voltage and wiper setting value.
0
1000
2000
3000
0326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-1
4
9
14
19
24
29
34
39
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNLRW
MCP40D17/18/19
DS22152B-page 18 © 2009 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-27: 10 k
Ω
: Full Scale Error
(FSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V).
FIGURE 2-28: 10 k
Ω
: Zero Scale Error
(ZSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V).
FIGURE 2-29: 10 k
Ω
: Nominal Resistance
(
Ω
) vs. Temperature and VDD.
FIGURE 2-30: 10 k
Ω
: RBW Tempco
Δ
RWB /
Δ
T vs. Code.
FIGURE 2-31: 10 k
Ω
: Power-Up Wiper
Response Time.
FIGURE 2-32: 10 k
Ω
: Digital Feedthrough
(SCL signal coupling to Wiper pin).
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
-40 0 40 80 120
Ambient Temperature (°C)
Full-Scale Error (FSE) (LSb)
2.7
5.5V
1.8V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
-40 0 40 80 120
Ambient Temperature (°C)
Zero-Scale Error (ZSE) (LSb)
2.7
5.5V
1.8V
9900
9950
10000
10050
10100
10150
10200
-40 0 40 80 120
Ambient Temperature (°C)
Nominal Resistance (RAB
)
(Ohms)
2.7
5.5V
1.8V
0
20
40
60
80
100
0 326496
Wiper Setting (decimal)
RBW Tempco (PPM)
2.7V
5.5V
Wiper
VDD
© 2009 Microchip Technology Inc. DS22152B-page 19
MCP40D17/18/19
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-33: 10 k
Ω
: Write Wiper
(40h
3Fh) Settling Time (VDD=5.5V).
FIGURE 2-34: 10 k
Ω
: Write Wiper
(40h
3Fh) Settling Time (VDD=2.7V).
FIGURE 2-35: 10 k
Ω
: Write Wiper
(40h
3Fh) Settling Time (VDD=1.8V).
FIGURE 2-36: 10 k
Ω
: Write Wiper
(FFh
00h) Settling Time (VDD=5.5V).
FIGURE 2-37: 10 k
Ω
: Write Wiper
(FFh
00h) Settling Time (VDD=2.7V).
FIGURE 2-38: 10 k
Ω
: Write Wiper
(FFh
00h) Settling Time (VDD=1.8V).
I. / “11$ .: .T u I. :. mum J“ flu. :. :. .I I. .. :. /y\ :.\/ d 3 w//\ .:
MCP40D17/18/19
DS22152B-page 20 © 2009 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-39: 50 k
Ω
Pot Mode : RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (VDD = 5.5V).
FIGURE 2-40: 50 k
Ω
Pot Mode : RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (VDD = 2.7V).
FIGURE 2-41: 50 k
Ω
Pot Mode : RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (VDD = 1.8V).
FIGURE 2-42: 50 k
Ω
Rheo Mode : RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (VDD = 5.5V).(IW = 90
µ
A, B = VSS)
FIGURE 2-43: 50 k
Ω
Rheo Mode : RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (VDD = 2.7V).(IW = 45
µ
A, B = VSS).
FIGURE 2-44:
50 k
Ω
Rheo Mode : R
W
(
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (V
DD
= 1.8V). (I
W
=260
µ
A, B = V
SS
).
20
40
60
80
100
120
0 326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
-40°C 25°C
85°C 125°C
20
60
100
140
180
220
260
300
0326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
-40°C
25°C
85°
RW
125°C
Note: Refer to AN1080 for additional informa-
tion on the characteristics of the wiper
resistance (RW) with respect to device
voltage and wiper setting value.
0
2000
4000
6000
8000
10000
0326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-0.35
-0.25
-0.15
-0.05
0.05
0.15
0.25
0.35
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
20
40
60
80
100
120
0 326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
R
W
-40°C 25°C
85°C 125°C
20
60
100
140
180
220
260
300
0 326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL RW
-40°C
25°C
85°C 125°C
Note: Refer to AN1080 for additional informa-
tion on the characteristics of the wiper
resistance (RW) with respect to device
voltage and wiper setting value.
0
2000
4000
6000
8000
10000
0326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-1
1
3
5
7
9
11
13
15
17
19
21
23
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
© 2009 Microchip Technology Inc. DS22152B-page 21
MCP40D17/18/19
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-45: 50 k
Ω
: Full Scale Error
(FSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V).
FIGURE 2-46: 50 k
Ω
: Zero Scale Error
(ZSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V).
FIGURE 2-47: 50 k
Ω
: Nominal Resistance
(
Ω
) vs. Temperature and VDD.
FIGURE 2-48: 50 k
Ω
: RBW Tempco
Δ
RWB /
Δ
T vs. Code.
FIGURE 2-49: 50 k
Ω
: Power-Up Wiper
Response Time.
FIGURE 2-50: 50 k
Ω
: Digital Feedthrough
(SCL signal coupling to Wiper pin).
-0.16
-0.12
-0.08
-0.04
0.00
-40 0 40 80 120
Ambient Temperature (°C)
Full-Scale Error (FSE) (LSb)
2.7 5.5V
1.8V
0.00
0.04
0.08
0.12
0.16
0.20
-40 0 40 80 120
Ambient Temperature (°C)
Zero-Scale Error (ZSE) (LSb)
2.7
5.5V
1.8V
48800
49000
49200
49400
49600
49800
-40 0 40 80 120
Ambient Temperature (°C)
Nominal Resistance (RAB
)
(Ohms)
2.7V
5.5V
1.8V
0
20
40
60
80
100
0 326496
Wiper Setting (decimal)
RBW Tempco (PPM)
2.7V
5.5V
Wiper
VDD
‘LLLLL.LLL.LLL.L‘L.LJ_ L.L
MCP40D17/18/19
DS22152B-page 22 © 2009 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-51: 50 k
Ω
: Write Wiper
(40h
3Fh) Settling Time (VDD=5.5V).
FIGURE 2-52: 50 k
Ω
: Write Wiper
(40h
3Fh) Settling Time (VDD=2.7V).
FIGURE 2-53: 50 k
Ω
: Write Wiper
(40h
3Fh) Settling Time (VDD=1.8V).
FIGURE 2-54: 50 k
Ω
: Write Wiper
(FFh
00h) Settling Time (VDD=5.5V).
FIGURE 2-55: 50 k
Ω
: Write Wiper
(FFh
00h) Settling Time (VDD=2.7V).
FIGURE 2-56: 50 k
Ω
: Write Wiper
(FFh
00h) Settling Time (VDD=1.8V).
.H OH 0H 1, .5 H9 k 14 OH HO 0H HO 0H HO
© 2009 Microchip Technology Inc. DS22152B-page 23
MCP40D17/18/19
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-57: 100 k
Ω
Pot Mode : RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (VDD = 5.5V).
FIGURE 2-58: 100 k
Ω
Pot Mode : RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (VDD = 2.7V).
FIGURE 2-59: 100 k
Ω
Pot Mode : RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (VDD = 1.8V).
FIGURE 2-60:
100 k
Ω
Rheo Mode : R
W
(
Ω
), INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (V
DD
= 5.5V). (I
W
= 45 µA, B = V
SS
).
FIGURE 2-61:
100 k
Ω
Rheo Mode : R
W
(
Ω
), INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (V
DD
= 2.7V). (I
W
= 21 µA, B = V
SS
).
FIGURE 2-62:
100 k
Ω
Rheo Mode : R
W
(
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (V
DD
= 1.8V). (I
W
=260
µ
A, B = V
SS
).
20
40
60
80
100
120
0 326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
-40°C 25°C
85°C 125°C
20
60
100
140
180
220
260
300
0326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
-40°C 25°C
85°
RW
125°C
Note: Refer to AN1080 for additional informa-
tion on the characteristics of the wiper
resistance (RW) with respect to device
voltage and wiper setting value.
0
2500
5000
7500
10000
12500
15000
0326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-0.35
-0.25
-0.15
-0.05
0.05
0.15
0.25
0.35
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
20
40
60
80
100
120
0 326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
R
W
-40°C 25°C
85°C 125°C
20
60
100
140
180
220
260
300
0 326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL RW
-40°C 25°C
85°C 125°C
Note: Refer to AN1080 for additional informa-
tion on the characteristics of the wiper
resistance (RW) with respect to device
voltage and wiper setting value.
0
2500
5000
7500
10000
12500
15000
0326496
Wiper Setting (decimal)
Wiper Resistance (RW
)
(ohms)
-1
1
3
5
7
9
11
13
15
17
19
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
MCP40D17/18/19
DS22152B-page 24 © 2009 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-63: 100 k
Ω
: Full Scale Error
(FSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V).
FIGURE 2-64: 100 k
Ω
: Zero Scale Error
(ZSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V).
FIGURE 2-65: 100 k
Ω
: Nominal
Resistance (
Ω
) vs. Temperature and VDD.
FIGURE 2-66: 100 k
Ω
: RBW Tempco
Δ
RWB /
Δ
T vs. Code.
FIGURE 2-67: 100 k
Ω
: Power-Up Wiper
Response Time.
FIGURE 2-68: 100 k
Ω
: Digital
Feedthrough (SCL signal coupling to Wiper pin).
-0.08
-0.06
-0.04
-0.02
0.00
-40 0 40 80 120
Ambient Temperature (°C)
Full-Scale Error (FSE) (LSb)
2.7
5.5V
1.8V
0.00
0.04
0.08
0.12
-40 0 40 80 120
Ambient Temperature (°C)
Zero-Scale Error (ZSE) (LSb)
2.7
5.5V
1.8V
97800
98000
98200
98400
98600
98800
99000
99200
99400
99600
99800
-40 0 40 80 120
Ambient Temperature (°C)
Nominal Resistance (RAB
)
(Ohms)
2.7V
5.5V
1.8V
0
20
40
60
80
100
0 326496
Wiper Setting (decimal)
RBW Tempco (PPM)
2.7V
5.5V
Wiper
VDD
Ill ,ll Plfll III III Fill IPI FIEIPIMIFI
© 2009 Microchip Technology Inc. DS22152B-page 25
MCP40D17/18/19
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-69: 100 k
Ω
: Write Wiper
(40h
3Fh) Settling Time (VDD = 5.5V).
FIGURE 2-70: 100 k
Ω
: Write Wiper
(40h
3Fh) Settling Time (VDD = 2.7V).
FIGURE 2-71: 100 k
Ω
: Write Wiper
(40h
3Fh) Settling Time (VDD = 1.8V).
FIGURE 2-72: 100 k
Ω
: Write Wiper
(FFh
00h) Settling Time (VDD = 5.5V).
FIGURE 2-73: 100 k
Ω
: Write Wiper
(FFh
00h) Settling Time (VDD = 2.7V).
FIGURE 2-74: 100 k
Ω
: Write Wiper
(FFh
00h) Settling Time (VDD = 1.8V).
MCP40D17/18/19
DS22152B-page 26 © 2009 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-75: VIH (SCL, SDA) vs. VDD and
Temperature.
FIGURE 2-76: VIL (SCL, SDA) vs. VDD and
Temperature.
FIGURE 2-77: VOL (SDA) vs. VDD and
Temperature.
FIGURE 2-78: POR/BOR Trip point vs. VDD
and Temperature.
0
0.5
1
1.5
2
2.5
3
3.5
4
-40 0 40 80 120
Temperature (°C)
VIH (V)
5.5V
2.7V
1.8V
0
0.5
1
1.5
2
-40 0 40 80 120
Temperature (°C)
VIL (V)
5.5V
2.7V
1.8V
0
0.05
0.1
0.15
0.2
0.25
0.3
-40 0 40 80 120
Temperature (°C)
VOL (mV)
5.5V (@ 3mA)
2.7V (@ 3mA)
1.8V (@ 1mA)
0
0.2
0.4
0.6
0.8
1
1.2
-40 0 40 80 120
Temperature (°C)
VDD (V)
5.5
V
2.7V
© 2009 Microchip Technology Inc. DS22152B-page 27
MCP40D17/18/19
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-79: 5k
Ω
– Gain vs. Frequency
(-3 dB).
FIGURE 2-80: 10 k
Ω
– Gain vs. Frequency
(-3 dB).
FIGURE 2-81: 50 k
Ω
– Gain vs. Frequency
(-3 dB).
FIGURE 2-82: 100 k
Ω
– Gain vs.
Frequency (-3 dB).
2.1 Test Circuits
FIGURE 2-83: Gain vs. Frequency Test
(-3 dB).
-50
-40
-30
-20
-10
0
10
100 1,000 10,000
Frequency (kHz)
dB
Code = 7Fh
Code = 3Fh
Code = 01h
Code = 0Fh Code = 1Fh
-60
-50
-40
-30
-20
-10
0
10
100 1,000 10,000
Frequency (kHz)
dB
Code = 7Fh
Code = 3Fh
Code = 01h
Code = 0Fh Code = 1Fh
-60
-50
-40
-30
-20
-10
0
10
100 1,000 10,000
Frequency (kHz)
dB
Code = 7Fh
Code = 3Fh
Code = 0Fh
Code = 1Fh
Code = 01h
-60
-50
-40
-30
-20
-10
0
10
100 1,000 10,000
Frequency (kHz)
dB
Code = 7Fh
Code = 3Fh
Code = 0Fh
Code = 1Fh
Code = 01h
+
-
VOUT
+5V
A
B
W
VIN
+5V
MCP40D17/18/19
DS22152B-page 28 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS22152B-page 29
MCP40D17/18/19
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
Additional descriptions of the device pins follow.
TABLE 3-1: PINOUT DESCRIPTION FOR THE MCP40D17/18/19
Pin
Name
Pin Number Pin
Type Buffer
Type Function
MCP40D17
(SC70-6) MCP40D18
(SC70-6) MCP40D19
(SC70-5)
VDD 1 1 1 P Positive Power Supply Input
VSS 2 2 2 P Ground
SCL333I/OST (OD)I
2C Serial Clock pin
SDA444I/OST (OD)I
2C Serial Data pin
B 5 I/O A Potentiometer Terminal B
W 6 5 5 I/O A Potentiometer Wiper Terminal
A 6 I/O A Potentiometer Terminal A
Legend: A = Analog input ST (OD) = Schmitt Trigger with Open Drain
I = Input O = Output I/O = Input/Output P = Power
MCP40D17/18/19
DS22152B-page 30 © 2009 Microchip Technology Inc.
3.1 Positive Power Supply Input (VDD)
The VDD pin is the device’s positive power supply input.
The input power supply is relative to VSS and can range
from 1.8V to 5.5V. A de-coupling capacitor on VDD
(to VSS) is recommended to achieve maximum
performance.
While the device’s voltage is in the range of
1.8V VDD < 2.7V, the Resistor Network’s electrical
performance of the device may not meet the data sheet
specifications.
3.2 Ground (VSS)
The VSS pin is the device ground reference.
3.3 I2C Serial Clock (SCL)
The SCL pin is the serial clock pin of the I2C interface.
The MCP40D17/18/19 acts only as a slave and the
SCL pin accepts only external serial clocks. The SCL
pin is an open-drain output. Refer to Section 5.0
“Serial Interface - I2C Module” for more details of I2C
Serial Interface communication.
3.4 I2C Serial Data (SDA)
The SDA pin is the serial data pin of the I2C interface.
The SDA pin has a Schmitt trigger input and an
open-drain output. Refer to Section 5.0 “Serial
Interface - I2C Module” for more details of I2C Serial
Interface communication.
3.5 Potentiometer Terminal B
The terminal B pin (available on some devices) is
connected to the internal potentiometer’s terminal B.
The potentiometer’s terminal B is the fixed connection
to the Zero Scale (0x00 tap) wiper value of the digital
potentiometer.
The terminal B pin is available on the MCP40D17
device. The terminal B pin does not have a polarity
relative to the terminal W pin. The terminal B pin can
support both positive and negative current. The voltage
on terminal B must be between VSS and VDD.
The terminal B pin is not available on the MCP40D18
and MCP40D19 devices. For these devices, the
potentiometer’s terminal B is internally connected to
VSS.
3.6 Potentiometer Wiper (W) Terminal
The terminal W pin is connected to the internal
potentiometer’s terminal W (the wiper). The wiper
terminal is the adjustable terminal of the digital
potentiometer. The terminal W pin does not have a
polarity relative to terminals A or B pins. The terminal
W pin can support both positive and negative current.
The voltage on terminal W must be between VSS and
VDD.
3.7 Potentiometer Terminal A
The terminal A pin (available on some devices) is
connected to the internal potentiometer’s terminal A.
The potentiometer’s terminal A is the fixed connection
to the Full Scale (0x7F tap) wiper value of the digital
potentiometer.
The terminal A pin is available on the MCP40D18
devices. The terminal A pin does not have a polarity
relative to the terminal W pin. The terminal A pin can
support both positive and negative current. The voltage
on terminal A must be between VSS and VDD.
The terminal A pin is not available on the MCP40D17
and MCP40D19 devices. For these devices, the
potentiometer’s terminal A is internally floating.
© 2009 Microchip Technology Inc. DS22152B-page 31
MCP40D17/18/19
4.0 GENERAL OVERVIEW
The MCP40D17/18/19 devices are general purpose
digital potentiometers intended to be used in
applications where a programmable resistance with
moderate bandwidth is desired.
This Data Sheet covers a family of three Digital
Potentiometer and Rheostat devices. The MCP40D18
device is the Potentiometer configuration, while the
MCP40D17 and MCP40D19 devices are the Rheostat
configuration.
Applications generally suited for the MCP40D17/18/19
devices include:
Computer Servers
Set point or offset trimming
Sensor calibration
Selectable gain and offset amplifier designs
Cost-sensitive mechanical trim pot replacement
As the Device Block Diagram shows, there are four
main functional blocks. These are:
POR/BOR Operation
Serial Interface - I2C Module
Resistor Network
The POR/BOR operation and the Memory Map are
discussed in this section and the I2C and Resistor
Network operation are described in their own sections.
The Serial Commands commands are discussed in
Section 5.4.
4.1 POR/BOR Operation
The Power-on Reset is the case where the device is
having power applied to it from VSS. The Brown-out
Reset occurs when a device had power applied to it,
and that power (voltage) drops below the specified
range.
The devices RAM retention voltage (VRAM) is lower
than the POR/BOR voltage trip point (VPOR/VBOR). The
maximum VPOR/VBOR voltage is less than 1.8V.
When VPOR/VBOR < VDD < 2.7V, the Resistor Network’s
electrical performance may not meet the data sheet
specifications. In this region, the device is capable of
reading and writing to its volatile memory if the proper
serial command is executed.
Table 4-1 shows the digital pot’s level of functionality
across the entire VDD range, while Figure 4-1 illustrates
the Power-up and Brown-out functionality.
4.1.1 POWER-ON RESET
When the device powers up, the device VDD will cross
the VPOR/VBOR voltage. Once the VDD voltage crosses
the VPOR/VBOR voltage, the following happens:
Volatile wiper register is loaded with the default
wiper value (3Fh)
The device is capable of digital operation
4.1.2 BROWN-OUT RESET
When the device powers down, the device VDD will
cross the VPOR/VBOR voltage. Once the VDD voltage
decreases below the VPOR/VBOR voltage the following
happens:
Serial Interface is disabled
If the VDD voltage decreases below the VRAM voltage
the following happens:
Volatile wiper registers may become corrupted
As the voltage recovers above the VPOR/VBOR voltage
see Section 4.1.1 “Power-on Reset”.
Serial commands not completed due to a Brown-out
condition may cause the memory location to become
corrupted.
4.1.3 WIPER REGISTER (RAM)
The Wiper Register is volatile memory that starts
functioning at the RAM retention voltage (VRAM). The
Wiper Register will be loaded with the default wiper
value when VDD will rise above the VPOR/VBOR voltage.
4.1.4 DEVICE CURRENTS
The current of the device can be classified into two
modes of the device operation. These are:
Serial Interface Inactive (Static Operation)
Serial Interface Active
Static Operation occurs when a Stop condition is
received. Static Operation is exited when a Start
condition is received.
DD <, s="" :="" s="">
MCP40D17/18/19
DS22152B-page 32 © 2009 Microchip Technology Inc.
TABLE 4-1: DEVICE FUNCTIONALITY AT EACH VDD REGION (NOTE 1)
FIGURE 4-1: Power-up and Brown-out.
VDD Level Serial
Interface Potentiometer
Terminals Wiper Setting Comment
VDD < VBOR < 1.8V Ignored “unknown” Unknown
VBOR VDD < 1.8V “Unknown” Operational with
reduced electrical
specs
Wiper Register loaded
with POR/BOR value
1.8V VDD < 2.7V Accepted Operational with
reduced electrical
specs
Wiper Register
determines Wiper
Setting
Electrical performance may not
meet the data sheet specifications.
2.7V VDD 5.5V Accepted Operational Wiper Register
determines Wiper
Setting
Meets the data sheet specifications
Note 1: For system voltages below the minimum operating voltage, the customer will be recommended to use a
voltage supervisor to hold the system in reset. This will ensure that MCP4017/18/19 commands are not
attempted out of the operating range of the device.
C FEE
© 2009 Microchip Technology Inc. DS22152B-page 33
MCP40D17/18/19
5.0 SERIAL INTERFACE -
I2C MODULE
A 2-wire I2C serial protocol is used to write or read the
digital potentiometer’s wiper register. The I2C protocol
utilizes the SCL input pin and SDA input/output pin.
The I2C serial interface supports the following features:
Slave mode of operation
7-bit addressing
The following clock rate modes are supported:
- Standard mode, bit rates up to 100 kb/s
- Fast mode, bit rates up to 400 kb/s
Support Multi-Master Applications
The serial clock is generated by the Master.
The I2C Module is compatible with the Phillips I2C
specification. Philips only defines the field types, field
lengths, timings, etc. of a frame. The frame content
defines the behavior of the device. The frame content
for the MCP40D17, MCP40D18, and MCP40D19
devices are defined in this section of the data sheet.
Figure 5-1 shows a typical I2C bus configurations.
FIGURE 5-1: Typical Application I2C Bus
Configurations.
Refer to Section 2.0 “Typical Performance Curves”,
AC/DC Electrical Characteristics table for detailed input
threshold and timing specifications.
5.1 I2C I/O Considerations
I2C specifications require active low, passive high
functionality on devices interfacing to the bus. Since
devices may be operating on separate power supply
sources, ESD clamping diodes are not permitted. The
specification recommends using open drain transistors
tied to VSS (common) with a pull-up resistor. The
specification makes some general recommendations
on the size of this pull-up, but does not specify the
exact value since bus speeds and bus capacitance
impacts the pull-up value for optimum system
performance.
Common pull-up values range from 1 kΩ to a maximum
of ~10 kΩ. Power sensitive applications tend to choose
higher values to minimize current losses during
communication but these applications also typically
utilize lower VDD.
The SDA and SCL float (are not driving) when the
device is powered down.
A "glitch" filter is on the SCL and SDA pins when the pin
is an input. When these pins are an output, there is a
slew rate control of the pin that is independent of device
frequency.
5.1.1 SLOPE CONTROL
The device implements slope control on the SDA
output. The slope control is defined by the fast mode
specifications.
For Fast (FS) mode, the device has spike suppression
and Schmidt trigger inputs on the SDA and SCL pins.
Single I2C Bus Configuration
Host
Controller
Device 1 Device 3 Device n
Device 2 Device 4
IIIIII r___.' |.___J
MCP40D17/18/19
DS22152B-page 34 © 2009 Microchip Technology Inc.
5.2 I2C Bit Definitions
I2C bit definitions include:
Start Bit
Data Bit
Acknowledge (A) Bit
Repeated Start Bit
Stop Bit
Clock Stretching
Figure 5-8 shows the waveform for these states.
5.2.1 START BIT
The Start bit (see Figure 5-2) indicates the beginning of
a data transfer sequence. The Start bit is defined as the
SDA signal falling when the SCL signal is “High”.
FIGURE 5-2: Start Bit.
5.2.2 DATA BIT
The SDA signal may change state while the SCL signal
is Low. While the SCL signal is High, the SDA signal
MUST be stable (see Figure 5-3).
FIGURE 5-3: Data Bit.
5.2.3 ACKNOWLEDGE (A) BIT
The A bit (see Figure 5-4) is a response from the Slave
device to the Master device. Depending on the context
of the transfer sequence, the A bit may indicate
different things. Typically the Slave device will supply
an A response after the Start bit and 8 “data” bits have
been received. The A bit will have the SDA signal low.
FIGURE 5-4: Acknowledge Waveform.
If the Slave Address is not valid, the Slave Device will
issue a Not A (A). The A bit will have the SDA signal
high.
If an error condition occurs (such as an A instead of A)
then a START bit must be issued to reset the command
state machine.
TABLE 5-1: MCP40D17/18/19 A / A
RESPONSES
5.2.4 REPEATED START BIT
The Repeated Start bit (see Figure 5-5) indicates
the current Master Device wishes to continue
communicating with the current Slave Device without
releasing the I2C bus. The Repeated Start condition is
the same as the Start condition, except that the
Repeated Start bit follows a Start bit (with the Data bits
+ A bit) and not a Stop bit.
The Start bit is the beginning of a data transfer
sequence and is defined as the SDA signal falling when
the SCL signal is “High”.
FIGURE 5-5: Repeat Start Condition
Waveform.
SDA
SCL S
1st Bit 2nd Bit
SDA
SCL S
1st Bit 2nd Bit
A
8
D0
9
SDA
SCL
Event Acknowledge
Bit Response Comment
General Call A
Slave Address
valid A
Slave Address
not valid A
Bus Collision N.A. I2C Module Resets,
or a “Don’t Care” if
the collision occurs
on the Masters
“Start bit”.
Note 1: A bus collision during the Repeated Start
condition occurs if:
SDA is sampled low when SCL goes
from low to high.
SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
SDA
SCL
Sr = Repeated Start
1st Bit
© 2009 Microchip Technology Inc. DS22152B-page 35
MCP40D17/18/19
5.2.5 STOP BIT
The Stop bit (see Figure 5-6) Indicates the end of the
I2C Data Transfer Sequence. The Stop bit is defined as
the SDA signal rising when the SCL signal is “High”.
A Stop bit resets the I2C interface of the other devices.
FIGURE 5-6: Stop Condition Receive or
Transmit Mode.
5.2.6 CLOCK STRETCHING
“Clock Stretching” is something that the Secondary
Device can do, to allow additional time to “respond” to
the “data” that has been received.
The MCP40D17/18/19 will not strech the clock signal
(SCL) since memory read accesses occur fast enough.
5.2.7 ABORTING A TRANSMISSION
If any part of the I2C transmission does not meet the
command format, it is aborted. This can be intentionally
accomplished with a START or STOP condition. This is
done so that noisy transmissions (usually an extra
START or STOP condition) are aborted before they
corrupt the device.
5.2.8 IGNORING AN I2C TRANSMISSION
AND “FALLING OFF” THE BUS
The MCP40D17/18/19 expects to receive entire, valid
I2C commands and will assume any command not
defined as a valid command is due to a bus corruption
and will enter a passive high condition on the SDA
signal. All signals will be ignored until the next valid
START condition and CONTROL BYTE are received.
FIGURE 5-7: Typical 16-bit I2C Waveform Format.
FIGURE 5-8: I2C Data States and Bit Sequence.
SCL
SDA A / A
P
1st
SDA
SCL
S2nd 3rd 4th 5th 6th 7th 8th PA/A
Bit Bit Bit Bit Bit Bit Bit Bit 1st 2nd 3rd 4th 5th 6th 7th 8th A/A
Bit Bit Bit Bit Bit Bit Bit Bit
SCL
SDA
START
Condition STOP
Condition
Data allowed
to change Data or
A valid
MCP40D17/18/19
DS22152B-page 36 © 2009 Microchip Technology Inc.
5.2.9 I2C COMMAND PROTOCOL
The MCP40D17/18/19 is a slave I2C device which
supports 7-bit slave addressing. The slave address
contains seven fixed bits. Figure 5-9 shows the control
byte format.
5.2.9.1 Control Byte (Slave Address)
The Control Byte is always preceded by a START
condition. The Control Byte contains the slave address
consisting of seven fixed bits and the R/W bit. Figure 5-
9shows the control byte format and Table 5-2 shows
the I2C address for the devices.
All devices are offered with the I2C slave address of
0101110”, while the MCP40D18 also offers a second
standard I2C slave address of “0111110”.
FIGURE 5-9: Slave Address Bits in the
I2C Control Byte (Slave Address = “0101110”).
TABLE 5-2: DEVICE I2C ADDRESS
5.2.9.2 Hardware Address Pins
The MCP40D17/MCP40D18/MCP40D19 does not
support hardware address bits.
5.2.10 GENERAL CALL
The General Call is a method that the Master device
can communicate with all other Slave devices.
The MCP40D17/18/19 devices do not respond to
General Call address and commands, and therefore
the communications are Not Acknowledged.
FIGURE 5-10: General Call Formats.
SA6A5A4A3A2A1A0R/W A/A
Start
bit
Slave Address
R/W bit
A bit (controlled by slave device)
R/W = 0 = write
R/W = 1 = read
A = 0 = Slave Device Acknowledges byte
A = 1 = Slave Device does not Acknowledge byte
“0” “1” “0” “1” “1” “1” “0”
Device I2C Address Comment
MCP40D17 ‘0101110’
MCP40D18 ‘0101110’ MCP40D18-xxxE/LT
‘0111110’ MCP40D18-xxxAE/LT
MCP40D19 ‘0101110’
© 2009 Microchip Technology Inc. DS22152B-page 37
MCP40D17/18/19
5.3 Software Reset Sequence
At times it may become necessary to perform a
Software Reset Sequence to ensure the MCP40D17/
18/19 device is in a correct and known I2C Interface
state. This only resets the I2C state machine.
This is useful if the MCP40D17/18/19 device powers up
in an incorrect state (due to excessive bus noise, etc),
or if the Master Device is reset during communication.
Figure 5-11 shows the communication sequence to
software reset the device.
FIGURE 5-11: Software Reset Sequence
Format.
The 1st Start bit will cause the device to reset from a
state in which it is expecting to receive data from the
Master Device. In this mode, the device is monitoring
the data bus in Receive mode and can detect the Start
bit forces an internal Reset.
The nine bits of ‘1’ are used to force a Reset of those
devices that could not be reset by the previous Start bit.
This occurs only if the MCP40D17/18/19 is driving an A
on the I2C bus, or is in output mode (from a Read
command) and is driving a data bit of ‘0’ onto the I2C
bus. In both of these cases, the previous Start bit could
not be generated due to the MCP40D17/18/19 holding
the bus low. By sending out nine ‘1’ bits, it is ensured
that the device will see a A (the Master Device does not
drive the I2C bus low to acknowledge the data sent by
the MCP40D17/18/19), which also forces the
MCP40D17/18/19 to reset.
The 2nd Start bit is sent to address the rare possibility
of an erroneous write. This could occur if the Master
Device was reset while sending a Write command to
the MCP40D17/18/19, AND then as the Master Device
returns to normal operation and issues a Start condition
while the MCP40D17/18/19 is issuing an A. In this case
if the 2nd Start bit is not sent (and the Stop bit was sent)
the MCP40D17/18/19 could initiate a write cycle.
The Stop bit terminates the current I2C bus activity.
The MCP40D17/18/19 wait to detect the next Start
condition.
This sequence does not effect any other I2C devices
which may be on the bus, as they should disregard this
as an invalid command.
5.4 Serial Commands
The MCP40D17/18/19 devices support 2 serial
commands. These commands are:
Write Operation
Read Operations
The I2C command formats have been defined so to
support the SMBus version 2.0 Write Byte/Word
Protocol formats and Read Byte/Word Protocol
formats. The SMBus specification defines this
operation is Section 5 of the Version 2.0 document
(August 3, 2000).
This protocol format may be convienient for customers
using library routines for the I2C bus, where all they
need to do is specify the command (read, write, ...) with
the Device Address, the Register Address, and the
Data.
If higher data throughput is desired, please look at the
MCP4017/18/19 devices which have a simplier I2C
command format.
Note: This technique should be supported by
any I2C compliant device. The 24XXXX
I2C Serial EEPROM devices support this
technique, which is documented in
AN1028.
Note: The potential for this erroneous write
ONLY occurs if the Master Device is reset
while sending a Write command to the
MCP40D17/18/19.
S
‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’
S P
Start
bit
Nine bits of ‘1’
Start bit
Stop bit
MCP40D17/18/19
DS22152B-page 38 © 2009 Microchip Technology Inc.
5.4.1 WRITE OPERATION
The write operation requires the START condition,
Control Byte, Acknowledge, Command Code,
Acknowledge, Data Byte, Acknowledge and STOP (or
RESTART) condition. The Control (Slave Address)
Byte requires the R/W bit equal to a logic zero (R/W =
“0”) to generate a write sequence. The MCP40D17/
18/19 is responsible for generating the Acknowledge
(A) bits.
Data is written to the MCP40D17/18/19 after every byte
transfer (during the A bit). If a STOP or RESTART
condition is generated during a data transfer (before
the A bit), the data will not be written to MCP40D17/18/
19.
Data bytes may be written after each Acknowledge.
The command is terminated once a Stop (P) condition
occurs. Refer to Figure 5-12 for the single byte write
sequence and Figure 5-13 for the generic (multi-byte)
write sequence. For a single byte write, the master
sends a STOP or RESTART condition after the 1st data
byte is sent.
The MSb of each Data Byte is a don’t care, since the
wiper register is only 7-bits wide.
The command is terminated once a Stop (P) or Restart
(S) condition occurs.
Figure 5-14 shows the I2C write communication
behavior of the Master Device and the MCP40D17/18/
19 device and the resultant I2C bus values.
5.4.2 READ OPERATIONS
The read operation requires the START condition,
Control Byte, Acknowledge, Command Code,
Acknowledge, Restart Condition, Control Byte,
Acknowledge, Data Byte, the master generating the
Aand STOP (or RESTART) condition. The first Control
Byte requires the R/W bit equal to a logic zero (R/W =
“0”) to write the Command Code, while the second
Control Byte requires the R/W bit equal to a logic one
(R/W = “1”) to generate a read sequence. The
MCP40D17/18/19 will A the Slave Address Byte and A
all the Data Bytes. The I2C Master will A the Slave
Address Byte and the last Data Byte. If there are
multiple Data Bytes, the I2C Master will A all Data Bytes
except the last Data Byte (which it will A).
The MCP40D17/18/19 maintains control of the SDA
signal until all data bits have been clocked out.
The command is terminated once a Stop (P) or Restart
(S) condition occurs. Refer to Figure 5-15 for the read
command sequence. For a single read, the master
sends a STOP or RESTART condition after the 1st data
byte (and A bit) is sent from the slave.
Figure 5-16 shows the I2C read communication
behavior of the Master Device and the MCP40D17/18/
19 device and the resultant I2C bus values.
FIGURE 5-12: I2C Single Byte Write Command Format (Slave Address = “0101110”).
Note: A command code with a non-zero value
will cause the data not to be written to the
wiper register
Note: A command code with a non-zero value
will cause the data not to be read from the
wiper register
\HHH D D D H \H HHHHHH HHH \HHH \HHH D D D HHM\HHHHHHHHHHH D $111113:
© 2009 Microchip Technology Inc. DS22152B-page 39
MCP40D17/18/19
FIGURE 5-13: I2C Write Command Format (Slave Address = “0101110”).
FIGURE 5-14: I2C Write Communication Behavior (Slave Address = “0101110”).
HHH \HHH HHH D D D HHHHHHHHHHHHHHM $111111: $111311: HHH \HHH HHH D D D HHHHHHHHHHHHHHM
MCP40D17/18/19
DS22152B-page 40 © 2009 Microchip Technology Inc.
FIGURE 5-15: I2C Read Command Format (Slave Address = “0101110”).
FIGURE 5-16: I2C Read Communication Behavior (Slave Address = “0101110”).
© 2009 Microchip Technology Inc. DS22152B-page 41
MCP40D17/18/19
6.0 RESISTOR NETWORK
The Resistor Network is made up of two parts. These
are:
Resistor Ladder
•Wiper
Figure 6-1 shows a block diagram for the resistive
network.
Digital potentiometer applications can be divided into
two resistor network categories:
Rheostat configuration
Potentiometer (or voltage divider) configuration
The MCP40D17 is a true rheostat, with terminal B and
the wiper (W) of the variable resistor available on pins.
The MCP40D18 device offers a voltage divider
(potentiometer) with terminal B internally connected to
ground.
The MCP40D19 device is a Rheostat device with
terminal A of the resistor floating, terminal B internally
connected to ground, and the wiper (W) available on
pin.
6.1 Resistor Ladder Module
The resistor ladder is a series of equal value resistors
(RS) with a connection point (tap) between the two
resistors. The total number of resistors in the
series (ladder) determines the RAB resistance
(see Figure 6-1). The end points of the resistor ladder
are connected to the device Terminal A and Terminal B
pins. The RAB (and RS) resistance has small variations
over voltage and temperature.
The Resistor Network has 127 resistors in a string
between terminal A and terminal B. This gives 7-bits of
resolution.
The wiper can be set to tap onto any of these 127
resistors thus providing 128 possible settings
(including terminal A and terminal B). This allows zero
scale to full scale connections.
A wiper setting of 00h connects the Terminal W (wiper)
to Terminal B (Zero Scale). A wiper setting of 3Fh is the
Mid scale setting. A wiper setting of 7Fh connects
the Terminal W (wiper) to Terminal A (Full Scale).
Table 6-1 illustrates the full wiper setting map.
Terminal A and B as well as the wiper W do not have a
polarity. These terminals can support both positive and
negative current.
FIGURE 6-1: Resistor Network Block
Diagram.
TABLE 6-1: WIPER SETTING MAP
Wiper Setting Properties
07Fh Full Scale (W = A)
07Eh - 040h W = N
03Fh W = N (Mid Scale)
03Eh - 001h W = N
000h Zero Scale (W = B)
RS
A
RS
RS
RS
B
N = 127
N = 126
N = 125
N = 1
N = 0
RW (1)
W
01h
Analog
Mux
RW (1)
00h
RW (1)
7Dh
RW (1)
7Eh
RW (1)
7Fh
Note 1: The wiper resistance is tap dependent.
That is, each tap selection resistance
has a small variation. This variation has
more effect on devices with smaller RAB
resistance (5.0 kΩ).
MCP40D17/18/19
DS22152B-page 42 © 2009 Microchip Technology Inc.
Step resistance (RS) is the resistance from one tap
setting to the next. This value will be dependent on the
RAB value that has been selected. Equation 6-1 shows
the calculation for the step resistance while Table 6-2
shows the typical step resistances for each device.
EQUATION 6-1: RS CALCULATION
Equation 6-2 illustrates the calculation used to
determine the resistance between the wiper and
terminal B.
EQUATION 6-2: RWB CALCULATION
The digital potentiometer is available in four nominal
resistances (RAB) where the nominal resistance is
defined as the resistance between terminal A and
terminal B. The four nominal resistances are 5 kΩ,
10 kΩ, 50 kΩ, and 100 kΩ.
The total resistance of the device has minimal variation
due to operating voltage (see Figure 2-11, Figure 2-29,
Figure 2-47, or Figure 2-65).
TABLE 6-2: STEP RESISTANCES
A POR/BOR event will load the Volatile Wiper register
value with the default value. Table 6-3 shows the
default values offered.
TABLE 6-3: DEFAULT FACTORY
SETTINGS SELECTION
Part Number
Resistance (Ω)
Case Total
(RAB) Step (RS)
MCP40D17/18/19-
502
Minimum 4000 31.496
Typical 5000 39.370
Maximum 6000 47.244
MCP40D17/18/19-
103
Minimum 8000 62.992
Typical 10000 78.740
Maximum 12000 94.488
MCP40D17/18/19-
503
Minimum 40000 314.961
Typical 50000 393.701
Maximum 60000 472.441
MCP40D17/18/19-
104
Minimum 80000 629.921
Typical 100000 787.402
Maximum 120000 944.882
RS
RAB
127
---------=
RWB
RABN
127
--------------R
W
+=
N = 0 to 127 (decimal)
Resistance
Code Typical
RAB Value
Default POR Wiper
Setting Code (1)
-502 5.0 kΩMid-scale 3Fh
-103 10.0 kΩMid-scale 3Fh
-503 50.0 kΩMid-scale 3Fh
-104 100.0 kΩMid-scale 3Fh
Note 1: Custom POR/BOR Wiper Setting options
are available, contact the local Microchip
Sales Office for additional information.
Custom options have minimum volume
requirements.
© 2009 Microchip Technology Inc. DS22152B-page 43
MCP40D17/18/19
6.2 Resistor Configurations
6.2.1 RHEOSTAT CONFIGURATION
When used as a rheostat, two of the three digital
potentiometer’s terminals are used as a resistive
element in the circuit. With terminal W (wiper) and
either terminal A or terminal B, a variable resistor is
created. The resistance will depend on the tap setting
of the wiper (and the wipers resistance). The
resistance is controlled by changing the wiper setting
The unused terminal (B or A) should be left floating.
Figure 6-2 shows the two possible resistors that can be
used. Reversing the polarity of the A and B terminals
will not affect operation.
FIGURE 6-2: Rheostat Configuration.
This allows the control of the total resistance between
the two nodes. The total resistance depends on the
“starting” terminal to the Wiper terminal. So at the code
00h, the RBW resistance is minimal (RW), but the RAW
resistance in maximized (RAB + RW). Conversely, at the
code 3Fh, the RAW resistance is minimal (RW), but the
RBW resistance in maximized (RAB + RW).
The resistance Step size (RS) equates to one LSb of
the resistor.
The pinout for the rheostat devices is such that as the
wiper register is incremented, the resistance of the
resistor will increase (as measured from Terminal B to
the W Terminal).
6.2.2 POTENTIOMETER
CONFIGURATION
When used as a potentiometer, all three terminals of
the device are tied to different nodes in the circuit. This
allows the potentiometer to output a voltage
proportional to the input voltage. This configuration is
sometimes called voltage divider mode. The
potentiometer is used to provide a variable voltage by
adjusting the wiper position between the two endpoints
as shown in Figure 6-3. Reversing the polarity of the A
and B terminals will not affect operation.
FIGURE 6-3: Potentiometer
Configuration.
The temperature coefficient of the RAB resistors is
minimal by design. In this configuration, the resistors all
change uniformly, so minimal variation should be seen.
The Wiper resistor temperature coefficient is different
to the RAB temperature coefficient. The voltage at node
V3 (Figure 6-3) is not dependent on this Wiper
resistance, just the ratio of the RAB resistors, so this
temperature coefficient in most cases can be ignored.
Note: To avoid damage to the internal wiper
circuitry in this configuration, care should
be taken to insure the current flow never
exceeds 2.5 mA.
A
B
W
Resistor
RAW RBW
or
Note: To avoid damage to the internal wiper
circuitry in this configuration, care should
be taken to insure the current flow never
exceeds 2.5 mA.
A
B
W
V1
V3
V2
MCP40D17/18/19
DS22152B-page 44 © 2009 Microchip Technology Inc.
6.3 Wiper Resistance
Wiper resistance is the series resistance of the analog
switch that connects the selected resistor ladder node
to the Wiper Terminal common signal (see Figure 6-1).
A value in the volatile wiper register selects which
analog switch to close, connecting the W terminal to
the selected node of the resistor ladder.
The resistance is dependent on the voltages on the
analog switch source, gate, and drain nodes, as well as
the device’s wiper code, temperature, and the current
through the switch. As the device voltage decreases,
the wiper resistance increases (see Figure 6-4 and
Table 6-4).
The wiper can connect directly to Terminal B or to
Terminal A. A zero scale connections, connects the
Terminal W (wiper) to Terminal B (wiper setting of
000h). A full scale connections, connects the
Terminal W (wiper) to Terminal A (wiper setting of 7Fh).
In these configurations the only resistance between the
Terminal W and the other Terminal (A or B) is thaΩt of
the analog switches.
The wiper resistance is typically measured when the
wiper is positioned at either zero scale (00h) or full
scale (3Fh).
The wiper resistance in potentiometer-generated
voltage divider applications is not a significant source
of error.
The wiper resistance in rheostat applications can
create significant nonlinearity as the wiper is moved
toward zero scale (00h). The lower the nominal
resistance, the greater the possible error.
In a rheostat configuration, this change in voltage
needs to be taken into account. Particularly for the
lower resistance devices. For the 5.0 kΩ device the
maximum wiper resistance at 5.5V is approximately
3.2% of the total resistance, while at 2.7V it is
approximately 6.5% of the total resistance.
In a potentiometer configuration, the wiper resistance
variation does not effect the output voltage seen on the
W pin.
The slope of the resistance has a linear area (at the
higher voltages) and a non-linear area (at the lower
voltages). In where resistance increases faster than the
voltage drop (at low voltages).
FIGURE 6-4: Relationship of Wiper
Resistance (RW) to Voltage.
Since there is minimal variation of the total device
resistance over voltage, at a constant temperature (see
Figure 2-11, Figure 2-29, Figure 2-47, or Figure 2-65),
the change in wiper resistance over voltage can have a
significant impact on the INL and DNL error.
TABLE 6-4: TYPICAL STEP RESISTANCES AND RELATIONSHIP TO WIPER RESISTANCE
RW
VDD
Note: The slope of the resistance has a linear
area (at the higher voltages) and a non-
linear area (at the lower voltages).
Resistance (?) RW / RS (%) (1)
R
W / RAB (%) (2)
Typical Wiper (RW) RW =
Typical RW = Max
@ 5.5V RW = Max
@ 2.7V RW =
Typical RW = Max
@ 5.5V RW = Max
@ 2.7V
Total
(RAB) Step
(RS) Typical Max @
5.5V Max @
2.7V
5000 39.37 100 170 325 254.00% 431.80% 825.5% 2.00% 3.40% 6.50%
10000 78.74 100 170 325 127.00% 215.90% 412.75% 1.00% 1.70% 3.25%
50000 393.70 100 170 325 25.40% 43.18% 82.55% 0.20% 0.34% 0.65%
100000 787.40 100 170 325 12.70% 21.59% 41.28% 0.10% 0.17% 0.325%
Note 1: RS is the typical value. The variation of this resistance is minimal over voltage.
2: RAB is the typical value. The variation of this resistance is minimal over voltage.
© 2009 Microchip Technology Inc. DS22152B-page 45
MCP40D17/18/19
6.4 Operational Characteristics
Understanding the operational characteristics of the
device’s resistor components is important to the system
design.
6.4.1 ACCURACY
6.4.1.1 Integral Non-linearity (INL)
INL error for these devices is the maximum deviation
between an actual code transition point and its
corresponding ideal transition point after offset and
gain errors have been removed. These endpoints are
from 0x00 to 0x7F. Refer to Figure 6-5.
Positive INL means higher resistance than ideal.
Negative INL means lower resistance than ideal.
FIGURE 6-5: INL Accuracy.
6.4.1.2 Differential Non-linearity (DNL)
DNL error is the measure of variations in code widths
from the ideal code width. A DNL error of zero would
imply that every code is exactly 1 LSb wide.
FIGURE 6-6: DNL Accuracy.
6.4.1.3 Ratiometric temperature coefficient
The ratiometric temperature coefficient quantifies the
error in the ratio RAW/RWB due to temperature drift.
This is typically the critical error when using a
potentiometer device (MCP40D18) in a voltage divider
configuration.
6.4.1.4 Absolute temperature coefficient
The absolute temperature coefficient quantifies the
error in the end-to-end resistance (Nominal resistance
RAB) due to temperature drift. This is typically the
critical error when using a rheostat device (MCP40D17
and MCP40D19) in an adjustable resistor
configuration.
111
110
101
100
011
010
001
000
Digital
Input
Code
Actual
transfer
function
INL < 0
Ideal transfer
function
INL < 0
Digital Pot Output
111
110
101
100
011
010
001
000
Digital
Input
Code
Actual
transfer
function
Ideal transfer
function
Narrow code < 1 LSb
Wide code, > 1 LSb
Digital Pot Output
MCP40D17/18/19
DS22152B-page 46 © 2009 Microchip Technology Inc.
6.4.2 MONOTONIC OPERATION
Monotonic operation means that the device’s
resistance increases with every step change (from
terminal A to terminal B or terminal B to terminal A).
The wiper resistances difference at each tap location.
When changing from one tap position to the next (either
increasing or decreasing), the ΔRW is less than the
ΔRS. When this change occurs, the device voltage and
temperature are “the same” for the two tap positions.
FIGURE 6-7: RBW.
0x3F
0x3E
0x3D
0x03
0x02
0x01
0x00
Digital Input Code
Resistance (RBW)
RW
(@ tap)
RS0
RS1
RS3
RS62
RS63
RBW = RSn + RW(@ Tap n)
n = 0
n = ?
© 2009 Microchip Technology Inc. DS22152B-page 47
MCP40D17/18/19
7.0 DESIGN CONSIDERATIONS
In the design of a system with the MCP40D17/18/19
devices, the following considerations should be taken
into account. These are:
The Power Supply
The Layout
In the design of a system with the MCP40D17/18/19
devices, the following considerations should be taken
into account:
Power Supply Considerations
Layout Considerations
7.1 Power Supply Considerations
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 7-1 illustrates an
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close to the device power pin (VDD) as possible (within
4mm).
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
FIGURE 7-1: Typical Microcontroller
Connections.
7.2 Layout Considerations
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP40D17/18/19’s
performance. Careful board layout will minimize these
effects and increase the Signal-to-Noise Ratio (SNR).
Bench testing has shown that a multi-layer board
utilizing a low-inductance ground plane, isolated inputs,
isolated outputs and proper decoupling are critical to
achieving the performance that the silicon is capable of
providing. Particularly harsh environments may require
shielding of critical signals.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
7.2.1 RESISTOR TEMPCO
Characterization curves of the resistor temperature
coefficient (Tempco) are shown in Figure 2-11,
Figure 2-29, Figure 2-47, and Figure 2-65.
These curves show that the resistor network is
designed to correct for the change in resistance as
temperature increases. This technique reduces the
end to end change is RAB resistance.
VDD
VDD
VSS VSS
MCP40D17/18/19
0.1 µF
PICmicro® Microcontroller
0.1 µF
SCL
SDA
W
B
A
MCP40D17/18/19
DS22152B-page 48 © 2009 Microchip Technology Inc.
NOTES:
TRIP
© 2009 Microchip Technology Inc. DS22152B-page 49
MCP40D17/18/19
8.0 APPLICATIONS EXAMPLES
Digital potentiometers have a multitude of practical
uses in modern electronic circuits. The most popular
uses include precision calibration of set point
thresholds, sensor trimming, LCD bias trimming, audio
attenuation, adjustable power supplies, motor control
overcurrent trip setting, adjustable gain amplifiers and
offset trimming. The MCP40D17/18/19 devices can be
used to replace the common mechanical trim pot in
applications where the operating and terminal voltages
are within CMOS process limitations (VDD = 2.7V to
5.5V).
8.1 Set Point Threshold Trimming
Applications that need accurate detection of an input
threshold event often need several sources of error
eliminated. Use of comparators and operational
amplifiers (op amps) with low offset and gain error can
help achieve the desired accuracy, but in many
applications, the input source variation is beyond the
designer’s control. If the entire system can be
calibrated after assembly in a controlled environment
(like factory test), these sources of error are minimized
if not entirely eliminated.
Figure 8-1 illustrates a common digital potentiometer
configuration. This configuration is often referred to as
a “windowed voltage divider”. Note that R1 is not
necessary to create the voltage divider, but its
presence is useful when the desired threshold has
limited range. It is “windowed” because R1 can narrow
the adjustable range of VTRIP to a value much less than
VDD – VSS. If the output range is reduced, the
magnitude of each output step is reduced. This
effectively increases the trimming resolution for a fixed
digital potentiometer resolution. This technique may
allow a lower-cost digital potentiometer to be utilized
(64 steps instead of 256 steps).
The MCP40D18’s low DNL performance is critical to
meeting calibration accuracy in production without
having to use a higher precision digital potentiometer.
EQUATION 8-1: CALCULATING THE
WIPER SETTING FROM
THE DESIRED VTRIP
FIGURE 8-1: Using the Digital
Potentiometer to Set a Precise Output Voltage.
8.1.1 TRIMMING A THRESHOLD FOR AN
OPTICAL SENSOR
If the application has to calibrate the threshold of a
diode, transistor or resistor, a variation range of 0.1V is
common. Often, the desired resolution of 2 mV or
better is adequate to accurately detect the presence of
a precise signal. A “windowed” voltage divider, utilizing
the MCP40D18, would be a potential solution.
Figure 8-2 illustrates this example application.
FIGURE 8-2: Set Point or Threshold
Calibration.
VTRIP VDD
RWB
R1R2
+
-------------------
⎝⎠
⎛⎞
=
D = Digital Potentiometer Wiper Setting (0-127)
RAB = RNominal
RWB = RAB
D
127
D = (R1 + RAB )
127
VTRIP
VDD
VDD
VOUT
A
R1
W
B
SDA
SCL
MCP40D18
VTRIP
0.1 µF
Comparator
VCC+
VCC-
VDD
Rsense
R1
B
A
VDD
W
SDA
SCL MCP6021
MCP40D18
MCP40D17/18/19
DS22152B-page 50 © 2009 Microchip Technology Inc.
8.2 Operational Amplifier
Applications
Figure 8-3 and Figure 8-4 illustrate typical amplifier
circuits that could replace fixed resistors with the
MCP40D17/18/19 to achieve digitally-adjustable
analog solutions.
FIGURE 8-3: Trimming Offset and Gain in
a Non-Inverting Amplifier.
FIGURE 8-4: Programmable Filter.
Op Amp
VIN
VOUT
+
R1
B
A
VDD
WR3
MCP6291
MCP40D17
MCP40D18
Op Amp
VIN VOUT
A
B
W
+
R1
B
A
VDD
W
R4
fc1
2
π
REq C
⋅⋅
-----------------------------=
REq R1RAB RWB
+()R2RWB
+()Rw
+
||
=
Thevenin
Equivalent
MCP6021
MCP40D18
MCP40D18
© 2009 Microchip Technology Inc. DS22152B-page 51
MCP40D17/18/19
8.3 Temperature Sensor Applications
Thermistors are resistors with very predictable
variation with temperature. Thermistors are a popular
sensor choice when a low-cost temperature-sensing
solution is desired. Unfortunately, thermistors have
non-linear characteristics that are undesirable, typically
requiring trimming in an application to achieve greater
accuracy. There are several common solutions to trim
and linearize thermistors. Figure 8-5 and Figure 8-6
are simple methods for linearizing a 3-terminal NTC
thermistor. Both are simple voltage dividers using a
Positive Temperature Coefficient (PTC) resistor (R1)
with a transfer function capable of compensating for the
linearity error in the Negative Temperature Coefficient
(NTC) thermistor.
The circuit, illustrated by Figure 8-5, utilizes a digital
rheostat for trimming the offset error caused by the
thermistor’s part-to-part variation. This solution puts the
digital potentiometer’s RW into the voltage divider
calculation. The MCP40D17/18/19’s RAB temperature
coefficient is a low 50 ppm (-20°C to +70°C). RWs error
is substantially greater than RAB’s error because RW
varies with VDD, wiper setting and temperature. For the
50 kΩ devices, the error introduced by RW is, in most
cases, insignificant as long as the wiper setting is > 6.
For the 2 kΩ devices, the error introduced by RW is
significant because it is a higher percentage of RWB.
For these reasons, the circuit illustrated in Figure 8-5 is
not the most optimum method for “exciting” and
linearizing a thermistor.
FIGURE 8-5: Thermistor Calibration using
a Digital Potentiometer in a Rheostat
Configuration.
The circuit illustrated by Figure 8-6 utilizes a digital
potentiometer for trimming the offset error. This
solution removes RW from the trimming equation along
with the error associated with RW. R2 is not required,
but can be utilized to reduce the trimming “window” and
reduce variation due to the digital pot’s RAB part-to-part
variability.
FIGURE 8-6: Thermistor Calibration using
a Digital Potentiometer in a Potentiometer
Configuration.
NTC
VDD
VOUT
Thermistor
R1
R2
MCP40D17
NTC
VDD
VOUT
Thermistor
R1
MCP40D18
MCP40D17/18/19
DS22152B-page 52 © 2009 Microchip Technology Inc.
8.4 Wheatstone Bridge Trimming
Another common configuration to “excite” a sensor
(such as a strain gauge, pressure sensor or thermistor)
is the wheatstone bridge configuration. The
wheatstone bridge provides a differential output
instead of a single-ended output. Figure 8-7 illustrates
a wheatstone bridge utilizing one to three digital
potentiometers. The digital potentiometers in this
example are used to trim the offset and gain of the
wheatstone bridge.
FIGURE 8-7: Wheatstone Bridge
Trimming.
VDD
VOUT
5kΩ
50 kΩ50 kΩ
MCP40D17
MCP40D17 MCP40D17
© 2009 Microchip Technology Inc. DS22152B-page 53
MCP40D17/18/19
9.0 DEVELOPMENT SUPPORT
9.1 Development Tools
The MCP40D17/18/19 devices can be evaluated with
the MCP4XXXDM-PGA board, but it will require the
removal of the MCP4017 device and the installation of
the MCP40D17 device. Please check the Microchip
web site for the release of this board. The board part
number is tentatively MCP4XXXDM-PGA, and is
expected to be available in the fall of 2009.
9.2 Technical Documentation
Several additional technical documents are available to
assist you in your design and development. These
technical documents include Application Notes,
Technical Briefs, and Design Guides. Table 9-1 shows
some of these documents.
TABLE 9-1: TECHNICAL DOCUMENTATION
Note: The MCP40D17 device is identical to the
MCP4017 device with the exception of the
I2C interface protocol format.
Application
Note Number Title Literature #
AN1080 Understanding Digital Potentiometers Resistor Variations DS01080
AN737 Using Digital Potentiometers to Design Low-Pass Adjustable Filters DS00737
AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692
AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691
AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219
Digital Potentiometer Design Guide DS22017
Signal Chain Design Guide DS21825
MCP40D17/18/19
DS22152B-page 54 © 2009 Microchip Technology Inc.
NOTES:
UUU WWW UUU NNN alor ( ‘)
© 2009 Microchip Technology Inc. DS22152B-page 55
MCP40D17/18/19
10.0 PACKAGING INFORMATION
10.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
Part Number Code
MCP40D19T-502E/LT BTNN
MCP40D19T-103E/LT BUNN
MCP40D19T-503E/LT BVNN
MCP40D19T-104E/LT BWNN
6-Lead SC70 Example:
Part Number Code Part Number Code
MCP40D17T-502E/LT AJNN MCP40D18T-502E/LT APNN
MCP40D17T-103E/LT AKNN MCP40D18T-502AE/LT ATNN
MCP40D17T-503E/LT ALNN MCP40D18T-103E/LT AQNN
MCP40D17T-104E/LT AMNN MCP40D18T-103AE/LT AUNN
MCP40D18T-503E/LT ARNN
MCP40D18T-503AE/LT AVNN
MCP40D18T-104E/LT ASNN
MCP40D18T-104AE/LT AWNN
5-Lead SC70
XXNN
Example:
ATNN
XXNN AJNN
1
11
1
M M I! L Em n _J ,ijj
MCP40D17/18/19
DS22152B-page 56 © 2009 Microchip Technology Inc.
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b
1
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E
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ee
c
L
A1
AA2
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© 2009 Microchip Technology Inc. DS22152B-page 57
MCP40D17/18/19
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6-Lead Plastic Small Outline Transistor (LT) [SC70] [Efl \ *"EEJ DDSCD/ NOTE 1/ , 1 SEATING PLANE Mlcrochip Technology Drawing No. co4451A SheeH ol 2
MCP40D17/18/19
DS22152B-page 58 © 2009 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
6-Lead Plastic Small Outline Transistor (LT) [8070] Units MiLLiMETERS Dimension Limits MIN 1 NOM 1 MAX Number of Pins N 6 Pitch e 0 65 BSC Overaii Height A 0.80 - 1.10 Moided Package Thickness A2 0.70 0.90 1.00 Standoff A1 0 00 - 0 10 Overaii Width E 2.10 380 Moided Package Width E1 1 25 BSC Overaii Length D 2.00 380 Fool Length L 010 0 20 0 46 Lead Thickness c 0.08 - 0.22 Lead Widih b 015 - 0 30 Notes: 1. Pin 1 visuai index feature may vary, but must be iocaled Within the naicned area. 2. Dimensions D and E1 do not inciude mold flash or protrusions. Mold flash or protrusions shali noi exceed a 15mm perside 3. Dimensianing and Ioierancing perASME v14 SM 350 Basic Dimension Theoreticaiiy exact value shown Without tolerances Microchip Technology Drawing No coar151A Sheet 2 of 2
© 2009 Microchip Technology Inc. DS22152B-page 59
MCP40D17/18/19
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
6-Lead Plastic Small Outline Transistor (LT) [SC70] . l E G _l x SlLK SCREEN Y RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MlN l NOM l MAX Contact Pitch E 0.65 BSC Contact Pad Spacing t: 2.20 Contact Pad Width (X28) X 0.40 Contact Pad Lengih (X28) v 0.90 Distance Between Pads G 0.25 Notes 1 Dimensiuning and tolerancing perASME Y14 5M BSC. Bash: Dimension. Theoretically exacl value shown wilhum tolerances. Microchip Technology Drawing No (30472151A
MCP40D17/18/19
DS22152B-page 60 © 2009 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2009 Microchip Technology Inc. DS22152B-page 61
MCP40D17/18/19
APPENDIX A: REVISION HISTORY
Revision B (August 2009)
the following is the List of Modifications:
1. Document updated to include the new standard
I2C slave address (“0111110“) for the
MCP40D18 device.
2. Section 10.0 “Packaging Information”: Cor-
rected the Marking codes for 5-lead SC70
Codes shown were for the 6-lead SC70.
Updated Package Outline Drawings.
Revision A (May 2009)
Original Release of this Document.
MCP40D17/18/19
DS22152B-page 62 © 2009 Microchip Technology Inc.
NOTES:
PART NO. XXX /XX
© 2009 Microchip Technology Inc. DS22152B-page 63
MCP40D17/18/19
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP40D17: Single Rheostat with I2C interface
MCP40D17T:Single Rheostat with I2C interface
(Tape and Reel)
MCP40D18: Single Potentiometer to GND with
I2C Interface
MCP40D18T:Single Potentiometer to GND with
I2C Interface (Tape and Reel)
MCP40D19: Single Rheostat to GND with
I2C Interface
MCP40D19T:Single Rheostat to GND with
I2C Interface (Tape and Reel)
Resistance
Version: 502 = 5 kΩ
103 = 10 kΩ
503 = 50 kΩ
104 = 100 kΩ
I2C Device
Address
Version:
blank = 0101110
A=0111110(1)
Temperature
Range: E = -40°C to +125°C
Package: LT = Plastic Small Outline Transistor (SC70),
5-lead, 6-lead
Note 1: This address is a standard option on the MCP40D18
device only. It is a custom device on the MCP40D17
and MCP40D19 devices.
Examples:
a) MCP40D17T-502E/LT: 5 kΩ,
6-LD SC70
b) MCP40D17T-103E/LT: 10 kΩ,
6-LD SC70
c) MCP40D17T-503E/LT: 50 kΩ,
6-LD SC70
d) MCP40D17T-104E/LT: 100 kΩ,
6-LD SC70
a) MCP40D18T-502E/LT: 5 kΩ,
6-LD SC70
b) MCP40D18T-103E/LT: 10 kΩ,
6-LD SC70
c) MCP40D18T-503E/LT: 50 kΩ,
6-LD SC70
d) MCP40D18T-104E/LT: 100 kΩ,
6-LD SC70
a) MCP40D18T-502AE/LT: 5 kΩ,
6-LD SC70
b) MCP40D18T-103AE/LT: 10 kΩ,
6-LD SC70
c) MCP40D18T-503AE/LT: 50 kΩ,
6-LD SC70
d) MCP40D18T-104AE/LT: 100 kΩ,
6-LD SC70
a) MCP40D19T-502E/LT: 5 kΩ,
5-LD SC70
b) MCP40D19T-103E/LT: 10 kΩ,
5-LD SC70
c) MCP40D19T-503E/LT: 50 kΩ,
5-LD SC70
d) MCP40D19T-104E/LT: 100 kΩ,
5-LD SC70
PART NO. X/XX
PackageTemperature
Range
Device
XXX
Resistance
Version
X
I2C Device
Address
MCP40D17/18/19
DS22152B-page 64 © 2009 Microchip Technology Inc.
NOTES:
QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV = ISO/TS 1694922002 =
© 2009 Microchip Technology Inc. DS22152B-page 65
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
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conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
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Analog-for-the-Digital Age, Application Maestro, CodeGuard,
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ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
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SQTP is a service mark of Microchip Technology Incorporated
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All other trademarks mentioned herein are property of their
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© 2009, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
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are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
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Q ‘MICROCHIP
DS22152B-page 66 © 2009 Microchip Technology Inc.
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Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4080
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
WORLDWIDE SALES AND SERVICE
03/26/09

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