28F008,016,160,320,640,800B3 Spec Update Datasheet by Intel

View All Related Products | Download PDF Datasheet
inte|®
3VoltIntel
®Advanced Boot
Block Flash Memory
28F004/400/008/800/
016/160/320/640B3 (x8/x16)
Specification Update
April 2002
Notice: The 28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 may contain
design defects or errors known as errata, which may cause the product to deviate from published
specifications. Current characterized errata are documented in this specification update.
Order Number: 297948-012
intelg
2Specification Update
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no
liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are
not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 may contain design defects or errors known as errata which may cause
the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 1998–2002
*Other names and brands may be claimed as the property of others.
intelg
Specification Update 3
Contents
Revision History....................................................................................... 5
Preface ...................................................................................................... 6
Summary Table of Changes.................................................................... 7
Identification Information........................................................................ 9
Errata....................................................................................................... 10
Specification Changes .......................................................................... 18
Specification Clarifications................................................................... 18
Documentation Changes....................................................................... 18
intelg
4Specification Update
intelg
Specification Update 5
Revision History
Date Version Description
06/02/98 -001 Document includes all known specifications to date (original version).
07/09/98 -002 Added specification change for µBGA* package pinout
08/10/98 -003
Added Errata for Program and Erase Failure when VPP = 12 V and VCCQ =1.65V
–2.5V
Added Errata for Maximum ICCD Change
10/02/98 -004
This document references 290580-006
Removed Valid Ordering Information Combinations Change for 32-Mbit Densities
(fixed in 290580-006)
Removed µBGA* Package Pinout Change (fixed in 290580-006)
Removed µBGA* Package Mark Clarification (fixed in 290580-006)
Removed IPPD Test Condition Clarification (fixed in 290580-006)
Name changed from Smart 3 Advanced Boot Block Flash Memory Family
12/01/98 -005 Erratum #1 fixed in A-1 Stepping
02/16/99 -006 Specification Update title modified—added part numbers for clarity
02/03/99 -007
Merged existing document with 28F160B3 specification update document
(297835-004).
Added 32-Mb Maximum VCC Change specification change.
10/05/00 -008
Renamed Specification Change #1, 32-Mb Maximum VCC Change,to0.25
µ
m32-
Mb VCC Change, and modified it to indicate that the affected product is the 32-Mb
product on the 0.25µm process
05/03/01 -009 Added Erratum #6, 28F320B3TC Block Locking Failure
Added Erratum #7, 28F320B3xC Reset Failure
07/20/01 -010 Updated Erratum #7, 28F320B3xC Reset Failure, added 3.3v VCC max
11/05/01 -011 Added Erratum #8, 28F640C3xC for Maximum ICCD /I
CCS Change
3/21/02 -012 Added Erratum #9, 28F160B3xC Erase Resume Issue
intelg
6Specification Update
Preface
Preface
This document is an update to the specifications contained in the Affected Documents/Related
Documents table below. This document is a compilation of device and documentation errata,
specification clarifications and changes. It is intended for hardware system manufacturers and
software developers of applications, operating systems, or tools.
Information types defined in Nomenclature are consolidated into the specification update and are
no longer published in other documents.
This document may also contain information that was not previously published.
Affected Documents/Related Documents
Nomenclature
Errata are design defects or errors. These may cause the behavior of the 28F004/400B3, 28F008/
800B3, 28F016/160B3, 28F320B3, 28F640B3 to deviate from published specifications. Hardware
and software designed to be used with any given stepping must assume that all errata documented
for that stepping are present on all devices.
Specification Changes are modifications to the current published specifications. These changes
will be incorporated in any new release of the specification.
Specification Clarifications describe a specification in greater detail or further highlight a
specification’s impact to a complex design situation. These clarifications will be incorporated in
any new release of the specification.
Documentation Changes include typos, errors, or omissions from the current published
specifications. These will be incorporated in any new release of the specification.
Note: Errata remain in the specification update throughout the product’s life cycle, or until a particular
stepping is no longer commercially available. Under these circumstances, errata removed from the
specification update are archived and available upon request. Specification changes, specification
clarifications, and documentation changes are removed from the specification update when the
appropriate changes are made to the appropriate product specification or user documentation
(datasheets, manuals, etc.).
Title Order
3 Volt Intel®Advanced Boot Block Flash Memory, 28F004/400B3, 28F008/800B3,
28F016/160B3, 28F320B3, 28F640B3 Datasheet 290580-011
intelg
Specification Update 7
Summary Table of Changes
Summary Table of Changes
The following table indicates the errata, specification changes, specification clarifications, or
documentation changes which apply to the 28F004/400B3, 28F008/800B3, 28F016/160B3,
28F320B3, 28F640B3 product. Intel may fix some of the errata in a future stepping of the
component, and account for the other outstanding issues through documentation or specification
changes as noted. This table uses the following notations:
Codes Used in Summary Table
Stepping
X: This erratum exists in the stepping indicated. Specification Change or
Clarification that applies to this stepping.
(No mark) or (Blank box): This erratum is fixed in listed stepping, or specification change does not
apply to listed stepping.
Page
(Page): Page location of item in this document.
Status
Doc: Document change or update will be implemented.
Fix: This erratum is intended to be fixed in a future step of the component.
Fixed: This erratum has been previously fixed.
NoFix: There are no plans to fix this erratum.
Eval: Plans to fix this erratum are under evaluation.
Row
Change bar to left of table row indicates this erratum is either new or
modified from the previous version of the document.
inteL
8Specification Update
Summary Table of Changes
Errata
No.
Steppings
Page Status Errata
0.4
micron
A-0
0.4
micron
A-1
0.25
micron
A–0
0.25
micron
A–2
0.18
micron
A-0,
A-2,
A-3
1XX 10 Fixed
Block Locking during Write
Operations if CE# is Toggled
High
2XX 11 Fixed Invalid Read Durations for CE#
High Pulse Width
3XX 11 Fixed Temperature Effect on VCC
Ramp
4X12 Fixed
Program and Erase Failure
When VPP =12VandV
CCQ =
1.65 V – 2.5 V
512 Doc Maximum ICCD Change
6X13 Fix 28F320B3TC Block Locking
Failure
7X14 Fix 28F320B3xC Reset Failure
8X11Fix
28F640C3xC Maximum ICCS
and ICCD Change
9X12Fix
28F160B3xC Erase Resume
Issue
Specification Changes
Number Page Specification Changes
118 0.25µm 32-Mb Maximum VCC Change
Specification Clarifications
Number
Steppings
Page Specification Clarifications
A–0
N/A 18 None in this specification update revision
Documentation Changes
Number Document Revision Page Documentation Changes
N/A 18 None in this specification update revision
intelg
Specification Update 9
Identification Information
Identification Information
Markings
The Finished Processing Order (FPO) number correlates to a specific device stepping as illustrated
in the table below:
Stepping(1) Identifier
0.4micronAstepping NinthdigitontopsideFPOmark(thirdline)=J,K,L,M,orN.
NOTE:
1. Device steppings are based on continuous improvements made in manufacturing and testing of the device
and represent the current material shipped.
intelg
10 Specification Update
Errata
Errata
1. Block Locking during Write Operations If CE# Is Toggled High
Problem: In normal operation, WP# = VIL locks the upper two (or lower two, in the case of a bottom boot
device) parameter blocks. If a program or erase command is issued to a locked block, the WSM
sets the program or erase status bit and the block lock status bit to “1” and prevents the program or
erase operation to the locked block.
However, initial samples of the 28F160B3 flash memory device ignore the WP# pin if CE# is
toggled high during the second cycle of a program or erase operation. Any program and/or erase
commands issued to locked blocks may change memory contents even if WP# = VIL (assuming
VPP >V
PPLK).
Implication: This erratum causes the lockable blocks to be unlocked regardless of the state of WP# when CE# is
toggled high during the write cycle(s).
Workaround: Applications using A-0 material should hold CE# low and toggle WE# to latch command, address,
and data during a program or erase operation.
Only 28F160B3 A-0 stepping (0.4 µm material) is affected by this erratum. This erratum has been
fixedintheA-1stepping.RefertoSummary Table of Changes to determine the affected
stepping(s).
ADDRESSES (A)
V
IH
V
IL
WE# (W)
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
OE# (G)
CE# (E)
D
IN
D
IN
A
IN
A
IN
Valid SRD
This transition forces
WP#toV
IH
internally
High Z
V
IH
V
IL
V
IH
V
IL
DATA (D/Q)
WP#
Program/Erase Cycle
intelg L—J |<—»\><—>\ |<—>\ \ \ \ :X \X\X\X\ :x»;
Specification Update 11
Errata
2. Invalid Read Durations for CE# High Pulse Width
Problem: During consecutive read operations, CE# may be left low or toggled as desired. If CE# is toggled
high (see diagram below) for 4 µs–11 µs between read operations, subsequent reads will return
incorrect data.
Implication: If CE# is not toggled between consecutive reads, there is no impact. Any application that toggles
CE# between read operations will be affected if the CE# high pulse width is within the nonfunc-
tional range, i.e., 4 µs tEHEL 11 µs.
Workaround: Either of the following actions will prevent this erratum:
1. Do not toggle CE# between consecutive read operations
2. Insure tEHEL is less than 4 ms or greater than 11 µs
Status: Only 28F160B3 A-0 stepping (0.4 µm material) is affected by this erratum. This erratum has been
fixed in the A-1 stepping. Refer to Summary Table of Changes to determine the affected
stepping(s).
3. Temperature Effect on VCC Ramp
Problem: The 28F160B3 flash memory operates from 2.7 V–3.6 V across the full extended temperature
range (–40 °C to +85 °C). For a limited number of 28F160B3 engineering samples, when ramping
VCC to below 3.0 V and below +10 °C (–40 °C to +10 °C), the device is not guaranteed to respond
to read, program, and erase operations (see diagram below). If VCC ramps to a value between 3.0 V
and 3.6 V, the device functions normally across the entire extended temperature range.
Implication: If VCC is ramped to [and maintained at] a level below 3 V between –40 °C and +10 °C, the device
may not function properly.
Good
Data
Incorrect
Data
Incorrect
Data
Good
Data
t
EHEL
t
EHEL
t
EHEL
t
EHEL
12 µs 10 µs 7 µs 15 µs
CE#
A
0-19
DQ
0-15
40°C
(Cold)
+10°
(Room)
+85°
(Hot)
0V
2.7–3.0V
VCC
0V
3.0–3.6V
VCC
Read, program & erase not guaranteed
Normal operation
Normal operation
Normal operation
intelg
12 Specification Update
Errata
Workaround: Either of the following actions will prevent this erratum:
1. Ramp VCC above 3.0 V in order to trip the VCC detector; once the detector has “tripped,” the
voltage may be lowered below 3.0 V for normal operation
2. Only ramp VCC at temperatures above +10 °C.
Status: Only engineering samples of 28F160B3 A-0 stepping (0.4 µm material) from lot 7705998FOB and
7705999FOB [backside mark] are affected. This erratum affects all A-0 µBGA* package
engineering samples. Only A-0 TSOP samples with a printed backside mark are affected. If the
TSOP package has no backside mark then it is not affected. This erratum has been fixed in the
A-1 stepping.
4. Program and Erase Failure When VPP =12VandV
CCQ = 1.65 V - 2.5 V
Problem: During production programming (VPP = 12 V) with VCCQ between 1.65 V and 2.5 V, the device
will fail to program or erase.
Implication: Customers should not implement 12 V production programming with VCCQ between 1.65 V and
2.5 V. This may be corrected on future steppings.
Status: Refer to the Summary Tables of Changes to determine the affected stepping(s).
5. Maximum ICCD Change
Problem: The maximum ICCD increases from 20 µA to 25 µA. The following in the revised ICCD specifi-
cation:
Implication: The maximum ICCD is specified under worst case conditions only (VCC = 3.6 V, temperature =
+85 °C). The typical ICCD specification should be used to determine ICCD current draw under
typical conditions (VCC = 3.3 V, temperature = +25 °C). The typical ICCD specification has not
changed.
Status: Refer to the Summary Tables of Changes to determine the affected stepping(s)
Sym Parameter
VCC 2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V
Unit Test ConditionsVCCQ 2.7V3.6V 1.65V2.5V 1.8V2.5V
Note Typ Max Typ Ma x Ty p Max
ICCD
VCC Power-
Down Current 6 725725725µA
VCC =V
CC Max
VCCQ =V
CCQ Max
VIN =V
CCQ or GND
RP#=GN0.2V
NOTE: Since each column lists specifications for a different VCC and VCCQ voltage range combination, the test conditions VCC
Max, VCCQ Max, VCC Min, and VCCQ Min refer to the maximum or minimum VCC or VCCQ voltage listed at the top of each
column.
inteL
Specification Update 13
Errata
6. 28F320B3TC Block Locking Failure
Problem: For the 0.18µm 32 M-bit top boot devices affected by this erratum, block locking functionality
deviates from the datasheet specification. WP#=VIL protects blocks #63 and #64, instead of blocks
#69 and #70).
Implication: There are two implications to this erratum:
1) The two Lockable Parameter Blocks (blocks #69 and #70) are not protected when WP#=VIL;
and
2) When WP#=VIL, blocks #63 and #64 will be locked, and any attempts to program or erase these
two blocks may fail.
Workaround: There are two workarounds for this erratum:
1) Set WP#=VIH when programming or erasing blocks #63 and #64. In addition, hold VPPVPPLK
when not programming or erasing for additional protection against accidental writes; and
2) Temporarily, have software swap the contents of blocks #63 and #64 with the contents of blocks
#69 and #70. If code was originally in blocks #69 and #70, utilize jump routine to blocks #63 and
#64.
Status: This erratum affects all 0.18µm 28F320B3 top boot devices. A fix has been identified for this
erratum and is intended to be implemented in a future microcode revision.
4-Kword Lockable Parameter Block
28F320B3TC Memory Map
70
4-Kword Lockable Parameter Block 69
32-Kword Main Block 62
2
32-Kword Main Block
4-Kword Parameter Block
4-Kword Parameter Block
4-Kword Parameter Block
0
64
65
66
4-Kword Parameter Block
4-Kword Parameter Block 67
68
000000
007FFF
008000
1EFFFF
1F0000
1F7FFF
1F8000
1F8FFF
1F9000
1F9FFF
1FA000
1FAFFF
1FB000
1FBFFF
1FC000
1FCFFF
1FD000
1FDFFF
1FE000
1FEFFF
4-Kword Parameter Block 63
1FF000
1FFFFF
WP#=VIL locks Lockable
Parameter Blocks
Datasheet Specification
WP#=VIL locks Parameter
Blocks #63 and #64
Erratum Behavior
intelg
14 Specification Update
Errata
7. 28F320B3xC Reset Failure
Problem: The 0.18µm 28F320B3xC devices can unintentionally reset under certain conditions where VPP
toggles.
Implication: When the reset occurs, any command being executed is interrupted and the flash switches to read
array mode.
Workaround: There are four workarounds for this erratum:
1) Tie VPP to VCC
2) If the third and forth digits on the top side FPO mark (third line) are equal or greater than “23”,
then VCC may be set from 2.7 V to 3.3 V. VCC must not exceed 3.3 V.
3) Set VPP to a static high or static low level as shown here; and
4) Wait 2 ms after a VPP transition to access the flash device as shown here.
Hold VPP Static No restrictions on
other waveforms
VPP
CE#
WE#
VPP
CE#
WE#
2ms 2ms
intelg
Specification Update 15
Errata
Note: This erratum affects all 0.18µm 28F320B3 devices. Root cause has been identified and fixes are
being evaluated.
8. 28F640B3xC Maximum ICCS and ICCD Change
Problem: On the 0.1m 28F640B3xC device, the maximum ICCS and ICCD deviates from the published
specification and increases from 15 µA to 20 µA. The following table shows the revised ICCS and
ICCD specifications.
Sym Parameter
VCC 2.7V–3.6V
Unit Test ConditionsVCCQ 2.7V–3.6V
Note Type Max
ICCS VCC Standby Current 1,2 7 20 µA
VCC =V
CCMax
CE# = RP# = VCCQ
or during Program/ Erase
Suspend
WP# = VCCQ or GND
ICCD
VCC Deep Power-Down
Current 1,2 7 20 µA
VCC =V
CCMax
VCCQ =V
CCQMax
VIN =V
CCQ or GND
RP#=GND±0.2V
NOTE:
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC,T
A=+2C.
2. The test conditions VCCMax, VCCQMax, VCCMin, and VCCQMin refer to the maximum or minimum VCC or
VCCQ voltage listed at the top of each column.
intelg
16 Specification Update
Errata
9. 28F160B3xC Erase Resume Issue
Problem: On the 0.18µm 28F160B3xC device, a design anomaly was discovered. During an Erase-Suspend
operation, if the Program (40H/10H) sequence is executed, under limited conditions the proceeding
Erase Resume command (D0H) may not actually resume the device. No customers have reported
failures in product applications. Customers who use any version of FDI (Intel Flash Data
Integrator) software will not see this issue. If the Read Array command is issued prior to the Erase
Resume command, users will not see the issue (typical in XIP applications).
Implication: The Resume Command (D0H) may be ignored by the device and will not correctly resume. The
device will appear to remain in suspend (via status register). After a reset of the flash device the
status register will clear. This failure has been recreated in a lab environment only.
Workaround: There are 2 workarounds for this erratum.
1. If FDI (Intel Flash Data Integrator) software is used, users will not see the issue.
2. During an Erase-Suspend (B0H), user must issue any of the following commands listed in
Table-1 after issuing the Program (40H/10H) and data sequence but before issuing the Erase-
Resume (D0H) command.
.
Command
First Bus Cycle Second Bus Cycle
Oper Addr Data Oper Addr
Read Array Write X FFH
Read Identifier Write X 90H Read IA
Read Status Register Write X 70H Read X
Clear Status Register Write X 50H
Program/Erase Suspend Write X B0H
NOTES:
IA: Identifier Address X: Don’t Care
________ IIIII :
Specification Update 17
Errata
Status: Root cause has been identified. New material will be available in August 2002.
Figure 1. Workaround Placment
start
Erase Suspend
(B0H)
Program
(40H/10H)
andData
EraseResume
(D0H)
Erase may not
Resume
start
Erase Suspend
(B0H)
Program
(40H/10H)
andData
EraseResume
(D0H)
EraseResumed
Workaround
commands:
FFH
90H
70H
50H
B0H
ISSUE HERE
Any Valid
Operation(s)
Standard Sequence Pass Sequence
intelg
18 Specification Update
Specification Changes
Specification Changes
1. 0.25µm 32-Mb Maximum VCC Change
Issue: The maximum VCC decreases from 3.6 V to 3.3 V on 0.25µm32-Mb versions only. The following
table shows the revised VCC specification.
Other implied specification changes, as a result of the VCC change, are described in the following
table:
The maximum VCC has changed on the 0.25µm 32-Mb devices. The maximum VCC specification
has not changed on the 16-Mb, 8-Mb, or devices on the 0.18µm process. This may become an issue
if the system voltage regulator used has a VCC range tolerance that is outside the new specification,
which may cause the device to operate in a condition which is outside the specifications of the
current datasheet.
Specification Clarifications
There are no specification clarifications in this Specification Update revision.
Documentation Changes
There are no documentation changes in this Specification Update revision.
Symbol Parameter Notes Min Max Units
VCC VCC Supply Voltage 1 2.7 3.3 Volts
Symbol Parameter Notes Min Max Units
VCC1 VCC Supply Voltage 1 2.7 3.3 Volts
VCC2 VCC Supply Voltage 1 3.0 3.3 Volts
VCCQ1 I/O Supply Voltage 1 2.7 3.3 Volts
VPP1 Supply Voltage 1 1.65 3.3 Volts
NOTE: 1. VCC and VCCQ must share the same the same supply when they are in the VCC1 range.

Products related to this Datasheet

IC FLASH 32M PARALLEL 48UBGA CSP
IC FLASH 32M PARALLEL 48UBGA CSP
IC FLASH 32M PARALLEL 48UBGA CSP
IC FLASH 16M PARALLEL 48TSOP
IC FLASH 16M PARALLEL 48TSOP