IS6(1,4)WV25616EDBLL Datasheet by ISSI, Integrated Silicon Solution Inc

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Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. A1
02/10/2017
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS61WV25616EDBLL
IS64WV25616EDBLL
FEATURES
• High-speedaccesstime:8,10ns
• LowActivePower:85mW(typical)
• LowStandbyPower:7mW(typical)
CMOS standby
• Singlepowersupply
Vdd2.4Vto3.6V(10ns)
Vdd 3.3V±10%(8ns)
• Fullystaticoperation:noclockorrefresh
required
• Threestateoutputs
• Datacontrolforupperandlowerbytes
• IndustrialandAutomotivetemperaturesupport
• Lead-freeavailable
• ErrorDetectionandErrorCorrection
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH ECC
DESCRIPTION
The ISSI IS61/64WV25616EDBLL is a  high-speed,
4,194,304-bit static RAMs organized as 262,144 words
by 16 bits. It is fabricated using ISSI's high-performance
CMOS technology.This highly reliable process coupled
with innovative circuit design techniques, yields high-
performance and low power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be re-
duced down with CMOS input levels.
EasymemoryexpansionisprovidedbyusingChipEnable
andOutputEnableinputs,CE and OE.TheactiveLOW
WriteEnable(WE) controls both writing and reading of the
memory.AdatabyteallowsUpperByte(UB)andLower
Byte(LB) access.
TheIS61/64WV25616EDBLLispackagedintheJEDEC
standard44-pinTSOP-IIand48-pinMiniBGA(6mmx
8mm).
FUNCTIONAL BLOCK DIAGRAM
FEBRUARY 2017
Memory
Lower IO
Array-
256Kx8
ECC
Array-
256K
x4
Decoder
I/O Data
Circuit
ECC
Column I/O
IO0-7
Control
Circuit
A0-A17
IO8-15
8
ECC
8
8
8
12
12
Memory
Upper IO
Array-
256Kx8
ECC
Array-
256K
x4
8 4 48
/CE
/OE
/WE
/UB
/LB
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IS61/64WV25616EDBLL
TRUTH TABLE
I/O PIN
Mode WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 VDD Current
NotSelected X H X X X High-Z High-Z Isb1, Isb2
OutputDisabled H L H X X High-Z High-Z Icc
  X L X H H High-Z High-Z
Read H L L L H dout High-Z Icc
H L L H L High-Z dout
H L L L L dout dout
 Write L L X L H dIn High-Z Icc
  L L X H L High-Z dIn
L L X L L dIn dIn
PIN DESCRIPTIONS
A0-A17 Address Inputs
I/O0-I/O15 DataInputs/Outputs
CE ChipEnableInput
OE OutputEnableInput
WE WriteEnableInput
LB Lower-byteControl(I/O0-I/O7)
UB Upper-byteControl(I/O8-I/O15)
NC No Connection
Vdd Power
GND Ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
A17
A16
A15
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
PIN CONFIGURATIONS
44-Pin TSOP (Type II)
*soJ package under evaluation.
OOOOOOOO O®OOOO®O 00000000 00000000 66000000 @0000000 5432 10 3222233322: HHHHHHHHHHH
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IS61/64WV25616EDBLL
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
TOP VIEW
WE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A17
A16
A15
A14
A13
A12
A11
A10
OE
UB
LB
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB OE A0 A1 A2 N/C
I/O
8
UB A3 A4 CE I/O
0
I/O
9
I/O
10
A5 A6 I/O
1
I/O
2
GND I/O
11
A17 A7 I/O
3
V
DD
V
DD
I/O
12
NC A16 I/O
4
GND
I/O
14
I/O
13
A14 A15 I/O
5
I/O
6
I/O
15
NC A12 A13 WE I/O
7
NC A8 A9 A10 A11 NC
48-Pin mini BGA (6mm x 8mm)
PIN CONFIGURATIONS
44-Pin LQFP*
PIN DESCRIPTIONS
A0-A17 Address Inputs
I/O0-I/O15 DataInputs/Outputs
CE ChipEnableInput
OE OutputEnableInput
WE WriteEnableInput
LB Lower-byteControl(I/O0-I/O7)
UB Upper-byteControl(I/O8-I/O15)
NC No Connection
Vdd Power
GND Ground
*LQFP package under evaluation.
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IS61/64WV25616EDBLL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
Vterm TerminalVoltagewithRespecttoGND –0.5toVdd+0.5 V
Vdd VddRelatestoGND –0.3to4.0 V
tstg StorageTemperature –65to+150 °C
Pt PowerDissipation 1.0 W
Notes:
1.StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycausepermanentdamageto
thedevice.Thisisastressratingonlyandfunctionaloperationofthedeviceattheseoranyotherconditions
abovethoseindicatedintheoperationalsectionsofthisspecificationisnotimplied.Exposuretoabsolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
cIn Input Capacitance VIn = 0V 6 pF
cI/o Input/Output Capacitance Vout = 0V 8 pF
Notes:
1.Testedinitiallyandafteranydesignorprocesschangesthatmayaffecttheseparameters.
2. Testconditions:T
a = 25°c, f=1MHz,Vdd = 3.3V.
ERROR DETECTION AND ERROR CORRECTION
• IndependentECCforeachbyte
• Detectandcorrectonebiterrorperbyte
• Betterreliabilitythanparitycodeschemeswhichcanonlydetectanerrorbutnotcorrectanerror
• BackwardCompatible:Dropinreplacementtocurrentinindustrystandarddevices(withoutECC)
OPERATING RANGE (VDD)1
Range Ambient Temperature IS61WV25616EDBLL IS64WV25616EDBLL
VDD (8, 10nS) VDD (10nS)
Industrial –40°Cto+85°C 2.4V-3.6V(10ns) —   
  3.3V±10%(8ns)
 Automotive(A1) –40°Cto+85°C — 2.4V-3.6V
Automotive(A3) –40°Cto+125°C — 2.4V-3.6V
Note:
1.ContactSRAM@issi.comfor1.8Voption
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POWER SUPPLY CHARACTERISTICS(1) (OverOperatingRange)
-8 -10 -20
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
Icc VddDynamicOperating Vdd = Max., Com.  — 40 — 30 — 25 mA
Supply Current Iout = 0 mA, f = fmaX Ind.  — 45 — 35 — 30  
  Auto.  — — — 50 — 45
typ.(2) 21 21
Icc1 Operating Vdd = Max., Com. 20 20 20 mA
Supply Current Iout = 0 mA, f = 0 Ind.  — 25 — 25 — 25  
Auto. 40 40
Isb1 TTLStandbyCurrent Vdd = Max., Com. 10 10 10 mA
  (TTLInputs) VIn = VIH or VIL Ind.  — 15 — 15 — 15
CE VIH, f = 0 Auto. 30 30
Isb2 CMOS Standby Vdd = Max., Com. 5 5 5 mA
  Current(CMOSInputs) CE Vdd – 0.2V, Ind. 6 6 6
VIn Vdd – 0.2V, or Auto.  — — — 15 15
VIn 0.2V
, f = 0 typ.(2)  1.5 1.5
Note:
1. At f = fmaX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2.TypicalvaluesaremeasuredatVdd=3.0V,Ta=25oC and not 100% tested.
DC ELECTRICAL CHARACTERISTICS (OverOperatingRange)
VDD = 2.4V-3.6V
Symbol Parameter Test Conditions Min. Max. Unit
VoH OutputHIGHVoltage Vdd = Min., IoH = –1.0mA 1.8 — V
VoL OutputLOWVoltage Vdd = Min., IoL = 1.0 mA 0.4 V
VIH InputHIGHVoltage 2.0 Vdd + 0.3 V
VIL InputLOWVoltage(1) –0.3 0.8 V
ILI InputLeakage GND VIn Vdd –1 1 µA
ILo OutputLeakage GND Vout Vdd, OutputsDisabled –1 1 µA
Note:
1. VIL (min.) = –0.3VDC;VIL(min.)=–2.0VAC(pulsewidth<20ns).Not100%tested.
VIH (max.) = Vdd + 0.3V dc; VIH (max.) = Vdd + 2.0V ac(pulsewidth<20ns).Not100%tested.
DC ELECTRICAL CHARACTERISTICS (OverOperatingRange)
VDD = 3.3V + 10%
Symbol Parameter Test Conditions Min. Max. Unit
VoH OutputHIGHVoltage Vdd = Min., IoH = –4.0mA 2.4 — V
VoL OutputLOWVoltage Vdd = Min., IoL = 8.0mA — 0.4 V
VIH InputHIGHVoltage 2 Vdd + 0.3 V
VIL InputLOWVoltage(1) –0.3 0.8 V
ILI InputLeakage GND VIn Vdd –1 1 µA
ILo OutputLeakage GND Vout Vdd, OutputsDisabled –1 1 µA
Note:
1. VIL (min.) = –0.3VDC;VIL(min.)=–2.0VAC(pulsewidth<20ns).Not100%tested.
VIH (max.) = Vdd + 0.3V dc; VIH (max.) = Vdd + 2.0V ac(pulsewidth<20ns).Not100%tested.
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IS61/64WV25616EDBLL
READ CYCLE SWITCHING CHARACTERISTICS(1) (OverOperatingRange)
-8 -10 -20
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
trc ReadCycleTime 8  — 10  — 20  — ns
taa AddressAccessTime — 8 —  10 —  20 ns
toHa OutputHoldTime 2.0  — 2.0  — 2.5  — ns
tace CEAccessTime — 8 —  10 —  20 ns
tdoe OEAccessTime —  4.5 —  4.5 — 8 ns
tHzoe(2) OEtoHigh-ZOutput —  3 —  4 0  8 ns
tLzoe(2) OEtoLow-ZOutput 0  — 0  — 0  — ns
tHzce(2 CEtoHigh-ZOutput 0  3 0  4 0  8 ns
tLzce(2) CEtoLow-ZOutput 3  — 3  — 3  — ns
tba LB, UBAccessTime —  5.5 —  6.5 — 8 ns
tHzb(2) LB, UBtoHigh-ZOutput 0  3 0  3 0  8 ns
tLzb(2) LB, UBtoLow-ZOutput 0  — 0  — 0  — ns
tPu PowerUpTime 0  — 0  — 0  — ns
tPd PowerDownTime — 8 —  10 —  20 ns
Notes:
1. TestconditionsandoutputloadingconditionsarespecifiedintheACTestConditionsandACTestLoads(Figure1).
2. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.
AC TEST LOADS
Figure 1.
319
5 pF
Including
jig and
scope
353
OUTPUT
3.3V
Figure 2.
AC TEST CONDITIONS
Parameter Unit
(2.4V-3.6V)
InputPulseLevel 0.4VtoVdd-0.3V
 InputRiseandFallTimes 1V/ns
 InputandOutputTiming Vdd/2
 andReferenceLevel(VRef)
 OutputLoad SeeFigures1and2
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DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (AddressControlled)(CE = OE = VIL, UB or LB = VIL)
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z DATA VALID
UB_CEDR2.eps
t
HZB
ADDRESS
OE
CE
LB, UB
D
OUT
t
HZCE
t
BA
t
LZB
t
RC
t
PD
I
SB
I
CC
50%
V
DD
Supply
Current
50%
t
PU
READ CYCLE NO. 2(1,3)
Notes:
1. WEisHIGHforaReadCycle.
2. Thedeviceiscontinuouslyselected.OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CELOWtransition.
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WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (OverOperatingRange)
-8 -10 -20
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
twc WriteCycleTime 8 —  10  — 20 — ns
tsce CEtoWriteEnd 6.5  — 8  — 12 — ns
taw AddressSetupTime 6.5  — 8  — 12 — ns
   toWriteEnd
tHa AddressHoldfromWriteEnd 0  — 0  — 0 — ns
tsa AddressSetupTime 0  — 0  — 0 — ns
tPwb LB, UBValidtoEndofWrite 6.5  — 8  — 12 — ns
tPwe1 WEPulseWidth 6.5  — 8  — 12 — ns
tPwe2 WEPulseWidth(OE=LOW) 8 —  10  — 17 — ns
tsd DataSetuptoWriteEnd 5  — 6  — 9 — ns
tHd DataHoldfromWriteEnd 0  — 0  — 0 — ns
tHzwe(2) WELOWtoHigh-ZOutput — 3.5  —  5 — 9 ns
tLzwe(2) WEHIGHtoLow-ZOutput 2  — 2  — 3 — ns
Notes:
1. TestconditionsandoutputloadingconditionsarespecifiedintheACTestConditionsandACTestLoads(Figure1).
2. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
3. TheinternalwritetimeisdefinedbytheoverlapofCELOWandUB or LB, and WELOW.Allsignalsmustbeinvalidstates
toinitiateaWrite,butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedto
the rising or falling edge of the signal that terminates the write. Shaded area product in development
E‘ g} E
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WRITE CYCLE NO. 2
(WE Controlled. OE isHIGHDuringWriteCycle)(1,2)
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
PWB
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
DOUT
DIN
OE
DATA
IN
VALID
t
LZWE
t
SD
UB_CEWR2.eps
Notes:
1. WRITEisaninternallygeneratedsignalassertedduringanoverlapoftheLOWstatesontheCE and WE inputs and at least
one of the LB and UBinputsbeingintheLOWstate.
2. WRITE=(CE) [(LB)=(UB) ](WE).
AC WAVEFORMS
WRITE CYCLE NO. 1
(CE Controlled, OEisHIGHorLOW)(1)
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
PWB
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN DATA
IN
VALID
t
LZWE
t
SD
UB_CEWR1.eps
4—K —> 7 H, 05 —» “TE \ 7, 7 Z P a F a‘ \ e 4»+ a R: 1“: fl» CT; (TE + + + + 7 *4 WE + +\ 4 LET: w . w 2 +‘ ‘
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AC WAVEFORMS
WRITE CYCLE NO. 3
(WE Controlled. OE isLOWDuringWriteCycle)(1)
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
PWB
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATAIN VALID
t
LZWE
t
SD
UB_CEWR3.eps
WRITE CYCLE NO. 4
(LB, UB Controlled,Back-to-BackWrite)(1,3)
DATA UNDEFINED
t
WC
ADDRESS 1 ADDRESS 2
t
WC
HIGH-Z
t
PWB
WORD 1
LOW
WORD 2
UB_CEWR4.eps
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATAIN
VALID
t
LZWE
t
SD
t
PWB
DATAIN
VALID
t
SD
t
HD
t
SA
t
HA
t
HA
Notes:
1. TheinternalWritetimeisdefinedbytheoverlapofCE = Low, UB and/or LB = Low, and WE=LOW.Allsignalsmustbein
validstatestoinitiateaWrite,butanycanbedeassertedtoterminatetheWrite.Thet sa, t Ha, t sd, and t Hd timing is referenced
totherisingorfallingedgeofthesignalthatterminatestheWrite.
2. TestedwithOEHIGHforaminimumof4nsbeforeWE=LOWtoplacetheI/OinaHIGH-Zstate.
3. WEmaybeheldLOWacrossmanyaddresscyclesandtheLB, UBpinscanbeusedtocontroltheWritefunction.
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DATA RETENTION WAVEFORM (CE Controlled)
HIGH SPEED (IS61/64WV25616EDBLL)
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
Symbol Parameter Test Condition Options Min. Typ.(1) Max. Unit
Vdr VddforDataRetention SeeDataRetentionWaveform 2.0 — 3.6 V
Idr DataRetentionCurrent Vdd = 2.0V, CE Vdd–0.2V Com. — 0.5 5 mA
Ind. 6
   Auto. 15
tsdr DataRetentionSetupTime SeeDataRetentionWaveform 0 — — ns
trdr RecoveryTime SeeDataRetentionWaveform trc — ns
Note 1: TypicalvaluesaremeasuredatVdd = Vdr(min),Ta = 25
o
c and not 100% tested.
VDD
CE V
DD
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
Data Retention Mode
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Automotive (A1) Range: -40°C to +85°C
Speed (ns) Order Part No. Package
10 IS64WV25616EDBLL-10BA1 48miniBGA(6mmx8mm)   
IS64WV25616EDBLL-10BLA1 48miniBGA(6mmx8mm),Lead-free
IS64WV25616EDBLL-10CTA1 TSOP(TypeII),CopperLeadframe 
IS64WV25616EDBLL-10CTLA1 TSOP(TypeII),Lead-free,CopperLeadframe
Automotive (A3) Range: -40°C to +125°C
Speed (ns) Order Part No. Package
10 IS64WV25616EDBLL-10BA3 48miniBGA(6mmx8mm)   
IS64WV25616EDBLL-10BLA3 48miniBGA(6mmx8mm),Lead-free
IS64WV25616EDBLL-10CTA3 TSOP(TypeII),CopperLeadframe 
IS64WV25616EDBLL-10CTLA3 TSOP(TypeII),Lead-free,CopperLeadframe
ORDERING INFORMATION (HIGH SPEED)
Industrial Range: -40°C to +85°C
Speed (ns) Order Part No. Package
8 IS61WV25616EDBLL-8BI 48miniBGA(6mmx8mm)   
  IS61WV25616EDBLL-8BLI 48miniBGA(6mmx8mm),Lead-free
IS61WV25616EDBLL-8TI TSOP(TypeII)    
  IS61WV25616EDBLL-8TLI TSOP(TypeII),Lead-free
10 IS61WV25616EDBLL-10BI 48miniBGA(6mmx8mm)   
  IS61WV25616EDBLL-10BLI 48miniBGA(6mmx8mm),Lead-free
IS61WV25616EDBLL-10TI TSOP(TypeII)    
  IS61WV25616EDBLL-10TLI TSOP(TypeII),Lead-free
EE m a: «-moflmaoov 15 BE , mmmmmmmmmmmmmmmmmmmmmm ‘ ,4 ‘
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2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
1. CONTROLLING DIMENSION : MM
NOTE :
Θ
Θ
06/04/2008
Package Outline
PEG 5mm «damp. Efiwxe Aw? much A, 7 cg / ”DP
14 Integrated Silicon Solution, Inc. — www.issi.com
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2. Reference document : JEDEC MO-207
1. CONTROLLING DIMENSION : MM .
NOTE :
08/12/2008
Package Outline

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