LTC6360 Datasheet by Analog Devices Inc.

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LTLII‘IM TECHNOLOGY / I L7 LJUW 1
LTC6360
1
6360f
VOUT (VP-P)
0
DISTORTION (dBc)
–60
–70
–80
–90
–100
–110
–120
–130
–140 1 2 3
HD3
54
6360 TA01b
HD2
fIN = 20kHz
VOUT = 0V TO VP-P
Typical applicaTion
FeaTures DescripTion
Very Low Noise Single-Ended
SAR ADC Driver
with True Zero Output
ADC Driver
applicaTions
n Output Swings to True Zero on Single Supply
n 2.3nV/Hz Noise Density
n Fast Settling Time: 150ns, 16-Bit, 4V Step
n 110dB SNR in 3MHz Bandwidth
n Low Distortion, HD2 = –103dBc and HD3 = –109dBc
for 4VP-P Output at 40kHz
n Low Offset Voltage: 250µV Max
n Low Power Shutdown: 35A Max
n 3mm × 3mm 8-Pin DFN and 8-lead MSOP Packages
n 16-Bit and 18-Bit SAR ADC Driver
n High Speed Buffer Amplifiers
n Low Noise Signal Processing
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
The LTC
®
6360 is a very low noise, high precision, high
speed amplifier suitable for driving SAR ADCs. The
LTC6360 features a total output noise of 2.3nV/√Hz
combined with 150ns settling time to 16-bit levels (AV = 1).
While powered from a single 5V supply, the amplifier out-
put can swing to 0V while maintaining high linearity. This
is made possible with the inclusion of a very low noise
on-chip charge pump that generates a negative voltage
to bias the output stage of the amplifier, increasing the
allowable negative voltage swing.
The LTC6360 is available in a compact 3mm × 3mm,
8-pin leadless DFN package and an 8-pin MSOP package
with exposed pad and operates over a –40°C to 125°C
temperature range.
Harmonic Distortion vs
Output Amplitude
ADC
5V
6360 TA01a
CPO
OUT
10Ω
330pF
0.1µF
VCC
RADC
VDD
GND
–IN
CHARGE
PUMP
CPI
LTC6360
SHDN+IN
5V
0.1µF
VIN
0V TO 4V
+
F
+
10µF
5V
LTCéSéO
LTC6360
2
6360f
Total Supply Voltage
(VCC/VDD GND) .................................................5.5V
Input Current (Note 2) .......................................... ±10mA
Output Short Circuit Duration (Note 3) ............ Indefinite
Operating Ambient Temperature Range
(Note 4) .................................................. 40°C to 125°C
absoluTe MaxiMuM raTings
Specified Temperature Range (Note 5) .... 40°C to 125°C
Maximum Junction Temperature .......................... 150°C
Storage Temperature Range .................. 65°C to 150°C
Lead Temperature (Soldering, 10 sec) MS8E Only ...... 300°C
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6360CDD#PBF LTC6360CDD#TRPBF LFQT 8-Lead (3mm × 3mm) Plastic DFN 0°C to 7C
LTC6360IDD#PBF LTC6360IDD#TRPBF LFQT 8-Lead (3mm × 3mm) Plastic DFN 40°C to 8C
LTC6360HDD#PBF LTC6360HDD#TRPBF LFQT 8-Lead (3mm × 3mm) Plastic DFN 40°C to 125°C
LTC6360CMS8E#PBF LTC6360CMS8E#TRPBF LTFQS 8-Lead Plastic MSOP C to 70°C
LTC6360IMS8E#PBF LTC6360IMS8E#TRPBF LTFQS 8-Lead Plastic MSOP 4C to 85°C
LTC6360HMS8E#PBF LTC6360HMS8E#TRPBF LTFQS 8-Lead Plastic MSOP 40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
pin conFiguraTion
TOP VIEW
DD-8 PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
5
6
7
8
9
GND
4
3
2
1–IN
OUT
VCC
VDD
+IN
SHDN
CPI
CPO
TJMAX = 150°C, θJA = 43°C/W
EXPOSED PAD (PIN 9) PCB CONNECTION TO GND
1
2
3
4
–IN
OUT
VCC
VDD
8
7
6
5
+IN
SHDN
CPI
CPO
TOP VIEW
9
GND
MS8E PACKAGE
8-LEAD PLASTIC MSOP WITH EXPOSED PAD
TJMAX = 150°C, θJA = 40°C/W
EXPOSED PAD (PIN 9) PCB CONNECTION TO GND
(Note 1)
LTCéSéO L7 LJUW 3
LTC6360
3
6360f
elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage (MS8E) V+IN = 0V
l
30 250
600 µV
µV
V+IN = 2V
l
30 250
600 µV
µV
V+IN = 4.25V
l
40 300
700 µV
µV
VOS Input Offset Voltage (DD8) V+IN = 0V
l
90 400
900 µV
µV
V+IN = 2V
l
90 400
900 µV
µV
V+IN = 4.25V
l
170 600
1200 µV
µV
VOS/∆T Offset Voltage Drift l1.3 µV/°C
IBInput Bias Current (at +IN, –IN) V+IN = 0V
l
–30
–39 17 µA
µA
V+IN = 2V
l
–28
–36 15 µA
µA
V+IN = 4.25V
l
–26
31 –13.5 µA
µA
IOS Input Offset Current (at +IN, –IN) V+IN = 0V
V+IN = 2V
V+IN = 4.25V
l
l
l
0.1
0.1
0.1
1.0
1.0
1.0
µA
µA
µA
enInput Voltage Noise Density f = 1MHz 2.3 nV/Hz
inInput Current Noise Density f = 1MHz 3 pA/√Hz
SNR Signal to Noise Ratio VOUT = 4VP-P, 3MHz Noise Bandwidth 110 dB
VCMR Input Common Mode Voltage Range Guaranteed by CMRR l04.25 V
RIN Input Resistance Differential Mode
Common Mode 8
940 kΩ
CIN Input Capacitance +IN, –IN 2pF
AVOL Large Signal Voltage Gain VOUT = 0V to 4.5V
l
235
200 1000 V/mV
V/mV
CMRR Common Mode Rejection Ratio V+IN = V–IN = 0V to 3V l83 114 dB
V+IN = V–IN = 0V to 4.25V (MS8E) l78 111 dB
V+IN = V–IN = 0V to 4.25V (DD8) l75 96 dB
PSRR Power Supply Rejection Ratio
(∆VS/∆VOS)VCC = 4.75V to 5.25V 99 dB
VSSupply Voltage VCC = VDD l4.75 55.25 V
INL DC Linearity (Note 6) V+IN = 0V to 4.25V 40 µV
VOH Output Voltage High No Load
Sourcing 1mA
l
l
4.80
4.75 4.91
4.89 V
V
VOL Output Voltage Low No Load
Sinking 1mA
l
l
0.48
0.47 0.20
0.15 V
V
ISC Output Short Circuit Current Sourcing, Output Shorted to GND,
V+IN – V–IN = 200mV
l
18
16 45 mA
mA
Sinking, Output Shorted to VCC,
V+IN – V–IN = –200mV
l
4.1
3.2 5.8 mA
mA
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless noted otherwise, VCC = VDD = 5V, V+IN = 2V, VSHDN = 5V. See
Figure 1 for circuit configuration.
LTCéSéO 4 L7LJ1W
LTC6360
4
6360f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VLSHDN Pin Input Voltage, Logic Low l0.8 V
VHSHDN Pin Input Voltage, Logic High l2.0 V
ISHDNH SHDN Pin Current, Logic High VSHDN = 5V l100 nA
ISHDNL SHDN Pin Current, Logic Low VSHDN = 0V l–15 9.5 µA
ICC VCC Supply Current VSHDN = 2.0V
l
6.6 8
9mA
mA
IDD VDD Supply Current VSHDN = 2.0V
l
7.0 9.5
10 mA
mA
ITOT Total Supply Current ICC + IDD VSHDN = 2.0V
l
13.6 17.5
19 mA
mA
ICC(SHDN) VCC Supply Current in Shutdown VSHDN = 0.8V l110 200 µA
IDD(SHDN) VDD Supply Current in Shutdown VSHDN = 0.8V l80 150 µA
ITOT (SHDN) Total Supply Current ICC + IDD in
Shutdown VSHDN = 0.8V l190 350 µA
GBW Gain-Bandwidth Product Noninverting, f = 1MHz 1 GHz
BW Closed Loop –3dB Bandwidth VOUT = 50mVP-P, AV = 1 150 250 MHz
FPBW Full Power Bandwidth (Note 7) VOUT = 0V to 4V 2.7 MHz
SR Slew Rate AV = –1
Rising
Falling
135
95
V/µs
V/µs
HD2/HD3 Harmonic Distortion VOUT = 0V to 2V
fIN = 10kHz
fIN = 40kHz
fIN = 1MHz
–121/–130
–121/–123
96/116
dBc
dBc
dBc
HD2/HD3 Harmonic Distortion VOUT = 0V to 4V
fIN = 10kHz
fIN = 40kHz
fIN = 1MHz
–101/–110
–103/–109
87/–105
dBc
dBc
dBc
tSSettling Time 4V Step
0.25%
0.025%
0.0015% (±1LSB, 16-Bit, Falling Edge)
45
110
150
ns
ns
ns
tOVDR Overdrive Recovery Time V+IN to GND and VCC 30 ns
tON Turn-On Time VSHDN = 0V to 5V 1 µs
tOFF Turn-Off Time VSHDN = 5V to 0V 0.3 µs
VCPO CPO Output Voltage l0.8 –0.6 0.3 V
VCPORIPPLE CPO Ripple Voltage No External CPO/CPI Capacitors, 100MHz
Measurement Bandwidth 1.5 mVRMS
VOUTRIPPLE Output Ripple Voltage No External CPO/CPI Capacitors, 50MHz
Measurement Bandwidth 11.5 µVRMS
fRIPPLE Ripple Frequency
l
9.5
9.25 10 10.5
10.75 MHz
MHz
ICPO(MAX) Maximum Continuous CPO Output
Current VCPO ≤ –0.4V (Note 8) 3.5 4.5 mA
RCPO CPO DC Output Impedance ICPO = 0 to 3.5mA (Note 8) l30 65 Ω
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless noted otherwise, VCC = VDD = 5V, V+IN = 2V, VSHDN = 5V. See
Figure 1 for circuit configuration.
LTCéSéO CAL UNITS 10 4V L7 LJUW 5
LTC6360
5
6360f
Typical perForMance characTerisTics
TA = 25°C, VCC = VDD = 5V, V+IN = 2V, VSHDN = 5V,
see Figure 1 for circuit configuration.
∆VOS Distribution, MS8E
(PNP to NPN Stage)VOS Distribution, MS8E (NPN Stage)
VOS Distribution, MS8E (PNP Stage)
Offset Voltage vs Input Common
Mode Voltage VOS vs Temperature
Input Bias Current vs Input
Common Mode Voltage
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Inputs are protected by back-to-back diodes and diodes to each
supply. If the inputs are taken beyond the supplies or the differential input
voltage exceeds 0.7V, the input current must be limited to less than 10mA.
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely.
Note 4: The LTC6360C/LTC6360I/LTC6360H are guaranteed functional over
the temperature range –40°C to 125°C.
Note 5: The LTC6360C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6360C is designed, characterized and expected to
meet specified performance from –40°C to 125°C, but are not tested or
QA sampled at these temperatures. The LTC6360I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6360H is guaranteed
to meet specified performance from –40°C to 125°C.
Note 6: DC linearity is calculated by measuring the output vs input voltage
and calculating the maximum deviation from the least squares best fit line
at 100mV increments.
Note 7: FPBW is determined from distortion performance with HD2, HD3
< –70dBc as the criteria for a valid output. FPBW is limited by the charge
pump current sinking capability. See text for details.
Note 8: ICPO(MAX) and RCPO are measured with CPO disconnected from
CPI and CPI driven by external –0.7V source.
INPUT OFFSET VOLTAGE (µV)
–200
NUMBER OF UNITS
40
60
200
6360 G01
20
0–100 0100
–150 –50 50 150
80
30
50
10
70
440 TYPICAL UNITS
V+IN = 2V
INPUT OFFSET VOLTAGE (µV)
–200
NUMBER OF UNITS
40
60
200
6360 G02
20
0–100 0100
–150 –50 50 150
80
30
50
10
70
440 TYPICAL UNITS
V+IN = 4V
INPUT COMMON MODE VOLTAGE (V)
–0.5
INPUT OFFSET VOLTAGE (µV)
0
4.5
6360 G04
–100
–300 0.5 1.5 2.5 3.5
300
100
–200
200
TA = –40°C
TA = 25°C
TA = 125°C
TEMPERATURE (°C)
–50
INPUT OFFSET VOLTAGE (µV)
0
125
6360 G05
–300
–200
–100
–500 –25 0 25 50 75 100
500
300
200
100
–400
400
V+IN = 2V
V+IN = 4V
INPUT COMMON MODE VOLTAGE (V)
–1
INPUT BIAS CURRENT (µA)
–5
–10
–15
5
6360 G06
–30
–25
–20
–40 01 2 3 4
20
10
5
0
–35
15
TA = 125°C
TA = 25°C
TA = –40°C
CHANGE IN INPUT OFFSET VOLTAGE (µV)
–200
NUMBER OF UNITS
40
60
200
6360 G03
20
0–100 0100
–150 –50 50 150
80
30
50
10
70
440 TYPICAL UNITS
V+IN = 2V TO 4V
LTCbSéO 6 L7LJ1‘JW
LTC6360
6
6360f
Typical perForMance characTerisTics
Total Supply Currents vs Supply
Voltage
Total Supply Currents vs
SHDN Voltage
Turn-On and Turn-Off Transient
Response
Input Voltage Noise vs Frequency 0.1Hz to 10Hz Voltage Noise
Output Settling Time vs
Output Step
TA = 25°C, VCC = VDD = 5V, V+IN = 2V, VSHDN = 5V,
see Figure 1 for circuit configuration.
SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (mA)
16
14
12
10
5
6360 G10
012 3 4
20
18
8
6
4
2
TA = 125°C
TA = 25°C
TA = –40°C
TIME (1s/DIV)
VOLTAGE NOISE (nV)
1500
1000
500
6360 G14
–2000
2000
0
–500
–1000
–1500
Input Bias Current vs Temperature
Total Supply Current vs
Temperature
Total Supply Current in Shutdown
vs Temperature
TEMPERATURE (°C)
–50
INPUT BIAS CURRENT (µA)
–12
–14
125
6360 G07
–16
–20 –25 0 25 50 75 100
–6
–8
–10
–18
V+IN = 4V
V+IN = 2V
OUTPUT STEP (V)
–4 –3
SETTLING TIME (ns)
100
80
60
3 4
6360 G15
0–2 –1 0 1 2
120
40
20
TO 10mV
TO 1mV
SHDN PIN VOLTAGE (V)
0
SUPPLY CURRENT (mA)
16
14
12
10
5
6360 G11
012 3 4
18
8
6
4
2
TA = 125°C
TA = 25°C
TA = –40°C
TEMPERATURE (°C)
–50
SUPPLY CURRENT (mA)
15
125
6360 G08
14
12 –25 0 25 50 75 100
16
13
VSHDN = 5V
TEMPERATURE (°C)
–50
SUPPLY CURRENT (µA)
250
125
6360 G09
200
100 –25 0 25 50 75 100
300
150
VSHDN = 0V
5µs/DIV
VOLTAGE (V)
5
4
3
6360 G12
–1
6
2
1
0
VSHDN
VOUT
VCPO
FREQUENCY (Hz)
10
1
VOLTAGE NOISE (nV/√Hz)
100
100 1k 10k 100k1M 1G10M 100M
6360 G13
10
LTCéSéO L7 LJUW 7
LTC6360
7
6360f
Typical perForMance characTerisTics
Output Short Circuit Current vs
Temperature Output Overdrive Recovery
Common Mode Rejection Ratio
vs Frequency
Frequency Response vs Gain
Frequency Response vs
Temperature
Output Low Voltage vs
Load Current
Output High Voltage vs
Load Current Output Impedance vs Frequency
TA = 25°C, VCC = VDD = 5V, V+IN = 2V, VSHDN = 5V,
see Figure 1 for circuit configuration.
LOAD CURRENT (mA)
0
OUTPUT HIGH VOLTAGE (V)
4
3
6050
6360 G17
010 20 30 40
5
2
1TA = 125°C
TA = 25°C
TA = –40°C
FREQUENCY (MHz)
0.001
OUTPUT IMPEDANCE (Ω)
0.1
100
1001010.10.01 1000
6360 G18
0.01
1
10
AV = 1
FREQUENCY (MHz)
0.1 10 100
COMMON MODE REJECTION RATIO (dB)
1 1000
6360 G21
100
80
60
0
120
40
20
FREQUENCY (MHz)
0.1 10 100
GAIN MAGNITUDE (dB)
1 1000
6360 G23
2
0
–8
4
–2
–4
–6 TA = 125°C
TA = 25°C
TA = –40°C
FREQUENCY (MHz)
0.1 10 100
GAIN (dB)
1 1000
6360 G22
25
20
15
–5
30
10
5
0
AV = 20
AV = 10
AV = 5
AV = 2
AV = 1
SEE TABLE 1 FOR CIRCUIT
COMPONENTS VALUES
Open Loop Gain and Phase vs
Frequency
LOAD CURRENT (mA)
0
OUTPUT LOW VOLTAGE (V)
65
6360 G16
12 3 4
–0.3
0
–0.1
–0.2
–0.4
–0.5
–0.6
TA = 125°C
TA = 25°C
TA = –40°C
FREQUENCY (Hz)
10 1k 10k 100k 1M 10M100M
GAIN (dB)
PHASE (DEG)
100 1G
6360 G23a
120
100
–20
140
80
60
40
20
0
135
90
–180
180
45
0
–45
–90
–135
PHASE
GAIN
TEMPERATURE (°C)
–50 –25
SHORT CIRCUIT CURRENT (mA)
0
10
–10
–20
100 125
6360 G19
–60 025 50 75
20
–40
–30
–50
SINKING, OUTPUT SHORTED TO VCC
SOURCING, OUTPUT SHORTED TO GROUND
500ns/DIV
VIN, VOUT (V)
4
5
3
2
6360 G20
–2
6
0
1
–1
AV = 5
SEE TABLE 1 FOR CIRCUIT
COMPONENT VALUES
VIN x 5
VOUT
LTCbSéO 8 L7LJ1‘JW
LTC6360
8
6360f
Typical perForMance characTerisTics
Harmonic Distortion vs Output
Amplitude Harmonic Distortion vs Frequency
CPO Voltage vs CPO Load Current
TA = 25°C, VCC = VDD = 5V, V+IN = 2V, VSHDN = 5V,
see Figure 1 for circuit configuration.
CPO Ripple Frequency vs
Temperature
Large Signal Step Response Slew Rate vs Filter Capacitor
Slew Rate vs Temperature
TEMPERATURE (°C)
–50 –25
SLEW RATE (V/µs)
140
120
100
100 125
6360 G27
40 025 50 75
160
80
60
RISING
FALLING
RFILT = 10Ω
CFILT = 330pF
Small Signal Step Response
FREQUENCY (kHz)
0.1
DISTORTION (dBc)
–100
–110
100
6360 G29
–140 110
–60
–70
–80
–90
–120
–130
VOUT = 0V TO 2V
HD2
HD3
TEMPERATURE (°C)
CPO RIPPLE FREQUENCY (MHz)
100 12575
6360 G31
9.8
9.7
9.6
9.5
–50 –25 0 25 50
10.5
10.4
10.3
10.2
10.1
10.0
9.9
200ns/DIV
OUTPUT VOLTAGE (V)
2.05
2.00
6360 G24
1.90
2.10
1.95
200ns/DIV
OUTPUT VOLTAGE (V)
4
3
6360 G25
–1
5
2
1
0
FILTER CAPACITOR (pF)
100
1
SLEW RATE (V/µs)
10
100
1000
1000 10000
6360 G26
RISING
RFILT = 10Ω
FALLING
CPO LOAD CURRENT (mA)
CPO VOLTAGE (V)
0.2
0
86 75
6360 G30
–0.6
–0.4
–0.2
–1.0 01 2 3 4
1.0
0.6
0.4
–0.8
0.8 CPO PIN DISCONNECTED FROM CPI PIN
CPI PIN CONNECTED TO EXTERNAL
SOURCE
TA = 125°C
TA = 25°C
TA = –40°C
VOUT (VP-P)
0
DISTORTION (dBc)
–70
–80
–90
–100
4 5
6360 G28
–140 123
–60
–110
–120
–130
fIN = 20kHz
VOUT = 0V TO VP-P
HD3
HD2
LTCéSéO E _l_—_L— ”-1-— :E ' :1 T E ' ' [a] as 4 —>I——>I— —>I——N— I——>I— I——>I— <-><-‘ vccshdn="" gnd="" cw="" n="" l7="" ljuw="" 9="">
LTC6360
9
6360f
pin FuncTions
IN (Pin 1): Inverting Amplifier Input.
OUT (Pin 2): Output of Amplifier.
VCC (Pin 3): Analog Power Supply. Normally connected
to a 5V supply.
VDD (Pin 4): Digital Power Supply. Normally connected
to VCC.
CPO (Pin 5): Output of Charge Pump. This pin is internally
biased at –0.6V below GND.
CPI (Pin 6): Input for Amplifier Negative Rail. Normally
connected to CPO.
SHDN (Pin 7): Shutdown Pin. If tied high or left floating,
the part is enabled. If tied low, the part is disabled and
draws less than 350µA of supply current.
+IN (Pin 8): Noninverting Amplifier Input. Provides a high
impedance input.
GND (Exposed Pad Pin 9): Ground Pin. Normally con-
nected to ground.
block DiagraM
6360 BD
VDD
GND
OUT
RFILT
10Ω
IN VCC
CPI
CPIGND
SHDN
SHDN
+IN
GND VCC
VCC
8 7 6 5
1 2
9
3 4
CHARGE
PUMP
GND
SHDN
VDD
+
+
GND VCC
FVIN
GND VCC
GND VCC
GND VCC
CPO
GND VDD
0.1µF
CFILT
330pF
0.1µF 10µF
5V
LTCéSéO 1L __ _L ¥ "-4-" «H: w ‘IO
LTC6360
10
6360f
TesT circuiT
Figure 1. Test Circuit
VSHDN +
RFILT
10Ω
0.1µF
V+
VIN
6360 F01
CPO
VDD
GND
LTC6360
OUT–IN VCC
VOUT
CPISHDN+IN
+CHARGE
PUMP
10µF
0.1µF
CFILT
330pF
+
F
L7 LJUW LTCéSéO h ¥ 1-" 1- __ _L ? "-E h ¥ 1-" 1 __ _L 1—" "-E 11
LTC6360
11
6360f
operaTion
The LTC6360 is a low noise amplifier suitable for driving
single-ended high performance successive approximation
register (SAR) ADCs. The LTC6360 uses a single ampli-
fier with negative charge pump topology as shown in the
Block Diagram.
The output can swing from –0.48V to 4.91V. The ampli-
fier is designed to drive a series 10Ω resistor and 330pF
capacitor filter network to ground, although larger load
capacitances can be driven.
An on-chip low noise charge pump generates a small
negative voltage (typically –0.6V) at the CPO pin. This
negative voltage is normally connected to the amplifier’s
output stage via the CPI pin, allowing the output to swing
to true zero on a single 5V supply. Compared to typical
rail-to-rail output amplifiers that can only swing to within
a few hundred millivolts of ground, the LTC6360 provides
improved linearity and increased functionality for applica-
tions that benefit from a true zero output swing.
The LTC6360 features a low noise amplifier that can
support a signal-to-noise ratio of 110dB over a 3MHz
noise bandwidth.
Basic Connections
Shown in Figure 2 is a typical application for the LTC6360
as a unity gain driver. The amplifier’s two inputs (+IN and
IN) can accommodate a voltage range of 0V to 4.25V on
a single 5V rail. This provides a simple interface for 5V
ADCs with a 4.096V full-scale range.
Noninverting gain (shown in Figure 3) and inverting gain
(shown in Figure 4) configurations are also possible. For
best DC precision, RS should be made equal to the paral-
lel combination of RF and RG. RS can be bypassed with a
capacitor to reduce its noise contribution.
Figure 2. Unity Gain Driver.
Figure 3. Noninverting Gain Configuration.
Figure 4. Inverting Gain Configuration
5V
VIN
0V TO 4V
10Ω
0.1µF
5V
6360 F02
CPO
VDD
GND
LTC6360
OUT–IN VCC
VOUT
CPISHDN+IN
+CHARGE
PUMP
0.1µF 10µF
330pF
+
4V
0V
VIN
4V
0V
F
5V
VIN
RS
0.1µF
5V
6360 F03
CPO
VDD
GND
LTC6360
OUT–IN VCC
VOUT
RF
CF
RG
CPISHDN+IN
+CHARGE
PUMP
0.1µF 10µF
+
F
RFILT
CFILT
CS
5V
RS
0.1µF
5V
6360 F04
CPO
VDD
GND
LTC6360
OUT–IN VCC
VOUT
RF
RG
VIN
CPISHDN+IN
+CHARGE
PUMP
0.1µF 10µF
+
CF
F
RFILT
CFILT
chésbo 1'" 7'? I -I|—>|—_”_ 3% “$155? :4 '
LTC6360
12
6360f
applicaTions inForMaTion
Amplifier Characteristics
Figure 5 shows a simplified schematic of the LTC6360’s
amplifier. The input stage has NPN and PNP differential
pairs operating in parallel. This topology allows the inputs
to swing all the way from the negative rail to within 0.75V
of the positive supply rail. The PNP differential pair is
the primary input differential pair and is active when the
common mode voltage is less than 1.5V from the positive
rail. When the common mode voltage exceeds VCC – 1.5V,
the NPN pair is activated and the PNP is deactivated. The
input stage transconductance, gm, is maintained nearly
constant during the handover from PNP pair to NPN pair.
Additionally, a precision two-point trim algorithm is used
to maintain near constant offset voltage over the entire
input common mode range.
Input bias current flows out of the +IN and –IN inputs. The
magnitude of this current is regulated via an input current
compensation circuit which eliminates the discontinuity
and polarity reversal of input bias current that would oth-
erwise occur when transitioning from one input pair to the
other. Typical total change in input bias current over the
entire input common mode range is approximately 3.5µA.
Amplifier Feedback Components
When feedback resistors are used to set gain, care should
be taken to ensure that the pole formed by the feedback
resistors and the total capacitance at the inverting input,
IN, does not degrade stability. For instance, to set the
LTC6360 in a gain of +2, RF and RG of Figure 3 could be
set to 2k. If the total capacitance at –IN (LTC6360 plus
PC board) were 2pF, a new pole would be formed in the
loop response at 80MHz, which could lead to instability or
ringing in the step response. A capacitor connected across
the feedback resistor and having the same value as the
total –IN parasitic capacitance will eliminate any ringing
or oscillation. Special care should be taken during layout,
including using the shortest possible trace lengths and
removing the ground plane under the –IN pin, to minimize
the parasitic capacitance.
Figure 5. Amplifier Simplified Schematic
6360 F05
VCC
VCC
VCC
CPI
OUT
DESD5
DESD6
VCC
DESD1 DESD2
+IN
–IN DESD3 DESD4
D1 D2
INPUT
CURRENT
COMPENSATION
INPUT PAIR
CONTROL
DIFFERENTIAL
DRIVE
GENERATOR
LTCéSéO L7HEJWEGR 1 3
LTC6360
13
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Input bias current induced DC voltage offsets can be
minimized by matching the parallel impedance of RF and
RG to the source impedance, RS. For example, in the
typical application when the amplifier is configured as a
unity gain buffer, choosing RF equal to RS will minimize
the offset. Since nonzero values of RF will contribute to the
total output noise, RF may be bypassed with a capacitor
to reduce the noise bandwidth.
Input Protection
Back-to-back diodes (D1 and D2 in Figure 5) are included
between +IN and –IN to protect the input devices. The
inputs do not have internal resistors in series with the
input transistors, a technique often used to protect the
input transistors from excessive current flow during an
overdrive condition. Adding series input resistors would
significantly degrade the low noise performance. Therefore,
if the voltage across the amplifiers inputs is allowed to
exceed ±0.7V, steady state current conducted through the
protection diodes should be externally limited to ±10mA.
The input diodes are rugged enough to handle transient
currents due to amplifier slew rate overdrive or momentary
clipping without protection resistors.
Driving the input signal sufficiently beyond the specified
input common mode voltage range will cause the input
transistors to saturate. When saturation occurs, the ampli-
fier loses a stage of phase inversion and the output will
begin to invert. Diode D1 or D2 (Figure 5) forward biases
and holds the output within a diode drop of the input signal.
To avoid this inversion, limit the input drive to within the
specified input common mode range.
ESD
The LTC6360 has ESD protection diodes on all inputs
and outputs. The diodes are reverse biased during nor-
mal operation. If the input pins are driven beyond either
supply, large currents will flow through these diodes. If
the current is transient and limited to 10mA or less, no
damage to the device will occur.
On-Chip Charge Pump
A low noise on-chip charge pump generates a small nega-
tive voltage that is used to bias the output stage of the
amplifier, enabling output swing below 0V. The charge
pump output voltage is typically –0.6V. Several design
techniques have been used to lower the ripple present
at OUT due to the switching action of the charge pump.
The charge pump output is made available via the CPO
pin, and the amplifier’s charge pump input at the CPI pin.
This allows additional external filtering via a capacitor
connected from CPI to GND.
The charge pump operates at a nominal frequency of
10MHz. The output voltage at CPO will have small frequency
components at multiples of 5MHz. These components
are further reduced by the PSRR of the amplifier’s out-
put stage. The amplitude of the fundamental component
at the OUT pin is typically 1µVRMS with a 0.1µF bypass
capacitor at CPI.
Conventionally, a two chip solution is chosen to provide
output swing to true zero on a single supply: one ampli-
fier and an inverting charge pump to provide a negative
rail. Compared to a two chip solution, the LTC6360 offers
several advantages: a more compact layout with lower
part count, lower output ripple, less EMI and lower power.
Figure 6 shows the ripple voltage spectrum at the output,
VOUT, with a 0.1µF external CPI bypass capacitor.
Figure 6. Output Ripple Voltage
FREQUENCY (MHz)
VOUT (µVRMS)
1
0.1
10
100806040200
6360 F06
INPUT GROUNDED
0.1µF CPI BYPASS CAPACITOR
chésbo Ea» ”HE
LTC6360
14
6360f
applicaTions inForMaTion
The charge pump is capable of sinking up to 4.5mA of
DC current with a typical DC output impedance of 30Ω. If
more current is demanded of the charge pump, the volt-
age at CPO will collapse towards 0V. A diode connected
from CPO to GND limits the CPO node from being pulled
above ground by more than one diode drop.
Transient currents are absorbed by the filter capacitors
from CPO/CPI to GND. Care should be taken in selecting
the filter capacitors such that there is minimum ripple
voltage and droop during peak transient current demand.
Using multiple small surface mount capacitors is ad-
vised, with each capacitor covering a portion of the total
frequency range.
Slew Rate and Full Power Bandwidth
Additional consideration needs to be paid to the current
demanded of the charge pump. When driving a capaci-
tive load, the LTC6360 will exhibit a clipped distortion
characteristic at a lower frequency than where slew rate
limited distortion would occur. In contrast to a traditional
amplifier, where the full power bandwidth is determined
from the amplifier’s slew rate, when driving capacitive
loads, the full power bandwidth of the LTC6360 will be
limited by the charge pump sinking capability.
The average current sunk by the charge pump when driving
a capacitive load can be approximated as:
ICP(AVG) = 2VP • CFILT • f + 1mA (1)
where VP and f are the amplitude and frequency of the
driven signal respectively.
The maximum frequency that the charge pump can support
while maintaining the CPO pin below –0.4V is:
fFPBW = (ICP(MAX) 1mA)/(2VP • CFILT) (2)
where ICP(MAX) is given in the specification table. Full-scale
signals beyond this frequency will cause the charge pump
to collapse towards 0V, limiting the output amplitude and
causing distortion.
Output Compensation
The LTC6360 is internally compensated to be gain of 5
stable. Lower gains require an external RC network at
the output to provide compensation. The amplifier has
been decompensated to provide the highest possible
gain-bandwidth with a typical RC load of 10Ω in series
with 330pF. The extra gain-bandwidth obtained serves to
reduce distortion over a wider bandwidth. Since an external
RC filter network is desired in most ADC applications, the
decompensation is transparent in these cases and actually
serves to improve distortion performance.
The RC network at the output contributes a pole-zero pair
that reduces the loop gain above the pole frequency. The
simplified circuit model at high frequencies is shown in
Figure 7. At high frequencies, the open-loop output imped-
ance of the amplifier can be represented by an equivalent
resistor, ro, of 45Ω.
The pole frequency is:
fP = 1/(2π(RFILT + ro)CFILT) (3)
The zero frequency is:
fZ = 1/(2πRFILTCFILT) (4)
which is also the –3dB bandwidth of the filter formed by
RFILT and CFILT. The zero-pole ratio is given by:
fZ/fP = 1 + ro/RFILT (5)
Figure 7. Pole-Zero Introduced by RC Network at Output
6360 F07
TO FEEDBACK
NETWORK
AMPLIFIER fZ = 1/[2πRFILTCFILT]
fρ = 1/[2π(RFILT + ro)CFILT]
OUT
RFILT
CFILT
ro
VO
+
LTCéSéO on W h \‘x M V , r L7HEJWEGR 1 5
LTC6360
15
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applicaTions inForMaTion
The amount that the loop gain and subsequent bandwidth
will be reduced is equal to this zero-pole ratio. For example,
for 20dB of loop gain reduction (one decade bandwidth
reduction), RFILT should be made equal to 5Ω.
Figure 8 shows the open loop gain without compensation
and with a 10Ω/330pF RC compensation network. The
pole-zero can be seen to reduce the open loop gain above
10MHz, stabilizing the amplifier for unity gain applications.
This sets a lower limit on CL of:
CFILT > (fZ / fP • NG)/(2πRFILTfC(AMP)) (8)
Note that for large zero-pole ratios, additional margin
may be needed. In this case, setting fZ equal to fC yields
a phase margin of at best 45°. In practice, the ampli-
fier’s higher order poles will further reduce the phase
margin below 45°. Therefore, fZ should be made lower
than fC in order to ensure adequate phase margin. Phase
margin in the case of large pole-zero ratios case can
be estimated as tan–1(fC/fZ).
Likewise for small zero-pole ratios, the pole will not
have contributed a full 90° of lagging phase prior to the
zero contributing leading phase. The requirement for
fZ being lower than fC can be relaxed in these cases.
3. Select RFILT and CFILT to yield the desired filter bandwidth
while meeting the two constraints listed above.
The layout of the filter RC network is critical to the stability
of the part and care should be taken to minimize parasitic
inductance in this path.
Table 1 lists suggested RC filter values for some common
circuit gains. Note that longer filter time constants can be
implemented by increasing the CFILT value beyond what is
shown in Table 1 without degrading stability. For large CFILT
values, it may be necessary to use multiple high quality
surface mount capacitors to reduce ESR and maintain a
high self resonant frequency.
Table 1. Component Values for Various Circuit Gains
Noise Gain (NG) RFCFRGRFILT CFILT
1 0 DNI DNI 10 330pF
22k 2pF 2k 25 150pF
52k 0.2pF 500 DNI DNI
10 2k DNI 222 DNI DNI
20 2k DNI 181 DNI DNI
DNI – Do Not Install
Interfacing the LTC6360 to A/D Converters
When driving an ADC, a single-pole RC filter between
the output of the LTC6360 and the input of the ADC can
improve system performance. The sampling process
of ADCs creates a charge transient at the ADC input
The following is a guideline for designing the RC filter to
ensure stability with a circuit gain less than five:
1. In order to sufficiently reduce the gain prior to the
unity loop gain crossover point, fC, the zero-pole ratio
should be greater than 5/NG, where NG is the circuit
noise gain. For example, based on Equation 5, a unity
gain configuration allows a maximum RFILT value of
11.25Ω.
2. The zero should be located below to the unity gain
crossover frequency, fC. Once the RC network is in-
troduced, fC will occur at a lower frequency given by:
fC = fC(AMP)/(fZ / fP • NG) (6)
where fC(AMP) is the unity gain-bandwidth of the amplifier
without the RC network. Thus, the following condition
should be met:
fZ < fC(AMP)/(fZ / fP • NG) (7)
where fC(AMP) is approximately 1GHz.
Figure 8. Open Loop Gain and Phase with and without
Output Compensation
FREQUENCY (Hz)
10 1k 10k 100k 1M 10M100M
GAIN (dB)
PHASE (DEG)
100 1G
6360 F08
120
100
–20
140
80
60
40
20
0
135
90
–180
180
45
0
–45
–90
–135
PHASE UNCOMPENSATED
UNCOMPENSATED
10Ω/330pF
COMPENSATED
10Ω/330pF
COMPENSATED
GAIN
LTCéSéO h 1-— 1-— 9 | I: _ 1 vs vD 5v 1 L 3 i: "—1—— " 5v ' ADC __ + 16 L7LJCUEN2
LTC6360
16
6360f
applicaTions inForMaTion
caused by the switching of the ADC sampling capacitor.
This momentarily disturbs the output of the amplifier as
charge is transferred between amplifier and ADC. The
amplifier must recover and settle from this load transient
before the acquisition period ends. An RC network at
the output of the LTC6360 helps decouple the sampling
transient of the ADC from the amplifier, reducing the
demands on the amplifiers output stage (see Figure 9).
The resistor at the input of the ADC minimizes the sampling
transients that discharge the RC filter capacitor.
Figure 9. Driving an ADC
eleven RC time constants of a first order filter. Note also
that too small a resistor will not properly dampen the load
transient of the sampling process, prolonging the time
required for settling.
High quality resistors and capacitors should be used for
the RC filter network since these components stabilize
the internal amplifier and can also contribute their own
distortion. For lowest distortion, choose capacitors with
a high quality dielectric, such as a C0G multilayer ceramic
capacitor. Metal film surface mount resistors are more
linear than carbon types.
SHDN
The SHDN pin is 5V TTL or 3.6V CMOS level compatible.
If the SHDN pin (Pin 7) is pulled low, below 0.8V, the
LTC6360 will power down. If the pin is left open or pulled
high, above 2.0V, the part will enter normal active opera-
tion. The turn-on time between the shutdown and active
states is typically 1μs, and turn-off time is typically 0.3µs.
In shutdown, the output pin (OUT) appears as an open
collector with a nonlinear capacitor to ground and steer-
ing diodes to VCC and ground. Because of the nonlinear
capacitance, the output will still have the ability to sink and
source small amounts of transient current if exposed to
significant voltage transients. The input protection diodes
between +IN and –IN can still conduct if voltage transients
at the input exceed 700mV.
Noise Considerations
The LTC6360 has a low noise density en of 2.3nV/√Hz.
This is equivalent to the voltage noise of a 320Ω resistor
at the +IN input. For source resistors larger than 320Ω,
voltage noise due to the source resistance will start to
dominate. The current noise density is 3pA/Hz, thus
source resistors larger than about 770Ω will interact with
the input current noise and result in output noise that is
amplifier current noise dominant.
Note that the parallel combination of gain setting resis-
tors RF and RG behaves like the source resistance, RS, in
noise calculations.
The filter capacitor serves to provide the bulk of the charge
during the sampling process, while the filter resistor
dampens and attenuates any charge injected by the ADC.
The RC filter has the additional benefit of band limiting
broadband output noise.
The selection of the RC time constant depends on the ap-
plication; but generally, longer time constants will improve
SNR at the expense of longer settling time. Excessive
settling time can introduce gain errors and distortion
if the filter components are not perfectly linear. 16-bit
applications typically require a minimum settling time of
ADC
5V
6360 F09
CPO
OUT
10Ω
330pF
0.1µF
VCC
RADC
VDD
GND
–IN
CHARGE
PUMP
CPI
LTC6360
SHDN+IN
5V
0.1µF
VIN
0V TO 4V
+
F
+
10µF
5V
LTCéSéO L7HEJWEGR 1 7
LTC6360
17
6360f
applicaTions inForMaTion
routing. The CPI pin can be filtered with several high qual-
ity X5R or X7R capacitors returned to GND with minimal
trace routing. Small geometry (e.g., 0603) surface mount
ceramic capacitors have a much higher self resonant
frequency than do leaded capacitors, and perform best
with the LTC6360.
Stray parasitic capacitance at the –IN pin should be kept
to a minimum to prevent degraded stability response re-
sulting in excessive ringing or oscillations. Traces at –IN
should be kept as short as possible, and any ground plane
should be stripped from under the pin and trace.
The RC filter network at the output serves both as a filter
and compensation network. Parasitic trace inductance
in this path will tend to destabilize the amplifier. The RC
filter network at the output should return directly to a
low impedance ground plane and trace routing should be
minimized in this path. A high quality COG/NPO surface
mount capacitor should be used to optimize distortion
performance and reduce destabilizing series resistance and
inductance. When large filter capacitor values are required,
multiple surface mount capacitors may be necessary with
the smallest-valued capacitor placed closest to the output.
The DC1639A demoboard has been designed for the evalu-
ation of the LTC6360 following the above layout practices.
Its schematic and layout are shown in Figures 10 and 11.
Lower value gain and feedback resistors, RG and RF, will
result in lower output noise at the expense of increased
distortion due to increased loading of the amplifier.
External loading should not be less than 2kΩ to avoid de-
grading distortion performance. When using RS equal to
RF||RG, wideband noise can be substantially reduced by
bypassing with a small capacitor across RF.
Using a single pole passive RC filter network at the output
of the LTC6360 reduces the output noise bandwidth and
thereby increases the signal to noise ratio of the system.
For example, in a typical system with an output sig-
nal of 4VP-P, an RC output filter with RFILT = 10Ω and
CFILT = 330pF will reduce the total integrated noise from
57µV (250MHz –3dB bandwidth at OUT) to 27µV (48MHz
3dB bandwidth) and improve the SNR from 90dB to 97dB.
Keep in mind that long RC time constants in the output
filter can increase the settling time at the inputs of the
ADC. Incomplete settling can cause gain errors or increase
apparent crosstalk in multiplexed systems.
Board Layout and Bypass Capacitors/DC1639A
Demoboard
It is recommended that a high quality X5R or X7R, 0.1μF
bypass capacitor be placed directly between the VCC and
the GND pin; the GND pin (exposed pad) should be tied
directly to a low impedance ground plane with minimal
LTCéSéO % ‘r o m 5; ___| T : ”—0 ”H ._| 0 I"— .||_ :|: N H: _| 18 L7LJCUEN2
LTC6360
18
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applicaTions inForMaTion
Figure 10. DC1639A Demoboard Schematic
CPO
VDD
R14
OUT
GND
–IN
R7
C8
VCC
VCC
1 2 3 4
5
LTC6360CMS8E
678
9
CPISHDN+IN
+IN
J1
SMA
R15
C3
OPT
V+
JP1
ENABLE
DISABLE
SHDN
R3* 0Ω
R2
49.9
0805
VCC
C2
OPT
0805
R1
R12
20k
R11
30.1k
EXT
VCM
R13*
OPT
C4
0.1µF
C5
F
R5
OPT
0805
OPT
NPO
C7
OPT R6
OPT
R9
OPT
E4
GND E5
GND
AC MODE
*SEE TABLE BELOW FOR ALTERNATE VALUES
INSTALL
INSTALL
R3 = 1µF
R13 = 10k
INSTALL
NOT INSTALL
R3 = 0Ω
R13 = OPEN
DC MODE (SHOWN)
–IN
J2
SMA
C6
OPT
0805
R4
C1
F
E1
V+
4.75V TO 5.25V
V+E3
E2
2
3
1
C15**
330pF
NPO
0805
C16
OPT
NPO
0805
R8**
10Ω
R10
OPT
6360 F08
NOTE: UNLESS OTHERWISE SPECIFIED ALL
RESISTORS: Ω, 0603, 1%, 1/10W
**R8 AND C15 ARE NEEDED FOR STABILITY
OUT
J3
SMA
C9
0.01µF
C10
0.1µF
C11
10µF
0805
C12
10µF
0805
C13
0.1µF
C14
10µF
0805
LTC6360 LTCGISOCMSBE .LOW NOISE ADO DRIVER Vl/TRUE ZERO OUTPUT DEMO CIRCUIT 1539A H" mm 5mm mu m VDI . E . mu msm: . z 92 W o.75v-5.15v . 001 22:; i a . L7lél m mm" '. LTC CUNFIJENTIAL—FW CUSTOIER USE OllV L7 HEW 19
LTC6360
19
6360f
applicaTions inForMaTion
Figure 11. DC1639A Demoboard Layout
6360 F11
LTCéSéO [VOUT(MAX) V0UT(M\N)] [H 1 \ 67k 20 L7ELUEN2
LTC6360
20
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applicaTions inForMaTion
Interfacing to High Voltage Signals
Using the amplifier in the inverting configuration, with a
fixed input common mode voltage, allows the input signal
to traverse a swing beyond the LTC6360 supply rails.
A practical application for the inverting gain configuration
is translating a high voltage signal to a range suitable for
a low voltage SAR ADC. For a clean interface, two condi-
tions must be met:
1. The gain is selected so that full-scale signals at HVIN
are translated at the output of the LTC6360 to the ap-
propriate full-scale range for the ADC.
2. VOUT = VFS/2 when HVIN is centered at HVNOM, where
VFS is the ADC full-scale input voltage and HVNOM is
the average level of the input voltage.
Figure 12. Interfacing a ±10V Input Signal to a 5V ADC
Applying the above constraints to the design equations
gives values for RF/RG and V1:
RF/ RG=VOUT(MAX) VOUT(MIN)
[ ]
HVIN(MAX) – HVIN(MIN)
[ ]
(9)
V1 = [VFS/2 + RF/RG • HVNOM]/(1 + RF/RG) (10)
Applying these formulas to the case where ±10V input
signal is to be translated to a 0V to 4V full-scale range
yields the values shown in Figure 12.
Figure 13. Low Noise, True Zero 1MΩ DC Precise Photodiode
Transimpedance Amplifier
5V
V1
1.67V
10Ω
10pF
2k10k
0.1µF
5V
6360 F12
CPO
VDD
GND
LTC6360
OUT–IN VCC
VOUT
HVIN
CPISHDN+IN
+CHARGE
PUMP
0.1µF 10µF
330pF
+
1.67k
10V
–10V
0V
4V
0V
2V
0.1µF F
6360 F13
R6
1k
U3
LTC2054
5V
C5
0.1µF
C6
0.1µF
R2
1k
J1 NXP
BF862
+
U1
5V
R1
1M
10k
IPD
R5
2k
5V
R3
10M
SFH213
PHOTODIODE
CPI
C1
50fF (PARASITIC)
C4
0.1µF
F
CPO CPI
+
LTC6360
CPO CPI
10µF
LTCéSéO L7 LJUW 2 1
LTC6360
21
6360f
applicaTions inForMaTion
Low Noise, True Zero 1MΩ Photodiode
Transimpedance Amplifier
Figure 13 shows the LTC6360 applied as a transimped-
ance amplifier. The LTC6360 charge pump drives the
anode of the photodiode. The BF862 ultra low noise JFET
(J1) acts as a source follower, buffering the input of the
LTC6360 and making it suitable for the high impedance
feedback element R1. The BF862 has a minimum IDSS of
10mA and a pinchoff voltage between –0.3V and –1.2V.
The LTC2054 chopper stabilized op amp acts to servo
the DC voltage at the JFET gate to 0V, which allows the
output of the LTC6360 to swing to 0V when there is no
photo diode current.
Amplifier output noise density is dominated by the
130nV/Hz of the feedback resistor at low frequency, rising
to 320nV/Hz at 1MHz. Note that because the JFET has a
gm of approximately 1/100Ω, its attenuation looking into
R2 is only about 10%. The closed loop bandwidth using
a SFH213 photodiode was measured at approximately
3.2MHz.
LTCéSéO ¢ F’fiflfljfi: ,fi H T i \ U \UU 7 ,,,\,,, * flip, , \T + 1 Jr ‘0 \ MW l * La+ ix W7 22 L7ELUEN2
LTC6360
22
6360f
package DescripTion
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698 Rev C)
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.125
TYP
2.38 ±0.10
14
85
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(DD8) DFN 0509 REV C
0.25 ± 0.05
2.38 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1.65 ±0.05
(2 SIDES)2.10 ±0.05
0.50
BSC
0.70 ±0.05
3.5 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
LTCéSéO + W 0889mm (035: L705) wawmz 32m 345 (055+ um; (‘25 ‘35; Hfl:q]}+iq] L755 u42+nuaa (0255; (m5 + mm) fl mu 1—, Ln L7HEJWEGR 23
LTC6360
23
6360f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibilit y is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
package DescripTion
MS8E Package
8-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1662 Rev I)
MSOP (MS8E) 0910 REV I
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
1 2 34
4.90 ± 0.152
(.193 ± .006)
8
8
1
BOTTOM VIEW OF
EXPOSED PAD OPTION
765
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0.52
(.0205)
REF
1.68
(.066)
1.88
(.074)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
1.68 ± 0.102
(.066 ± .004)
1.88 ± 0.102
(.074 ± .004) 0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.65
(.0256)
BSC
0.42 ± 0.038
(.0165 ± .0015)
TYP
0.1016 ± 0.0508
(.004 ± .002)
DETAIL “B”
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.05 REF
0.29
REF
chésbo
LTC6360
24
6360f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2010
LT 0711 • PRINTED IN USA
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LT6350 Low Noise Single-Ended to Differential
Converter/ADC Driver 1.9nV/Hz, 2.7V to 12V Operation, 240ns 0.01% Settling Time
LTC6253 720MHz, 3.5mA Dual Power Efficient
Rail-to-Rail I/O Op Amps 720MHz, 3.3mA, 2.75nV/Hz, 280V/μs, 350μV, –77dBc at 4MHz
LT1818/LT1819 Single/Dual Wide Bandwidth, High Slew Rate
Low Noise and Distortion Op Amps 400MHz, 9mA, 6nV/√Hz, 2500V/μs, 1.5mV, –85dBc at 5MHz
LT1806/LT1807 Single/Dual Low Noise Rail-to-Rail I/O Op Amps 325MHz, 13mA, 3.5nV/√Hz, 140V/μs, 550μV, 85mA Output Drive
Precision Ultralow Noise True Zero Photodiode Amplifier
6360 TA02
0.1µF
0.1µF
133
F
100k
NXP
BF862
5V
40fF
(PARASITIC)
1M 1%
CPO CPI
GAIN = 1MΩ
–3dB BW = 4MHz
OUTPUT NOISE = 710µVRMS ON A 4MHz BANDWIDTH
OUTPUT OFFSET = 50µV TYPICAL EXCLUDING
PHOTODIODE DARK CURRENT
10k
5V
10M
10M
OSRAM
PHOTODIODE
SFH213
OR EQUIVALENT
CPI
806
100
0.1µF
0.1µF
10µF
CPO CPI
F
+
+
LTC6360
LTC2054
5V
IPD

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