ICM-42688-P Datasheet by TDK InvenSense

@TDI( InvenSense APIMCU momma/Sm um um Icmzww LGA
ICM-42688-P Datasheet
High Precision 6-Axis MEMS MotionTrackingTM Device
This document contains information on a pre-production product,
and should not be considered for production until qualification is
complete. InvenSense Inc. reserves the right to change specifications
and information herein without notice.
TDK Corporation
1745 Technology Drive, San Jose, CA 95110 U.S.A
+1(408) 9887339
www.invensense.com
Document Number: DS-000347
Revision: 1.2
Rev. Date: 04/19/2020
ICM-42688-P HIGHLIGHTS
The ICM-42688-P is a 6-axis MEMS
MotionTracking device that combines a 3-axis
gyroscope and a 3-axis accelerometer. It has a
configurable host interface that supports I3CSM,
I2C and SPI serial communication, features a 2 kB
FIFO and 2 programmable interrupts with ultra-
low-power wake-on-motion support to minimize
system power consumption.
ICM-42688-P supports highly accurate external clock
input, that helps to reduce system level sensitivity
error, improve orientation measurement from
gyroscope data, reduce ODR sensitivity to
temperature and device to device variation.
The device includes industry first 20-bits data format
support in FIFO for high-data resolution. This FIFO
format encapsulates 19-bits of gyroscope data and 18-
bits of accelerometer data.
Other industry-leading features include
InvenSense on-chip APEX Motion Processing
engine for gesture recognition, activity
classification, and pedometer, along with
programmable digital filters, and an embedded
temperature sensor.
The device supports a VDD operating range of
1.71V to 3.6V, and a separate digital IO supply,
VDDIO from 1.71V to 3.6V.
BLOCK DIAGRAM
ICM-42688-P FEATURES
Gyroscope Noise: 2.8 mdps/Hz &
Accelerometer Noise: 70 µg/Hz
o Low-Noise mode 6-axis current
consumption of 0.88 mA
User selectable Gyro Full-scale range (dps):
± 15.6/31.2/62.5/125/250/500/1000/2000
User selectable Accelerometer Full-scale
range (g): ± 2/4/8/16
User-programmable digital filters for gyro,
accel, and temp sensor
APEX Motion Functions:
o Pedometer, Tilt Detection, Tap Detection
o Wake on Motion, Raise to Wake/Sleep,
Significant Motion Detection
Host interface: 12.5 MHz I3CSM, 1 MHz I2C,
24 MHz SPI
APPLICATIONS
AR/VR Controllers
Head Mounted Displays
Wearables
Sports
Robotics
IoT Applications
ORDERING INFORMATION
PART
TEMP RANGE
PACKAGE
ICM-42688-P
−40°C to +85°C
2.5x3mm 14-Pin
LGA
Denotes RoHS and Green-Compliant Package
TDK-INVENSENSE SENSORS FOR SMARTPHONE, MOBILE & IOT APPLICATIONS
Parameter
ICM-40607
Sensorhub
ICM-42605
Sensorhub
ICM-42686-P
Handheld Action
ICM-42688-P
HMD & Robotics
GYRO Noise (mdps/rt-Hz)
7
3.8
5.3
2.8
GYRO Offset Temp Stability (mdps/°C)
±30
±20
±10
±5
GYRO Range & Resolution
±2000dps; 16-bits
±2000dps; 16-bits
±4000dps; 16/19-bits
±2000dps; 16/19-bits
ACCEL Noise (µg/rt-Hz)
110
70
70
AXY: 65; AZ: 70
ACCEL Range & Resolution
±16g; 16-bits
±16g; 16-bits
±32g; 16/18-bits
±16g; 16/18-bits
ODR & Sample Synch
8kHz; No RTC
8kHz; No RTC
32kHz; RTC
32kHz; RTC
@TDI( lnvenSense
ICM-42688-P
Page 2 of 109
Document Number: DS-000347
Revision: 1.2
TABLE OF CONTENTS
ICM-42688-P Highlights ....................................................................................................................................... 1
Block Diagram ...................................................................................................................................................... 1
ICM-42688-P Features ......................................................................................................................................... 1
Applications ......................................................................................................................................................... 1
Ordering Information ........................................................................................................................................... 1
TDK-Invensense Sensors for Smartphone, Mobile & IoT Applications ................................................................ 1
Table of Figures ............................................................................................................................................................... 8
Table of Tables ................................................................................................................................................................ 8
1 Introduction ......................................................................................................................................................... 9
1.1 Purpose and Scope .................................................................................................................................... 9
1.2 Product Overview...................................................................................................................................... 9
1.3 Applications ............................................................................................................................................... 9
2 Features ............................................................................................................................................................. 10
2.1 Gyroscope Features ................................................................................................................................ 10
2.2 Accelerometer Features .......................................................................................................................... 10
2.3 Motion Features ...................................................................................................................................... 10
2.4 Additional Features ................................................................................................................................. 10
3 Electrical Characteristics .................................................................................................................................... 11
3.1 Gyroscope Specifications ........................................................................................................................ 11
3.2 Accelerometer Specifications .................................................................................................................. 12
3.3 Electrical Specifications ........................................................................................................................... 13
3.4 I2C Timing Characterization ..................................................................................................................... 15
3.5 SPI Timing Characterization 4-Wire SPI Mode ..................................................................................... 16
3.6 SPI Timing Characterization 3-Wire SPI Mode ..................................................................................... 17
3.7 Absolute Maximum Ratings .................................................................................................................... 18
4 Applications Information ................................................................................................................................... 19
4.1 Pin Out Diagram and Signal Description ................................................................................................. 19
4.2 Typical Operating Circuit ......................................................................................................................... 20
4.3 Bill of Materials for External Components .............................................................................................. 21
4.4 System Block Diagram ............................................................................................................................. 22
4.5 Overview ................................................................................................................................................. 22
4.6 Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning ............................................... 22
4.7 Three-Axis MEMS Accelerometer with 16-bit ADCs and Signal Conditioning ......................................... 22
4.8 I3CSM, I2C and SPI Host Interface ............................................................................................................. 22
4.9 Self-Test................................................................................................................................................... 22
4.10 Clocking ............................................................................................................................................... 23
4.11 Sensor Data Registers ......................................................................................................................... 23
@TDI( lnvenSense
ICM-42688-P
Page 3 of 109
Document Number: DS-000347
Revision: 1.2
4.12 Interrupts ............................................................................................................................................ 23
4.13 Digital-Output Temperature Sensor ................................................................................................... 24
4.14 Bias and LDOs ..................................................................................................................................... 24
4.15 Charge Pump ...................................................................................................................................... 24
4.16 Standard Power Modes ...................................................................................................................... 24
5 Signal Path ......................................................................................................................................................... 25
5.1 Summary of Parameters Used to Configure the Signal Path .................................................................. 25
5.2 Notch Filter ............................................................................................................................................. 25
5.3 Anti-Alias Filter ........................................................................................................................................ 27
5.4 User Programmable Offset ..................................................................................................................... 29
5.5 UI Filter Block .......................................................................................................................................... 29
5.6 UI Path ODR And FSR Selection ............................................................................................................... 33
6 FIFO .................................................................................................................................................................... 36
6.1 Packet Structure ...................................................................................................................................... 36
6.2 FIFO Header ............................................................................................................................................ 38
6.3 Maximum FIFO Storage ........................................................................................................................... 39
6.4 FIFO Configuration Registers ................................................................................................................... 39
7 Programmable Interrupts .................................................................................................................................. 41
8 APEX Motion Functions ..................................................................................................................................... 42
8.1 APEX ODR Support .................................................................................................................................. 42
8.2 DMP Power Save Mode .......................................................................................................................... 43
8.3 Pedometer Programming ........................................................................................................................ 43
8.4 Tilt Detection Programming .................................................................................................................... 44
8.5 Raise to Wake/Sleep Programming ........................................................................................................ 44
8.6 Tap Detection Programming ................................................................................................................... 45
8.7 Wake on Motion Programming ............................................................................................................... 46
8.8 Significant Motion Detection Programming ........................................................................................... 46
9 Digital Interface ................................................................................................................................................. 48
9.1 I3CSM, I2C and SPI Serial Interfaces .......................................................................................................... 48
9.2 I3CSM Interface ........................................................................................................................................ 48
9.3 I2C Interface ............................................................................................................................................. 48
9.4 I2C Communications Protocol ................................................................................................................. 48
9.5 I2C Terms ................................................................................................................................................. 50
9.6 SPI Interface ............................................................................................................................................ 52
10 Assembly ............................................................................................................................................................ 53
10.1 Orientation of Axes ............................................................................................................................. 53
10.2 Package Dimensions ........................................................................................................................... 54
11 Part Number Package Marking .......................................................................................................................... 56
12 Use Notes ........................................................................................................................................................... 57
12.1 Accelerometer Mode Transitions ....................................................................................................... 57
@TDI( lnvenSense
ICM-42688-P
Page 4 of 109
Document Number: DS-000347
Revision: 1.2
12.2 Accelerometer Low Power (LP) Mode Averaging Filter Setting .......................................................... 57
12.3 Settings for I2C, I3CSM, and SPI Operation ........................................................................................... 57
12.4 Notch Filter and Anti-Alias Filter Operation ....................................................................................... 57
12.5 External Clock Input Effect on ODR .................................................................................................... 57
12.6 INT_ASYNC_RESET Configuration ....................................................................................................... 58
12.7 FIFO Timestamp Interval Scaling......................................................................................................... 58
12.8 Supplementary Information for FIFO_HOLD_LAST_DATA_EN ........................................................... 58
13 Register Map ...................................................................................................................................................... 60
13.1 User Bank 0 Register Map................................................................................................................... 60
13.2 User Bank 1 Register Map................................................................................................................... 61
13.3 User Bank 2 Register Map................................................................................................................... 62
13.4 User Bank 4 Register Map................................................................................................................... 62
14 User Bank 0 Register Map Descriptions .......................................................................................................... 63
14.1 DEVICE_CONFIG .................................................................................................................................. 63
14.2 DRIVE_CONFIG .................................................................................................................................... 63
14.3 INT_CONFIG ........................................................................................................................................ 64
14.4 FIFO_CONFIG ...................................................................................................................................... 64
14.5 TEMP_DATA1 ...................................................................................................................................... 64
14.6 TEMP_DATA0 ...................................................................................................................................... 65
14.7 ACCEL_DATA_X1 ................................................................................................................................. 65
14.8 ACCEL_DATA_X0 ................................................................................................................................. 65
14.9 ACCEL_DATA_Y1 ................................................................................................................................. 65
14.10 ACCEL_DATA_Y0 ................................................................................................................................. 66
14.11 ACCEL_DATA_Z1 ................................................................................................................................. 66
14.12 ACCEL_DATA_Z0 ................................................................................................................................. 66
14.13 GYRO_DATA_X1 .................................................................................................................................. 66
14.14 GYRO_DATA_X0 .................................................................................................................................. 66
14.15 GYRO_DATA_Y1 .................................................................................................................................. 67
14.16 GYRO_DATA_Y0 .................................................................................................................................. 67
14.17 GYRO_DATA_Z1 .................................................................................................................................. 67
14.18 GYRO_DATA_Z0 .................................................................................................................................. 67
14.19 TMST_FSYNCH .................................................................................................................................... 67
14.20 TMST_FSYNCL ..................................................................................................................................... 68
14.21 INT_STATUS ........................................................................................................................................ 68
14.22 FIFO_COUNTH..................................................................................................................................... 68
14.23 FIFO_COUNTL ..................................................................................................................................... 69
14.24 FIFO_DATA .......................................................................................................................................... 69
14.25 APEX_DATA0 ....................................................................................................................................... 69
14.26 APEX_DATA1 ....................................................................................................................................... 69
14.27 APEX_DATA2 ....................................................................................................................................... 70
@TDI( lnvenSense
ICM-42688-P
Page 5 of 109
Document Number: DS-000347
Revision: 1.2
14.28 APEX_DATA3 ....................................................................................................................................... 70
14.29 APEX_DATA4 ....................................................................................................................................... 71
14.30 APEX_DATA5 ....................................................................................................................................... 71
14.31 INT_STATUS2 ...................................................................................................................................... 72
14.32 INT_STATUS3 ...................................................................................................................................... 72
14.33 SIGNAL_PATH_RESET .......................................................................................................................... 72
14.34 INTF_CONFIG0 .................................................................................................................................... 73
14.35 INTF_CONFIG1 .................................................................................................................................... 74
14.36 PWR_MGMT0 ..................................................................................................................................... 75
14.37 GYRO_CONFIG0 .................................................................................................................................. 76
14.38 ACCEL_CONFIG0 ................................................................................................................................. 77
14.39 GYRO_CONFIG1 .................................................................................................................................. 78
14.40 GYRO_ACCEL_CONFIG0 ...................................................................................................................... 79
14.41 ACCEL_CONFIG1 ................................................................................................................................. 80
14.42 TMST_CONFIG .................................................................................................................................... 80
14.43 APEX_CONFIG0 ................................................................................................................................... 81
14.44 SMD_CONFIG ...................................................................................................................................... 81
14.45 FIFO_CONFIG1 .................................................................................................................................... 82
14.46 FIFO_CONFIG2 .................................................................................................................................... 82
14.47 FIFO_CONFIG3 .................................................................................................................................... 82
14.48 FSYNC_CONFIG ................................................................................................................................... 83
14.49 INT_CONFIG0 ...................................................................................................................................... 83
14.50 INT_CONFIG1 ...................................................................................................................................... 84
14.51 INT_SOURCE0 ..................................................................................................................................... 84
14.52 INT_SOURCE1 ..................................................................................................................................... 85
14.53 INT_SOURCE3 ..................................................................................................................................... 85
14.54 INT_SOURCE4 ..................................................................................................................................... 86
14.55 FIFO_LOST_PKT0 ................................................................................................................................. 86
14.56 FIFO_LOST_PKT1 ................................................................................................................................. 86
14.57 SELF_TEST_CONFIG ............................................................................................................................. 87
14.58 WHO_AM_I ......................................................................................................................................... 87
14.59 REG_BANK_SEL ................................................................................................................................... 87
15 User Bank 1 Register Map Descriptions .......................................................................................................... 88
15.1 SENSOR_CONFIG0 .............................................................................................................................. 88
15.2 GYRO_CONFIG_STATIC2 ..................................................................................................................... 88
15.3 GYRO_CONFIG_STATIC3 ..................................................................................................................... 88
15.4 GYRO_CONFIG_STATIC4 ..................................................................................................................... 89
15.5 GYRO_CONFIG_STATIC5 ..................................................................................................................... 89
15.6 GYRO_CONFIG_STATIC6 ..................................................................................................................... 89
15.7 GYRO_CONFIG_STATIC7 ..................................................................................................................... 89
@TDI( lnvenSense
ICM-42688-P
Page 6 of 109
Document Number: DS-000347
Revision: 1.2
15.8 GYRO_CONFIG_STATIC8 ..................................................................................................................... 90
15.9 GYRO_CONFIG_STATIC9 ..................................................................................................................... 90
15.10 GYRO_CONFIG_STATIC10 ................................................................................................................... 90
15.11 XG_ST_DATA ....................................................................................................................................... 91
15.12 YG_ST_DATA ....................................................................................................................................... 91
15.13 ZG_ST_DATA ....................................................................................................................................... 91
15.14 TMSTVAL0 ........................................................................................................................................... 91
15.15 TMSTVAL1 ........................................................................................................................................... 92
15.16 TMSTVAL2 ........................................................................................................................................... 92
15.17 INTF_CONFIG4 .................................................................................................................................... 92
15.18 INTF_CONFIG5 .................................................................................................................................... 93
15.19 INTF_CONFIG6 .................................................................................................................................... 93
16 User Bank 2 Register Map Descriptions .......................................................................................................... 94
16.1 ACCEL_CONFIG_STATIC2 .................................................................................................................... 94
16.2 ACCEL_CONFIG_STATIC3 .................................................................................................................... 94
16.3 ACCEL_CONFIG_STATIC4 .................................................................................................................... 94
16.4 XA_ST_DATA ....................................................................................................................................... 94
16.5 YA_ST_DATA ....................................................................................................................................... 95
16.6 ZA_ST_DATA ....................................................................................................................................... 95
17 User Bank 4 Register Map Descriptions .......................................................................................................... 96
17.1 APEX_CONFIG1 ................................................................................................................................... 96
17.2 APEX_CONFIG2 ................................................................................................................................... 97
17.3 APEX_CONFIG3 ................................................................................................................................... 98
17.4 APEX_CONFIG4 ................................................................................................................................... 99
17.5 APEX_CONFIG5 ................................................................................................................................... 99
17.6 APEX_CONFIG6 ................................................................................................................................. 100
17.7 APEX_CONFIG7 ................................................................................................................................. 100
17.8 APEX_CONFIG8 ................................................................................................................................. 100
17.9 APEX_CONFIG9 ................................................................................................................................. 101
17.10 ACCEL_WOM_X_THR ........................................................................................................................ 101
17.11 ACCEL_WOM_Y_THR ........................................................................................................................ 101
17.12 ACCEL_WOM_Z_THR ........................................................................................................................ 101
17.13 INT_SOURCE6 ................................................................................................................................... 102
17.14 INT_SOURCE7 ................................................................................................................................... 102
17.15 INT_SOURCE8 ................................................................................................................................... 103
17.16 INT_SOURCE9 ................................................................................................................................... 103
17.17 INT_SOURCE10 ................................................................................................................................. 104
17.18 OFFSET_USER0 .................................................................................................................................. 104
17.19 OFFSET_USER1 .................................................................................................................................. 104
17.20 OFFSET_USER2 .................................................................................................................................. 105
@TDI( lnvenSense
ICM-42688-P
Page 7 of 109
Document Number: DS-000347
Revision: 1.2
17.21 OFFSET_USER3 .................................................................................................................................. 105
17.22 OFFSET_USER4 .................................................................................................................................. 105
17.23 OFFSET_USER5 .................................................................................................................................. 105
17.24 OFFSET_USER6 .................................................................................................................................. 106
17.25 OFFSET_USER7 .................................................................................................................................. 106
17.26 OFFSET_USER8 .................................................................................................................................. 106
18 Reference ......................................................................................................................................................... 107
19 Document Information .................................................................................................................................... 108
19.1 Revision History ................................................................................................................................ 108
@TDI( lnvenSense
ICM-42688-P
Page 8 of 109
Document Number: DS-000347
Revision: 1.2
TABLE OF FIGURES
Figure 1. I2C Bus Timing Diagram ........................................................................................................................................ 15
Figure 2. 4-Wire SPI Bus Timing Diagram ............................................................................................................................ 16
Figure 3. 3-Wire SPI Bus Timing Diagram ............................................................................................................................ 17
Figure 4. Pin Out Diagram for ICM-42688-P 2.5x3.0x0.91 mm LGA.................................................................................... 19
Figure 5. ICM-42688-P Application Schematic (I3CSM / I2C Interface to Host) ..................................................................... 20
Figure 6. ICM-42688-P Application Schematic (SPI Interface to Host) ................................................................................ 20
Figure 7. ICM-42688-P System Block Diagram .................................................................................................................... 22
Figure 8. ICM-42688-P Signal Path ...................................................................................................................................... 25
Figure 9. FIFO Packet Structure ........................................................................................................................................... 36
Figure 10. Maximum FIFO Storage ...................................................................................................................................... 39
Figure 11. START and STOP Conditions ............................................................................................................................. 49
Figure 12. Acknowledge on the I2C Bus ............................................................................................................................... 49
Figure 13. Complete I2C Data Transfer ................................................................................................................................. 50
Figure 14. Typical SPI Master/Slave Configuration .............................................................................................................. 52
Figure 15. Orientation of Axes of Sensitivity and Polarity of Rotation .................................................................................. 53
TABLE OF TABLES
Table 1. Gyroscope Specifications ....................................................................................................................................... 11
Table 2. Accelerometer Specifications ................................................................................................................................. 12
Table 3. D.C. Electrical Characteristics ................................................................................................................................ 13
Table 4. A.C. Electrical Characteristics ................................................................................................................................. 14
Table 5. I2C Timing Characteristics ....................................................................................................................................... 15
Table 6. 4-Wire SPI Timing Characteristics (24-MHz Operation) ......................................................................................... 16
Table 7. 3-Wire SPI Timing Characteristics (24-MHz Operation) ......................................................................................... 17
Table 8. Absolute Maximum Ratings .................................................................................................................................... 18
Table 9. Signal Descriptions ................................................................................................................................................. 19
Table 10. Bill of Materials ...................................................................................................................................................... 21
Table 11. Standard Power Modes for ICM-42688-P ............................................................................................................. 24
Table 12. I2C Terms .............................................................................................................................................................. 51
@TDI( lnvenSense
ICM-42688-P
Page 9 of 109
Document Number: DS-000347
Revision: 1.2
1 INTRODUCTION
1.1 PURPOSE AND SCOPE
This document is a product specification, providing a description, specifications, and design related information on the ICM-42688-P
Single-Interface MotionTracking device. The device is housed in a small 2.5x3x0.91 mm 14-pin LGA package.
1.2 PRODUCT OVERVIEW
The ICM-42688-P is a 6-axis MotionTracking device that combines a 3-axis gyroscope, and a 3-axis accelerometer in a small
2.5x3x0.91 mm (14-pin LGA) package. It also features a 2K-byte FIFO that can lower the traffic on the serial bus interface, and
reduce power consumption by allowing the system processor to burst read sensor data and then go into a low-power mode. ICM-
42688-P, with its 6-axis integration, enables manufacturers to eliminate the costly and complex selection, qualification, and system
level integration of discrete devices, guaranteeing optimal motion performance for consumers.
The gyroscope supports eight programmable full-scale range settings from ±15.625dps to ±2000dps, and the accelerometer supports
four programmable full-scale range settings from ±2g to ±16g.
ICM-42688-P also supports external clock input for highly accurate 31kHz to 50kHz clock, that helps to reduce system level sensitivity
error, improve orientation measurement from gyroscope data, reduce ODR sensitivity to temperature and device to device
variation.
The device includes industry first 20-bits data format support in FIFO for high-data resolution. This FIFO format encapsulates 19-bits
of gyroscope data and 18-bits of accelerometer data for high precision applications. Other industry-leading features include on-chip
16-bit ADCs, programmable digital filters, an embedded temperature sensor, and programmable interrupts. The device features
I3CSM, I2C and SPI serial interfaces, a VDD operating range of 1.71 V to 3.6 V, and a separate VDDIO operating range of 1.71 V to 3.6
V.
The host interface can be configured to support I3CSM slave, I2C slave, or SPI slave modes. The I3CSM interface supports speeds up to
12.5MHz (data rates up to 12.5Mbps in SDR mode, 25Mbps in DDR mode), the I2C interface supports speeds up to 1 MHz, and the
SPI interface supports speeds up to 24 MHz.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers with companion
CMOS electronics through wafer-level bonding, InvenSense has driven the package size down to a footprint and thickness of
2.5x3x0.91 mm (14-pin LGA), to provide a very small yet high performance low cost package. The device provides high robustness by
supporting 20,000g shock reliability.
1.3 APPLICATIONS
AR/VR Controllers
Head Mounted Displays
Wearables
Sports
Robotics
@TDI( lnvenSense
ICM-42688-P
Page 10 of 109
Document Number: DS-000347
Revision: 1.2
2 FEATURES
2.1 GYROSCOPE FEATURES
The triple-axis MEMS gyroscope in the ICM-42688-P includes a wide range of features:
Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with programmable full-scale range of ±15.625, ±31.25,
±62.5, ±125, ±250, ±500, ±1000, and ±2000 degrees/sec
Low Noise (LN) power mode support
Digitally-programmable low-pass filters
Factory calibrated sensitivity scale factor
Self-test
2.2 ACCELEROMETER FEATURES
The triple-axis MEMS accelerometer in ICM-42688-P includes a wide range of features:
Digital-output X-, Y-, and Z-axis accelerometer with programmable full-scale range of ±2g, ±4g ±8g and ±16g
Low Noise (LN) and Low Power (LP) power modes support
User-programmable interrupts
Wake-on-motion interrupt for low power operation of applications processor
Self-test
2.3 MOTION FEATURES
ICM-42688-P includes the following motion features, also known as APEX (Advanced Pedometer and Event Detection neXt gen)
Pedometer: Tracks Step Count, also issues Step Detect interrupt
Tilt Detection: Issues an interrupt when the Tilt angle exceeds 35 for more than a programmable time
Raise to Wake/Sleep: Gesture detection for wake and sleep events. Interrupt is issued when either of these two events are
detected
Tap Detection: Issues an interrupt when a tap is detected, along with the tap count
Wake on Motion: Detects motion when accelerometer data exceeds a programmable threshold
Significant Motion Detection: Detects Significant Motion if Wake on Motion events are detected during a programmable time
window
2.4 ADDITIONAL FEATURES
ICM-42688-P includes the following additional features:
External clock input supports highly accurate clock input from 31kHz to 50kHz, helps to reduce system level sensitivity error,
improve orientation measurement from gyroscope data, reduce ODR sensitivity to temperature and device to device variation
2K byte FIFO buffer enables the applications processor to read the data in bursts
20-bits data format support in FIFO for high-data resolution
User-programmable digital filters for gyroscope, accelerometer, and temperature sensor
12.5MHz I3CSM (data rates up to 12.5Mbps in SDR mode, 25Mbps in DDR mode) / 1 MHz I2C / 24 MHz SPI slave host interface
Digital-output temperature sensor
Smallest and thinnest LGA package for portable devices: 2.5x3x0.91 mm (14-pin LGA)
20,000 g shock tolerant
MEMS structure hermetically sealed and bonded at wafer level
RoHS and Green compliant
@TDI( InvenSense
ICM-42688-P
Page 11 of 109
Document Number: DS-000347
Revision: 1.2
3 ELECTRICAL CHARACTERISTICS
3.1 GYROSCOPE SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
GYROSCOPE SENSITIVITY
Full-Scale Range
GYRO_FS_SEL=0
±2000
º/s
2
GYRO_FS_SEL =1
±1000
º/s
2
GYRO_FS_SEL =2
±500
º/s
2
GYRO_FS_SEL =3
±250
º/s
2
GYRO_FS_SEL =4
±125
º/s
2
GYRO_FS_SEL =5
±62.5
º/s
2
GYRO_FS_SEL =6
±31.25
º/s
2
GYRO_FS_SEL =7
±15.625
º/s
2
Gyroscope ADC Word Length
Output in two’s complement format
16
bits
2, 5
Sensitivity Scale Factor
GYRO_FS_SEL=0
16.4
LSB/(º/s)
2
GYRO_FS_SEL =1
32.8
LSB/(º/s)
2
GYRO_FS_SEL =2
65.5
LSB/(º/s)
2
GYRO_FS_SEL =3
131
LSB/(º/s)
2
GYRO_FS_SEL =4
262
LSB/(º/s)
2
GYRO_FS_SEL =5
524.3
LSB/(º/s)
2
GYRO_FS_SEL =6
1048.6
LSB/(º/s)
2
GYRO_FS_SEL =7
2097.2
LSB/(º/s)
2
Sensitivity Scale Factor Initial Tolerance
Component and Board-level, 25°C
±0.5
%
1
Sensitivity Scale Factor Variation Over
Temperature
0°C to +70°C
±0.005
%/ºC
3
Nonlinearity
Best fit straight line; 25°C
±0.1
%
3
Cross-Axis Sensitivity
Board-level
±1.25
%
3
ZERO-RATE OUTPUT (ZRO)
Initial ZRO Tolerance
Board-level, 25°C
±0.5
º/s
3
ZRO Variation vs. Temperature
0°C to +70°C
±0.005
º/s/ºC
3
OTHER PARAMETERS
Rate Noise Spectral Density
@ 10 Hz
0.0028
º/s /√Hz
1
Total RMS Noise
Bandwidth = 100 Hz
0.028
º/s-rms
4
Gyroscope Mechanical Frequencies
25
27
29
KHz
1
Low Pass Filter Response
ODR < 1kHz
5
500
Hz
2
ODR ≥ 1kHz
42
3979
Hz
2
Gyroscope Start-Up Time
Time from gyro enable to gyro drive ready
30
ms
3
Output Data Rate
12.5
32000
Hz
2
Table 1. Gyroscope Specifications
Notes:
1. Tested in production.
2. Guaranteed by design.
3. Derived from validation or characterization of parts, not tested in production.
4. Calculated from Rate Noise Spectral Density.
5. 20-bits data format supported in FIFO, see section 6.1.
@TDI( InvenSense
ICM-42688-P
Page 12 of 109
Document Number: DS-000347
Revision: 1.2
3.2 ACCELEROMETER SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
ACCELEROMETER SENSITIVITY
Full-Scale Range
ACCEL_FS_SEL =0
±16
g
2
ACCEL_FS_SEL =1
±8
g
2
ACCEL_FS_SEL =2
±4
g
2
ACCEL_FS_SEL =3
±2
g
2
ADC Word Length
Output in two’s complement format
16
bits
2, 5
Sensitivity Scale Factor
ACCEL_FS_SEL =0
2,048
LSB/g
2
ACCEL_FS_SEL =1
4,096
LSB/g
2
ACCEL_FS_SEL =2
8,192
LSB/g
2
ACCEL_FS_SEL =3
16,384
LSB/g
2
Sensitivity Scale Factor Initial Tolerance
Component and Board-level, 25°C
±0.5
%
1
Sensitivity Change vs. Temperature
-40°C to +85°C
±0.005
%/ºC
3
Nonlinearity
Best Fit Straight Line, ±2g
±0.1
%
3
Cross-Axis Sensitivity
Board-level
±1
%
3
ZERO-G OUTPUT
Initial Tolerance
Board-level, all axes
±20
mg
3
Zero-G Level Change vs. Temperature
-40°C to +85°C
±0.15
mg/ºC
3
OTHER PARAMETERS
Power Spectral Density
@ 10 Hz
X and Y-axis
65
µg/√Hz
1
Z-axis
70
µg/√Hz
1
RMS Noise
Bandwidth = 100 Hz
X and Y-axis
0.65
mg-rms
4
Z-axis
0.70
mg-rms
4
Low-Pass Filter Response
ODR < 1kHz
5
500
Hz
2
ODR ≥ 1kHz
42
3979
Hz
2
Accelerometer Startup Time
From sleep mode to valid data
10
ms
3
Output Data Rate
1.5625
32000
Hz
2
Table 2. Accelerometer Specifications
Notes:
1. Tested in production.
2. Guaranteed by design.
3. Derived from validation or characterization of parts, not tested in production.
4. Calculated from Power Spectral Density.
5. 20-bits data format supported in FIFO, see section 6.1.
@TDI( lnvenSense
ICM-42688-P
Page 13 of 109
Document Number: DS-000347
Revision: 1.2
3.3 ELECTRICAL SPECIFICATIONS
3.3.1 D.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SUPPLY VOLTAGES
VDD
1.71
1.8
3.6
V
1
VDDIO
1.71
1.8
3.6
V
1
SUPPLY CURRENTS
Low-Noise Mode
6-Axis Gyroscope + Accelerometer
0.88
mA
2
3-Axis Accelerometer
0.28
mA
2
3-Axis Gyroscope
0.73
mA
2
Full-Chip Sleep Mode
At 25ºC
7.5
µA
2
TEMPERATURE RANGE
Specified Temperature Range
Performance parameters are not applicable
beyond Specified Temperature Range
-40
+85
°C
1
Table 3. D.C. Electrical Characteristics
Notes:
1. Guaranteed by design.
2. Derived from validation or characterization of parts, not tested in production.
@TDI( InvenSense
ICM-42688-P
Page 14 of 109
Document Number: DS-000347
Revision: 1.2
3.3.2 A.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SUPPLIES
Supply Ramp Time
Monotonic ramp. Ramp rate is 10% to 90% of
the final value
0.01
3
ms
1
Power Supply Noise
10
mV
peak-peak
1
TEMPERATURE SENSOR
Operating Range
Ambient
-40
85
°C
1
25°C Output
0
LSB
3
ADC Resolution
Output in two’s complement format
16
bits
2
ODR
With Filter
25
8000
Hz
2
Room Temperature Offset
25°C
-5
5
°C
3
Stabilization Time
14000
µs
2
Sensitivity
Untrimmed
132.48
LSB/°C
1
Sensitivity for FIFO data
2.07
LSB/°C
1
POWER-ON RESET
Start-up time for register read/write
From power-up
1
ms
1
I2C ADDRESS
I2C ADDRESS
AP_AD0 = 0
AP_AD0 = 1
1101000
1101001
DIGITAL INPUTS (FSYNC, SCLK, SDI, CS)
VIH, High Level Input Voltage
0.7*VDDIO
V
1
VIL, Low Level Input Voltage
0.3*VDDIO
V
CI, Input Capacitance
< 10
pF
DIGITAL OUTPUT (SDO, INT1, INT2)
VOH, High Level Output Voltage
RLOAD=1 MΩ;
0.9*VDDIO
V
1
VOL1, LOW-Level Output Voltage
RLOAD=1 MΩ;
0.1*VDDIO
V
VOL.INT, INT Low-Level Output Voltage
OPEN=1, 0.3 mA sink
Current
0.1
V
Output Leakage Current
OPEN=1
100
nA
tINT, INT Pulse Width
int_tpulse_duration= 0 , 1 (100us, 8us ) ;
8
100
µs
I2C I/O (SCL, SDA)
VIL, LOW-Level Input Voltage
-0.5 V
0.3*VDDIO
V
1
VIH, HIGH-Level Input Voltage
0.7*VDDIO
VDDIO +
0.5 V
V
Vhys, Hysteresis
0.1*VDDIO
V
VOL, LOW-Level Output Voltage
3 mA sink current
0
0.4
V
IOL, LOW-Level Output Current
VOL=0.4 V
VOL=0.6 V
3
6
mA
mA
Output Leakage Current
100
nA
tof, Output Fall Time from VIHmax to VILmax
Cb bus capacitance in pf
20+0.1Cb
300
ns
INTERNAL CLOCK SOURCE
Clock Frequency Initial Tolerance
CLKSEL=`2b00 or gyro inactive; 25°C
-3
+3
%
1
CLK_SEL=`2b01 and gyro active; 25°C
-1
+1
%
1
Frequency Variation over Temperature
CLK_SEL=`2b00 or gyro inactive; -40°C to +85°C
±3
%
1
CLK_SEL=`2b01 and gyro active; -40oC to +85oC
±2
%
1
EXTERNAL CLOCK SOURCE
Clock Frequency
31
32
50
kHz
1
Table 4. A.C. Electrical Characteristics
Notes:
1. Expected results based on design, will be updated after characterization. Not tested in production.
2. Guaranteed by design.
3. Production tested.
@TDI( InvenSense
ICM-42688-P
Page 15 of 109
Document Number: DS-000347
Revision: 1.2
3.4 I2C TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
Parameters
Conditions
Min
Typical
Max
Units
Notes
I2C TIMING
I2C FAST-MODE PLUS
fSCL, SCL Clock Frequency
1
MHz
1
tHD.STA, (Repeated) START Condition Hold Time
0.26
µs
1
tLOW, SCL Low Period
0.5
µs
1
tHIGH, SCL High Period
0.26
µs
1
tSU.STA, Repeated START Condition Setup Time
0.26
µs
1
tHD.DAT, SDA Data Hold Time
0
µs
1
tSU.DAT, SDA Data Setup Time
50
ns
1
tr, SDA and SCL Rise Time
Cb bus cap. from 10 to 400 pF
120
ns
1
tf, SDA and SCL Fall Time
Cb bus cap. from 10 to 400 pF
120
ns
1
tSU.STO, STOP Condition Setup Time
0.5
µs
1
tBUF, Bus Free Time Between STOP and START
Condition
0.5
µs
1
Cb, Capacitive Load for each Bus Line
< 400
pF
1
tVD.DAT, Data Valid Time
0.45
µs
1
tVD.ACK, Data Valid Acknowledge Time
0.45
µs
1
Table 5. I2C Timing Characteristics
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
SDA
SCL
SDA
SCL
70%
30%
tf
S
70%
30%
trtSU.DAT
tr
tHD.DAT
70%
30%
tHD.STA 1/fSCL
1st clock cycle
70%
30%
tLOW tHIGH
tVD.DAT
9th clock cycle
continued below at A
A
Sr PS
70%
30%
tSU.STA tHD.STA tVD.ACK tSU.STO
tBUF
70%
30%
9th clock cycle
tf
Figure 1. I2C Bus Timing Diagram
@TDI( InvenSense fl IIII i X X
ICM-42688-P
Page 16 of 109
Document Number: DS-000347
Revision: 1.2
3.5 SPI TIMING CHARACTERIZATION 4-WIRE SPI MODE
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SPI TIMING
fSPC, SCLK Clock Frequency
Default
24
MHz
1
tLOW, SCLK Low Period
17
ns
1
tHIGH, SCLK High Period
17
ns
1
tSU.CS, CS Setup Time
39
ns
1
tHD.CS, CS Hold Time
18
ns
1
tSU.SDI, SDI Setup Time
13
ns
1
tHD.SDI, SDI Hold Time
8
ns
1
tVD.SDO, SDO Valid Time
Cload = 20 pF
21.5
ns
1
tHD.SDO, SDO Hold Time
Cload = 20 pF
3.5
ns
1
tDIS.SDO, SDO Output Disable Time
28
ns
1
Table 6. 4-Wire SPI Timing Characteristics (24-MHz Operation)
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
tHIGH
70%
30%
1/fCLK tHD;CS
CS
SCLK
SDI
SDO MSB OUT
MSB IN LSB IN
LSB OUT
tDIS;SDO
70%
30%
tSU;CS
tSU;SDI tHD;SDI
70%
30%
tHD;SDO
70%
30%
tVD;SDO
tLOW
tFall tRise
Figure 2. 4-Wire SPI Bus Timing Diagram
@TDI( InvenSense T
ICM-42688-P
Page 17 of 109
Document Number: DS-000347
Revision: 1.2
3.6 SPI TIMING CHARACTERIZATION 3-WIRE SPI MODE
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SPI TIMING
fSPC, SCLK Clock Frequency
Default
24
MHz
1
tLOW, SCLK Low Period
17
ns
1
tHIGH, SCLK High Period
17
ns
1
tSU.CS, CS Setup Time
39
ns
1
tHD.CS, CS Hold Time
5
ns
1
tSU.SDIO, SDIO Input Setup Time
13
ns
1
tHD.SDIO, SDIO Input Hold Time
8
ns
1
tVD.SDIO, SDIO Output Valid Time
Cload = 20 pF
18.5
ns
1
tHD.SDIO, SDIO Output Hold Time
Cload = 20 pF
3.5
ns
1
tDIS.SDIO, SDIO Output Disable Time
28
ns
1
Table 7. 3-Wire SPI Timing Characteristics (24-MHz Operation)
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
tHIGH
70%
30%
1/fCLK tHD;CS
CS
SCLK
I
OMSB OUT
MSB IN LSB IN
LSB OUT
tDIS;SDIO
70%
30%
tSU;CS
tSU;SDIO tHD;SDIO
70%
30%
tHD;SDIO
70%
30%
tVD;SDIO
tLOW
tFall tRise
SDIO
Figure 3. 3-Wire SPI Bus Timing Diagram
@TDI( lnvenSense
ICM-42688-P
Page 18 of 109
Document Number: DS-000347
Revision: 1.2
3.7 ABSOLUTE MAXIMUM RATINGS
Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these conditions is not implied. Exposure to the absolute maximum ratings conditions for
extended periods may affect device reliability.
Parameter
Rating
Supply Voltage, VDD
-0.5 V to +4 V
Supply Voltage, VDDIO
-0.5 V to +4 V
Input Voltage Level (FSYNC, SCL, SDA)
-0.5 V to VDDIO + 0.5 V
Acceleration (Any Axis, unpowered)
20,000g for 0.2 ms
Operating Temperature Range
-40°C to +85°C
Storage Temperature Range
-40°C to +125°C
Electrostatic Discharge (ESD) Protection
2 kV (HBM);
500 V (CDM)
Latch-up
JEDEC Class II (2),125°C
±100 mA
Table 8. Absolute Maximum Ratings
@TDI( lnvenSense
ICM-42688-P
Page 19 of 109
Document Number: DS-000347
Revision: 1.2
4 APPLICATIONS INFORMATION
4.1 PIN OUT DIAGRAM AND SIGNAL DESCRIPTION
Pin Number
Pin Name
Pin Description
1
AP_SDO / AP_AD0
AP_SDO: AP SPI serial data output (4-wire mode);
AP_AD0: AP I3CSM / I2C slave address LSB
2
RESV
No Connect or Connect to GND
3
RESV
No Connect or Connect to GND
4
INT1 / INT
INT1: Interrupt 1 (Note: INT1 can be push-pull or open drain)
INT: All interrupts mapped to pin 4
5
VDDIO
IO power supply voltage
6
GND
Power supply ground
7
RESV
Connect to GND
8
VDD
Power supply voltage
9
INT2 / FSYNC / CLKIN
INT2: Interrupt 2 (Note: INT2 can be push-pull or open drain)
FSYNC: Frame sync input; Connect to GND if FSYNC not used
CLKIN: External clock input
10
RESV
No Connect or Connect to GND
11
RESV
No Connect or Connect to GND
12
AP_CS
AP SPI Chip select (AP SPI interface); Connect to VDDIO if using AP I3CSM / I2C
interface
13
AP_SCL / AP_SCLK
AP_SCL: AP I3CSM / I2C serial clock; AP_SCLK: AP SPI serial clock
14
AP_SDA / AP_SDIO /
AP_SDI
AP_SDA: AP I3CSM / I2C serial data; AP_SDIO: AP SPI serial data I/O (3-wire
mode); AP_SDI: AP SPI serial data input (4-wire mode)
Table 9. Signal Descriptions
AP_SCL / AP_SCLK
AP_SDA / AP_SDIO / AP_SDI
AP_CS
RESV
AP_SDO / AP_AD0
RESV
INT1 / INT
ICM-42688-P
1
2
3
4
14
13
12
RESV
RESV
VDD
INT2 / FSYNC / CLKIN
11
10
9
8
VDDIO
GND
RESV
5
6
7
+Z
+X+Y
Figure 4. Pin Out Diagram for ICM-42688-P 2.5x3.0x0.91 mm LGA
@TDI( lnvenSense
ICM-42688-P
Page 20 of 109
Document Number: DS-000347
Revision: 1.2
4.2 TYPICAL OPERATING CIRCUIT
INT2 / FSYNC / CLKIN
VDD 3.6VDC
AP_SDA
AP_AD0
2
1
4
3
5 6 7
10
11
8
9
14 13 12
AP_SCL
INT1 / INT
GND
RESV
ICM-42688-P
RESV
RESV
C1, 0.1 mF C2, 2.2 mF
RESV
VDDIO
C3, 10 nF
3.6VDC
VDDIO
RESV
Figure 5. ICM-42688-P Application Schematic (I3CSM / I2C Interface to Host)
Note: I2C lines are open drain and pull-up resistors (e.g. 10 kΩ) are required.
INT2 / FSYNC / CLKIN
VDD 3.6VDC
AP_SDIO /
AP_SDI
AP_SDO
2
1
4
3
5 6 7
10
11
8
9
14 13 12
AP_SCLK
INT1 / INT
GND
RESV
ICM-42688-P
RESV
RESV
C1, 0.1 mF C2, 2.2 mF
RESV
AP_CS
C3, 10 nF
3.6VDC
VDDIO
RESV
Figure 6. ICM-42688-P Application Schematic (SPI Interface to Host)
@TDI( lnvenSense
ICM-42688-P
Page 21 of 109
Document Number: DS-000347
Revision: 1.2
4.3 BILL OF MATERIALS FOR EXTERNAL COMPONENTS
Component
Label
Specification
Quantity
VDD Bypass Capacitors
C1
C2
X7R, 0.1µF ±10%
X7R, 2.2µF ±10%
1
1
VDDIO Bypass Capacitor
C3
X7R, 10nF ±10%
1
Table 10. Bill of Materials
@TDI( lnvenSense AP/MCU I3C5M/IZC/SPI INTW | NT2 ICM-42688-P
ICM-42688-P
Page 22 of 109
Document Number: DS-000347
Revision: 1.2
4.4 SYSTEM BLOCK DIAGRAM
Figure 7. ICM-42688-P System Block Diagram
Note: The above block diagram is an example. Please refer to the pin-out (section 4.1) for other configuration options.
4.5 OVERVIEW
The ICM-42688-P is comprised of the following key blocks and functions:
Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning
o 20-bits data format support in FIFO for high-data resolution (see section 6 for details)
Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning
o 20-bits data format support in FIFO for high-data resolution (see section 6 for details)
I3CSM, I2C and SPI serial communications interfaces
Self-Test
Clocking
Sensor Data Registers
FIFO
Interrupts
Digital-Output Temperature Sensor
Bias and LDOs
Charge Pump
Standard Power Modes
4.6 THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The ICM-42688-P includes a vibratory MEMS rate gyroscope, which detects rotation about the X-, Y-, and Z- Axes. When the
gyroscope is rotated about any of the sense axes, the Coriolis Effect causes a vibration that is detected by a capacitive pickoff. The
resulting signal is amplified, demodulated, and filtered to produce a voltage that is proportional to the angular rate. This voltage is
digitized using on-chip Analog-to-Digital Converters (ADCs) to sample each axis. The full-scale range of the gyro sensors may be
digitally programmed to ±15.625, ±31.25, ±62.5, ±125, ±250, ±500, ±1000, and ±2000 degrees per second (dps).
4.7 THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The ICM-42688-P includes a 3-Axis MEMS accelerometer. Acceleration along a particular axis induces displacement of a proof mass
in the MEMS structure, and capacitive sensors detect the displacement. The ICM-42688-P architecture reduces the accelerometers’
susceptibility to fabrication variations as well as to thermal drift. When the device is placed on a flat surface, it will measure 0g on
the X- and Y-axes and +1g on the Z-axis. The accelerometers’ scale factor is calibrated at the factory and is nominally independent of
supply voltage. The full-scale range of the digital output can be adjusted to ±2g, ±4g, ±8g and ±16g.
4.8 I3CSM, I2C AND SPI HOST INTERFACE
The ICM-42688-P communicates to the application processor using an I3CSM, I2C, or SPI serial interface. The ICM-42688-P always acts
as a slave when communicating to the application processor.
4.9 SELF-TEST
Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each measurement axis can
be activated by means of the gyroscope and accelerometer self-test registers.
@TDI( lnvenSense
ICM-42688-P
Page 23 of 109
Document Number: DS-000347
Revision: 1.2
When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The output signal is
used to observe the self-test response.
The self-test response is defined as follows:
Self-test response = Sensor output with self-test enabled Sensor output with self-test disabled
When the value of the self-test response is within the specified min/max limits of the product specification, the part has passed self-
test. When the self-test response exceeds the min/max values, the part is deemed to have failed self-test.
4.10 CLOCKING
The ICM-42688-P has a flexible clocking scheme, allowing external or internal clock sources to be used for the internal synchronous
circuitry. This synchronous circuitry includes the signal conditioning and ADCs, and various control circuits and registers.
The CLKIN pin on ICM-42688-P provides the ability to input an external clock. A highly accurate external clock may be used rather
than the internal clocks sources, if greater clock accuracy is desired. External clock input supports highly accurate clock input from
31kHz to 50kHz, resulting in improvement of the following:
a) ODR uncertainty due to process, temperature, operating mode (PLL vs. RCOSC), and design limitations. This uncertainty can
be as high as ±8% in RCOSC mode and ±1% in PLL mode. The CLKIN, assuming a 50ppm or better 32.768kHz source, will
improve the ODR accuracy from ±80,000ppm to ±50ppm in RCOSC mode, or from ±10,000ppm to ±50ppm in PLL mode.
b) System level sensitivity error. Any clock uncertainty directly impacts gyroscope sensitivity at the system level.
Sophisticated systems can estimate ODR inaccuracy to some extent, but not to the extent improved by using CLKIN.
c) System-level clock/sensor synchronization. When using CLKIN, the accelerometer and gyroscope are on the same clock as
the host. There is no need to continually re-synchronize the sensor data as the sensor sample points and period are known
to be in exact alignment with the common system clock.
d) CLKIN helps EIS (Electronic Image Stabilization) performance by providing:
o Very accurate gyroscope sample points for use during integration to find true angular displacement.
o Automatic time alignment between the motion sensor and the host and potentially the camera system.
e) Other applications that benefit from CLKIN include navigation, gaming, robotics.
Allowable internal sources for generating the internal clock are:
a) An internal relaxation oscillator
b) Auto-select between internal relaxation oscillator and gyroscope MEMS oscillator to use the best available source
For internal sources, the only setting supporting specified performance in all modes is option b). It is recommended that option b)
be used when using internal clock source.
4.11 SENSOR DATA REGISTERS
The sensor data registers contain the latest gyroscope, accelerometer, and temperature measurement data. They are read-only
registers, and are accessed via the serial interface. Data from these registers may be read anytime.
4.12 INTERRUPTS
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the interrupt pins
configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that can trigger an interrupt are (1)
Clock generator locked to new reference oscillator (used when switching clock sources); (2) new data is available to be read (from
the FIFO and Data registers); (3) accelerometer event interrupts; (4) FIFO watermark; (5) FIFO overflow. The interrupt status can be
read from the Interrupt Status register.
@TDI( lnvenSense
ICM-42688-P
Page 24 of 109
Document Number: DS-000347
Revision: 1.2
4.13 DIGITAL-OUTPUT TEMPERATURE SENSOR
An on-chip temperature sensor and ADC are used to measure the ICM-42688-P die temperature. The readings from the ADC can be
read from the FIFO or the Sensor Data registers.
Temperature sensor register data TEMP_DATA is updated with new data at max(Accelerometer ODR, Gyroscope ODR).
Temperature data value from the sensor data registers can be converted to degrees centigrade by using the following formula:
Temperature in Degrees Centigrade = (TEMP_DATA / 132.48) + 25
Temperature data stored in FIFO is an 8-bit quantity, FIFO_TEMP_DATA. It can be converted to degrees centigrade by using the
following formula:
Temperature in Degrees Centigrade = (FIFO_TEMP_DATA / 2.07) + 25
4.14 BIAS AND LDOS
The bias and LDO section generates the internal supply and the reference voltages and currents required by the ICM-42688-P.
4.15 CHARGE PUMP
An on-chip charge pump generates the high voltage required for the MEMS oscillator.
4.16 STANDARD POWER MODES
The following table lists the user-accessible power modes for ICM-42688-P.
Mode
Name
Gyro
Accel
1
Sleep Mode
Off
Off
2
Standby Mode
Drive On
Off
3
Accelerometer Low-Power Mode
Off
Duty-Cycled
4
Accelerometer Low-Noise Mode
Off
On
5
Gyroscope Low-Noise Mode
On
Off
6
6-Axis Low-Noise Mode
On
On
Table 11. Standard Power Modes for ICM-42688-P
@TDI( lnvenSense 4» Notch mm 7 74 mm (MP)
ICM-42688-P
Page 25 of 109
Document Number: DS-000347
Revision: 1.2
5 SIGNAL PATH
The following figure shows a block diagram of the signal path for ICM-42688-P.
UI Filter Block
(order, BW, ODR)
Decimation
Filter
(32kHz) Notch Filter Anti-Alias
Filter (AAF) 0
1
AAF_DIS
Gyro Only
ADC Sensor
Registers
FSR Selection
0
1
GYRO_NF_DIS
UI Interface
User
Programmable
Offset
Figure 8. ICM-42688-P Signal Path
The signal path starts with ADCs for the gyroscope and accelerometer. Other components of the signal path are described below in
further detail.
5.1 SUMMARY OF PARAMETERS USED TO CONFIGURE THE SIGNAL PATH
The following table shows the parameters that can control the signal path.
Parameter Name
Description
GYRO_AAF_DIS
Disables the Gyroscope Anti Alias Filter (AAF)
GYRO_AAF_DELT
GYRO_AAF_DELTSQR
GYRO_AAF_BITSHIFT
Three parameters required to program the gyroscope AAF. This is a 2nd order filter with
programmable low pass filter. This is a user programmable filter which can be used to select
the desired BW. This filter allows trading off RMS noise vs. latency for a given ODR.
ACCEL_AAF_DIS
Disables the Accelerometer Anti Alias Filter
ACCEL_AAF_DEL
ACCEL_AAF_DELTSQR
ACCEL_AAF_BITSHIFT
Three parameters required to program the accelerometer AAF. This is a 2nd order filter with
programmable low pass filter. This is a user programmable filter which can be used to select
the desired BW. This filter allows trading off RMS noise vs. latency for a given ODR.
GYRO_NF_DIS
Disables the gyro Notch Filter
GYRO_X/Y/Z_NF_COSWZ
GYRO_X/Y/Z_NF_COSWZ_SEL
Factory trimmed parameters, designed to position a Notch at or near the sense peak
frequency of Gyro. This allows the user to suppress only sense peak contribution to noise,
while still maintaining a low latency high BW/ODR interface from the Sensor. This filter is
available only in Gyro, and the parameters for X, Y, and Z are chosen independently.
GYRO_NF_BW_SEL
Factory trimmed parameter to cancel noise created by sense peak from Gyro. This parameter
is common to all three axes
5.2 NOTCH FILTER
The Notch Filter is supported only for the gyroscope signal path. The following steps can be used to program the notch filter. Note
that the notch filter is specific to each axis in the gyroscope, so the X, Y and Z axis can be programmed independently.
Frequency of Notch Filter (each axis)
To operate the Notch filter, two parameters NF_COSWZ, and NF_COSWZ_SEL must be programmed for each gyroscope axis.
Parameters NF_COSWZ are defined for each axis of the gyroscope as GYRO_X_NF_COSWZ (register bank 1, register 0x0Fh & register
0x12h), GYRO_Y_NF_COSWZ (register bank 1, register 0x10h & register 0x12h), GYRO_Z_NF_COSWZ (register bank 1, register 0x11h
& register 0x12h). Note that the parameters have 9-bit values across two different registers.
@TDI( lnvenSense
ICM-42688-P
Page 26 of 109
Document Number: DS-000347
Revision: 1.2
Parameters NF_COSWZ_SEL are defined for each axis of the gyroscope as GYRO_X_NF_COSWZ_SEL (register bank 1, register 0x12h,
bit 3), GYRO_Y_NF_COSWZ_SEL (register bank 1, register 0x12h, bit 4), GYRO_Z_NF_COSWZ_SEL (register bank 1, register 0x12h, bit
5).
Each value must be calculated using the steps described below, and programmed into the corresponding register locations
mentioned above.
fdesired is the desired frequency of the Notch Filter in kHz. The lower bound for fdesired is 1kHz, and the upper bound is 3kHz.
Operating the notch filter outside this range is not supported.
Step1: COSWZ = cos(2*pi*fdesired/32)
Step2:
If abs(COSWZ)≤0.875
NF_COSWZ = round[COSWZ*256]
NF_COSWZ_SEL = 0
else
NF_COSWZ_SEL = 1
if COSWZ > 0.875
NF_COSWZ = round [8*(1-COSWZ)*256]
else if COSWZ < -0.875
NF_COSWZ = round [-8*(1+COSWZ)*256]
end
End
Bandwidth of Notch Filter (common to all axes)
The notch filter allows the user to control the width of the notch from eight possible values using a 3-bit parameter
GYRO_NF_BW_SEL in register bank 1, register 0x13h, bits 6:4. This parameter is common to all three axes.
GYRO_NF_BW_SEL
Notch Filter Bandwidth (Hz)
0
1449
1
680
2
329
3
162
4
80
5
40
6
20
7
10
The notch filter can be selected or bypassed by using the parameter GYRO_NF_DIS in register bank 1, register 0x0Bh, bit 0 as shown
below.
GYRO_NF_DIS
Function
0
Enable notch filter
1
Disable notch filter
@TDI( InvenSense
ICM-42688-P
Page 27 of 109
Document Number: DS-000347
Revision: 1.2
5.3 ANTI-ALIAS FILTER
Anti-alias filters for gyroscope and accelerometer can be independently programmed to have bandwidths ranging from 42 Hz to
3979 Hz. To program the anti-alias filter for a required bandwidth, use the table below to map the bandwidth to register values as
shown:
a. Register bank 2, register 0x03h, bits 6:1, ACCEL_AAF_DELT: Code from 1 to 63 that allows programming the
bandwidth for accelerometer anti-alias filter
b. Register bank 2, register 0x04h, bits 7:0 and Bank 2, register 0x05h, bits 3:0, ACCEL_AAF_DELTSQR: Square of the
delt value for accelerometer
c. Register bank 2, register 0x05h, bits 7:4, ACCEL_AAF_BITSHIFT: Bitshift value for accelerometer used in hardware
implementation
d. Register bank 1, register 0x0Ch, bits 5:0, GYRO_AAF_DELT: Code from 1 to 63 that allows programming the
bandwidth for gyroscope anti-alias filter
e. Register bank 1, register 0x0Dh, bits 7:0 and Bank 1, register 0x0Eh, bits 3:0, GYRO_AAF_DELTSQR: Square of the
delt value for gyroscope
f. Register bank 1, register 0x0Eh, bits 7:4, GYRO_AAF_BITSHIFT: Bitshift value for gyroscope used in hardware
implementation
3dB Bandwidth (Hz)
ACCEL_AAF_DELT;
GYRO_AAF_DELT
ACCEL_AAF_DELTSQR;
GYRO_AAF_DELTSQR
ACCEL_AAF_BITSHIFT;
GYRO_AAF_BITSHIFT
42
1
1
15
84
2
4
13
126
3
9
12
170
4
16
11
213
5
25
10
258
6
36
10
303
7
49
9
348
8
64
9
394
9
81
9
441
10
100
8
488
11
122
8
536
12
144
8
585
13
170
8
634
14
196
7
684
15
224
7
734
16
256
7
785
17
288
7
837
18
324
7
890
19
360
6
943
20
400
6
997
21
440
6
1051
22
488
6
1107
23
528
6
1163
24
576
6
1220
25
624
6
1277
26
680
6
1336
27
736
5
@TDI( InvenSense
ICM-42688-P
Page 28 of 109
Document Number: DS-000347
Revision: 1.2
1395
28
784
5
1454
29
848
5
1515
30
896
5
1577
31
960
5
1639
32
1024
5
1702
33
1088
5
1766
34
1152
5
1830
35
1232
5
1896
36
1296
5
1962
37
1376
4
2029
38
1440
4
2097
39
1536
4
2166
40
1600
4
2235
41
1696
4
2306
42
1760
4
2377
43
1856
4
2449
44
1952
4
2522
45
2016
4
2596
46
2112
4
2671
47
2208
4
2746
48
2304
4
2823
49
2400
4
2900
50
2496
4
2978
51
2592
4
3057
52
2720
4
3137
53
2816
3
3217
54
2944
3
3299
55
3008
3
3381
56
3136
3
3464
57
3264
3
3548
58
3392
3
3633
59
3456
3
3718
60
3584
3
3805
61
3712
3
3892
62
3840
3
3979
63
3968
3
The anti-alias filter can be selected or bypassed for the gyroscope by using the parameter GYRO_AAF_DIS in register bank 1, register
0x0Bh, bit 1 as shown below.
GYRO_AAF_DIS
Function
0
Enable gyroscope anti-aliasing filter
1
Disable gyroscope anti-aliasing filter
@TDI( lnvenSense
ICM-42688-P
Page 29 of 109
Document Number: DS-000347
Revision: 1.2
The anti-alias filter can be selected or bypassed for the accelerometer by using the parameter ACCEL_AAF_DIS in register bank 2,
register 0x03h, bit 0 as shown below.
ACCEL_AAF_DIS
Function
0
Enable accelerometer anti-aliasing filter
1
Disable accelerometer anti-aliasing filter
5.4 USER PROGRAMMABLE OFFSET
Gyroscope and accelerometer offsets can be programmed by the user by using registers OFFSET_USER0, through OFFSET_USER8, in
bank 0, registers 0x77h through 0x7Fh (bank 4) as shown below.
Register Address
Register Name
Bits
Function
0x77h
OFFSET_USER0
7:0
Lower bits of X-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
0x78h
OFFSET_USER1
3:0
Upper bits of X-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
7:4
Upper bits of Y-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
0x79h
OFFSET_USER2
7:0
Lower bits of Y-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
0x7Ah
OFFSET_USER3
7:0
Lower bits of Z-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
0x7Bh
OFFSET_USER4
3:0
Upper bits of Z-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
7:4
Upper bits of X-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
0x7Ch
OFFSET_USER5
7:0
Lower bits of X-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
0x7Dh
OFFSET_USER6
7:0
Lower bits of Y-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
0x7Eh
OFFSET_USER7
3:0
Upper bits of Y-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
7:4
Upper bits of Z-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
0x7Fh
OFFSET_USER8
7:0
Lower bits of Z-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
5.5 UI FILTER BLOCK
The UI filter block can be programmed to select filter order and bandwidth independently for gyroscope and accelerometer.
Gyroscope filter order can be selected by programming the parameter GYRO_UI_FILT_ORD in register bank 0, register 0x51h, bits
3:2, as shown below.
@TDI( InvenSense
ICM-42688-P
Page 30 of 109
Document Number: DS-000347
Revision: 1.2
GYRO_UI_FILT_ORD
Filter Order
00
1st order
01
2nd order
10
3rd order
11
Reserved
Accelerometer filter order can be selected by programming the parameter ACCEL_UI_FILT_ORD in register bank 0, register 0x53h,
bits 4:3, as shown below.
ACCEL_UI_FILT_ORD
Filter Order
00
1st order
01
2nd order
10
3rd order
11
Reserved
Gyroscope and accelerometer filter 3dB bandwidth can be selected by programming the parameter GYRO_UI_FILT_BW in register
bank 0, register 0x52h, bits 3:0, and the parameter ACCEL_UI_FILT_BW in register bank 0, register 0x52h, bits 7:4, as shown below.
The values shown in bold correspond to low noise and the values shown in italics correspond to low latency. User can select the
appropriate setting based on the application requirements for power and latency. Corresponding Noise Bandwidth (NBW) and
Group Delay values are also shown.
1st Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay
3dB Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=0 (1st order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR
ODR(Hz)
0
1
2
3
4
5
6
7
14
15
1
32000
8400.0
2
16000
4194.1
3
8000
2096.3
4
4000
1048.1
5
2000
524.0
6
1000
498.3
227.2
188.9
111.0
92.4
59.6
48.8
23.9
262.0
2096.3
15
500
249.1
113.6
94.4
55.5
46.2
29.8
24.4
11.9
131.0
1048.1
7
200
99.6
90.9
75.5
44.4
37.0
23.8
19.5
9.6
104.8
419.2
8
100
49.8
90.9
75.5
44.4
37.0
23.8
19.5
9.6
104.8
209.6
9
50
24.9
90.9
75.5
44.4
37.0
23.8
19.5
9.6
104.8
104.8
10
25
12.5
90.9
75.5
44.4
37.0
23.8
19.5
9.6
104.8
52.4
11
12.5
12.5
90.9
75.5
44.4
37.0
23.8
19.5
9.6
104.8
52.4
NBW Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=0 (1st order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR
ODR(Hz)
0
1
2
3
4
5
6
7
14
15
1
32000
8831.7
2
16000
4410.6
3
8000
2204.6
@TDI( lnvenSense
ICM-42688-P
Page 31 of 109
Document Number: DS-000347
Revision: 1.2
4
4000
1102.2
5
2000
551.1
6
1000
551.1
230.8
196.3
126.5
108.9
75.8
64.1
34.1
275.6
2204.6
15
500
280.5
115.4
98.2
63.3
54.5
37.9
32.1
17.1
137.8
1102.2
7
200
112.2
92.4
78.5
50.6
43.6
30.3
25.7
13.7
110.3
440.9
8
100
56.1
92.4
78.5
50.6
43.6
30.3
25.7
13.7
110.3
220.5
9
50
28.1
92.4
78.5
50.6
43.6
30.3
25.7
13.7
110.3
110.3
10
25
14.1
92.4
78.5
50.6
43.6
30.3
25.7
13.7
110.3
55.2
11
12.5
14.1
92.4
78.5
50.6
43.6
30.3
25.7
13.7
110.3
55.2
Group Delay @DC (ms) for GYRO/ACCEL_UI_FILT_ORD=0 (1st order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR
ODR(Hz)
0
1
2
3
4
5
6
7
14
15
1
32000
0.1
2
16000
0.1
3
8000
0.2
4
4000
0.4
5
2000
0.8
6
1000
0.6
1.8
2.0
2.8
3.1
4.1
4.7
8.1
1.5
0.2
15
500
1.1
3.6
4.0
5.5
6.1
8.1
9.3
16.2
3.0
0.4
7
200
2.7
4.4
5.0
6.8
7.6
10.2
11.7
20.3
3.8
1.0
8
100
5.3
4.4
5.0
6.8
7.6
10.2
11.7
20.3
3.8
1.9
9
50
10.5
4.4
5.0
6.8
7.6
10.2
11.7
20.3
3.8
3.8
10
25
21.0
4.4
5.0
6.8
7.6
10.2
11.7
20.3
3.8
7.5
11
12.5
21.0
4.4
5.0
6.8
7.6
10.2
11.7
20.3
3.8
7.5
2nd Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay
3dB Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=1 (2nd order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR
ODR(Hz)
0
1
2
3
4
5
6
7
14
15
1
32000
8400.0
2
16000
4194.1
3
8000
2096.3
4
4000
1048.1
5
2000
524.0
6
1000
493.3
230.7
191.6
117.5
97.1
59.6
48.0
21.3
262.0
2096.3
15
500
246.7
115.3
95.8
58.8
48.5
29.8
24.0
10.6
131.0
1048.1
7
200
98.7
92.3
76.6
47.0
38.8
23.8
19.2
8.5
104.8
419.2
8
100
49.3
92.3
76.6
47.0
38.8
23.8
19.2
8.5
104.8
209.6
9
50
24.7
92.3
76.6
47.0
38.8
23.8
19.2
8.5
104.8
104.8
10
25
12.3
92.3
76.6
47.0
38.8
23.8
19.2
8.5
104.8
52.4
11
12.5
12.3
92.3
76.6
47.0
38.8
23.8
19.2
8.5
104.8
52.4
@TDI( lnvenSense
ICM-42688-P
Page 32 of 109
Document Number: DS-000347
Revision: 1.2
NBW Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=1 (2nd order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR
ODR(Hz)
0
1
2
3
4
5
6
7
14
15
1
32000
8831.7
2
16000
4410.6
3
8000
2204.6
4
4000
1102.2
5
2000
551.1
6
1000
551.1
223.7
189.9
122.7
102.8
64.7
52.5
23.7
275.6
2204.6
15
500
259.6
111.9
95.0
61.4
51.4
32.4
26.3
11.9
137.8
1102.2
7
200
103.9
89.5
76.0
49.1
41.2
25.9
21.0
9.5
110.3
440.9
8
100
52.0
89.5
76.0
49.1
41.2
25.9
21.0
9.5
110.3
220.5
9
50
26.0
89.5
76.0
49.1
41.2
25.9
21.0
9.5
110.3
110.3
10
25
13.0
89.5
76.0
49.1
41.2
25.9
21.0
9.5
110.3
55.2
11
12.5
13.0
89.5
76.0
49.1
41.2
25.9
21.0
9.5
110.3
55.2
Group Delay @DC (ms) for GYRO/ACCEL_UI_FILT_ORD=1 (2nd order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR
ODR(Hz)
0
1
2
3
4
5
6
7
14
15
1
32000
0.1
2
16000
0.1
3
8000
0.2
4
4000
0.4
5
2000
0.8
6
1000
0.7
2.1
2.4
3.2
3.7
5.2
6.1
12.0
1.5
0.2
15
500
1.3
4.1
4.7
6.4
7.3
10.4
12.2
24.0
3.0
0.4
7
200
3.3
5.1
5.8
8.0
9.1
12.9
15.3
30.0
3.8
1.0
8
100
6.5
5.1
5.8
8.0
9.1
12.9
15.3
30.0
3.8
1.9
9
50
12.9
5.1
5.8
8.0
9.1
12.9
15.3
30.0
3.8
3.8
10
25
25.7
5.1
5.8
8.0
9.1
12.9
15.3
30.0
3.8
7.5
11
12.5
25.7
5.1
5.8
8.0
9.1
12.9
15.3
30.0
3.8
7.5
3rd Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay
3dB Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=2 (3rd order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR
ODR(Hz)
0
1
2
3
4
5
6
7
14
15
1
32000
8400.0
2
16000
4194.1
3
8000
2096.3
4
4000
1048.1
5
2000
524.0
6
1000
492.9
234.7
195.8
118.9
97.9
60.8
46.8
25.2
262.0
2096.3
15
500
246.4
117.4
97.9
59.5
48.9
30.4
23.4
12.6
131.0
1048.1
7
200
98.6
93.9
78.3
47.6
39.2
24.3
18.7
10.1
104.8
419.2
@TDI( lnvenSense
ICM-42688-P
Page 33 of 109
Document Number: DS-000347
Revision: 1.2
8
100
49.3
93.9
78.3
47.6
39.2
24.3
18.7
10.1
104.8
209.6
9
50
24.6
93.9
78.3
47.6
39.2
24.3
18.7
10.1
104.8
104.8
10
25
12.3
93.9
78.3
47.6
39.2
24.3
18.7
10.1
104.8
52.4
11
12.5
12.3
93.9
78.3
47.6
39.2
24.3
18.7
10.1
104.8
52.4
NBW Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=0 (1st order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR
ODR(Hz)
0
1
2
3
4
5
6
7
14
15
1
32000
8831.7
2
16000
4410.6
3
8000
2204.6
4
4000
1102.2
5
2000
551.1
6
1000
551.1
221.3
188.5
120.1
100.0
62.9
48.6
26.4
275.6
2204.6
15
500
252.0
110.7
94.3
60.1
50.0
31.5
24.3
13.2
137.8
1102.2
7
200
100.8
88.6
75.4
48.1
40.0
25.2
19.5
10.6
110.3
440.9
8
100
50.4
88.6
75.4
48.1
40.0
25.2
19.5
10.6
110.3
220.5
9
50
25.2
88.6
75.4
48.1
40.0
25.2
19.5
10.6
110.3
110.3
10
25
12.6
88.6
75.4
48.1
40.0
25.2
19.5
10.6
110.3
55.2
11
12.5
12.6
88.6
75.4
48.1
40.0
25.2
19.5
10.6
110.3
55.2
Group Delay @DC (ms) for GYRO/ACCEL_UI_FILT_ORD=2 (3rd order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR
ODR(Hz)
0
1
2
3
4
5
6
7
14
15
1
32000
0.1
2
16000
0.1
3
8000
0.2
4
4000
0.4
5
2000
0.8
6
1000
0.8
2.3
2.7
4.0
4.6
6.6
8.2
14.1
1.5
0.2
15
500
1.6
4.6
5.4
7.9
9.2
13.2
16.3
28.1
3.0
0.4
7
200
4.0
5.8
6.8
9.8
11.4
16.5
20.4
35.2
3.8
1.0
8
100
8.0
5.8
6.8
9.8
11.4
16.5
20.4
35.2
3.8
1.9
9
50
15.9
5.8
6.8
9.8
11.4
16.5
20.4
35.2
3.8
3.8
10
25
31.8
5.8
6.8
9.8
11.4
16.5
20.4
35.2
3.8
7.5
11
12.5
31.8
5.8
6.8
9.8
11.4
16.5
20.4
35.2
3.8
7.5
5.6 UI PATH ODR AND FSR SELECTION
Gyroscope ODR can be selected by programming the parameter GYRO_ODR in register bank 0, register 0x4Fh, bits 3:0 as shown
below.
GYRO_ODR
Gyroscope ODR Value
0000
Reserved
0001
32kHz
@TDI( lnvenSense
ICM-42688-P
Page 34 of 109
Document Number: DS-000347
Revision: 1.2
0010
16kHz
0011
8kHz
0100
4kHz
0101
2kHz
0110
1kHz (default)
0111
200Hz
1000
100Hz
1001
50Hz
1010
25Hz
1011
12.5Hz
1100
Reserved
1101
Reserved
1110
Reserved
1111
500Hz
Gyroscope FSR can be selected by programming the parameter GYRO_UI_FS_SEL in register bank 0, register 0x4Fh, bits 7:5 as shown
below.
GYRO_UI_FS_SEL
Gyroscope FSR Value
000
2000dps
001
1000dps
010
500dps
011
250dps
100
125dps
101
62.5dps
110
31.25dps
111
15.625dps
Accelerometer ODR can be selected by programming the parameter ACCEL_ODR in register bank 0, register 0x50h, bits 3:0 as shown
below.
ACCEL_ODR
Accelerometer ODR Value
0000
Reserved
0001
32kHz (LN mode)
0010
16kHz (LN mode)
0011
8kHz (LN mode)
0100
4kHz (LN mode)
0101
2kHz (LN mode)
0110
1kHz (LN mode) (default)
0111
200Hz (LP or LN mode)
1000
100Hz (LP or LN mode)
1001
50Hz (LP or LN mode)
1010
25Hz (LP or LN mode)
@TDI( lnvenSense
ICM-42688-P
Page 35 of 109
Document Number: DS-000347
Revision: 1.2
1011
12.5Hz (LP or LN mode)
1100
6.25Hz (LP mode)
1101
3.125Hz (LP mode)
1110
1.5625Hz (LP mode)
1111
500Hz (LP or LN mode)
Accelerometer FSR can be selected by programming the parameter ACCEL_UI_FS_SEL in register bank 0, register 0x50h, bits 7:5 as
shown below.
ACCEL_UI_FS_SEL
Accelerometer FSR Value
000
16g
001
8g
010
4g
011
2g
100
Reserved
101
Reserved
110
Reserved
111
Reserved
@TDI( lnvenSense
ICM-42688-P
Page 36 of 109
Document Number: DS-000347
Revision: 1.2
6 FIFO
The ICM-42688-P contains a 2K byte FIFO register that is accessible via the serial interface. The FIFO configuration register
determines which data is written into the FIFO. Possible choices include gyroscope data, accelerometer data, temperature readings,
and FSYNC input. A FIFO counter keeps track of how many bytes of valid data are contained in the FIFO.
6.1 PACKET STRUCTURE
The following figure shows the FIFO packet structures supported in ICM-42688-P. Base data format for gyroscope and
accelerometer is 16-bits per element. 20-bits data format support is included in one of the packet structures. When 20-bits data
format is used, gyroscope data consists of 19-bits of actual data and the LSB is always set to 0, accelerometer data consists of 18-bits
of actual data and the two lowest order bits are always set to 0. When 20-bits data format is used, the only FSR settings that are
operational are ±2000dps for gyroscope and ±16g for accelerometer, even if the FSR selection register settings are configured for
other FSR values. The corresponding sensitivity scale factor values are 131 LSB/dps for gyroscope and 8192 LSB/g for
accelerometer.
Header
(1 byte)
Accelerometer Data
(6 bytes)
Temperature Data
(1 byte)
Header
(1 byte)
Gyroscope Data
(6 bytes)
Temperature Data
(1 byte)
Header
(1 byte)
Accelerometer Data
(6 bytes)
Gyroscope Data
(6 bytes)
TimeStamp
(2 bytes)
Temperature Data
(1 byte)
Header
(1 byte)
Accelerometer Data
(6 bytes)
Gyroscope Data
(6 bytes)
TimeStamp
(2 bytes)
Temperature Data
(2 bytes)
20-bit Extension
(3 bytes)
Packet 1 Packet 2
Packet 3
Packet 4
Figure 9. FIFO Packet Structure
The rest of this sub-section describes how individual data is packaged in the different FIFO packet structures.
@TDI( InvenSense
ICM-42688-P
Page 37 of 109
Document Number: DS-000347
Revision: 1.2
Packet 1: Individual data is packaged in Packet 1 as shown below.
Byte
Content
0x00
FIFO Header
0x01
Accel X [15:8]
0x02
Accel X [7:0]
0x03
Accel Y [15:8]
0x04
Accel Y [7:0]
0x05
Accel Z [15:8]
0x06
Accel Z [7:0]
0x07
Temperature[7:0]
Packet 2: Individual data is packaged in Packet 2 as shown below.
Byte
Content
0x00
FIFO Header
0x01
Gyro X [15:8]
0x02
Gyro X [7:0]
0x03
Gyro Y [15:8]
0x04
Gyro Y [7:0]
0x05
Gyro Z [15:8]
0x06
Gyro Z [7:0]
0x07
Temperature[7:0]
Packet 3: Individual data is packaged in Packet 3 as shown below.
Byte
Content
0x00
FIFO Header
0x01
Accel X [15:8]
0x02
Accel X [7:0]
0x03
Accel Y [15:8]
0x04
Accel Y [7:0]
0x05
Accel Z [15:8]
0x06
Accel Z [7:0]
0x07
Gyro X [15:8]
0x08
Gyro X [7:0]
0x09
Gyro Y [15:8]
0x0A
Gyro Y [7:0]
0x0B
Gyro Z [15:8]
0x0C
Gyro Z [7:0]
0x0D
Temperature[7:0]
0x0E
TimeStamp[15:8]
0x0F
TimeStamp[7:0]
@TDI( InvenSense
ICM-42688-P
Page 38 of 109
Document Number: DS-000347
Revision: 1.2
Packet 4: Individual data is packaged in Packet 4 as shown below.
Byte
Content
0x00
FIFO Header
0x01
Accel X [19:12]
0x02
Accel X [11:4]
0x03
Accel Y [19:12]
0x04
Accel Y [11:4]
0x05
Accel Z [19:12]
0x06
Accel Z [11:4]
0x07
Gyro X [19:12]
0x08
Gyro X [11:4]
0x09
Gyro Y [19:12]
0x0A
Gyro Y [11:4]
0x0B
Gyro Z [19:12]
0x0C
Gyro Z [11:4]
0x0D
Temperature[15:8]
0x0E
Temperature[7:0]
0x0F
TimeStamp[15:8]
0x10
TimeStamp[7:0]
0x11
Accel X [3:0]
Gyro X [3:0]
0x12
Accel Y [3:0]
Gyro Y [3:0]
0x13
Accel Z [3:0]
Gyro Z [3:0]
6.2 FIFO HEADER
The following table shows the structure of the 1byte FIFO header.
Bit Field
Item
Description
7
HEADER_MSG
1: FIFO is empty
0: Packet contains sensor data
6
HEADER_ACCEL
1: Packet is sized so that accel data have location in the packet, FIFO_ACCEL_EN
must be 1
0: Packet does not contain accel sample
5
HEADER_GYRO
1: Packet is sized so that gyro data have location in the packet, FIFO_GYRO_EN must
be 1
0: Packet does not contain gyro sample
4
HEADER_20
1 : Packet has a new and valid sample of extended 20-bit data for gyro and/or accel
0 : Packet does not contain a new and valid extended 20-bit data
3:2
HEADER_TIMESTAMP_FSYNC
00: Packet does not contain timestamp or FSYNC time data
01: Reserved
10: Packet contains ODR Timestamp
11: Packet contains FSYNC time, and this packet is flagged as first ODR after FSYNC
(only if FIFO_TMST_FSYNC_EN is 1)
1
HEADER_ODR_ACCEL
1: The ODR for accel is different for this accel data packet compared to the previous
accel packet
0: The ODR for accel is the same as the previous packet with accel
0
HEADER_ODR_GYRO
1: The ODR for gyro is different for this gyro data packet compared to the previous
gyro packet
0: The ODR for gyro is the same as the previous packet with gyro
Note at least HEADER_ACCEL or HEADER_GYRO must be set for a sensor data packet to be set.
@TDI( lnvenSense >4
ICM-42688-P
Page 39 of 109
Document Number: DS-000347
Revision: 1.2
6.3 MAXIMUM FIFO STORAGE
The maximum number of packets that can be stored in FIFO is a variable quantity depending on the use case. As shown in the figure
below, the physical FIFO size is 2048 bytes. A number of bytes equal to the packet size selected (see section 6.1) is reserved to
prevent reading a packet during write operation. Additionally, a read cache 2 packets wide is available.
When there is no serial interface operation, the read cache is not available for storing packets, being fed by the serial interface clock.
When serial interface operation happens, depending on the operation length and the packet size chosen, either 1 or 2 of the packet
entries in read cache may become available for storing packets. In that case the total storage available is up to the maximum
number of packets that can be accommodated in 2048 (2040 in case of 20 bytes packets) bytes + 1 packet size, depending on the
packet size used.
Due to the non-deterministic nature of system operation, driver memory allocation should always be the largest size of 2080 bytes.
Read Cache
FIFO 2048 Bytes 2 Packet Size
1 Packet Size
Reserved to prevent reading a
packet during write operation
2048 Bytes 1 packet size
Figure 10. Maximum FIFO Storage
6.4 FIFO CONFIGURATION REGISTERS
The following control bits in bank 0, register 0x5Fh determine what data is placed into the FIFO. The values of these bits may change
while the FIFO is being filled without corruption of the FIFO.
BIT
NAME
FUNCTION
4
FIFO_HIRES_EN
0: Default setting; Sensor data have regular resolution
1: Sensor data in FIFO will have extended resolution enabling the 20 Bytes
packet with priority on other setting below
3
FIFO_TMST_FSYNC_EN
0: FIFO will only contain ODR timestamp information
1: FIFO can also contain FSYNC time and FSYNC flag for one ODR after an
FSYNC event
1
FIFO_GYRO_EN
0: Default setting; Gyroscope data not placed into FIFO
1: Enables gyroscope data packets of 6-bytes to be placed in FIFO
0
FIFO_ACCEL_EN
0: Default setting; Accelerometer data not placed into FIFO
1: Enables accelerometer data packets of 6-bytes to be placed in FIFO
Configuration register settings above impact FIFO header and FIFO packet size as follows:
@TDI( lnvenSense
ICM-42688-P
Page 40 of 109
Document Number: DS-000347
Revision: 1.2
FIFO_HIRES_EN
FIFO_ACCEL_EN
FIFO_GYRO_EN
FIFO_TMST_
FSYNC_EN
Header
Packet size
1
X
X
0
8’b_0111_10xx
20 Bytes
1
X
X
1
8’b_0111_11xx
20 Bytes
0
1
1
0
8’b_0110_10xx
16 Bytes
0
1
1
1
8’b_0110_11xx
16 Bytes
0
1
0
X
8’b_0100_00xx
8 Bytes
0
0
1
X
8’b_0010_00xx
8 Bytes
0
0
0
X
No FIFO writes
No FIFO writes
@TDI( lnvenSense
ICM-42688-P
Page 41 of 109
Document Number: DS-000347
Revision: 1.2
7 PROGRAMMABLE INTERRUPTS
The ICM-42688-P has a programmable interrupt system that can generate an interrupt signal on the INT pins. Status flags indicate
the source of an interrupt. Interrupt sources may be enabled and disabled individually. There are two interrupt outputs. Any
interrupt may be mapped to either interrupt pin as explained in the register section. The following configuration options are
available for the interrupts
INT1 and INT2 can be push-pull or open drain
Level or pulse mode
Active high or active low
Additionally, ICM-42688-P includes In-band Interrupt (IBI) support for the I3CSM interface.
@TDI( lnvenSense
ICM-42688-P
Page 42 of 109
Document Number: DS-000347
Revision: 1.2
8 APEX MOTION FUNCTIONS
The APEX (Advanced Pedometer and Event Detection neXt gen) features ICM-42688-P consist of:
Pedometer: Tracks Step count and issues a Step Detect Interrupt
Tilt Detection: Issues an interrupt when the Tilt angle exceeds 35 degrees for more than a programmable time.
Raise to Wake/Sleep: Gesture detection for wake and sleep events. Interrupt is issued when either of these two events are
detected.
Tap Detection: Issues an interrupt when Tap is detected, along with a register containing the Tap Count.
Wake on Motion (WoM): Detects motion when accelerometer samples exceed a programmable threshold. This motion
event can be used to enable chip operation from sleep mode.
Significant Motion Detector (SMD): Detects motion if WoM events are detected during a programmable time window (2s or
4s).
8.1 APEX ODR SUPPORT
APEX algorithms are designed to work with the accelerometer, for a variety of ODR settings. However, there is a minimum ODR
required for each algorithm. The following table shows the relationship between the available accelerometer ODRs and the
operation of the APEX algorithms. In order to allow more flexible operation where we can control the ODR of the APEX algorithms
independent of the accelerometer ODR, we allow for an additional selection determined by the field DMP_ODR. The tables below
shows how DMP_ODR should be configured in relation to the accelerometer ODR and the expected performance.
Accel ODR
DMP_ODR
Tap Detection
Pedometer
Tilt Detection
Raise to Wake/Sleep
< 25Hz
X
Disabled
Disabled
Disabled
Disabled
≥ 25Hz
0 (25Hz)
Disabled
Low Power
Low Power
Enabled
≥ 50Hz
2 (50Hz)
Disabled
Normal
Normal
Enabled
Accel ODR
Tap Detection
200Hz
Low Power
500Hz
Normal
1kHz
High Performance
> 1kHz
Disabled
If the accelerometer ODR is set below the minimum DMP ODR (25 Hz), the APEX features cannot be enabled.
When the accelerometer ODR needs to be set differently from the DMP ODR, only the integer multiple of DMP ODR for
accelerometer sensor ODR is suitable to use with DMP. For example, when the accelerometer ODR is set as 200 Hz, the APEX
features can be enabled with choices of 25 Hz, or 50 Hz, depending on the DMP_ODR register setting.
DMP ODR should not be changed on the fly. The following sequence should be followed for changing the DMP ODR:
@TDI( lnvenSense
ICM-42688-P
Page 43 of 109
Document Number: DS-000347
Revision: 1.2
1. Disable Pedometer, and Tilt Detection if they are enabled
2. Change DMP ODR
3. Set DMP_INIT_EN for one cycle (Register 0x4Bh in Bank 0)
4. Unset DMP_INIT_EN (Register 0x4Bh in Bank 0)
5. Enable APEX features of interest
8.2 DMP POWER SAVE MODE
DMP Power Save Mode can be enabled or disabled by DMP_POWER_SAVE (Register 0x56h in Bank 0). When the DMP Power Save
Mode is enabled, APEX features are enabled only when WOM is detected. WOM must be explicitly enabled for the DMP to work in
this mode. When WOM is not detected the APEX features are on pause. If the user does not want to use DMP Power Save Mode
they may set DMP_POWER_SAVE = 0, and use APEX functions without WOM detection.
8.3 PEDOMETER PROGRAMMING
Pedometer configuration parameters
1. LOW_ENERGY_AMP_TH_SEL (Register 0x40h in Bank 4)
2. PED_AMP_TH_SEL (Register 0x41h in Bank 4)
3. PED_STEP_CNT_TH_SEL (Register 0x41h in Bank 4)
4. PED_HI_EN_TH_SEL (Register 0x42h in Bank 4)
5. PED_SB_TIMER_TH_SEL (Register 0x42h in Bank 4)
6. PED_STEP_DET_TH_SEL (Register 0x42h in Bank 4)
7. SENSITIVITY_MODE (Register 0x48h in Bank 4)
8. There are 2 ODR and 2 sensitivity modes
Accel ODR (DMP_ODR)
normal
slow walk
25 Hz (0)
low power
low power and slow walk
50 Hz (2)
high performance
slow walk
Initialize Sensor in a typical configuration
1. Set accelerometer ODR to 50 Hz (Register 0x50h in Bank 0)
2. Set accelerometer to Low Power mode (Register 0x4Eh in Bank 0)
ACCEL_MODE = 2 and (Register 0x4Eh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode
3. Set DMP ODR = 50 Hz and turn on Pedometer feature (Register 0x56h in Bank 0)
4. Wait 1 millisecond
Initialize APEX hardware
1. Set DMP_MEM_RESET_EN to 1 (Register 0x4Bh in Bank 0)
2. Wait 1 millisecond
3. Set LOW_ENERGY_AMP_TH_SEL to 10 (Register 0x40h in Bank 4)
4. Set PED_AMP_TH_SEL to 8 (Register 0x41h in Bank 4)
5. Set PED_STEP_CNT_TH_SEL to 5 (Register 0x41h in Bank 4)
6. Set PED_HI_EN_TH_SEL to 1 (Register 0x42h in Bank 4)
7. Set PED_SB_TIMER_TH_SEL to 4 (Register 0x42h in Bank 4)
8. Set PED_STEP_DET_TH_SEL to 2 (Register 0x42h in Bank 4)
9. Set SENSITIVITY_MODE to 0 (Register 0x48h in Bank 4)
10. Set DMP_INIT_EN to 1 (Register 0x4Bh in Bank 0)
11. Enable STEP detection, source for INT1 by setting bit 5 in register INT_SOURCE6 (Register 0x4Dh in Bank 4) to 1. Or
if INT2 is selected for STEP detection, enable STEP detection source by setting bit 5 in register INT_SOURCE7
(Register 0x4Eh in Bank 4) to 1.
12. Wait 50 milliseconds
13. Turn on Pedometer feature by setting PED_ENABLE to 1 (Register 0x56h in Bank 0)
@TDI( lnvenSense
ICM-42688-P
Page 44 of 109
Document Number: DS-000347
Revision: 1.2
Output registers
1. Read interrupt register (Register 0x38h in Bank 0) for STEP_DET_INT
2. If the step count is equal to or greater than 65535 (uint16), the STEP_CNT_OVF_INT (Register 0x38h in Bank 0) will
be set to 1. Example:
Take 1 step =>output step count = 65533 (real step count is 65533)
Take 1 step => output step count = 65534 (real step count is 65534)
Take 1 step => output step count = 0 and interrupt is fired (real step count is 65535+0= 65535)
Take 1 step => output step count = 1 (real step count is 65535+1=65536)
3. Read the step count in STEP_CNT (Register 0x31h and 0x32h in Bank 0)
4. Read the step cadence in STEP_CADENCE (Register 0x33h in Bank 0)
5. Read the activity class in ACTIVITY_CLASS (Register 0x34h in Bank 0)
8.4 TILT DETECTION PROGRAMMING
Tilt Detection configuration parameters
1. TILT_WAIT_TIME (Register 0x43h in Bank 4)
This parameter configures how long of a delay after tilt is detected before interrupt is triggered
Default is 2 (4 s).
Range is 0 = 0 s, 1 = 2 s, 2 = 4 s, 3 = 6 s
For example, setting TILT_WAIT_TIME = 2 is equivalent to 4 seconds for all ODRs
Initialize Sensor in a typical configuration
1. Set accelerometer ODR (Register 0x50h in Bank 0)
ACCEL_ODR = 9 for 50 Hz or 10 for 25 Hz
2. Set Accel to Low Power mode (Register 0x4Eh in Bank 0)
ACCEL_MODE = 2 and (Register 0x4Dh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode
3. Set DMP ODR (Register 0x56h in Bank 0)
DMP_ODR = 0 for 25 Hz, 2 for 50 Hz
4. Wait 1 millisecond
Initialize APEX hardware
1. Set DMP_MEM_RESET_EN to 1 (Register 0x4Bh in Bank 0)
2. Wait 1 millisecond
3. Set TILT_WAIT_TIME (Register 0x43h in Bank 4) if default value does not meet needs
4. Wait 1 millisecond
5. Set DMP_INIT_EN to 1 (Register 0x4Bh in Bank 0)
6. Enable Tilt Detection, source for INT1 by setting bit 3 in register INT_SOURCE6 (Register 0x4Dh in Bank 4) to 1. Or
if INT2 is selected for Tilt Detection, enable Tilt Detection source by setting bit 3 in register INT_SOURCE7 (Register
0x4Eh in Bank 4) to 1.
7. Wait 50 milliseconds
8. Turn on Tilt Detection feature by setting TILT_ENABLE to 1 (Register 0x56h in Bank 0)
Output registers
1. Read interrupt register (Register 0x38h in Bank 0) for TILT_DET_INT
8.5 RAISE TO WAKE/SLEEP PROGRAMMING
Raise to Wake/Sleep configuration parameters
1. SLEEP_TIME_OUT (Register 0x43h in Bank 4)
2. MOUNTING_MATRIX (Register 0x44h in Bank 4)
3. SLEEP_GESTURE_DELAY (Register 0x45h in Bank 4)
Initialize Sensor in a typical configuration
1. Set accelerometer ODR (Register 0x50h in Bank 0)
ACCEL_ODR = 10 for 25 Hz
@TDI( lnvenSense
ICM-42688-P
Page 45 of 109
Document Number: DS-000347
Revision: 1.2
2. Set Accel to Low Power mode (Register 0x4Eh in Bank 0)
ACCEL_MODE = 2 and (Register 0x4Dh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode
3. Set DMP ODR (Register 0x56h in Bank 0)
DMP_ODR = 0 for 25 Hz, 2 for 50 Hz
4. Wait 1 millisecond
Initialize APEX hardware
1. Set DMP_MEM_RESET_EN to 1 (Register 0x4Bh in Bank 0)
2. Wait 1 millisecond
3. Set SLEEP_TIME_OUT (Register 0x43h in Bank 4) if default value does not meet needs
4. Wait 1 millisecond
5. Set MOUNTING_MATRIX (Register 0x44h in Bank 4) if default value does not meet needs
6. Wait 1 millisecond
7. Set SLEEP_GESTURE_DELAY (Register 0x45h in Bank 4) if default value does not meet needs
8. Wait 1 millisecond
9. Set DMP_INIT_EN to 1 (Register 0x4Bh in Bank 0)
10. Enable Raise to Wake/Sleep, source for INT1 by setting bit 2,1 in register INT_SOURCE6 (Register 0x4Dh in Bank 4)
to 1. Or if INT2 is selected for Raise to Wake/Sleep, enable Raise to Wake/Sleep source by setting bit 2,1 in register
INT_SOURCE7 (Register 0x4Eh in Bank 4) to 1.
11. Wait 50 milliseconds
12. Turn on Raise to Wake/Sleep feature by setting R2W_EN to 1 (Register 0x56h in Bank 0)
Output registers
1. Read interrupt register (Register 0x38h in Bank 0) for WAKE_INT, SLEEP_INT
8.6 TAP DETECTION PROGRAMMING
Tap Detection configuration parameters
1. TAP_TMAX (Register 0x47h in Bank 4)
2. TAP_TMIN (Register 0x47h in Bank 4)
3. TAP_TAVG (Register 0x47h in Bank 4)
4. TAP_MIN_JERK_THR (Register 0x46h in Bank 4)
5. TAP_MAX_PEAK_TOL (Register 0x46h in Bank 4)
6. TAP_ENABLE (Register 0x56h in Bank 0)
Initialize Sensor in a typical configuration
1. Set accelerometer ODR (Register 0x50h in Bank 0)
ACCEL_ODR = 15 for 500 Hz (ODR of 200Hz or 1kHz may also be used)
2. Set power modes and filter configurations as shown below
For ODR up to 500Hz, set Accel to Low Power mode (Register 0x4Eh in Bank 0)
ACCEL_MODE = 2 and ACCEL_LP_CLK_SEL = 0, (Register 0x4Dh in Bank 0) for low power mode
Set filter settings as follows: ACCEL_DEC2_M2_ORD = 2 (Register 0x53h in Bank 0); ACCEL_UI_FILT_BW = 4
(Register 0x52h in Bank 0)
For ODR of 1kHz, set Accel to Low Noise mode (Register 0x4Eh in Bank 0) ACCEL_MODE = 1
Set filter settings as follows: ACCEL_UI_FILT_ORD = 2 (Register 0x53h in Bank 0); ACCEL_UI_FILT_BW =
0 (Register 0x52h in Bank 0)
3. Wait 1 millisecond
Initialize APEX hardware
1. Set TAP_TMAX to 2 (Register 0x47h in Bank 4)
2. Set TAP_TMIN to 3 (Register 0x47h in Bank 4)
3. Set TAP_TAVG to 3 (Register 0x47h in Bank 4)
4. Set TAP_MIN_JERK_THR to 17 (Register 0x46h in Bank 4)
5. Set TAP_MAX_PEAK_TOL to 2 (Register 0x46h in Bank 4)
@TDI( lnvenSense
ICM-42688-P
Page 46 of 109
Document Number: DS-000347
Revision: 1.2
6. Wait 1 millisecond
7. Enable TAP source for INT1 by setting bit 0 in register INT_SOURCE6 (Register 0x4Dh in Bank 4) to 1. Or if INT2 is
selected for TAP, enable TAP source by setting bit 0 in register INT_SOURCE7 (Register 0x4Eh in Bank 4) to 1.
8. Wait 50 milliseconds
9. Turn on TAP feature by setting TAP_ENABLE to 1 (Register 0x56h in Bank 0)
Output registers
1. Read interrupt register (Register 0x38h in Bank 0) for TAP_DET_INT
2. Read the tap count in TAP_NUM (Register 0x35h in Bank 0)
3. Read the tap axis in TAP_AXIS (Register 0x35h in Bank 0)
4. Read the polarity of tap pulse in TAP_DIR (Register 0x35h in Bank 0)
8.7 WAKE ON MOTION PROGRAMMING
Wake on Motion configuration parameters
1. WOM_X_TH (Register 0x4Ah in Bank 4)
2. WOM_Y_TH (Register 0x4Bh in Bank 4)
3. WOM_Z_TH (Register 0x4Ch in Bank 4)
4. WOM_INT_MODE (Register 0x57h in Bank 0)
5. WOM_MODE (Register 0x57h in Bank 0)
Initialize Sensor in a typical configuration
1. Set accelerometer ODR (Register 0x50h in Bank 0)
ACCEL_ODR = 9 for 50 Hz
2. Set Accel to Low Power mode (Register 0x4Eh in Bank 0)
ACCEL_MODE = 2 and (Register 0x4Dh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode
3. Wait 1 millisecond
Initialize APEX hardware
1. Set WOM_X_TH to 98 (Register 0x4Ah in Bank 4)
2. Set WOM_Y_TH to 98 (Register 0x4Bh in Bank 4)
3. Set WOM_Z_TH to 98 (Register 0x4Ch in Bank 4)
4. Wait 1 millisecond
5. Enable all 3 axes as WOM sources for INT1 by setting bits 2:0 in register INT_SOURCE1 (Register 0x66h in Bank 0)
to 1. Or if INT2 is selected for WOM, enable all 3 axes as WOM sources by setting bits 2:0 in register INT_SOURCE4
(Register 0x69h in Bank 0) to 1.
6. Wait 50 milliseconds
7. Turn on WOM feature by setting WOM_INT_MODE to 0, WOM_MODE to 1, SMD_MODE to 1 (Register 0x56h in
Bank 0)
Output registers
1. Read interrupt register (Register 0x7Dh in Bank 0) for WOM_X_INT
2. Read interrupt register (Register 0x7Dh in Bank 0) for WOM_Y_INT
3. Read interrupt register (Register 0x7Dh in Bank 0) for WOM_Z_INT
8.8 SIGNIFICANT MOTION DETECTION PROGRAMMING
Significant Motion Detection configuration parameters
1. WOM_X_TH (Register 0x4Ah in Bank 4)
2. WOM_Y_TH (Register 0x4Bh in Bank 4)
3. WOM_Z_TH (Register 0x4Ch in Bank 4)
4. WOM_INT_MODE (Register 0x57h in Bank 0)
5. WOM_MODE (Register 0x57h in Bank 0)
6. SMD_MODE (Register 0x57h in Bank 0)
Initialize Sensor in a typical configuration
@TDI( lnvenSense
ICM-42688-P
Page 47 of 109
Document Number: DS-000347
Revision: 1.2
1. Set accelerometer ODR (Register 0x50h in Bank 0)
ACCEL_ODR = 9 for 50 Hz
2. Set Accel to Low Power mode (Register 0x4Eh in Bank 0)
ACCEL_MODE = 2 and (Register 0x4Dh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode
3. Wait 1 millisecond
Initialize APEX hardware
1. Set WOM_X_TH to 98 (Register 0x4Ah in Bank 4)
2. Set WOM_Y_TH to 98 (Register 0x4Bh in Bank 4)
3. Set WOM_Z_TH to 98 (Register 0x4Ch in Bank 4)
4. Wait 1 millisecond
5. Enable SMD source for INT1 by setting bit 3 in register INT_SOURCE1 (Register 0x66h in Bank 0) to 1. Or if INT2 is
selected for SMD, enable SMD source by setting bit 3 in register INT_SOURCE4 (Register 0x69h in Bank 0) to 1.
6. Wait 50 milliseconds
7. Turn on SMD feature by setting WOM_INT_MODE to 0, WOM_MODE to 1, SMD_MODE to 3 (Register 0x56h in
Bank 0)
Output registers
1. Read interrupt register (Register 0x7Dh in Bank 0) for SMD_INT
@TDI( lnvenSense
ICM-42688-P
Page 48 of 109
Document Number: DS-000347
Revision: 1.2
9 DIGITAL INTERFACE
9.1 I3CSM, I2C AND SPI SERIAL INTERFACES
The internal registers and memory of the ICM-42688-P can be accessed using I3CSM at 12.5MHz (data rates up to 12.5Mbps in SDR
mode, 25Mbps in DDR mode), I2C at 1 MHz or SPI at 24 MHz. SPI operates in 3-wire or 4-wire mode. Pin assignments for serial
interfaces are described in Section 4.1.
9.2 I3CSM INTERFACE
I3CSM is a new 2-wire digital interface comprised of the signals serial data (SDA) and serial clock (SCLK). I3CSM is intended to improve
upon the I2C interface, while preserving backward compatibility.
I3CSM carries the advantages of I²C in simplicity, low pin count, easy board design, and multi-drop (vs. point to point), but provides
the higher data rates, simpler pads, and lower power of SPI. I3CSM adds higher throughput for a given frequency, in-band interrupts
(from slave to master), dynamic addressing.
ICM-42688-P supports the following features of I3CSM:
SDR data rate up to 12.5Mbps
DDR data rate up to 25Mbps
Dynamic address allocation
In-band Interrupt (IBI) support
Support for synchronous timing control
Support for asynchronous timing control mode 0
Error detection (CRC and/or Parity)
Common Command Code (CCC)
The ICM-42688-P always operates as an I3CSM slave device when communicating to the system processor, which thus acts as the
I3CSM master. I3CSM master controls an active pullup resistance on SDA, which it can enable and disable. The pullup resistance may
be a board level resistor controlled by a pin, or it may be internal to the I3CSM master.
9.3 I2C INTERFACE
I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are open-drain and bi-
directional. In a generalized I2C interface implementation, attached devices can be a master or a slave. The master device puts the
slave address on the bus, and the slave device with the matching address acknowledges the master.
The ICM-42688-P always operates as a slave device when communicating to the system processor, which thus acts as the master.
SDA and SCL lines typically need pull-up resistors to VDDIO. The maximum bus speed is 1 MHz.
The slave address of the ICM-42688-P is b110100X, which is 7 bits long. The LSB bit of the 7-bit address is determined by the logic
level on pin AP_AD0. This allows two ICM-42688-Ps to be connected to the same I2C bus. When used in this configuration, the
address of one of the devices should be b1101000 (pin AP_AD0 is logic low) and the address of the other should be b1101001 (pin
AP_AD0 is logic high).
9.4 I2C COMMUNICATIONS PROTOCOL
START (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined as a HIGH-to-LOW
transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy until the master puts a STOP
condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH (see figure below).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
@TDI( lnvenSense r—1 __'\I_C: [I _ W] ‘l _ x i: , ;i\ \_/\_ _____ J\_/\_
ICM-42688-P
Page 49 of 109
Document Number: DS-000347
Revision: 1.2
SDA
SCL S
START condition STOP condition
P
Figure 11. START and STOP Conditions
Data Format / Acknowledge
I2C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per data transfer. Each byte
transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge signal is generated by the master,
while the receiver generates the actual acknowledge signal by pulling down SDA and holding it low during the HIGH portion of the
acknowledge clock pulse.
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it can hold SCL
LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready, and releases the clock line
(refer to the following figure).
DATA OUTPUT BY
TRANSMITTER (SDA)
DATA OUTPUT BY
RECEIVER (SDA)
SCL FROM
MASTER
START
condition
clock pulse for
acknowledgement
acknowledge
not acknowledge
1 2 8 9
Figure 12. Acknowledge on the I2C Bus
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by an 8th bit, the
read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to the slave device. Then, the
master releases the SDA line and waits for the acknowledge signal (ACK) from the slave device. Each byte transferred must be
followed by an acknowledge bit. To acknowledge, the slave device pulls the SDA line LOW and keeps it LOW for the high period of
the SCL line. Data transmission is always terminated by the master with a STOP condition (P), thus freeing the communications line.
However, the master can generate a repeated START condition (Sr), and address another slave without first generating a STOP
condition (P). A LOW to HIGH transition on the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take
place when SCL is low, with the exception of start and stop conditions.
ICM-42688-P
Page 50 of 109
Document Number: DS-000347
Revision: 1.2
SDA
START
condition
SCL
ADDRESS R/W ACK DATA ACK DATA ACK STOP
condition
S P
1 7 8 9 1 7 8 9 1 7 8 9
Figure 13. Complete I2C Data Transfer
To write the internal ICM-42688-P registers, the master transmits the start condition (S), followed by the I2C address and the write
bit (0). At the 9th clock cycle (when the clock is high), the ICM-42688-P acknowledges the transfer. Then the master puts the register
address (RA) on the bus. After the ICM-42688-P acknowledges the reception of the register address, the master puts the register
data onto the bus. This is followed by the ACK signal, and data transfer may be concluded by the stop condition (P). To write multiple
bytes after the last ACK signal, the master can continue outputting data rather than transmitting a stop signal. In this case, the ICM-
42688-P automatically increments the register address and loads the data to the appropriate register. The following figures show
single and two-byte write sequences.
Single-Byte Write Sequence
Burst Write Sequence
To read the internal ICM-42688-P registers, the master sends a start condition, followed by the I2C address and a write bit, and then
the register address that is going to be read. Upon receiving the ACK signal from the ICM-42688-P, the master transmits a start signal
followed by the slave address and read bit. As a result, the ICM-42688-P sends an ACK signal and the data. The communication ends
with a not acknowledge (NACK) signal and a stop bit from master. The NACK condition is defined such that the SDA line remains high
at the 9th clock cycle. The following figures show single and two-byte read sequences.
Single-Byte Read Sequence
Burst Read Sequence
9.5 I2C TERMS
Signal
Description
S
Start Condition: SDA goes from high to low while SCL is high
AD
Slave I2C address
Master
S
AD+W
RA
DATA
P
Slave
ACK
ACK
ACK
Master
S
AD+W
RA
DATA
DATA
P
Slave
ACK
ACK
ACK
ACK
Master
S
AD+W
RA
S
AD+R
NACK
P
Slave
ACK
ACK
ACK
DATA
Master
S
AD+W
RA
S
AD+R
ACK
NACK
P
Slave
ACK
ACK
ACK
DATA
DATA
@TDI( lnvenSense
ICM-42688-P
Page 51 of 109
Document Number: DS-000347
Revision: 1.2
W
Write bit (0)
R
Read bit (1)
ACK
Acknowledge: SDA line is low while the SCL line is high at the 9th clock
cycle
NACK
Not-Acknowledge: SDA line stays high at the 9th clock cycle
RA
ICM-42688-P internal register address
DATA
Transmit or received data
P
Stop condition: SDA going from low to high while SCL is high
Table 12. I2C Terms
@TDI( lnvenSense
ICM-42688-P
Page 52 of 109
Document Number: DS-000347
Revision: 1.2
9.6 SPI INTERFACE
The ICM-42688-P supports 3-wire or 4-wire SPI for the host interface. The ICM-42688-P always operates as a Slave device during
standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SCLK), the Serial Data Output (SDO), the Serial Data Input (SDI), and the Serial
Data IO (SDIO) are shared among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line from the master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is active at a time, ensuring
that only one slave is selected at any given time. The CS lines of the non-selected slave devices are held high, causing their SDO lines
to remain in a high-impedance (high-z) state so that they do not interfere with any active devices.
SPI Operational Features
1. Data is delivered MSB first and LSB last
2. Data is latched on the rising edge of SCLK
3. Data should be transitioned on the falling edge of SCLK
4. The maximum frequency of SCLK is 24 MHz
5. SPI read operations are completed in 16 or more clock cycles (two or more bytes). The first byte contains the SPI Address,
and the following byte(s) contain(s) the SPI data. The first bit of the first byte contains the Read/Write bit and indicates
the Read (1) operation. The following 7 bits contain the Register Address. In cases of multiple-byte Reads, data is two or
more bytes:
SPI Address format
MSB
LSB
R/W
A6
A5
A4
A3
A2
A1
A0
SPI Data format
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
6. SPI write operations are completed in 16 clock cycles (two bytes). The first byte contains the SPI Address, and the second
byte contains the SPI data. The first bit of the first byte contains the Read/Write bit and indicates the Write (0) operation.
The following 7 bits contain the Register Address.
7. Supports Single or Burst Reads and Single Writes.
SPI Master SPI Slave 1
SPI Slave 2
CS1
CS2
SCLK
SDIO
nCS
SCLK
SDIO
nCS
Figure 14. Typical SPI Master/Slave Configuration
@TDI( lnvenSense (A. 1?
ICM-42688-P
Page 53 of 109
Document Number: DS-000347
Revision: 1.2
10 ASSEMBLY
This section provides general guidelines for assembling InvenSense Micro Electro-Mechanical Systems (MEMS) devices packaged in
LGA package.
10.1 ORIENTATION OF AXES
The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1 identifier () in the
figure.
+Z
+X
+Y
+Z
+Y
+X