PIC16(L)F720/721 Datasheet by Microchip Technology

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6‘ MICROCHIP
2010-2015 Microchip Technology Inc. DS40001430F-page 1
PIC16(L)F720/721
Devices Included In This Data Sheet:
High-Performance RISC CPU:
Only 35 Instructions to Learn:
- All single-cycle instructions except branches
Operating Speed:
- DC – 16 MHz oscillator/clock input
- DC – 250 ns instruction cycle
Up to 4K x 14 Words of Flash Program Memory
Up to 256 bytes of Data Memory (RAM)
Interrupt Capability
8-Level Deep Hardware Stack
Direct, Indirect and Relative Addressing modes
Processor Self-Write/Read access to Program
Memory
Memory
High-Endurance Flash Data Memory
- 128B of nonvolatile data storage
- 100K erase/write cycles
Special Microcontroller Features:
Precision Internal Oscillator:
- 16 MHz or 500 kHz operation
- Factory calibrated to ±1%, typical
- Software tunable
- Software selectable ÷1, ÷2, ÷4 or ÷8 divider
Power-Saving Sleep mode
Industrial and Extended Temperature Range
Power-on Reset (POR)
Power-up Timer (PWRT)
Brown-out Reset (BOR)
Multiplexed Master Clear with Pull-up/Input Pin
Programmable Code Protection
In-Circuit Serial ProgrammingTM (ICSPTM) via Two
Pins
Wide Operating Voltage Range:
- 1.8V to 5.5V (PIC16F720/721)
- 1.8V to 3.6V (PIC16LF720/721)
Extreme Low-Power (XLP) Features:
Sleep Current:
- 40 nA @ 1.8V, typical
Low-Power Watchdog Timer Current:
- 500 nA @ 1.8V, typical
Peripheral Features:
Up to 17 I/O Pins and One Input-only Pin:
- High-current source/sink for direct LED drive
- Interrupt-on-change pins
- Individually programmable weak pull-ups
A/D Converter:
- 8-bit resolution
- 12 channels
- Selectable Voltage reference
Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
Enhanced Timer1
- 16-bit timer/counter with prescaler
- External Gate Input mode with toggle and
Single Shot modes
- Interrupt-on-gate completion
Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
Capture, Compare, PWM module (CCP)
- 16-bit Capture, max resolution 12.5 ns
- 16-bit Compare, max resolution 250 ns
- 10-bit PWM, max frequency 15 kHz
Addressable Universal Synchronous
Asynchronous Receiver Transmitter (AUSART)
Synchronous Serial Port (SSP)
- SPI (Master/Slave)
-I
2C (Slave) with Address Mask
• PIC16F720 • PIC16LF720
• PIC16F721 • PIC16LF721
20-Pin Flash Microcontrollers
PIC16(L)F720/721
DS40001430F-page 2 2010-2015 Microchip Technology Inc.
PIC16(L)F72X Family Types
Device
Data Sheet Index
Program Memory
Flash (words)
Data SRAM
(bytes)
High-Endurance Flash
Memory (bytes)
I/O’s(2)
8-bit ADC (ch)
CapSense (ch)
Timers
(8/16-bit)
AUSART
SSP (I2C/SPI)
CCP
Debug(1)
XLP
PIC16(L)F707 (1) 8192 363 036 14 32 4/2 1 1 2 I Y
PIC16(L)F720 (2) 2048 128 128 18 12 — 2/1 1 1 1 I Y
PIC16(L)F721 (2) 4096 256 128 18 12 — 2/1 1 1 1 I Y
PIC16(L)F722 (4) 2048 128 025 11 82/1 1 1 2 I Y
PIC16(L)F722A (3) 2048 128 025 11 82/1 1 1 2 I Y
PIC16(L)F723 (4) 4096 192 025 11 82/1 1 1 2 I Y
PIC16(L)F723A (3) 4096 192 025 11 82/1 1 1 2 I Y
PIC16(L)F724 (4) 4096 192 036 14 16 2/1 1 1 2 I Y
PIC16(L)F726 (4) 8192 368 025 11 82/1 1 1 2 I Y
PIC16(L)F727 (4) 8192 368 036 14 16 2/1 1 1 2 I Y
Note 1: I - Debugging, Integrated on Chip; H - Debugging, Requires Debug Header.
2: One pin is input-only.
Data Sheet Index: (Unshaded devices are described in this document.)
1: DS41418 PIC16(L)F707 Data Sheet, 40/44-Pin Flash, 8-bit Microcontrollers
2: DS41430 PIC16(L)F720/721 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers
3: DS41417 PIC16(L)F722A/723A Data Sheet, 28-Pin Flash, 8-bit Microcontrollers
4: DS41341 PIC16(L)F72X Data Sheet, 28/40/44-Pin Flash, 8-bit Microcontrollers
Note: For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
1111111111 [[[EEEEEEE
2010-2015 Microchip Technology Inc. DS40001430F-page 3
PIC16(L)F720/721
PIN DIAGRAMS
FIGURE 1: 20-PIN DIAGRAM FOR PIC16(L)F720/721
Pin Diagrams 20-PIN DIAGRAM FOR PIC16(L)F720/721
PDIP, SOIC, SSOP
PIC16(L)F720/721
1
2
3
4
20
19
18
17
5
6
7
16
15
14
VDD
RA5/T1CKI/CLKIN
RA4/AN3/T1G/CLKOUT
RA3/MCLR/VPP
RC5/CCP1
RC4
RC3/AN7
VSS
RA0/AN0/ICSPDAT
RA1/AN1/ICSPCLK
RA2/AN2/T0CKI/INT
RC0/AN4
RC1/AN5
RC2/AN6
8
9
10
13
12
11
RC6/AN8/SS
RC7/AN9/SDO
RB7/TX/CK
RB4/AN10/SDI/SDA
RB5/AN11/RX/DT
RB6/SCK/SCL
2
3
6
1
1819
20
15
7
1617
5
4
PIC16(L)F720/721
VDD
RA5/T1CKI/CLKIN
RA4/AN3/T1G/CLKOUT
RA3/MCLR/VPP
RC5/CCP1
RC4
RC3/AN7
RC6/AN8/SS
RC7/AN9/SDO
RB7/TX/CK
VSS
RA0/AN0/ICSPDAT
RA1/AN1/ICSPCLK
RA2/AN2/T0CKI/INT
RC0/AN4
RC1/AN5
RC2/AN6
RB4/AN10/SDI/SDA
RB5/AN11/RX/DT
RB6/SCK/SCL
8910
11
12
13
14
QFN (4x4)
PIC16(L)F720/721
DS40001430F-page 4 2010-2015 Microchip Technology Inc.
TABLE 1: 20-PIN ALLOCATION TABLE (PIC16(L)F720/721)
I/O
20-Pin PDIP/SOIC/
SSOP
20-Pin QFN
A/D
Timers
CCP
AUSART
SSP
Interrupt
Pull-up
Basic
RA0 19 16 AN0 — — IOC YICSPDAT
RA1 18 15 AN1 IOC Y ICSPCLK
RA2 17 14 AN2 T0CKI INT/IOC — —
RA3 4 1 IOC Y MCLR/VPP
RA4 320 AN3 T1G — — IOC YCLKOUT
RA5 2 19 T1CKI IOC Y CLKIN
RB4 13 10 AN10 SDI/SDA IOC Y —
RB5 12 9 AN11 — RX/DT IOC Y
RB6 11 8 SCK/SCL IOC Y —
RB7 10 7 — TX/CK IOC Y
RC0 16 13 AN4 — — — —
RC1 15 12 AN5
RC2 14 11 AN6 — — — —
RC3 7 4 AN7
RC4 6 3 — —
RC5 5 2 CCP1 —
RC6 8 5 AN8 — — SS — —
RC7 9 6 AN9 SDO
VDD 118 — — — — VDD
Vss 20 17 — — — VSS
2010-2015 Microchip Technology Inc. DS40001430F-page 5
PIC16(L)F720/721
Table of Contents
Device Overview ................................................................................................................................................................................... 7
Memory Organization .......................................................................................................................................................................... 11
Resets ................................................................................................................................................................................................. 24
Interrupts............................................................................................................................................................................................. 34
Low Dropout (LDO) Voltage Regulator ............................................................................................................................................... 41
I/O Ports .............................................................................................................................................................................................. 42
Oscillator Module ................................................................................................................................................................................ 62
Device Configuration ........................................................................................................................................................................... 67
Analog-to-Digital Converter (ADC) Module ......................................................................................................................................... 71
Fixed Voltage Reference .................................................................................................................................................................... 80
Temperature Indicator Module ............................................................................................................................................................ 82
Timer0 Module .................................................................................................................................................................................... 83
Timer1 Module with Gate Control ....................................................................................................................................................... 86
Timer2 Module .................................................................................................................................................................................... 98
Capture/Compare/PWM (CCP) Module ............................................................................................................................................ 100
Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) .................................................................... 109
SSP Module Overview ...................................................................................................................................................................... 129
Flash Program Memory Self-Read/Self-Write Control ...................................................................................................................... 151
Power-Down Mode (Sleep) ............................................................................................................................................................... 158
In-Circuit Serial Programming™ (ICSP™) ........................................................................................................................................ 160
Instruction Set Summary ................................................................................................................................................................... 161
Development Support ....................................................................................................................................................................... 170
Electrical Specifications .................................................................................................................................................................... 174
DC and AC Characteristics Graphs and Charts ................................................................................................................................ 200
Packaging Information ...................................................................................................................................................................... 220
Appendix A: Data Sheet Revision History ......................................................................................................................................... 230
Appendix B: Migrating From Other PIC® Devices ............................................................................................................................ 230
The Microchip Website ..................................................................................................................................................................... 231
Customer Change Notification Service ............................................................................................................................................. 231
Customer Support ............................................................................................................................................................................. 231
Product Identification System ........................................................................................................................................................... 232
PIC16(L)F720/721
DS40001430F-page 6 2010-2015 Microchip Technology Inc.
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2010-2015 Microchip Technology Inc. DS40001430F-page 7
PIC16(L)F720/721
1.0 DEVICE OVERVIEW
The PIC16(L)F720/721 devices are covered by this
data sheet. They are available in 20-pin packages.
Please refer to Section 25.0 “Packaging
Information” for further package information.
Figure 1-1 shows a block diagram of the
PIC16(L)F720/721 devices. Table 1-1 shows the pinout
descriptions.
PIC16(L)F720/721
DS40001430F-page 8 2010-2015 Microchip Technology Inc.
FIGURE 1-1: 20-PIN DEVICE BLOCK DIAGRAM FOR PIC16(L)F720/721
Flash
Program
Memory
8K x 14
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
368 x 8
Direct Addr 7
RAM Addr 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
CLKIN
CLKOUT
MCLR VDD
PORTA
PORTB
PORTC
RA4
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
8
8
Brown-out
Reset
AUSART
Timer0 Timer1 Timer2
RA3
RA1
RA0
8
3
Analog-To-Digital Converter
RB6
RB7
VSS
T0CKI T1G T1CKI
Synchronous
SDA SCL SSSDO
Serial Port
SDI
/
SCK/
TX/CKRX/DT
Internal
Oscillator
Block
Configuration
Flash
Program
Memory
8K x 14
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
368 x 8
Direct Addr 7
RAM Addr 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
MCLR VDD
PORTB
PORTC
RC1
8
8
Brown-out
Reset
AUSART
Timer0 Timer1 Timer2
8
3
VSS
T0CKI T1CKI
Synchronous
SDA SCL SSSDO
Serial Port
SCK/
Configuration
Flash
Program
Memory
(1)
13 Data Bus 8
14
Program
Bus
Instruction Reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
(1)
Direct Addr 7
RAM Addr 9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode &
Control
Timing
Generation
MCLR VDD
PORTB
PORTC
RA5
8
8
Timer0 Timer1 Timer2
RA2
8
3
RB4
RB5
VSS
T0CKI T1CKI
Synchronous
SDA SCL SSSDO
Serial Port
SCK/
Configuration
CCP1
CCP1
AN9
AN0 AN1 AN2 AN3 AN4 AN8 AN10 AN11
LDO
Regulator
AUSART
ICSPCLK
ICSPDAT
ICSP™
AN6AN5 AN7
PMDATL
PMADRL
Self read/
write Flash
memory
Note: PIC16(L)F720 – 2k x 14 Flash, 128 x 8 RAM
PIC16(L)F721 – 4k x 14 Flash, 256 x 8 RAM.
2010-2015 Microchip Technology Inc. DS40001430F-page 9
PIC16(L)F720/721
TABLE 1-1: PINOUT DESCRIPTION
Name Function IN OUT Description
RA0/AN0/ICSPDAT RA0 TTL CMOS General purpose I/O. Individually controlled
interrupt-on-change. Individually enabled pull-up.
AN0 AN A/D Channel 0 Input.
ICSPDAT ST CMOS ICSP™ Data I/O.
RA1/AN1/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled
interrupt-on-change. Individually enabled pull-up.
AN1 AN A/D Channel 1 Input.
ICSPCLK ST ICSP™ Clock.
RA2/AN2/T0CKI/INT RA2 TTL CMOS General purpose I/O with IOC and WPU.
AN2 AN A/D Channel 2 Input.
T0CKI ST Timer0 Clock Input.
INT ST External interrupt.
RA3/MCLR/VPP RA3 TTL General purpose input-only with IOC and WPU.
MCLR ST Master Clear with internal pull-up.
VPP HV Programming Voltage.
RA4/AN3/T1G/CLKOUT RA4 TTL CMOS General purpose I/O with IOC and WPU.
AN3 AN A/D Channel 3 Input.
T1G ST Timer1 Gate Input.
CLKOUT CMOS FOSC/4 output.
RA5/T1CKI/CLKIN RA5 TTL CMOS General purpose I/O with IOC and WPU.
T1CKI ST Timer1 Clock input.
CLKIN ST External Clock Input (EC mode).
RB4/AN10/SDI/SDA RB4 TTL CMOS General purpose I/O with IOC and WPU.
AN10 AN A/D Channel 10 Input.
SDI ST SPI Data Input.
SDA I2CODI
2C Data.
RB5/AN11/RX/DT RB5 TTL CMOS General purpose I/O with IOC and WPU.
AN11 AN A/D Channel 11 Input.
RX ST USART asynchronous input.
DT ST CMOS USART synchronous data.
RB6/SCK/SCL RB6 TTL CMOS General purpose I/O with IOC and WPU.
SCK ST CMOS SPI Clock.
SCL I2CODI
2C Clock.
RB7/TX/CK RB7 TTL CMOS General purpose I/O with IOC and WPU.
TX CMOS USART asynchronous transmit.
CK ST CMOS USART synchronous clock.
RC0/AN4 RC0 ST CMOS General purpose I/O.
AN4 AN A/D Channel 4 Input.
RC1/AN5 RC1 ST CMOS General purpose I/O.
AN5 AN A/D Channel 5 Input.
RC2/AN6 RC2 ST CMOS General purpose I/O.
AN6 AN A/D Channel 6 Input.
RC3/AN7 RC3 ST CMOS General purpose I/O.
AN7 AN A/D Channel 7 Input.
Legend: AN = Analog input or output, CMOS = CMOS compatible input or output, OD = Open Drain, TTL = TTL compatible
input, ST = Schmitt Trigger input with CMOS levels, I2C = Schmitt Trigger input with I2C, HV = High Voltage,
XTAL = Crystal levels
PIC16(L)F720/721
DS40001430F-page 10 2010-2015 Microchip Technology Inc.
RC4 RC4 ST CMOS General purpose I/O.
RC5/CCP1 RC5 ST CMOS General purpose I/O.
CCP1 ST CMOS Capture/Compare/PWM 1.
RC6/AN8/SS RC6 ST CMOS General purpose I/O.
AN8 AN A/D Channel 8 Input.
SS ST Slave Select input.
RC7/AN9/SDO RC7 ST CMOS General purpose I/O.
AN9 AN A/D Channel 9 Input.
SDO CMOS SPI Data Output.
VDD VDD Power Positive supply.
Vss Vss Power Ground supply.
TABLE 1-1: PINOUT DESCRIPTION (CONTINUED)
Name Function IN OUT Description
Legend: AN = Analog input or output, CMOS = CMOS compatible input or output, OD = Open Drain, TTL = TTL compatible
input, ST = Schmitt Trigger input with CMOS levels, I2C = Schmitt Trigger input with I2C, HV = High Voltage,
XTAL = Crystal levels
2010-2015 Microchip Technology Inc. DS40001430F-page 11
PIC16(L)F720/721
2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
The PIC16(L)F720/721 has a 13-bit program counter
capable of addressing a 8K x 14 program memory
space. Table 2-1 shows the memory sizes
implemented. Accessing a location above these
boundaries will cause a wrap-around within the
implemented memory space. The Reset vector is at
0000h and the interrupt vector is at 0004h.
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16(L)F720
FIGURE 2-2: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16(L)F721
TABLE 2-1: DEVICE SIZE AND ADDRESSES
Device Program Memory Size
(Words) Last Program Memory
Address High-Endurance Flash
Memory Address Range (1)
PIC16F720
PIC16LF720 2048 07FFh 0780h-07FFh
PIC16F721
PIC16LF721 4096 0FFFh 0F80h-0FFFh
Note 1: High-Endurance Flash applies to the low byte of each address in the
range.
PC<12:0>
13
0000h
0004H
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
CALL, RETURN
RETFIE, RETLW
Stack Level 2
0005h
On-chip
Program
Memory Page 0 07FFh
Wraps to Page 0
Wraps to Page 0
Wraps to Page 0
0800h
0FFFh
1000h
17FFh
1800h
1FFFh
PC<12:0>
13
0000h
0004H
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
CALL, RETURN
RETFIE, RETLW
Stack Level 2
0005h
On-chip
Program
Memory
Page 0
Page 1
07FFh
0800h
0FFFh
Wraps to Page 0
Wraps to Page 1
1000h
17FFh
1800h
1FFFh
PIC16(L)F720/721
DS40001430F-page 12 2010-2015 Microchip Technology Inc.
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPRs)
and the Special Function Registers (SFRs). Bits RP0
and RP1 are bank select bits.
RP1 RP0
00Bank 0 is selected
01Bank 1 is selected
10Bank 2 is selected
11Bank 3 is selected
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function
Registers are the General Purpose Registers,
implemented as static RAM. All implemented banks
contain Special Function Registers. Some frequently
used Special Function Registers from one bank are
mirrored in another bank for code reduction and
quicker access.
2.2.1 GENERAL PURPOSE REGISTER
FILE
The register file is organized as 128 x 8 bits in the
PIC16(L)F720, 256 x 8 bits in the PIC16(L)F721. Each
register is accessed either directly or indirectly through
the File Select Register (FSR), (Refer to Section 2.5
“Indirect Addressing, INDF and FSR Registers”).
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (refer to Table 2-2).
These registers are static RAM.
The Special Function Registers can be classified into
two sets: core and peripheral. The Special Function
Registers associated with the “core” are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.
2010-2015 Microchip Technology Inc. DS40001430F-page 13
PIC16(L)F720/721
FIGURE 2-3: PIC16(L)F720 SPECIAL FUNCTION REGISTERS
File Address
INDF(*) 00h INDF(*) 80h INDF(*) 100h INDF(*) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h 105h ANSELA 185h
PORTB 06h TRISB 86h 106h ANSELB 186h
PORTC 07h TRISC 87h 107h ANSELC 187h
08h 88h 108h 188h
09h 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch PMDATL 10Ch PMCON1 18Ch
0Dh 8Dh PMADRL 10Dh PMCON2 18Dh
TMR1L 0Eh PCON 8Eh PMDATH 10Eh 18Eh
TMR1H 0Fh T1GCON 8Fh PMADRH 10Fh 18Fh
T1CON 10h OSCCON 90h 110h 190h
TMR2 11h OSCTUNE 91h 111h 191h
T2CON 12h PR2 92h 112h 192h
SSPBUF 13h SSPADD/SSPMSK 93h 113h 193h
SSPCON 14h SSPSTAT 94h 114h 194h
CCPR1L 15h WPUA 95h WPUB 115h 195h
CCPR1H 16h IOCA 96h IOCB 116h 196h
CCP1CON 17h 97h 117h 197h
RCSTA 18h TXSTA 98h 118h 198h
TXREG 19h SPBRG 99h 119h 199h
RCREG 1Ah 9Ah 11Ah 19Ah
1Bh 9Bh 11Bh 19Bh
1Ch 9Ch 11Ch 19Ch
1Dh FVRCON 9Dh 11Dh 19Dh
ADRES 1Eh 9Eh 11Eh 19Eh
ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh
General
Purpose
Register
80 Bytes
20h
General
Purpose
Register
32 Bytes
A0h
BFh
120h 1A0h
C0h
06Fh EFh 16Fh 1EFh
Access RAM
070h
Accesses
70h – 7Fh
F0h
Accesses
70h – 7Fh
170h
Accesses
70h – 7Fh
1F0h
7Fh FFh 17Fh 1FFh
BANK 0 BANK 1 BANK 2 BANK 3
Legend: = Unimplemented data memory locations, read as ‘0’.
* = Not a physical register.
PIC16(L)F720/721
DS40001430F-page 14 2010-2015 Microchip Technology Inc.
FIGURE 2-4: PIC16(L)F721 SPECIAL FUNCTION REGISTERS
Legend: = Unimplemented data memory locations, read as ‘0’.
* = Not a physical register.
File Address
INDF(*) 00h INDF(*) 80h INDF(*) 100h INDF(*) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h 105h ANSELA 185h
PORTB 06h TRISB 86h 106h ANSELB 186h
PORTC 07h TRISC 87h 107h ANSELC 187h
08h 88h 108h 188h
09h 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch PMDATL 10Ch PMCON1 18Ch
0Dh 8Dh PMADRL 10Dh PMCON2 18Dh
TMR1L 0Eh PCON 8Eh PMDATH 10Eh 18Eh
TMR1H 0Fh T1GCON 8Fh PMADRH 10Fh 18Fh
T1CON 10h OSCCON 90h 110h 190h
TMR2 11h OSCTUNE 91h 111h 191h
T2CON 12h PR2 92h 112h 192h
SSPBUF 13h SSPADD/SSPMSK 93h 113h 193h
SSPCON 14h SSPSTAT 94h 114h 194h
CCPR1L 15h WPUA 95h WPUB 115h 195h
CCPR1H 16h IOCA 96h IOCB 116h 196h
CCP1CON 17h 97h 117h 197h
RCSTA 18h TXSTA 98h 118h 198h
TXREG 19h SPBRG 99h 119h 199h
RCREG 1Ah 9Ah 11Ah 19Ah
1Bh 9Bh 11Bh 19Bh
1Ch 9Ch 11Ch 19Ch
1Dh FVRCON 9Dh 11Dh 19Dh
ADRES 1Eh 9Eh 11Eh 19Eh
ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh
General
Purpose
Register
80 Bytes
20h
06Fh
070h
7Fh
General
Purpose
Register
80 Bytes
A0h
EFh
General
Purpose
Register
80 Bytes
120h
16Fh
1A0h
1EFh
Access RAM Accesses
70h – 7Fh
F0h
FFh
Accesses
70h – 7Fh
170h
17Fh
Accesses
70h – 7Fh
1F0h
1FFh
BANK 0 BANK 1 BANK 2 BANK 3
2010-2015 Microchip Technology Inc. DS40001430F-page 15
PIC16(L)F720/721
TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on all
other
Resets
Bank 0
00h(2)INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
01h TMR0 Timer0 module Register xxxx xxxx uuuu uuuu
02h(2)PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
03h(2)STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
04h(2)FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
05h PORTA RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx
06h PORTB RB7 RB6 RB5 RB4 — — — xxxx ---- uuuu ----
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
08h Unimplemented — —
09h Unimplemented — —
0Ah(1),( 2)PCLATH — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh(2)INTCON GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 0000 000x 0000 000x
0Ch PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh Unimplemented — —
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 —T1SYNC—TMR1ON0000 -0-0 uuuu -u-u
11h TMR2 Timer2 module Register 0000 0000 0000 0000
12h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register Low Byte xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register High Byte xxxx xxxx uuuu uuuu
17h CCP1CON DC1 B1 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG AUSART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG AUSART Receive Data Register 0000 0000 0000 0000
1Bh Unimplemented — —
1Ch Unimplemented — —
1Dh Unimplemented — —
1Eh ADRES ADC Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 CHS3 CHS2 CHS1 CHS0 GO/
DONE ADON --00 0000 --00 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the
upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Accessible only when SSPM<3:0> = 1001.
4: This bit is unimplemented and reads as ‘1’.
5: See Register 6-2.
PIC16(L)F720/721
DS40001430F-page 16 2010-2015 Microchip Technology Inc.
Bank 1
80h(2)INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
81h OPTION_
REG RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h(2)PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
83h(2)STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
84h(2)FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
85h(5) TRISA TRISA5 TRISA4 (4) TRISA2 TRISA1 TRISA0 --11 -111 --11 -111
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — 1111 ---- 1111 ----
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
88h Unimplemented — —
89h Unimplemented — —
8Ah(1),( 2)PCLATH — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh(2)INTCON GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 0000 000x 0000 000x
8Ch PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh Unimplemented — —
8Eh PCON — — — — —PORBOR ---- --qq ---- --uu
8Fh T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
DONE T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu
90h OSCCON IRCF1 IRCF0 ICSL ICSS --10 qq-- --10 qq--
91h OSCTUNE TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 --uu uuuu
92h PR2 Timer2 module Period Register 1111 1111 1111 1111
93h SSPADD ADD<7:0> 0000 0000 0000 0000
93h(3)SSPMSK MSK<7:0> 1111 1111 1111 1111
94h SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 0000 0000
95h WPUA WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111
96h IOCA IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000
97h Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
9Ah Unimplemented — —
9Bh Unimplemented — —
9Ch Unimplemented — —
9Dh FVRCON FVRRDY FVREN TSEN TSRNG ADFVR1 ADFVR0 q000 --00 q000 --00
9Eh Unimplemented — —
9Fh ADCON1 ADCS2 ADCS1 ADCS0 — — — -000 ---- -000 ----
TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on all
other
Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the
upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Accessible only when SSPM<3:0> = 1001.
4: This bit is unimplemented and reads as ‘1’.
5: See Register 6-2.
2010-2015 Microchip Technology Inc. DS40001430F-page 17
PIC16(L)F720/721
Bank 2
100h(2)INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
101h TMR0 Timer0 module Register xxxx xxxx uuuu uuuu
102h(2)PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
103h(2)STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
104h(2)FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
105h Unimplemented — —
106h Unimplemented — —
107h Unimplemented — —
108h Unimplemented — —
109h Unimplemented — —
10Ah(1),( 2)PCLATH — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
10Bh(2)INTCON GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 0000 000x 0000 000x
10Ch PMDATL Program Memory Read Data Register Low Byte xxxx xxxx xxxx xxxx
10Dh PMADRL Program Memory Read Address Register Low Byte 0000 0000 0000 0000
10Eh PMDATH Program Memory Read Data Register High Byte --xx xxxx --xx xxxx
10Fh PMADRH — — Program Memory Read Address Register High Byte ---0 0000 ---0 0000
110h Unimplemented — —
111h Unimplemented — —
112h Unimplemented — —
113h Unimplemented — —
114h Unimplemented — —
115h WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — 1111 ---- 1111 ----
116h IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — 0000 ---- 0000 ----
117h Unimplemented — —
118h Unimplemented — —
119h Unimplemented — —
11Ah Unimplemented — —
11Bh Unimplemented — —
11Ch Unimplemented — —
11Dh Unimplemented — —
11Eh Unimplemented — —
11Fh Unimplemented — —
TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on all
other
Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the
upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Accessible only when SSPM<3:0> = 1001.
4: This bit is unimplemented and reads as ‘1’.
5: See Register 6-2.
PIC16(L)F720/721
DS40001430F-page 18 2010-2015 Microchip Technology Inc.
Bank 3
180h(2)INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
181h OPTION_
REG RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
182h(2)PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
183h(2)STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
184h(2)FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
185h ANSELA — — —ANSA4 ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111
186h ANSELB ANSB5 ANSB4 — — — --11 ---- --11 ----
187h ANSELC ANSC7 ANSC6 ANSC3 ANSC2 ANSC1 ANSC0 11-- 1111 11-- 1111
188h Unimplemented — —
18Ah(1),( 2)PCLATH — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
18Bh(2)INTCON GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 0000 000x 0000 000x
18Ch PMCON1 (4) CFGS LWLO FREE —WRENWRRD1000 -000 1000 -000
18Dh PMCON2 Program Memory Control Register 2 (not a physical register) ---- ---- ---- ----
190h Unimplemented — —
191h Unimplemented — —
192h Unimplemented — —
193h Unimplemented — —
194h Unimplemented — —
195h Unimplemented — —
196h Unimplemented — —
197h Unimplemented — —
198h Unimplemented — —
199h Unimplemented — —
19Ah Unimplemented — —
19Bh Unimplemented — —
19Ch Unimplemented — —
19Dh Unimplemented — —
19Eh Unimplemented — —
19Fh Unimplemented — —
TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on all
other
Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the
upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Accessible only when SSPM<3:0> = 1001.
4: This bit is unimplemented and reads as ‘1’.
5: See Register 6-2.
2010-2015 Microchip Technology Inc. DS40001430F-page 19
PIC16(L)F720/721
2.2.2.1 STATUS Register
The STATUS register, shown in Register 2-1, contains:
the arithmetic status of the ALU
the Reset status
the bank select bits for data memory (SRAM)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 21.0
“Instruction Set Summary”).
Note 1: The C and DC bits operate as Borrow
and Digit Borrow out bits, respectively, in
subtraction.
REGISTER 2-1: STATUS: STATUS REGISTER
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDC
(1) C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)
1 = A carry out from the 4th low-order bit of the result occurred
0 = No carry out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry out from the Most Significant bit of the result occurred
0 = No carry out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate instructions (RRF, RLF), this bit is loaded with either the high-order or low-order
bit of the source register.
PIC16(L)F720/721
DS40001430F-page 20 2010-2015 Microchip Technology Inc.
2.2.2.2 OPTION_REG Register
The OPTION_REG register, shown in Register 2-2, is
a readable and writable register, which contains
various control bits to configure:
Software programmable prescaler for the Timer0/
WDT
External RA2/INT interrupt
•Timer0
Weak pull-ups on PORTA or PORTB
Note: To achieve a 1:1 prescaler assignment for
Timer0, assign the prescaler to the WDT
by setting the PSA bit of the
OPTION_REG register to ‘1’. Refer to
Section 12.1.3 “Software
Programmable Prescaler”.
REGISTER 2-2: OPTION_REG: OPTION REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RABPU: PORTA or PORTB Pull-up Enable bit
1 = PORTA or PORTB pull-ups are disabled
0 = PORTA or PORTB pull-ups are enabled by individual bits in the WPUA or WPUB register,
respectively
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value Timer0 Rate WDT Rate
2010-2015 Microchip Technology Inc. DS40001430F-page 21
PIC16(L)F720/721
2.2.2.3 PCON Register
The Power Control (PCON) register contains flag bits
(refer to Table 3-4) to differentiate between a:
Power-on Reset (POR)
Brown-out Reset (BOR)
Watchdog Timer Reset (WDT)
External MCLR Reset
The PCON register also controls the software enable of
the BOR.
The PCON register bits are shown in Register 2-3.
REGISTER 2-3: PCON: POWER CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 R/W-q R/W-q
— — —PORBOR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
q = Value depends on condition
bit 7-2 Unimplemented: Read as ‘0
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)
PIC16(L)F720/721
DS40001430F-page 22 2010-2015 Microchip Technology Inc.
2.3 PCL and PCLATH
The Program Counter (PC) is 13 bits wide. The low
byte comes from the PCL register, which is a readable
and writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from
PCLATH. On any Reset, the PC is cleared. Figure 2-5
shows the two situations for the loading of the PC. The
upper example in Figure 2-5 shows how the PC is
loaded on a write to PCL (PCLATH<4:0> PCH).
The lower example in Figure 2-5 shows how the PC is
loaded during a CALL or GOTO instruction
(PCLATH<4:3> PCH).
FIGURE 2-5: LOADING OF PC IN
DIFFERENT SITUATIONS
2.3.1 COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When perform-
ing a table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block). Refer to the
Application Note AN556, “Implementing a Table Read”
(DS00556).
2.3.2 STACK
All devices have an 8-level x 13-bit wide hardware
stack (refer to Figures 2-1 and 2-2). The stack space is
not part of either program or data space and the Stack
Pointer is not readable or writable. The PC is PUSHed
onto the stack when a CALL instruction is executed or
an interrupt causes a branch. The stack is POPed in
the event of a RETURN, RETLW or a RETFIE instruction
execution. PCLATH is not affected by a PUSH or POP
operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
PUSH overwrites the value that was stored from the
first PUSH. The tenth PUSH overwrites the second
PUSH (and so on).
2.4 Program Memory Paging
All devices are capable of addressing a continuous 8K
word block of program memory. The CALL and GOTO
instructions provide only 11 bits of address to allow
branching within any 2K program memory page. When
doing a CALL or GOTO instruction, the upper two bits of
the address are provided by PCLATH<4:3>. When
doing a CALL or GOTO instruction, the user must ensure
that the page Select bits are programmed so that the
desired program memory page is addressed. If a return
from a CALL instruction (or interrupt) is executed, the
entire 13-bit PC is POPed off the stack. Therefore,
manipulation of the PCLATH<4:3> bits is not required
for the RETURN instructions (which POPs the address
from the stack).
Example 2-1 shows the calling of a subroutine in page
1 of the program memory. This example assumes that
PCLATH is saved and restored by the Interrupt Service
Routine (if interrupts are used).
EXAMPLE 2-1: CALL OF A SUBROUTINE
IN PAGE 1 FROM PAGE 0
PC
12 8 7 0
5PCLATH<4:0>
PCLATH
Instruction with
ALU Result
GOTO, CALL
Opcode<10:0>
8
PC
12 11 10 0
11
PCLATH<4:3>
PCH PCL
87
2
PCLATH
PCH PCL
PCL as
Destination
Note 1: There are no Status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interrupt address.
Note: The contents of the PCLATH register are
unchanged after a RETURN or RETFIE
instruction is executed. The user must
rewrite the contents of the PCLATH
register for any subsequent subroutine
calls or GOTO instructions.
ORG 500h
PAGESEL SUB_P1 ;Select page 1
;(800h-FFFh)
CALL SUB1_P1 ;Call subroutine in
: ;page 1 (800h-FFFh)
:
ORG 900h ;page 1 (800h-FFFh)
SUB1_P1
: ;called subroutine
;page 1 (800h-FFFh)
:
RETURN ;return to
;Call subroutine
;in page 0
;(000h-7FFh)
{E
2010-2015 Microchip Technology Inc. DS40001430F-page 23
PIC16(L)F720/721
2.5 Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR register and the IRP bit of
the STATUS register, as shown in Figure 2-6.
A simple program to clear the RAM location 020h-02Fh
using indirect addressing is shown in Example 2-2.
EXAMPLE 2-2: INDIRECT ADDRESSING
FIGURE 2-6: DIRECT/INDIRECT ADDRESSING
MOVLW 020h ;initialize pointer
MOVWF FSR ;to RAM
BANKISEL 020h
NEXT CLRF INDF ;clear INDF register
INCF FSR ;inc pointer
BTFSS FSR,4 ;all done?
GOTO NEXT ;no clear next
CONTINUE ;yes continue
Note: For memory map detail, refer to Figures 2-3 and 2-4.
Data
Memory
Indirect AddressingDirect Addressing
Bank Select Location Select
RP1 RP0 6 0
From Opcode IRP File Select Register
70
Bank Select Location Select
00 01 10 11 180h
1FFh
00h
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
H13
PIC16(L)F720/721
DS40001430F-page 24 2010-2015 Microchip Technology Inc.
3.0 RESETS
The PIC16(L)F720/721 differentiates between various
kinds of Reset:
a) Power-on Reset (POR)
b) WDT Reset during normal operation
c) WDT Reset during Sleep
d) MCLR Reset during normal operation
e) MCLR Reset during Sleep
f) Brown-out Reset (BOR)
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:
Power-on Reset (POR)
•MCLR
Reset
•MCLR
Reset during Sleep
•WDT Reset
Brown-out Reset (BOR)
Most registers are not affected by a WDT wake-up
since this is viewed as the resumption of normal
operation. TO and PD bits are set or cleared differently
in different Reset situations, as indicated in Table 3-5.
These bits are used in software to determine the nature
of the Reset.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 23.0 “Electrical
Specifications” for pulse-width specifications.
FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
MCLR/VPP
VDD
WDT
Module
POR
WDTOSC
WDT
Time-out
Power-on Reset
PWRT
Chip_Reset
11-bit Ripple Counter
Reset
Enable PWRT
Sleep
Brown-out(1)
Reset
BOREN
CLKIN
Note 1: Refer to the Configuration Word Register 1 (Register 8-1).
MCLRE
2010-2015 Microchip Technology Inc. DS40001430F-page 25
PIC16(L)F720/721
TABLE 3-1: STATUS BITS AND THEIR SIGNIFICANCE
POR BOR TO PD Condition
0x11Power-on Reset or LDO Reset
0x0xIllegal, TO is set on POR
0xx0Illegal, PD is set on POR
1011Brown-out Reset
1101WDT Reset
1100WDT Wake-up
11uuMCLR Reset during normal operation
1110MCLR Reset during Sleep or interrupt wake-up from Sleep
TABLE 3-2: RESET CONDITION FOR SPECIAL REGISTERS(2)
Condition Program
Counter STATUS
Register PCON
Register
Power-on Reset 0000h 0001 1xxx ---- --0x
MCLR Reset during normal operation 0000h 000u uuuu ---- --uu
MCLR Reset during Sleep 0000h 0001 0uuu ---- --uu
WDT Reset 0000h 0000 1uuu ---- --uu
WDT Wake-up PC + 1 uuu0 0uuu ---- --uu
Brown-out Reset 0000h 0001 1uuu ---- --u0
Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the return address is
pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
2: If a Status bit is not implemented, that bit will be read as ‘0’.
PIC16(L)F720/721
DS40001430F-page 26 2010-2015 Microchip Technology Inc.
3.1 MCLR
The PIC16(L)F720/721 has a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a Reset does not drive the
MCLR pin low.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to VDD. The use of an RC
network, as shown in Figure 3-2, is suggested.
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
MCLRE = 0, the Reset signal to the chip is generated
internally. When the MCLRE = 1, the RA3/MCLR pin
becomes an external Reset input. In this mode, the
RA3/MCLR pin has a weak pull-up to VDD. In-Circuit
Serial Programming™ is not affected by selecting the
internal MCLR option.
FIGURE 3-2: RECOMMENDED MCLR
CIRCUIT
3.2 Power-on Reset (POR)
The on-chip POR circuit holds the chip in Reset until VDD
has reached a high enough level for proper operation. A
maximum rise time for VDD is required. See
Section 23.0 “Electrical Specifications” for details. If
the BOR is enabled, the maximum rise time specification
does not apply. The BOR circuitry will keep the device in
Reset until VDD reaches VBOR (see Section 3.5
“Brown-out Reset (BOR)”).
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
For additional information, refer to Application Note
AN607, Power-up Trouble Shooting (DS00000607).
3.3 Power-up Timer (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal)
time out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from the WDT
oscillator. For more information, see Section 7.3
“Internal Clock Modes”. The chip is kept in Reset as
long as PWRT is active. The PWRT delay allows the
VDD to rise to an acceptable level. A Configuration bit,
PWRTE, can disable (if set) or enable (if cleared or pro-
grammed) the Power-up Timer. The Power-up Timer
should be enabled when Brown-out Reset is enabled,
although it is not required.
The Power-up Timer delay will vary from chip-to-chip
and vary due to:
•V
DD variation
Temperature variation
Process variation
See DC parameters for details (Section 23.0
“Electrical Specifications”).
3.4 Watchdog Timer (WDT)
The WDT has the following features:
Shares an 8-bit prescaler with Timer0
Time-out period is from 17 ms to 2.2 seconds,
nominal
Enabled by a Configuration bit
WDT is cleared under certain conditions described in
Table 3-3.
3.4.1 WDT OSCILLATOR
The WDT derives its time base from 31 kHz internal
oscillator.
VDD PIC® MCU
MCLR
R1
10 k
C1
0.1 F
Note: The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word.
i] WDTEN
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PIC16(L)F720/721
3.4.2 WDT CONTROL
The WDTEN bit is located in the Configuration Word
Register 1. When set, the WDT runs continuously.
The PSA and PS<2:0> bits of the OPTION_REG
register control the WDT period. See Section 12.0
“Timer0 Module” for more information.
FIGURE 3-3: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 3-3: WDT STATUS
Conditions WDT
WDTEN = 0Cleared
CLRWDT Command
Exit Sleep + System Clock = INTOSC, EXTCLK
From TMR0
Postscaler
8
PS<2:0>
PSA
TO TMR0
1
10
0
Clock Source
To T1G
Divide by
512
WDTEN
TMR1GE
T1GSS = 11
WDTEN
WDT Reset
Low-Power
WDT OSC
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3.5 Brown-out Reset (BOR)
Brown-out Reset is enabled by programming the
BOREN<1:0> bits in the Configuration register.
Between the POR and BOR, complete voltage range
coverage for execution protection can be
implemented.
Two bits are used to enable the BOR. When
BOREN = 11, the BOR is always enabled. When
BOREN = 10, the BOR is enabled, but disabled during
Sleep. When BOREN = 0X, the BOR is disabled.
If VDD falls below VBOR for greater than parameter
(TBOR) (see Section 23.0 “Electrical Specifica-
tions”), the Brown-out situation will reset the device.
This will occur regardless the VDD slew rate. A Reset is
not ensured to occur if VDD falls below VBOR for more
than TBOR.
If VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above VBOR, the Power-up Timer will execute a
64 ms Reset.
FIGURE 3-4: BROWN-OUT SITUATIONS
64 ms(1)
VBOR
VDD
Internal
Reset
VBOR
VDD
Internal
Reset 64 ms(1)
< 64 ms
64 ms(1)
VBOR
VDD
Internal
Reset
Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.
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PIC16(L)F720/721
3.6 Time-out Sequence
PWRT time out is invoked after POR has expired. The
total time out will vary based on the oscillator
Configuration and the PWRTE bit status. For example,
in EC mode with PWRTE = 1 (PWRT disabled), there
will be no time out at all. Figure 3-5, Figure 3-6 and
Figure 3-7 depict time-out sequences.
Since the time outs occur from the POR pulse, if MCLR
is kept low long enough, the time outs will expire. Then,
bringing MCLR high will begin execution immediately
(see Figure 3-6). This is useful for testing purposes or
to synchronize more than one PIC16(L)F720/721
devices operating in parallel.
Table 3-5 shows the Reset conditions for some special
registers.
3.7 Power Control (PCON) Register
The Power Control (PCON) register has two Status bits
to indicate what type of Reset occurred last.
Bit 0 is BOR (Brown-out Reset). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
indicating that a Brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled
(BOREN<1:0> = 00 in the Configuration Word register).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., VDD may have
gone too low).
For more information, see Section 3.5 “Brown-out
Reset (BOR)”.
FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
TABLE 3-4: TIME OUT IN VARIOUS SITUATIONS
Oscillator Configuration Power-up Brown-out Reset Wake-up from
Sleep
PWRTE = 0PWRTE = 1PWRTE = 0PWRTE = 1
EC, INTOSC TPWRT —TPWRT ——
TABLE 3-5: RESET BITS AND THEIR SIGNIFICANCE
POR BOR TO PD Condition
0u11Power-on Reset
1011Brown-out Reset
uu0uWDT Reset
uu00WDT Wake-up
uuuuMCLR Reset during normal operation
uu10MCLR Reset during Sleep
Legend: u = unchanged, x = unknown
TPWRT
VDD
MCLR
Internal POR
PWRT Time out
Internal Reset
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DS40001430F-page 30 2010-2015 Microchip Technology Inc.
FIGURE 3-6: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2
FIGURE 3-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3
VDD
MCLR
Internal POR
PWRT Time out
Internal Reset
TPWRT
TPWRT
VDD
MCLR
Internal POR
PWRT Time out
Internal Reset
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PIC16(L)F720/721
TABLE 3-6: INITIALIZATION CONDITION FOR REGISTERS
Register Address Power-on Reset/
Brown-out Reset(1) MCLR Reset/
WDT Reset Wake-up from Sleep through
Interrupt/Time out
W—xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h/80h/
100h/180h
xxxx xxxx xxxx xxxx uuuu uuuu
TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h/82h/
102h/182h
0000 0000 0000 0000 PC + 1(3)
STATUS 03h/83h/
103h/183h
0001 1xxx 000q quuu(4) uuuq quuu(4)
FSR 04h/84h/
104h/184h
xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 05h --xx xxxx --xx xxxx --uu uuuu
PORTB 06h xxxx ---- xxxx ---- uuuu ----
PORTC 07h xxxx xxxx xxxx xxxx uuuu uuuu
PCLATH 0Ah/8Ah/
10Ah/18Ah
---0 0000 ---0 0000 ---u uuuu
INTCON 0Bh/8Bh/
10Bh/18Bh
0000 000x 0000 000x uuuu uuuu(2)
PIR1 0Ch 0000 0000 0000 0000 uuuu uuuu(2)
TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 10h 0000 -0-0 0000 -0-0 uuuu -u-u
TMR2 11h 0000 0000 0000 0000 uuuu uuuu
T2CON 12h -000 0000 -000 0000 -uuu uuuu
SSPBUF 13h xxxx xxxx xxxx xxxx uuuu uuuu
SSPCON 14h 0000 0000 0000 0000 uuuu uuuu
CCPR1L 15h xxxx xxxx xxxx xxxx uuuu uuuu
CCPR1H 16h xxxx xxxx xxxx xxxx uuuu uuuu
CCP1CON 17h --00 0000 --00 0000 --uu uuuu
RCSTA 18h 0000 000x 0000 000x uuuu uuuu
TXREG 19h 0000 0000 0000 0000 uuuu uuuu
RCREG 1Ah 0000 0000 0000 0000 uuuu uuuu
ADRES 1Eh xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 1Fh --00 0000 --00 0000 --uu uuuu
OPTION_REG 81h/181h 1111 1111 1111 1111 uuuu uuuu
TRISA 85h --11 -111 --11 -111 --uu -uuu
TRISB 86h 1111 ---- 1111 ---- uuuu ----
TRISC 87h 1111 1111 1111 1111 uuuu uuuu
PIE1 8Ch 0000 0000 0000 0000 uuuu uuuu
PCON 8Eh ---- --qq ---- --uu(1,5) ---- --uu
T1GCON 8Fh 0000 0x00 uuuu uxuu uuuu uxuu
OSCCON 90h --10 qq-- --10 qq-- --uu qq--
OSCTUNE 91h --00 0000 --uu uuuu --uu uuuu
PR2 92h 1111 1111 1111 1111 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 3-8 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
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SSPADD 93h 0000 0000 0000 0000 uuuu uuuu
SSPMSK 93h 1111 1111 1111 1111 uuuu uuuu
SSPSTAT 94h 0000 0000 0000 0000 uuuu uuuu
WPUB 115h 1111 ---- 1111 ---- uuuu ----
WPUA 95h --11 1111 --11 1111 --uu uuuu
IOCB 116h 0000 ---- 0000 ---- uuuu ----
IOCA 96h --00 0000 --00 0000 --uu uuuu
TXSTA 98h 0000 -010 0000 -010 uuuu -uuu
SPBRG 99h 0000 0000 0000 0000 uuuu uuuu
FVRCON 9Dh q000 --00 q000 --00 uuuu --uu
ADCON1 9Fh -000 ---- -000 ---- -uuu ----
PMDATL 10Ch xxxx xxxx xxxx xxxx uuuu uuuu
PMADRL 10Dh 0000 0000 0000 0000 uuuu uuuu
PMDATH 10Eh --xx xxxx --xx xxxx --uu uuuu
PMADRH 10Fh ---0 0000 ---0 0000 ---u uuuu
ANSELA 185h ---1 -111 ---1 -111 ---u -uuu
ANSELB 186h --11 ---- --11 ---- --uu ----
ANSELC 187h 11-- 1111 11-- 1111 uu-- uuuu
PMCON1 18Ch 1000 -000 1000 -000 1000 -000
TABLE 3-6: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Register Address Power-on Reset/
Brown-out Reset(1) MCLR Reset/
WDT Reset Wake-up from Sleep through
Interrupt/Time out
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 3-8 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
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PIC16(L)F720/721
TABLE 3-7: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Condition Program
Counter STATUS
Register PCON
Register
Power-on Reset 0000h 0001 1xxx ---- --0x
MCLR Reset during normal operation 0000h 000u uuuu ---- --uu
MCLR Reset during Sleep 0000h 0001 0uuu ---- --uu
WDT Reset 0000h 0000 uuuu ---- --uu
WDT Wake-up PC + 1 uuu0 0uuu ---- --uu
Brown-out Reset 0000h 0001 1xxx ---- --10
Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the PC is loaded with
the interrupt vector (0004h) after execution of PC + 1.
TABLE 3-8: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on
Page
STATUS IRP RP1 RP0 TO PD ZDC C19
PCON — — —PORBOR 21
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.
Shaded cells are not used by Resets.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
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DS40001430F-page 34 2010-2015 Microchip Technology Inc.
4.0 INTERRUPTS
The PIC16(L)F720/721 device family features an
interruptible core, allowing certain events to preempt
normal program flow. An Interrupt Service Routine
(ISR) is used to determine the source of the interrupt
and act accordingly. Some interrupts can be configured
to wake the MCU from Sleep mode.
The PIC16(L)F720/721 device family has 11 interrupt
sources, differentiated by corresponding interrupt
enable and flag bits:
Timer0 Overflow Interrupt
External Edge Detect on INT Pin Interrupt
Interrupt-on-change, PORTA and PORTB pins
Timer1 Gate Interrupt
A/D Conversion Complete Interrupt
AUSART Receive Interrupt
AUSART Transmit Interrupt
SSP Event Interrupt
CCP1 Event Interrupt
Timer2 Match with PR2 Interrupt
Timer1 Overflow Interrupt
A block diagram of the interrupt logic is shown in
Figure 4-1.
FIGURE 4-1: INTERRUPT LOGIC
TMR0IF
TMR0IE
INTF
INTE
RABIF
RABIE
GIE
PEIE
Wake-up (if in Sleep mode)(1)
Interrupt to CPU
TMR1GIE
TMR1GIF
ADIF
ADIE
CCP1IF
CCP1IE
IOC-RB4
IOCB4
IOC-RB5
IOCB5
IOC-RB6
IOCB6
IOC-RB7
IOCB7
RCIF
RCIE
TMR2IE
TMR2IF
SSPIE
SSPIF
TXIE
TXIF
TMR1IE
TMR1IF
Note 1: Some peripherals depend upon the
system clock for operation. Since the
system clock is suspended during
Sleep, these peripherals will not wake
the part from Sleep. See Section 19.1
“Wake-up from Sleep”.
IOC-RA3
IOCA3
IOC-RA4
IOCA4
IOC-RA5
IOCA5
IOC-RA1
IOCA1
IOC-RA2
IOCA2
IOC-RA0
IOCA0
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PIC16(L)F720/721
4.1 Operation
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
GIE bit of the INTCON register
Interrupt Enable bit(s) for the specific interrupt
event(s)
PEIE bit of the INTCON register (if the Interrupt
Enable bit of the interrupt event is contained in the
PIE1 register)
The INTCON and PIR1 registers record individual
interrupts via interrupt flag bits. Interrupt flag bits will be
set, regardless of the status of the GIE, PEIE and
individual Interrupt Enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
Current prefetched instruction is flushed
GIE bit is cleared
Current Program Counter (PC) is pushed onto the
stack
PC is loaded with the interrupt vector 0004h
The ISR determines the source of the interrupt by
polling the interrupt flag bits. The interrupt flag bits must
be cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its Interrupt Flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack and setting the GIE bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
4.2 Interrupt Latency
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is three instruction cycles. For asynchronous
interrupts, the latency is three to four instruction cycles,
depending on when the interrupt occurs. See Figure 4-2
for timing details.
FIGURE 4-2: INT PIN INTERRUPT TIMING
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
CLKIN
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
PC PC + 1 PC + 1 0004h 0005h
Inst (0004h) Inst (0005h)
Dummy Cycle
Inst (PC) Inst (PC + 1)
Inst (PC – 1) Inst (0004h)
Dummy Cycle
Inst (PC)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 23.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
(1)
(2)
(3)
(4)
(5)
(1)
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DS40001430F-page 36 2010-2015 Microchip Technology Inc.
4.3 Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to the Section 19.0
“Power-Down Mode (Sleep)” for more details.
4.4 INT Pin
The external interrupt, INT pin, causes an
asynchronous, edge-triggered interrupt. The INTEDG bit
of the OPTION_REG register determines on which edge
the interrupt will occur. When the INTEDG bit is set, the
rising edge will cause the interrupt. When the INTEDG
bit is clear, the falling edge will cause the interrupt. The
INTF bit of the INTCON register will be set when a valid
edge appears on the INT pin. If the GIE and INTE bits
are also set, the processor will redirect program
execution to the interrupt vector. This interrupt is
disabled by clearing the INTE bit of the INTCON register.
4.5 Context Saving
When an interrupt occurs, only the return PC value is
saved to the stack. If the ISR modifies or uses an
instruction that modifies key registers, their values
must be saved at the beginning of the ISR and restored
when the ISR completes. This prevents instructions
following the ISR from using invalid data. Examples of
key registers include the W, STATUS, FSR and
PCLATH registers.
The code shown in Example 4-1 can be used to do the
following.
Save the W register
Save the STATUS register
Save the PCLATH register
Execute the ISR program
Restore the PCLATH register
Restore the STATUS register
Restore the W register
Since most instructions modify the W register, it must
be saved immediately upon entering the ISR. The
SWAPF instruction is used when saving and restoring
the W and STATUS registers because it will not affect
any bits in the STATUS register. It is useful to place
W_TEMP in shared memory because the ISR cannot
predict which bank will be selected when the interrupt
occurs.
The processor will branch to the interrupt vector by
loading the PC with 0004h. The PCLATH register will
remain unchanged. This requires the ISR to ensure
that the PCLATH register is set properly before using
an instruction that causes PCLATH to be loaded into
the PC. See Section 2.3 “PCL and PCLATH” for
details on PC operation.
EXAMPLE 4-1: SAVING W, STATUS AND PCLATH REGISTERS IN RAM
Note: The microcontroller does not normally
require saving the PCLATH register.
However, if computed GOTOs are used,
the PCLATH register must be saved at the
beginning of the ISR and restored when
the ISR is complete to ensure correct
program flow.
MOVWFW_TEMP ;Copy W to W_TEMP register
SWAPFSTATUS,W ;Swap status to be saved into W
;Swaps are used because they do not affect the status bits
BANKSELSTATUS_TEMP ;Select regardless of current bank
MOVWFSTATUS_TEMP ;Copy status to bank zero STATUS_TEMP register
MOVF PCLATH,W ;Copy PCLATH to W register
MOVWF PCLATH_TEMP ;Copy W register to PCLATH_TEMP
:
:(ISR) ;Insert user code here
:
BANKSELSTATUS_TEMP ;Select regardless of current bank
MOVF PCLATH_TEMP,W ;
MOVWF PCLATH ;Restore PCLATH
SWAPFSTATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWFSTATUS ;Move W into STATUS register
SWAPFW_TEMP,F ;Swap W_TEMP
SWAPFW_TEMP,W ;Swap W_TEMP into W
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PIC16(L)F720/721
4.5.1 INTCON REGISTER
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, PORTB change and
external RA2/INT pin interrupts.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
REGISTER 4-1: INTCON: INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE TMR0IE INTE RABIE(1) TMR0IF(2) INTF RABIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
bit 3 RABIE: PORTA or PORTB Change Interrupt Enable bit(1)
1 = Enables the PORTA or PORTB change interrupt
0 = Disables the PORTA or PORTB change interrupt
bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit(2)
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred (must be cleared in software)
0 = The INT external interrupt did not occur
bit 0 RABIF: PORTA or PORTB Change Interrupt Flag bit
1 = When at least one of the PORTA or PORTB general purpose I/O pins changed state (must be
cleared in software)
0 = None of the PORTA or PORTB general purpose I/O pins have changed state
Note 1: The appropriate bits in the IOCB register must also be set.
2: TMR0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before
clearing TMR0IF bit.
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DS40001430F-page 38 2010-2015 Microchip Technology Inc.
4.5.2 PIE1 REGISTER
The PIE1 register contains the interrupt enable bits, as
shown in Register 4-2.
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 4-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit
1 = Enable the Timer1 gate acquisition complete interrupt
0 = Disable the Timer1 gate acquisition complete interrupt
bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3 SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
Cagluve mode Comgare mode PWM mode
2010-2015 Microchip Technology Inc. DS40001430F-page 39
PIC16(L)F720/721
4.5.3 PIR1 REGISTER
The PIR1 register contains the interrupt flag bits, as
shown in Register 4-3.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 4-3: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit
1 = Timer1 gate is inactive
0 = Timer1 gate is active
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = A/D conversion complete (must be cleared in software)
0 = A/D conversion has not completed or has not been started
bit 5 RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full (cleared by reading RCREG)
0 = The USART receive buffer is not full
bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty (cleared by writing to TXREG)
0 = The USART transmit buffer is full
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The Transmission/Reception is complete (must be cleared in software)
0 = Waiting to Transmit/Receive
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit
1 = A Timer2 to PR2 match occurred (must be cleared in software)
0 = No Timer2 to PR2 match occurred
bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = The TMR1 register overflowed (must be cleared in software)
0 = The TMR1 register did not overflow
PIC16(L)F720/721
DS40001430F-page 40 2010-2015 Microchip Technology Inc.
TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
INTCON GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 37
OPTION_REG RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 20
PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 38
PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 39
Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the
capture, compare and PWM.
2010-2015 Microchip Technology Inc. DS40001430F-page 41
PIC16(L)F720/721
5.0 LOW DROPOUT (LDO)
VOLTAGE REGULATOR
The PIC16F720/721 devices differ from the
PIC16LF720/721 devices due to an internal Low
Dropout (LDO) voltage regulator. The PIC16F720/721
contain an internal LDO, while the PIC16LF720/721 do
not.
The lithography of the die allows a maximum operating
voltage of 3.6V on the internal digital logic. In order to
continue to support 5.0V designs, a LDO voltage
regulator is integrated on the die. The LDO voltage
regulator allows for the internal digital logic to operate
at 3.2V, while the I/Os operate at 5.0V (VDD).
PIC16(L)F720/721
DS40001430F-page 42 2010-2015 Microchip Technology Inc.
6.0 I/O PORTS
There are as many as 18 general purpose I/O pins
available. Depending on which peripherals are
enabled, some or all of the pins may not be available as
general purpose I/O. In general, when a peripheral is
enabled, the associated pin may not be used as a
general purpose I/O pin.
6.1 PORTA and TRISA Registers
PORTA is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register 6-2). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). Example 6-1 shows how to
initialize PORTA.
Reading the PORTA register (Register 6-1) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch.
The TRISA register (Register 6-2) controls the PORTA
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISA register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
EXAMPLE 6-1: INITIALIZING PORTA
6.1.1 WEAK PULL-UPS
Each of the PORTA pins has an individually
configurable internal weak pull-up. Control bits
WPUA<5:0> enable or disable each pull-up (see
Register 6-5). Each weak pull-up is automatically
turned off when the port pin is configured as an output.
All pull-ups are disabled on a Power-on Reset by the
RABPU bit of the OPTION_REG register.
6.1.2 INTERRUPT-ON-CHANGE
All of the PORTA pins are individually configurable as
an interrupt-on-change pin. Control bits IOCA<5:0>
enable or disable the interrupt function for each pin
(see Register 6-6). The interrupt-on-change feature is
disabled on a Power-on Reset.
For enable interrupt-on-change pins, the present value
is compared with the old value latched on the last read
of PORTA to determine which bits have changed or
mismatched the old value. The ‘mismatch’ outputs of
the last read are OR’d together to set the PORTA
Change Interrupt Flag bit (RABIF) in the INTCON
register. This interrupt can wake the device from Sleep.
The user, in the Interrupt Service Routine, clears the
interrupt by:
1. Any read or write of PORTA. This will end the
mismatch condition.
2. Clear the flag bit RABIF.
A mismatch condition will continue to set flag bit RABIF.
Reading or writing PORTA will end the mismatch
condition and allow flag bit RABIF to be cleared. The
latch holding the last read value is not affected by a
MCLR or Brown-out Reset. After these Resets, the
RABIF flag will continue to be set if a mismatch is
present.
Note: The ANSELA register must be initialized
to configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’.
BANKSEL PORTA ;
CLRF PORTA ;Init PORTA
BANKSEL ANSELA ;
CLRF ANSELA ;digital I/O
BANKSEL TRISA ;
MOVLW 0Ch ;Set RA<3:2> as inputs
MOVWF TRISA ;and set RA<5:4,1:0>
;as outputs
Note: When a pin change occurs at the same
time as a read operation on PORTA, the
RABIF flag will always be set. If multiple
PORTA pins are configured for the inter-
rupt-on-change, the user may not be able
to identify which pin changed state.
2010-2015 Microchip Technology Inc. DS40001430F-page 43
PIC16(L)F720/721
REGISTER 6-1: PORTA: PORTA REGISTER
U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
RA5 RA4 RA3(1) RA2 RA1 RA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0
bit 5-0 RA<5:0>: PORTA I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1: RA<3> is input only.
REGISTER 6-2: TRISA: PORTA TRI-STATE REGISTER
U-0 U-0 R/W-1 R/W-1 U-1 R/W-1 R/W-1 R/W-1
TRISA5 TRISA4 (1) TRISA2 TRISA1 TRISA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0
bit 5-4 TRISA<5:4>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
bit 3 Unimplemented: Read as ‘1
bit 2-0 TRISA<2:0>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Note 1: TRISA<3> is unimplemented and read as 1.
REGISTER 6-3: WPUA: WEAK PULL-UP PORTA REGISTER
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—WPUA5WPUA4
WPUA3(2) WPUA2 WPUA1 WPUA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0
bit 5-0 WPUA<5:0>: Weak Pull-up PORTA Control bits
1 = Weak pull-up enabled(1)
0 = Weak pull-up disabled
Note 1: Enabling weak pull-ups also requires that the RABPU bit of the OPTION_REG register be cleared.
2: If MCLREN = 1, WPUA3 is always enabled.
PIC16(L)F720/721
DS40001430F-page 44 2010-2015 Microchip Technology Inc.
6.1.3 ANSELA REGISTER
The ANSELA register (Register 6-5) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELA bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
REGISTER 6-4: IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0
bit 5-0 IOCA<5:0>: Interrupt-on-Change PORTA Control bits
1 = Interrupt-on-change enabled(1)
0 = Interrupt-on-change disabled
Note 1: Interrupt-on-change also requires that the RABIE bit of the INTCON register be set.
REGISTER 6-5: ANSELA: PORTA ANALOG SELECT REGISTER
U-0 U-0 U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1
ANSA4 ANSA2 ANSA1 ANSA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0
bit 4 ANSA4: Analog Select between Analog or Digital Function on Pin RA<4>
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input. Digital input buffer is disabled(1).
bit 3 Unimplemented: Read as ‘0
bit 2-0 ANSA<2:0>: Analog Select between Analog or Digital Function on Pins RA<2:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input. Digital input buffer is disabled(1).
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry. Weak pull-ups, if
available, are unaffected. The corresponding TRIS bit must be set to Input mode by the user in order to
allow external control of the voltage on the pin.
2010-2015 Microchip Technology Inc. DS40001430F-page 45
PIC16(L)F720/721
6.1.4 PIN DESCRIPTIONS AND
DIAGRAMS
Each PORTA pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the A/D Converter (ADC), refer to the
appropriate section in this data sheet.
6.1.4.1 RA0/AN0/ICSPDAT
Figure 6-1 shows the diagram for this pin. This pin is
configurable to function as one of the following:
General purpose I/O
Analog input for the ADC
ICSP™ programming data (separate controls
from TRISA)
ICD Debugging data (separate controls from
TRISA)
6.1.4.2 RA1/AN1/ICSPCLK
Figure 6-2 shows the diagram for this pin. This pin is
configurable to function as one of the following:
General purpose I/O
Analog input for the ADC
ICSP programming clock (separate controls from
TRISA)
ICD Debugging clock (separate controls from
TRISA)
6.1.4.3 RA2/AN2/T0CKI/INT
Figure 6-3 shows the diagram for this pin. This pin is
configurable to function as one of the following:
General purpose I/O
Analog input for the ADC
External interrupt
Clock input for Timer0
The Timer0 clock input function works independently of
any TRIS register setting. Effectively, if TRISA2 = 0,
the PORTA2 register bit will output to the pad and Clock
Timer0 at the same time.
6.1.4.4 RA3/MCLR/VPP
Figure 6-4 shows the diagram for this pin. This pin is
configurable to function as one of the following:
General purpose I/O
Master Clear Reset with weak pull-up
6.1.4.5 RA4/AN3/T1G/CLKOUT
Figure 6-5 shows the diagram for this pin. This pin is
configurable to function as one of the following:
General purpose I/O
Analog input for the ADC
Timer1 gate input
Clock output
6.1.4.6 RA5/T1CKI/CLKIN
Figure 6-6 shows the diagram for this pin. This pin is
configurable to function as one of the following:
General purpose I/O
Timer1 Clock input
Clock input
PIC16(L)F720/721
DS40001430F-page 46 2010-2015 Microchip Technology Inc.
FIGURE 6-1: BLOCK DIAGRAM OF RA0
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
RD PORTA
RD
WR
WR
RD
WR
IOCA
RD
IOCA
Interrupt-on-Change
Analog(1)
Input mode
RABPU
Analog(1)
Input mode
Q3
WR
RD
WPUA
Data Bus
WPUA
PORTA
TRISA
TRISA
PORTA
Note 1: ANSEL determines Analog Input mode.
To A/D Converter
ICSP™ mode
DEBUG
0
1
1
0
0
1
0
1
TRIS_ICDDAT
PORT_ICDDAT
ICSPDAT
,4 67:5 2%
2010-2015 Microchip Technology Inc. DS40001430F-page 47
PIC16(L)F720/721
FIGURE 6-2: BLOCK DIAGRAM OF RA1
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR WPUA
RD WPUA
RD PORTA
RD PORTA
WR PORTA
WR TRISA
RD TRISA
WR IOCA
RD IOCA
Interrupt-on-Change
Analog(1)
Input mode
RABPU
Analog(1)
Input mode
Q3
Note 1: ANSEL determines Analog Input mode.
To A/D Converter
ICSP™ mode
DEBUG
0
1
1
0
0
1
0
1
TRIS_ICDCLK
PORT_ICDCLK
ICSPCLK
PIC16(L)F720/721
DS40001430F-page 48 2010-2015 Microchip Technology Inc.
FIGURE 6-3: BLOCK DIAGRAM OF RA2
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Analog(1)
Input mode
Data Bus
WR
WPUA
RD
WPUA
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
To A/D Converter
To INT
To Timer0
Analog(1)
Input mode
RABPU
RD PORTA
Interrupt-on-
Change
Q3
Note 1: ANSEL determines Analog Input mode.
To Voltage Regulator
(for
PIC16F720/721
only)
2010-2015 Microchip Technology Inc. DS40001430F-page 49
PIC16(L)F720/721
FIGURE 6-4: BLOCK DIAGRAM OF RA3 FIGURE 6-5: BLOCK DIAGRAM OF RA4
Input
VSS
D
Q
CK
Q
D
EN
Q
Data Bus
RD PORTA
RD
PORTA
WR
IOCA
RD
IOCA
Reset MCLRE
RD
TRISA VSS
D
EN
Q
MCLRE
VDD
Weak
MCLRE
Interrupt-on-
Change
Pin
Q3
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Analog
Input mode
Data Bus
WR
WPUA
RD
WPUA
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
FOSC/4
To A/D Converter
CLKOUT
0
1
CLKOUT
Enable
Enable
Analog(2)
Input mode
RABPU
RD PORTA
To T1G
INTOSC/
RC/EC(1)
CLK
modes
CLKOUT
Enable
Note 1: With CLKOUT option.
2: ANSEL determines Analog Input mode.
Interrupt-on-
Change
Q3
PIC16(L)F720/721
DS40001430F-page 50 2010-2015 Microchip Technology Inc.
FIGURE 6-6: BLOCK DIAGRAM OF RA5
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPUA
RD
WPUA
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
To TMR1 or CLKIN
INTOSC
mode
RD PORTA
INTOSC
mode
RABPU
Interrupt-on-
Change
Q3
TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELA — ANSA4 ANSA2 ANSA1 ANSA0 44
OPTION_REG RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 20
PORTA RA5 RA4 RA3 RA2 RA1 RA0 43
TRISA TRISA5 TRISA4 TRISA2 TRISA1 TRISA0 43
Legend: x = unknown, u = unchanged, – = unimplemented locations read as0’. Shaded cells are not used by
PORTA.
2010-2015 Microchip Technology Inc. DS40001430F-page 51
PIC16(L)F720/721
6.2 PORTB and TRISB Registers
PORTB is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISB
(Register 6-7). Setting a TRISB bit (= 1) will make the
corresponding PORTB pin an input (i.e., put the
corresponding output driver in a High Impedance mode).
Clearing a TRISB bit (= 0) will make the corresponding
PORTB pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 6-2 shows how to initialize PORTB.
Reading the PORTB register (Register 6-6) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write-to-a-port implies that the
port pins are read, this value is modified and then written
to the PORT data latch.
The TRISB register (Register 6-7) controls the PORTB
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISB register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’. Example 6-2 shows how to initialize PORTB.
EXAMPLE 6-2: INITIALIZING PORTB
6.2.1 ANSELB REGISTER
The ANSELB register (Register 6-10) is used to
configure the Input mode of an I/O pin to analog input.
Setting the appropriate ANSELB bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELB bits has no affect on digital
output functions. A pin with TRIS clear and ANSELB
set will still operate as a digital output, but the Input
mode will be analog. This can cause unexpected
behavior when executing read-modify-write
instructions on the affected port.
6.2.2 WEAK PULL-UPS
Each of the PORTB pins has an individually configurable
internal weak pull-up. Control bits WPUB<7:4> enable or
disable each pull-up (see Register 6-8). Each weak pull-
up is automatically turned off when the port pin is
configured as an output. All pull-ups are disabled on a
Power-on Reset by the RABPU bit of the OPTION_REG
register.
6.2.3 INTERRUPT-ON-CHANGE
All of the PORTB pins are individually configurable as an
interrupt-on-change pin. Control bits IOCB<7:4> enable
or disable the interrupt function for each pin. Refer to
Register 6-9. The interrupt-on-change feature is
disabled on a Power-on Reset.
For enabled interrupt-on-change pins, the present value
is compared with the old value latched on the last read
of PORTB to determine which bits have changed or
mismatched the old value. The ‘mismatch’ outputs of
the last read are OR’d together to set the PORTB
Change Interrupt Flag bit (RABIF) in the INTCON
register.
This interrupt can wake the device from Sleep. The user,
in the Interrupt Service Routine, clears the interrupt by:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear the flag bit RABIF.
A mismatch condition will continue to set flag bit RABIF.
Reading or writing PORTB will end the mismatch
condition and allow flag bit RABIF to be cleared. The latch
holding the last read value is not affected by a MCLR nor
Brown-out Reset. After these Resets, the RABIF flag will
continue to be set if a mismatch is present.
Note: The ANSELB register must be initialized
to configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’.
BANKSEL PORTB ;
CLRF PORTB ;Init PORTB
BANKSEL ANSELB
CLRF ANSELB ;Make RB<7:4> digital
BANKSEL TRISB ;
MOVLW B11110000;Set RB<7:4> as inputs
MOVWF TRISB ;
Note: When a pin change occurs at the same
time as a read operation on PORTB, the
RABIF flag will always be set. If multiple
PORTB pins are configured for the
interrupt-on-change, the user may not be
able to identify which pin changed state.
PIC16(L)F720/721
DS40001430F-page 52 2010-2015 Microchip Technology Inc.
REGISTER 6-6: PORTB: PORTB REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 U-0 U-0 U-0
RB7 RB6 RB5 RB4 — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 RB<7:4>: PORTB I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 3-0 Unimplemented: Read as ‘0
REGISTER 6-7: TRISB: PORTB TRI-STATE REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0
TRISB7 TRISB6 TRISB5 TRISB4 — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 TRISB<7:4>: PORTB Tri-State Control bit
1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output
bit 3-0 Unimplemented: Read as ‘0
REGISTER 6-8: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0
WPUB7 WPUB6 WPUB5 WPUB4 — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 WPUB<7:4>: Weak Pull-up PORTB Control bits
1 = Weak pull-up enabled (1,2)
0 = Weak pull-up disabled
bit 3-0 Unimplemented: Read as ‘0
Note 1: Global RABPU bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
2010-2015 Microchip Technology Inc. DS40001430F-page 53
PIC16(L)F720/721
REGISTER 6-9: IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
IOCB7 IOCB6 IOCB5 IOCB4 — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 IOCB<7:4>: Interrupt-on-Change PORTB Control bits
1 = Interrupt-on-change enabled(1)
0 = Interrupt-on-change disabled
bit 3-0 Unimplemented: Read as ‘0
Note 1: Interrupt-on-change also requires that the RABIE bit of the INTCON register be set.
REGISTER 6-10: ANSELB: PORTB ANALOG SELECT REGISTER
U-0 U-0 R/W-1 R/W-1 U-0 U-0 U-0 U-0
ANSB5 ANSB4 — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0
bit 5-4 ANSB<5:4>: Analog Select between Analog or Digital Function on Pins RB<5:4>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 3-0 Unimplemented: Read as ‘0
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry. Weak pull-ups, if
available, are unaffected. The corresponding TRIS bit must be set to Input mode by the user, in order to
allow external control of the voltage on the pin.
PIC16(L)F720/721
DS40001430F-page 54 2010-2015 Microchip Technology Inc.
6.2.4 PIN DESCRIPTIONS AND
DIAGRAMS
Each PORTB pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the SSP, I2C or interrupts, refer to the appropriate
section in this data sheet.
6.2.4.1 RB4/AN10/SDI/SDA
Figure 6-7 shows the diagram for this pin. The RB4 pin
is configurable to function as one of the following:
General purpose I/O. Individually controlled
interrupt-on-change. Individually enabled pull-up.
Analog input for the A/D
Synchronous Serial Port Input (SPI)
•I
2C data I/O
6.2.4.2 RB5/AN11/RX/DT
Figure 6-8 shows the diagram for this pin. The RB5 pin
is configurable to function as one of the following:
General purpose I/O. Individually controlled
interrupt-on-change. Individually enabled pull-up.
Analog input for the A/D
USART asynchronous receive
USART synchronous receive
6.2.4.3 RB6/SCK/SCL
Figure 6-9 shows the diagram for this pin. The RB6 pin
is configurable to function as one of the following:
General purpose I/O. Individually controlled
interrupt-on-change. Individually enabled pull-up.
Synchronous Serial Port clock for both SPI and
I2C
6.2.4.4 RB7/TX/CK
Figure 6-10 shows the diagram for this pin. The RB7
pin is configurable to function as one of the following:
General purpose I/O. Individually controlled
interrupt-on-change. Individually enabled pull-up.
USART asynchronous transmit
USART synchronous clock
FIGURE 6-7: BLOCK DIAGRAM OF RB4
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPUB
RD
WPUB
RD PORTB
RD
PORTB
WR
PORTB
WR
TRISB
RD
TRISB
WR
IOCB
RD
IOCB
Interrupt-on-
To SSP
Analog(1)
Input mode
RABPU
Analog(1)
Input mode
Change
Q3
To A/D Converter
ST
SSPEN
0
1
1
0
Note 1: ANSEL determines Analog Input mode.
0
1
1
0
SSP
From
SSP
2010-2015 Microchip Technology Inc. DS40001430F-page 55
PIC16(L)F720/721
FIGURE 6-8: BLOCK DIAGRAM OF RB5 FIGURE 6-9: BLOCK DIAGRAM OF RB6
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPUB
RD
WPUB
RD PORTB
RD
PORTB
WR
PORTB
WR
TRISB
RD
TRISB
WR
IOCB
RD
IOCB
Interrupt-on-
To AUSART RX/DT
Analog(1)
Input mode
RABPU
Analog(1)
Input mode
Change
Q3
To A/D Converter
SYNC
ST
AUSART
DT
SPEN
Note 1: ANSEL determines Analog Input mode.
0
1
1
0
0
1
1
0
From
AUSART
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPUB
RD
WPUB
RD PORTB
RD
PORTB
WR
PORTB
WR
TRISB
RD
TRISB
WR
IOCB
RD
IOCB
Interrupt-on-
To SSP
RABPU
Change
Q3
SSPEN
ST
0
1
1
0
0
1
1
0
From
SSP
SSP
Clock
PIC16(L)F720/721
DS40001430F-page 56 2010-2015 Microchip Technology Inc.
FIGURE 6-10: BLOCK DIAGRAM OF RB7
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPUB
RD
WPUB
RD PORTB
RD
PORTB
WR
PORTB
WR
TRISB
RD
TRISB
WR
IOCB
RD
IOCB
Interrupt-on-
RABPU
Change
Q3
SPEN
TXEN
CK
TX
SYNC
AUSART
AUSART
0
1
1
0
0
1
1
0
0
1
1
0
‘1’
TABLE 6-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on
Page
ANSELB ANSB5 ANSB4 53
INTCON GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 37
IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — 53
OPTION_REG RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 20
PORTB RB7 RB6 RB5 RB4 — — — 52
TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — 52
WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — 52
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTB.
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6.3 PORTC and TRISC Registers
PORTC is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISC
(Register 6-12). Setting a TRISC bit (= 1) will make the
corresponding PORTC pin an input (i.e., put the
corresponding output driver in a High Impedance mode).
Clearing a TRISC bit (= 0) will make the corresponding
PORTC pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 6-3 shows how to initialize PORTC.
Reading the PORTC register (Register 6-11) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch.
The TRISC register (Register 6-12) controls the PORTC
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISC register are set when using them as analog
inputs. I/O pins configured as analog input always read
0’.
EXAMPLE 6-3: INITIALIZING PORTC
6.3.1 ANSELC REGISTER
The ANSELC register (Register 6-13) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELC bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELC bits has no effect on digital
output functions. A pin with TRIS clear and ANSELC
set will still operate as a digital output, but the Input
mode will be analog. This can cause unexpected
behavior when executing read-modify-write
instructions on the affected port.
BANKSEL PORTC ;
CLRF PORTC ;Init PORTC
BANKSEL TRISC ;
MOVLW B‘00001100’ ;Set RC<3:2> as inputs
MOVWF TRISC ;and set RC<7:4,1:0>
;as outputs
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DS40001430F-page 58 2010-2015 Microchip Technology Inc.
REGISTER 6-11: PORTC: PORTC REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits
1 = Port pin is > VIH
0 = Port pin is < VIL
REGISTER 6-12: TRISC: PORTC TRI-STATE REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
REGISTER 6-13: ANSELC: ANALOG SELECT REGISTER FOR PORTC
R/W-1 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1
ANSC7 ANSC6 ANSC3 ANSC2 ANSC1 ANSC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 ANSC<7:6>: Analog Select between Analog or Digital Function on Pins RB<7:6>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 5-4 Unimplemented: Read as0
bit 3-0 ANSC<3:0>: Analog Select between Analog or Digital Function on Pins RC<3:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry. Weak pull-ups, if available,
are unaffected. The corresponding TRIS bit must be set to Input mode by the user in order to allow external
control of the voltage on the pin.
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6.3.2 RC0/AN4
Figure 6-11 shows the diagram for this pin. The RC0 pin
is configurable to function as one of the following:
General purpose I/O
Analog input for the A/D
6.3.3 RC1/AN5
Figure 6-11 shows the diagram for this pin. The RC1 pin
is configurable to function as one of the following:
General purpose I/O
Analog input for the A/D
6.3.4 RC2/AN6
Figure 6-12 shows the diagram for this pin. The RC2
pin is configurable to function as one of the following:
General purpose I/O
Analog input for the A/D
6.3.5 RC3/AN7
Figure 6-12 shows the diagram for this pin. The RC3 pin
is configurable to function as one of the following:
General purpose I/O
Analog input for the A/D
6.3.6 RC4
Figure 6-13 shows the diagram for this pin. The RC4 pin
functions as one of the following:
General purpose I/O
6.3.7 RC5/CCP1
Figure 6-14 shows the diagram for this pin. The RC5 pin
is configurable to function as one of the following:
General purpose I/O
Capture, Compare or PWM (one output)
6.3.8 RC6/AN8/SS
Figure 6-15 shows the diagram for this pin. The RC6 pin
is configurable to function as one of the following:
General purpose I/O
Analog input for the A/D
•SS
input to SSP
6.3.9 RC7/AN9/SDO
Figure 6-16 shows the diagram for this pin. The RC7 pin
is configurable to function as one of the following:
General purpose I/O
Analog input for the A/D
SDO output of SSP
FIGURE 6-11: BLOCK DIAGRAM OF RC0
AND RC1
FIGURE 6-12: BLOCK DIAGRAM OF RC2
AND RC3
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
WR
PORTC
WR
TRISC
RD
TRISC
To A/D Converter
RD
PORTC
Analog Input
mode(1)
Note 1: ANSEL determines Analog Input mode.
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
WR
PORTC
WR
TRISC
RD
TRISC
RD
PORTC
Analog Input
mode(1)
Note 1: ANSEL determines Analog Input mode.
I/O Pin
To A/D Converter
PIC16(L)F720/721
DS40001430F-page 60 2010-2015 Microchip Technology Inc.
FIGURE 6-13: BLOCK DIAGRAM OF RC4
FIGURE 6-14: BLOCK DIAGRAM OF RC5
FIGURE 6-15: BLOCK DIAGRAM OF RC6
FIGURE 6-16: BLOCK DIAGRAM OF RC7
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
WR
PORTC
WR
TRISC
RD
TRISC
RD
PORTC
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data bus
WR
PORTC
WR
TRISC
RD
TRISC
RD
PORTC
CCP1OUT
CCP1OUT
Enable
0
1
1
0I/O Pin
To CCP1 input
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
WR
PORTC
WR
TRISC
RD
TRISC
To A/D Converter
RD
PORTC
Analog Input
mode(1)
To SS Input
Note 1: ANSEL determines Analog Input mode.
I/O Pin
0
1
1
0
SDO
PORT/SDO
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
WR
PORTC
WR
TRISC
RD
TRISC
To A/D Converter
RD
PORTC
Analog Input
mode(1)
Note 1: ANSEL determines Analog Input mode.
I/O Pin
Select
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TABLE 6-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on
Page
ANSELC ANSC7 ANSC6 ANSC3 ANSC2 ANSC1 ANSC0 58
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 58
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 58
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTC.
V MUX MUX
PIC16(L)F720/721
DS40001430F-page 62 2010-2015 Microchip Technology Inc.
7.0 OSCILLATOR MODULE
7.1 Overview
The oscillator module has a variety of clock sources and
selection features that allow it to be used in a range of
applications while maximizing performance and
minimizing power consumption. Figure 7-1 illustrates a
block diagram of the oscillator module.
The system can be configured to use an internal
calibrated high-frequency oscillator as clock source, with
a choice of selectable speeds via software. In addition,
the system can also be configured to use an external
clock source via the CLKIN pin.
Clock source modes are configured by the FOSC bits
in Configuration Word 1 (CONFIG1). The oscillator
module can be configured for one of the following
modes of operation.
1. EC – CLKOUT function on RA4/CLKOUT pin,
CLKIN on RA5/CLKIN.
2. EC – I/O function on RA4/CLKOUT pin, CLKIN
on RA5/CLKIN.
3. INTOSC – CLKOUT function on RA4/CLKOUT
pin, I/O function on RA5/CLKIN
4. INTOSCIO – I/O function on RA4/CLKOUT pin,
I/O function on RA5/CLKIN
FIGURE 7-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
(CPU and Peripherals)
CLKIN EC
System Clock
Postscaler
MUX
MUX
16 MHz/500 kHz
8 MHz/250 kHz
4 MHz/125 kHz
2 MHz/62.5 kHz
IRCF<1:0>
11
10
01
00
FOSC<1:0>
(Configuration Word 1)
Internal Oscillator (OSCCON Register)
500 kHz INTOSC
32x
MUX
0
1
PLL
PLLEN
(Configuration Word 1)
MFINTOSC
HFINTOSC
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7.2 Clock Source Modes
Clock source modes can be classified as external or
internal.
Internal clock source (INTOSC) is contained
within the oscillator module and derived from a
500 kHz high-precision oscillator. The oscillator
module has eight selectable output frequencies,
with a maximum internal frequency of 16 MHz.
The External Clock mode (EC) relies on an
external signal for the clock source.
The system clock can be selected between external or
internal clock sources via the FOSC bits of the
Configuration Word 1.
7.3 Internal Clock Modes
The oscillator module has eight output frequencies
derived from a 500 kHz high-precision oscillator. The
IRCF bits of the OSCCON register select the
postscaler applied to the clock source dividing the
frequency by 1, 2, 4 or 8. Setting the PLLEN bit of the
Configuration Word 1 locks the internal clock source to
16 MHz before the postscaler is selected by the IRCF
bits. The PLLEN bit must be set or cleared at the time
of programming; therefore, only the upper or low four
clock source frequencies are selectable in software.
The internal oscillator block has one internal oscillator
and a dedicated Phase-Locked Loop that are used to
generate two internal system clock sources: the 16
MHz High-Frequency Internal Oscillator (HFINTOSC)
and the 500 kHz (MFINTOSC). Both can be user-
adjusted via software using the OSCTUNE register
(Register 7-2).
7.3.1 INTOSC AND INTOSCIO MODES
The INTOSC and INTOSCIO modes configure the
internal oscillators as system clock source when the
device is programmed using the oscillator selection or
the FOSC<1:0> bits in the CONFIG1 register. See
Section 8.0 “Device Configuration” for more
information.
In INTOSC mode, CLKIN is available for general
purpose I/O. CLKOUT outputs the selected internal
oscillator frequency divided by 4. The CLKOUT signal
may be used to provide a clock for external circuitry,
synchronization, Calibration, test or other application
requirements.
In INTOSCIO mode, CLKIN and CLKOUT are available
for general purpose I/O.
7.3.2 FREQUENCY SELECT BITS (IRCF)
The output of the 500 kHz MFINTOSC and 16 MHz
HFINTOSC, with Phase-Locked Loop enabled, con-
nect to a postscaler and multiplexer (see Figure 7-1).
The Internal Oscillator Frequency Select bits (IRCF) of
the OSCCON register select the frequency output of
the internal oscillator. Depending upon the PLLEN bit,
one of four frequencies of two frequency sets can be
selected via software:
If PLLEN = 1, HFINTOSC frequency selection is as
follows:
•16 MHz
8 MHz (default after Reset)
•4 MHz
•2 MHz
If PLLEN = 0, MFINTOSC frequency selection is as
follows:
•500 kHz
250 kHz (default after Reset)
•125 kHz
•62.5 kHz
There is no start-up delay before a new frequency
selected in the IRCF bits takes effect. This is because
the old and new frequencies are derived from INTOSC
via the postscaler and multiplexer.
Start-up delay specifications are located in the
Table 23-2 in Section 23.0 “Electrical
Specifications”.
7.3.3 INTERNAL OSCILLATOR STATUS
BITS
The internal oscillator (500 kHz) is a factory-calibrated
internal clock source. The frequency can be altered via
software using the OSCTUNE register (Register 7-2).
The Internal Oscillator Status Locked bit (ICSL) of the
OSCCON register indicates when the internal oscillator
is running within 2% of its final value.
The Internal Oscillator Status Stable bit (ICSS) of the
OSCCON register indicates when the internal oscillator
is running within 0.5% of its final value.
Note: Following any Reset, the IRCF<1:0> bits
of the OSCCON register are set to ‘10’ and
the frequency selection is set to 8 MHz or
250 kHz. The user can modify the IRCF
bits to select a different frequency.
When PLLEN : 7 16 MHZ HF‘NTOSC When PLLEN : 7 500 kHz MFINTOSC
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DS40001430F-page 64 2010-2015 Microchip Technology Inc.
7.4 Oscillator Control
The Oscillator Control (OSCCON) register (Figure 7-1)
displays the status and allows frequency selection of the
internal oscillator (INTOSC) system clock. The
OSCCON register contains the following bits:
Frequency selection bits (IRCF)
Status Locked bits (ICSL)
Status Stable bits (ICSS)
REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER
U-0 U-0 R/W-1 R/W-0 R-q R-q U-0 U-0
IRCF1 IRCF0 ICSL ICSS — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
q = Value depends on condition
bit 7-6 Unimplemented: Read as ‘0
bit 5-4 IRCF<1:0>: Internal Oscillator Frequency Select bits
When PLLEN = 1 (16 MHz HFINTOSC)
11 =16MHz
10 =8MHz (default)
01 =4MHz
00 =2MHz
When PLLEN = 0 (500 kHz MFINTOSC)
11 =500kHz
10 = 250 kHz (default)
01 =125kHz
00 =62.5kHz
bit 3 ICSL: Internal Clock Oscillator Status Locked bit
1 = 16 MHz/500 kHz internal oscillator is at least 2% accurate
0 = 16 MHz/500 kHz internal oscillator not 2% accurate
bit 2 ICSS: Internal Clock Oscillator Status Stable bit
1 = 16 MHz/500 kHz internal oscillator is at least 0.5% accurate
0 = 16 MHz/500 kHz internal oscillator not 0.5% accurate
bit 1-0 Unimplemented: Read as ‘0
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7.5 Oscillator Tuning
The INTOSC is factory-calibrated but can be adjusted
in software by writing to the OSCTUNE register
(Register 7-2).
The default value of the OSCTUNE register is ‘0’. The
value is a 6-bit two’s complement number.
When the OSCTUNE register is modified, the INTOSC
frequency will begin shifting to the new frequency. Code
execution continues during this shift. There is no
indication that the shift has occurred.
REGISTER 7-2: OSCTUNE: OSCILLATOR TUNING REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TUN5 TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0
bit 5-0 TUN<5:0>: Frequency Tuning bits
01 1111 = Maximum frequency
01 1110 =
00 0001 =
00 0000 = Oscillator module is running at the factory-calibrated frequency.
11 1111 =
10 0000 = Minimum frequency
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7.6 External Clock Modes
7.6.1 EC MODE
The External Clock (EC) mode allows an externally
generated logic level as the system clock source. When
operating in this mode, an external clock source is
connected to the CLKIN input and the CLKOUT is
available for general purpose I/O. Figure 7-2 shows the
pin connections for EC mode.
FIGURE 7-2: EXTERNAL CLOCK (EC)
MODE OPERATION
TABLE 7-2: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES
CLKIN
CLKOUT
I/O
Clock from
Ext. System PIC® MCU
TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on
Page
OSCCON IRCF1 IRCF0 ICSL ICSS — — 64
OSCTUNE TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 65
Legend: x = unknown, u = unchanged, = unimplemented locations read as ‘0’. Shaded cells are not used by
clock sources.
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register
on Page
CONFIG1 13:8 PLLEN BOREN1 BOREN0 68
7:0 CP MCLRE PWRTE WDTEN —FOSC1FOSC0
CONFIG2 13:8 — — 69
7:0 — — WRT1 WRT0
Legend: = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
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8.0 DEVICE CONFIGURATION
Device configuration consists of Configuration Word 1
and Configuration Word 2 registers, code protection
and Device ID.
8.1 Configuration Words
There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1
register at 2007h and Configuration Word 2 register at
2008h. These registers are only accessible during
programming.
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REGISTER 8-1: CONFIGURATION WORD 1
U-1 R/P-1 U-1 U-1 R/P-1 R/P-1
PLLEN —BOREN1BOREN0
bit 13 bit 8
U-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1
—CPMCLRE PWRTE WDTEN —FOSC1FOSC0
bit 7 bit 0
Legend: P = Programmable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 13 Unimplemented: Read as ‘1
bit 12 PLLEN: INTOSC PLL Enable bit
0 = INTOSC frequency is up to 500 kHz (Max. MFINTOSC)
1 = INTOSC frequency is up to 16 MHz (Max. HFINTOSC)
bit 11-10 Unimplemented: Read as ‘1
bit 9-8 BOREN<1:0>: Brown-out Reset Enable bits(1)
0x = Brown-out Reset disabled
10 = Brown-out Reset enabled during operation and disabled in Sleep
11 = Brown-out Reset enabled
bit 7 Unimplemented: Read as ‘1
bit 6 CP: Flash Program Memory Code Protection bit
0 = Program Memory code protection is enabled
1 = Program Memory code protection is disabled
bit 5 MCLRE: MCLR/VPP Pin Function Select bit
1 =MCLR
/VPP pin function is MCLR; Weak pull-up enabled.
0 =MCLR
/VPP pin function is digital input; MCLR internally disabled; Weak pull-up disabled
bit 4 PWRTE: Power-up Timer Enable bit
0 = PWRT enabled
1 = PWRT disabled
bit 3 WDTEN: Watchdog Timer Enable bit
0 = WDT disabled
1 = WDT enabled
bit 2 Unimplemented: Read as ‘1
bit 1-0 FOSC<1:0>: Oscillator Selection bits
11 = EC oscillator: CLKOUT function on CLKOUT pin, and CLKIN function on CLKIN pin
10 = EC oscillator: I/O function on CLKOUT pin, and CLKIN function on CLKIN pin
01 = INTOSC oscillator: CLKOUT function on CLKOUT pin, and I/O function on CLKIN pin
00 = INTOSCIO oscillator: I/O function on CLKOUT pin, and I/O function on CLKIN pin
Note 1: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled.
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REGISTER 8-2: CONFIGURATION WORD 2
U-1 U-1 U-1 U-1 U-1 U-1
— —
bit 13 bit 8
U-1 U-1 U-1 Reserved U-1 U-1 R/P-1 R/P-1
WRT1 WRT0
bit 7 bit 0
Legend: P = Programmable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 13-5 Unimplemented: Read as ‘1
bit 4 Reserved: Maintain as1
bit 3-2 Unimplemented: Read as ‘1
bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits
2 kW Flash memory: PIC16(L)F720:
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified by PMCON1 control
01 = 000h to 3FFh write-protected, 400h to 7FFh may be modified by PMCON1 control
00 = 000h to 7FFh write-protected, no addresses may be modified by PMCON1 control
4 kW Flash memory: PIC16(L)F721:
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to FFFh may be modified by PMCON1 control
01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by PMCON1 control
00 = 000h to FFFh write-protected, no addresses may be modified by PMCON1 control
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8.2 Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out using ICSP™ for verification purposes.
8.3 User ID
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during Program/Verify mode. Only
the Least Significant 7 bits of the ID locations are
reported when using MPLAB® X IDE. See the
PIC16(L)F720/721 Flash Memory Programming
Specification” (DS41409) for more information.
Note: The entire Flash program memory will be
erased when the code protection is turned
off. See the “PIC16(L)F720/721 Flash
Memory Programming Specification”
(DS41409) for more information.
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9.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows the
conversion of an analog input signal to a 8-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 8-bit binary result via successive
approximation and stores the conversion result into the
ADC result register (ADRES). Figure 9-1 shows the
block diagram of the ADC.
The ADC voltage reference, FVREF, is an internally
generated supply only.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
FIGURE 9-1: ADC BLOCK DIAGRAM
AN0
AN1
AN2
AN4
ADON
GO/DONE
CHS<3:0>
VSS
AN5
AN6
AN7
AN3
AN8
AN9
AN10
AN11
Temperature Indicator
FVREF
0000
0001
0010
0011
0100
0101
0111
0110
1000
1001
1010
1011
1110
1111
8
ADC
ADRES
VDD
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9.1 ADC Configuration
When configuring and using the ADC, the following
functions must be considered:
Port Configuration
Channel selection
ADC conversion clock source
Interrupt control
9.1.1 PORT CONFIGURATION
When converting analog signals, the I/O pin selected
as the input channel should be configured for analog by
setting the associated TRIS and ANSEL bits. Refer to
Section 6.0 “I/O Ports” for more information.
9.1.2 CHANNEL SELECTION
There are 14 channel selections available:
-AN<11:0> pins
- Temperature Indicator
- FVR (Fixed Voltage Reference) Output
Refer to Section 11.0 “Temperature Indicator Mod-
ule” and Section 10.0 “Fixed Voltage Reference” for
more information on these channel selections.
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 9.2
“ADC Operation” for more information.
9.1.3 CONVERSION CLOCK
The source of the conversion clock is software-
selectable via the ADCS bits of the ADCON1 register.
There are seven possible clock options:
•F
OSC/2
•FOSC/4
•FOSC/8
•F
OSC/16
•FOSC/32
•FOSC/64
•F
RC (dedicated internal oscillator)
The time to complete one bit conversion is defined as
TAD. One full 8-bit conversion requires 10 TAD periods
as shown in Figure 9-2.
For correct conversion, the appropriate TAD
specification must be met. Refer to the A/D conversion
requirements in Section 23.0 “Electrical
Specifications” for more information. Table 9-1 gives
examples of appropriate ADC clock selections.
Note: Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
Note: Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD) Device Frequency (FOSC)
ADC
Clock Source ADCS<2:0> 16 MHz 8 MHz 4 MHz 1 MHz
FOSC/2 000 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s
FOSC/4 100 250 ns(2) 500 ns(2) 1.0 s4.0 s
FOSC/8 001 0.5 s(2) 1.0 s2.0 s8 s(5)
FOSC/16 101 1.0 s2.0 s4.0 s16.0 s(5)
FOSC/32 010 2.0 s4.0 s8 s(5) 32.0 s(3)
FOSC/64 110 4.0 s8 s(5) 16.0 s(5) 64.0 s(3)
FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4)
Legend: Shaded cells are outside of the recommended range.
Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be performed during Sleep.
5: Recommended values for VDD 2.0V and temperature -40°C to 85°C. The 16.0 s setting should be
avoided for temperature > 85°C.
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FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
9.1.4 INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the GIE and PEIE bits of the INTCON
register must be disabled. If the GIE and PEIE bits of
the INTCON register are enabled, execution will switch
to the Interrupt Service Routine.
Please refer to Section 9.1.4 “Interrupts” for more
information.
9.2 ADC Operation
9.2.1 STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will start the
Analog-to-Digital conversion.
9.2.2 COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
Clear the GO/DONE bit
Set the ADIF Interrupt Flag bit
Update the ADRES register with new conversion
result
9.2.3 TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRES register will be updated with the partially
complete Analog-to-Digital conversion sample.
Incomplete bits will match the last bit converted.
TAD1 TAD2 TAD3TAD4TAD5 TAD6TAD7 TAD8 TAD9
Set GO/DONE bit
Holding Capacitor is disconnected from Analog Input (typically 100 ns)
b7 b6 b5 b4 b3 b2 b1 b0
TCY to TAD
Conversion Starts
ADRES register is loaded,
GO/DONE bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input
TAD0
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
Note: The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 9.2.6 “A/D Conversion
Procedure”.
Note: A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
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9.2.4 ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present
conversion to be aborted and the ADC module is
turned off, although the ADON bit remains set.
9.2.5 SPECIAL EVENT TRIGGER
The Special Event Trigger of the CCP module allows
periodic ADC measurements without software
intervention. When this trigger occurs, the GO/DONE
bit is set by hardware and the Timer1 counter resets to
zero.
Using the Special Event Trigger does not assure proper
ADC timing. It is the user’s responsibility to ensure that
the ADC timing requirements are met.
Refer to Section 15.0 “Capture/Compare/PWM
(CCP) Module” for more information.
9.2.6 A/D CONVERSION PROCEDURE
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
1. Configure Port:
Disable pin output driver (Refer to the TRIS
register)
Configure pin as analog (Refer to the ANSEL
register)
2. Configure the ADC module:
Select ADC conversion clock
Select ADC input channel
Turn on ADC module
3. Configure ADC interrupt (optional):
Clear ADC interrupt flag
Enable ADC interrupt
Enable peripheral interrupt
Enable global interrupt(1)
4. Wait the required acquisition time(2).
5. Start conversion by setting the GO/DONE bit.
6. Wait for ADC conversion to complete by one of
the following:
Polling the GO/DONE bit
Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result.
8. Clear the ADC interrupt flag (required if interrupt
is enabled).
EXAMPLE 9-1: A/D CONVERSION
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 9.3 “A/D Acquisition
Requirements.
;This code block configures the ADC
;for polling, Vdd reference, Frc clock
;and AN0 input.
;
;Conversion start & polling for completion
; are included.
;
BANKSEL ADCON1 ;
MOVLW B’01110000’ ;ADC Frc clock,
;VDD reference
MOVWF ADCON1 ;
BANKSEL TRISA ;
BSF TRISA,0 ;Set RA0 to input
BANKSEL ANSELA ;
BSF ANSELA,0 ;Set RA0 to analog
BANKSEL ADCON0 ;
MOVLW B’00000001’;AN0, On
MOVWF ADCON0 ;
CALL SampleTime ;Acquisiton delay
BSF ADCON0,GO ;Start conversion
BTFSC ADCON0,GO ;Is conversion done?
GOTO $-1 ;No, test again
BANKSEL ADRES ;
MOVF ADRES,W ;Read result
MOVWF RESULT ;store in GPR space
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9.2.7 ADC REGISTER DEFINITIONS
The following registers are used to control the
operation of the ADC.
REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0
bit 5-2 CHS<3:0>: Analog Channel Select bits
0000 =AN0
0001 =AN1
0010 =AN2
0011 =AN3
0100 =AN4
0101 =AN5
0110 =AN6
0111 =AN7
1000 =AN8
1001 =AN9
1010 =AN10
1011 =AN11
1110 = Temperature Indicator(1)
1111 = Fixed Voltage Reference (FVREF)(2)
bit 1 GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
Note 1: See Section 11.0 “Temperature Indicator Module” for more information.
2: See Section 10.0 “Fixed Voltage Reference” for more information.
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REGISTER 9-2: ADCON1: A/D CONTROL REGISTER 1
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0