DALC208 Datasheet by STMicroelectronics

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I Lower PCB area consumption versus discrete solution Complies with the following standards I IE0610007472 level 4 l MIL STD 883G7Method 30157: class 3, human body model Applications Where ESD and/or over and undershoot protection for dalalines is required: Sensitive logic input protection Microprocessor based equipment Audio / video inputs Portable electronics Networks ISDN equipment USB interface March 2008 ULI Description The DALCZOSSCS diode array is protect components which are c and transmission lines from over by electrostatic discharge (ESD) transients. It is a railrtorrail prole suited for overshoot and unders on senSitive logic inputs. The low capacitance ol the DAL prevents significant signal dislor Flev 7
March 2008 Rev 7 1/14
14
DALC208
Low capacitance diode array
Features
Protection of 4 lines
Peak reverse voltage: VRRM = 9 V per diode
Very low capacitance per diode: C < 5 pF
Very low leakage current: IR < 1 µA
Benefits
Cost-effective solution compared with discrete
solution
High efficiency in ESD suppression
No significant signal distortion thanks to very
low capacitance
High reliability offered by monolithic integration
Lower PCB area consumption versus discrete
solution
Complies with the following standards
IEC61000-4-2 level 4
MIL STD 883G-Method 3015-7: class 3,
human body model
Applications
Where ESD and/or over and undershoot
protection for datalines is required:
Sensitive logic input protection
Microprocessor based equipment
Audio / video inputs
Portable electronics
Networks
ISDN equipment
USB interface
Figure 1. Functional diagram
Description
The DALC208SC6 diode array is designed to
protect components which are connected to data
and transmission lines from over voltages caused
by electrostatic discharge (ESD) or other
transients. It is a rail-to-rail protection device also
suited for overshoot and undershoot suppression
on sensitive logic inputs.
The low capacitance of the DALC208SC6
prevents significant signal distortion.
1
SOT23-6L
(Plastic)
I/O 1
I/O 2 I/O 3
I/O 4
REF 2 REF 1
www.st.com
Tamb Tamb I/O REF1 if +V CC 2/14
Characteristics DALC208
2/14
1 Characteristics
Figure 2. Input capacitance measurement
Table 1. Absolute maximum ratings (Tamb = 25 °C)
Symbol Parameter Value Unit
VPP
IEC61000-4-2, air discharge
IEC61000-4-2, contact discharge
15
8kV
VRRM Peak reverse voltage per diode 9 V
ΔVREF Reference voltage gap between VREF2 and VREF1 9V
VIn max. Maximum operating signal input voltage VREF2 V
VIn min. Minimum operating signal input voltage VREF1 V
IFContinuous forward current (single diode loaded) 200 mA
IFRM Repetitive peak forward current (tp = 5 ms, F = 50 kHz) 700 mA
IFSM
Surge non repetitive forward current - rectangular waveform (See
curve on Figure 3.)
tp = 2.5 µs
tp = 1 µs
tp = 100 µs
6
2
1
A
Tstg
Tj
Storage temperature range
Maximum junction temperature
-55 to + 150
150
°C
°C
Table 2. Thermal resistance
Symbol Parameter Value Unit
Rth(j-a) Junction to ambient (1) 500 °C/W
1. Device mounted on FR4 PCB with recommended footprint dimensions.
Table 3. Electrical characteristics (Tamb = 25 °C)
Symbol Parameter Conditions Typ. Max. Unit
VFForward voltage IF = 50 mA 1.2 V
IRReverse leakage current per diode VR = 5 V 1 µA
C Input capacitance between Line and GND See Figure 2.7 10pF
G
REF1
I/O +V CC
REF1 connected to GND
REF2 connected to +Vcc
Input applied :
Vcc = 5 V, Vsign = 30 mV, F = 1 MHz
REF2
VR
DALC208 Characteristics
3/14
Figure 3. Maximum non-repetitive peak
forward current versus rectangular
pulse duration (Tj initial = 25 °C)
Figure 4. Reverse clamping voltage versus
peak pulse current
(Tj initial = 25 °C), typical values.
Rectangular waveform tp = 2.5 ms
0.001 0.01 0.1 1 10 100 1000
0
1
2
3
4
5
6
7
8
t (ms)
p
I (A)
FSM
I/O vs
REF1 or
REF2
5 1015202530
0.1
1.0
2.0
V (V)
CL
I (A)
pp
tp=2.5µs
I/O vs REF1
or REF2
Figure 5. Variation of leakage current versus
junction temperature
(typical values)
Figure 6. Input capacitance versus reverse
applied voltage (typical values)
Figure 7. Peak forward voltage drop versus
peak forward current
(typical values),
rectangular waveform tp = 2.5 ms
25 50 75 100 125 150
0.01
0.1
1
10
100
T (°C)
j
IR(µA)
012345
5.0
5.5
6.0
6.5
7.0
7.5
8.0
V (V)
R
C(pF)
F=1MHz
Vsign=30mV
Vref1/ref2=5V
0 2 4 6 8 10 12 14 16 18 20
0.1
1.0
10.0
V (V)
FM
I (A)
FM
Tj=25°C
Tj=150°C
I/O vs REF 1
or REF2
Technical information DALC208
4/14
2 Technical information
2.1 Surge protection
The DALC208SC6 is particularly optimized to perform surge protection based on the rail to
rail topology.
The clamping voltage VCL can be calculated as follow :
VCL+ = VREF2 + VF for positive surges
VCL- = VREF1 - VF for negative surges
with
VF = VT + Rd.Ip
(VF forward drop voltage) / (VT forward drop threshold voltage)
According to the curve Figure 7 we assume that the value of the dynamic resistance of the
clamping diode is typically Rd = 0.7 Ω and VT = 1.2 V.
For an IEC 61000-4-2 surge Level 4 (Contact Discharge: Vg=8 kV, Rg=330 Ω), VREF2 = +5 V,
VREF1 = 0 V, and if in first approximation, we assume that : Ip = Vg / Rg 24 A.
So, we find:
–V
CL++23V
–V
CL- -18V
Note: The calculations do not take into account phenomena due to parasitic inductances.
2.2 Surge protection application example
If we consider that the connections from the pin REF2 to VCC and from REF1 to GND are
done by two tracks of 10 mm long and 0.5 mm large; we assume that the parasitic
inductances of these tracks are about 6 nH. So when an IEC 61000-4-2 surge occurs, due
to the rise time of this spike (tr = 1 ns), the voltage VCL has an extra value equal to Lw.dI/dt.
The dI/dt is calculated as: dI/dt = Ip/tr 24 A/ns
The overvoltage due to the parasitic inductances is: Lw.dI/dt = 6 x 24 144V
By taking into account the effect of these parasitic inductances due to unsuitable layout, the
clamping voltage will be :
–V
CL+ = +23 + 144 167V
–V
CL- = -18 - 144 -162V
We can reduce as much as possible these phenomena with simple layout optimization.
It’s the reason why some recommendations have to be followed (See Section 2.3: How to
ensure good ESD protection).
DALC208 Technical information
5/14
Figure 8. ESD behavior: parasitic phenomena due to unsuitable layout
2.3 How to ensure good ESD protection
While the DALC208SC6 provides a high immunity to ESD surge, an efficient protection
depends on the layout of the board. In the same way, with the rail to rail topology, the track
from the VREF2 pin to the power supply +VCC and from the VREF1 pin to GND must be as short
as possible to avoid over voltages due to parasitic phenomena. See Figure 8.
It’s often harder to connect the power supply near to the DALC208SC6 unlike the ground
thanks to the ground plane that allows a short connection.
To ensure the same efficiency for positive surges when the connections can’t be short
enough, we recommend putting a capacitance of 100 nF close to the DALC208SC6,
between VREF2 and ground, to prevent these kinds of overvoltage disturbances.
See Figure 9.
The addition of this capacitance will allow a better protection by providing a constant voltage
during a surge.
Figure 10, Figure 11, and Figure 12 show the improvement of the ESD protection according
to the recommendations described above.
Lw
VI/O
ESD
SURGE
REF1=GND
I/O
REF2=+Vcc
Vf Lw di
dt
Lw di
dt
Vcl+ = Vcc+Vf+Lw di
dt surge >0
-Vf- Lw di
dt surge <0
Vcl- =
t
tr=1ns
Vcc+Vf
Lw di
dt
Vcl+
POSITIVE
SURGE
167V
-Lw di
dt
t
tr=1ns
-Vf
Vcl-
NEGATIVE
SURGE
-162V
Technical infarmatian Figure 9. ESD behavior: optimized layout and Figure 10. add at a capacitance at 100 nF E5“ L" “my“ PasmvE / SW-E sums \ u 2 \ E E :I \ W 7 / E j E :I m: mm my.» 7? m v i , w n “w“ "mm: sums mew C=100nF Important A precamion to 1ake is to pu11he protecfion device as close as pos source (generaily the connecmr). Note: The measurements have been done with the DALCZOBSCS in ope 6/14 E
Technical information DALC208
6/14
Important
A precaution to take is to put the protection device as close as possible to the disturbance
source (generally the connector).
Note: The measurements have been done with the DALC208SC6 in open circuit.
Figure 9. ESD behavior: optimized layout and
add of a capacitance of 100 nF
Figure 10. ESD behavior: measurement
conditions (with coupling
capacitance)
REF1=GND
VI/O
ESD
SURGE
I/O
REF2=+Vcc
C=100nF
Lw
Vcl+ = Vcc+Vf
-Vf
surge >0
surge <0
Vcl- =
t
Vcl+
POSITIVE
SURGE
t
Vcl-
NEGATIVE
SURGE
+5V
TEST BOARD
DALC
208
ESD
SURGE
Figure 11. Remaining voltage after the
DALC208SC6 during positive ESD
surge
Figure 12. Remaining voltage after the
DALC208SC6 during negative ESD
surge
IEC61000-4-2
Air Discharge
(150pF/330Ω)
Vpp=15kV
IEC61000-4-2
Air Discharge
(150pF/330Ω)
Vpp=15kV
VMW- WW ,r :
DALC208 Crosstalk behavior
7/14
3 Crosstalk behavior
3.1 Crosstalk phenomena
Figure 13. Crosstalk phenomena
The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor (β12
or β21) increases when the gap across lines decreases, particularly in silicon dice. In the
example in Figure 13 the expected signal on load RL2 is α2VG2, in fact the real voltage at this
point has got an extra value β21VG1. This part of the VG1 signal represents the effect of the
crosstalk phenomenon of line 1 on line 2. This phenomenon has to be taken into account
when the drivers impose fast digital data or high frequency analog signals in the disturbing
line. The disturbed line will be more affected if it works with low voltage signal or high load
impedance (few kΩ). The following sections give the value of both digital and analog
crosstalk.
3.2 Digital crosstalk
Figure 14 shows the measurement circuit used to quantify the crosstalk effect in a classical
digital application. Figure 15 shows that in such a condition: signal from 0 V to 5 V and a rise
time of 5 ns, the impact on the disturbed line is less than 100mV peak to peak. No data
disturbance was noted on the concerned line. The same results were obtained with falling
edges.
Line 1
Line 2
VG1
VG2
RG1
RG2
DRIVERS
RL1
RL2
RECEIVERS
αβ
+
1
12
VG1 VG2
αβ
+
221
VG2 VG1
Figure 14. Digital crosstalk measurements Figure 15. Digital crosstalk results
DALC208SC6
100nF
+5V
Line 1
Line 2
V
G1
β21 V
G1
+5V +5V
74HC04
+5V
Square
Pulse
Generator
5KHz
74HC04
Crosstalk behavior Note: 3.3 The measurements have been done in the worst case i. e. on two ad/ac 1/04). Analog crosstalk Figure 16. Analog crosstalk measurements l—l 2 %22'2 Figure 155hows the measurement cwrcmtlorihe analog application. F0 range of analog signals (up 10 100MHz) the eflect on disturbed line is | See Figure 17. 8/14 As the DALCZOBSCG lS designed to protect high speed data lines, it m transmission of operating signals. The altenuation curve give such an Figure 1Bshows that the DALCZOBSCG lS well suitable lor data line ira 100 Mbit/s while it works as a filter for undesxrable Signals such as GSM
Crosstalk behavior DALC208
8/14
Note: The measurements have been done in the worst case i.e. on two adjacent cells (I/O1 and
I/O4).
3.3 Analog crosstalk
Figure 16. Analog crosstalk measurements
Figure 16 shows the measurement circuit for the analog application. For the usual frequency
range of analog signals (up to 100MHz) the effect on disturbed line is less than -45 dBm.
See Figure 17.
As the DALC208SC6 is designed to protect high speed data lines, it must ensure a good
transmission of operating signals. The attenuation curve give such an information.
Figure 18 shows that the DALC208SC6 is well suitable for data line transmission up to
100 Mbit/s while it works as a filter for undesirable signals such as GSM carrier (900 MHz).
SPECTRUM ANALYSER
Vout
50Ω
TRACKING GENERATOR
Vg Vin
50Ω
TEST BOARD
+5V
DALC
208
C=100nF
Figure 17. Analog crosstalk results Figure 18. DALC208SC6 attenuation
1 10 100 1,000
-100
-80
-60
-40
-20
0
f(MHz)
dBm
1 10 100 1,000
-30
-20
-10
0
f(MHz)
dBm
Figure 21. USB part protection DATA TRANSCEIVER “x ‘1‘ 3H? sMPvi-a Figure 22. Analher way (a cannect the DALCZIJSSCS 1 T Note n Is absmme‘y necessary to connect me pm 5(REF1HQ GND‘
DALC208 Application examples
9/14
4 Application examples
Figure 19. Video line protection
Figure 22. Another way to connect the DALC208SC6
Pin N° Signal
1 RED VIDEO
2 GREEN VIDEO
or COMPOSITE SYNC with GREEN VIDEO
3 BLUE VIDEO
4 GROUND
5 DDC (Display Data Channel) GROUND
6 RED GROUND
7 GREEN GROUND
8 BLUE GROUND
9 NC
10 SYNC GROUND
11 GROUND
12 SDA (Sérial Data)
13 HORIZONTAL SYNC
or COMPOSITE SYNC
14 VERTICAL SYNC (VCLK)
15 SCL (Serial Clock)
DALC
208
+Vcc
1
15
5
DALC
208
+Vcc
100nF
100nF
Figure 20. T1/E1 protection Figure 21. USB port protection
DALC
208
+Vcc
100nF
DATA
TRANSCEIVER
SMP75-8
SMP75-8
Tx
Rx
USB
TRANS-
CEIVER
USB
TRANS-
CEIVER
DALC
208 +V
1.5k
(1)
1.5k
(2)
+V
VBUS
D+
D-
GND
VBUS
D+
D-
GND
15k 15k (1) Full speed
only
(2) Low speed
only
100nF
Note It is absolutely necessary to connect
the pin 5 (REF1) to GND !
DALC208
I/O2 I/O1
I/O3 I/O4
GND
no Dneg n.5u 1.45mi o 50 1 on we" ((ns) This simulation model is available only for an ambient temperature of 27 ”C. Th done (Figure 24, Figure 25 and Figure 26) show that the PSpice model is 0/03 product oeha vior. Voltage -zu -30 100 t to 100 I 00 f(MH1)
PSpice model DALC208
10/14
5 PSpice model
Figure 23 shows the PSpice model of one DALC208SC6 cell. In this model, the diodes are
defined by the PSpice parameters given in Ta bl e 4 .
Note: This simulation model is available only for an ambient temperature of 27 °C. The simulations
done (Figure 24, Figure 25 and Figure 26) show that the PSpice model is close to the
product behavior.
Figure 23. PSpice model of one DALC208SC6
cell
Figure 24. PSpice model simulation: surge > 0
IEC 61000-4-2 contact discharge
response
Vref2
Vref1
I/O
Dpos
Dneg
0.3Ω
0.5Ω
0.8nH
1.45nH
0.8nH 0.3Ω
0 50 100
0
10
20
30
40
50
60
t(ns)
Current (A) / Voltage (V)
Current
Surge
I/O
Voltage
Figure 25. PSpice model simulation: surge < 0
IEC61000-4-2 contact discharge
response
Figure 26. Attenuation comparison
0 50 100
-50
-40
-30
-20
-10
0
t(ns)
Current (A) / Voltage (V)
Current
Surge
I/O
Voltage
1 10 100 1,000
-30
-20
-10
0
f(MHz)
dBm
Measured
PSpice
DALC208 PSpice model
11/14
Table 4. PSpice parameter
Parameter DPOS DNEG
BV 9 9
CJO 7p 7p
IBV 1u 1u
IKF 28.357E-3 1000
IS 118.78E-15 5.6524E-9
ISR 100E-12 472.3E-9
M 0.3333 0.3333
N 1.3334 2.413
NR 2 2
RS 0.68377 0.71677
VJ 0.6 0.6
Package information DALC208
12/14
6 Package information
Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
www.st.com.
Figure 27. Footprint (dimensions in mm)
Table 5. SOT23-6L dimensions
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.90 1.45 0.035 0.057
A1 0 0.10 0 0.004
A2 0.90 1.30 0.035 0.051
b 0.35 0.50 0.014 0.020
c 0.09 0.20 0.004 0.008
D 2.80 3.05 0.11 0.118
E 1.50 1.75 0.059 0.069
e 0.95 0.037
H 2.60 3.00 0.102 0.118
L 0.10 0.60 0.004 0.024
θ 10° 0° 10°
A2
A
L
H
c
b
E
D
e
e
A1
θ
0.95
0.60
1.20
1.10
3.50 2.30
DALC208 Ordering information
13/14
7 Ordering information
8 Revision history
Table 6. Ordering information
Order code Marking Package Weight Base qty Packing mode
DALC208SC6 DALC SOT23-6L 16.7 mg 3000 Tape and reel
Table 7. Document revision history
Date Revision Changes
Feb-2002 5C Last update.
28-Oct-2004 6 SOT23-6L package dimensions change for reference “D” from 3.0
millimeters (0.118 inches) to 3.05 millimeters (0.120 inches).
20-Mar-2008 7Reformatted to current standard. Added ECOPACK paragraph.
DALC208
14/14
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