IS(61,64)WV10248(A,B)LL Datasheet by ISSI, Integrated Silicon Solution Inc

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. B3
01/30/2019
Copyright © 2019 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest
version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
®Long-term Support
World Class Quality
1M x 8 HIGH-SPEED CMOS STATIC RAM JANUARY 2019
FEATURES
High-speed access times: 8, 10, 20 ns
High-performance, low-power CMOS process
Multiple center power and ground pins for greater
noise immunity
Easy memory expansion with CE and OE options
CE power-down
Fully static operation: no clock or refresh
required
TTL compatible inputs and outputs
Single power supply
Vdd 1.65V to 2.2V (IS61WV10248ALL)
speed = 20ns for Vcc = 1.65V to 2.2V
Vdd 2.4V to 3.6V (IS61/64WV10248BLL)
speed = 10ns for Vcc = 2.4V to 3.6V
speed = 8ns for Vcc = 3.3V + 5%
Packages available:
48-ball miniBGA (9mm x 11mm)
– 44-pin TSOP (Type II)
Industrial and Automotive Temperature Support
Lead-free available
DESCRIPTION
The ISSI IS61WV10248ALL/BLL and
IS64WV10248BLL are very high-speed, low
power, 1M-word by 8-bit CMOS static RAM. The
IS61WV10248ALL/BLL and IS64WV10248BLL are fab-
ricated using ISSI's high-performance CMOS technol-
ogy. This highly reliable process coupled with innovative
circuit design techniques, yields higher performance
and low power consumption devices.
When CE is HIGH (deselected), the device assumes
a standby mode at which the power dissipation can be
reduced down with CMOS input levels.
The IS61WV10248ALL/BLL and IS64WV10248BLL
operate from a single power supply and all inputs are
TTL-compatible.
The IS61WV10248ALL/BLL and IS64WV10248BLL are
available in 48 ball mini BGA and 44-pin TSOP (Type
II) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A19
CE
OE
WE
1M X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
3333333333333333333333 EEEEEEEEEEEEEEEEEEEEEE OOOOOOOO OO®©©®OO OOOQ®OOO OOO®®OOO OO®®®®OO OOOOOOOO
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Rev. B3
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IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
®Long-term Support
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PIN DESCRIPTIONS
A0-A19 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Data Input / Output
Vdd Power
GND Ground
NC No Connection
48-pin Mini BGA (M ) (9mm x 11mm) 44-pin TSOP (Type II )
1 2 3 4 5 6
A
B
C
D
E
F
G
H
NC
NC
NC
GND
V
DD
NC
NC
A18
OE
NC
NC
NC
NC
NC
NC
A8
A0
A3
A5
A17
NC
A14
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CE
I/O1
I/O3
I/O4
I/O5
WE
A11
NC
I/O0
I/O2
V
DD
GND
I/O6
I/O7
A19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A14
A13
A12
A11
A10
A19
NC
NC
44
43
42
41
PIN CONFIGURATION
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Rev. B3
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IS61WV10248BLL
IS64WV10248BLL
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ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VTERm Terminal Voltage with Respect to GND –0.5 to Vdd + 0.5 V
Vdd Vdd Relates to GND –0.3 to 4.0 V
TSTg Storage Temperature –65 to +150 °C
PT Power Dissipation 1.0 W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
TRUTH TABLE
Mode WE CE OE I/O Operation VDD Current
Not Selected X H X High-Z ISb1, ISb2
(Power-down)
Output Disabled H L H High-Z Icc
Read H L L doUT Icc
Write L L X dIn Icc
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
cIn Input Capacitance VIn = 0V 6 pF
cI/o Input/Output Capacitance VoUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°c, f = 1 MHz, Vdd = 3.3V.
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Rev. B3
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IS61WV10248BLL
IS64WV10248BLL
®Long-term Support
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OPERATING RANGE (VDD) (IS61WV10248BLL)(1)
Range Ambient Temperature VDD (8 nS) VDD (10 nS)
Commercial 0°C to +70°C 3.3V + 5% 2.4V-3.6V
Industrial –40°C to +85°C 3.3V + 5% 2.4V-3.6V
Note:
1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of
3.3V + 5%, the device meets 8ns.
OPERATING RANGE (VDD) (IS64WV10248BLL)
Range Ambient Temperature VDD (10 nS)
Automotive –40°C to +125°C 2.4V-3.6V
OPERATING RANGE (VDD) (IS61WV10248ALL)
Range Ambient Temperature VDD (20 nS)
Commercial 0°C to +70°C 1.65V-2.2V
Industrial –40°C to +85°C 1.65V-2.2V
Automotive –40°C to +125°C 1.65V-2.2V
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Rev. B3
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IS61WV10248BLL
IS64WV10248BLL
®Long-term Support
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DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 2.4V-3.6V
Symbol Parameter Test Conditions Min. Max. Unit
Voh Output HIGH Voltage Vdd = Min., Ioh = –1.0 mA 1.8 V
Vol Output LOW Voltage Vdd = Min., Iol = 1.0 mA 0.4 V
VIh Input HIGH Voltage 2.0 Vdd + 0.3 V
VIl Input LOW Voltage(1) –0.3 0.8 V
IlI Input Leakage GND VIn Vdd –1 1 µA
Ilo Output Leakage GND VoUT Vdd, Outputs Disabled –1 1 µA
Note:
1. VIl (min.) = –0.3V DC; VIl (min.) = –2.0V AC (pulse width 2 ns). Not 100% tested.
VIh (max.) = Vdd + 0.3V dc; VIh (max.) = Vdd + 2.0V Ac (pulse width 2 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 3.3V + 5%
Symbol Parameter Test Conditions Min. Max. Unit
Voh Output HIGH Voltage Vdd = Min., Ioh = –4.0 mA 2.4 V
Vol Output LOW Voltage Vdd = Min., Iol = 8.0 mA 0.4 V
VIh Input HIGH Voltage 2 Vdd + 0.3 V
VIl Input LOW Voltage(1) –0.3 0.8 V
IlI Input Leakage GND VIn Vdd –1 1 µA
Ilo Output Leakage GND VoUT Vdd, Outputs Disabled –1 1 µA
Note:
1. VIl (min.) = –0.3V DC; VIl (min.) = –2.0V AC (pulse width 2 ns). Not 100% tested.
VIh (max.) = Vdd + 0.3V dc; VIh (max.) = Vdd + 2.0V Ac (pulse width 2 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 1.65V-2.2V
Symbol Parameter Test Conditions VDD Min. Max. Unit
Voh Output HIGH Voltage Ioh = -0.1 mA 1.65-2.2V 1.4 V
Vol Output LOW Voltage Iol = 0.1 mA 1.65-2.2V 0.2 V
VIh Input HIGH Voltage 1.65-2.2V 1.4 Vdd + 0.2 V
VIl(1) Input LOW Voltage 1.65-2.2V –0.2 0.4 V
IlI Input Leakage GND VIn Vdd –1 1 µA
Ilo Output Leakage GND VoUT Vdd, Outputs Disabled –1 1 µA
Note:
1. VIl (min.) = –0.3V DC; VIl (min.) = –2.0V AC (pulse width 2 ns). Not 100% tested.
VIh (max.) = Vdd + 0.3V dc; VIh (max.) = Vdd + 2.0V Ac (pulse width 2 ns). Not 100% tested.
6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B3
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IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
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AC TEST LOADS
Figure 1.
319
5 pF
Including
jig and
scope
353
OUTPUT
3.3V
Figure 2.
Z
O
= 50
1.5V
50
OUTPUT
30 pF
Including
jig and
scope
AC TEST CONDITIONS (HIGH SPEED)
Parameter Unit Unit Unit
(2.4V-3.6V) (3.3V + 5%) (1.65V-2.2V)
Input Pulse Level 0.4V to Vdd-0.3V 0.4V to Vdd-0.3V 0.4V to Vdd-0.2V
Input Rise and Fall Times 1.5ns 1.5ns 1.5ns
Input and Output Timing Vdd/2 Vdd/2 + 0.05 Vdd/2
and Reference Level (VRef)
Output Load See Figures 1 and 2 See Figures 1 and 2 See Figures 1 and 2
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IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
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POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 -10 -20
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
Icc Vdd Dynamic Operating Vdd = Max., Com. 110 95 90 mA
Supply Current IoUT = 0 mA, f = fmAx Ind. 120 100 100
Auto. 140 140
typ.(2) 60
Icc1 Operating Vdd = Max., Com. 30 30 30 mA
Supply Current IoUT = 0 mA, f = 0 Ind. 35 35 35
Auto. 60 70
ISb1 TTL Standby Current Vdd = Max., Com. 30 30 30 mA
(TTL Inputs) VIn = VIh or VIl Ind. 35 35 35
CE VIh, f = 0 Auto. 70 70
ISb2 CMOS Standby Vdd = Max., Com. 20 20 15 mA
Current (CMOS Inputs) CE Vdd – 0.2V, Ind. 25 25 20
VIn Vdd – 0.2V, or Auto. 70 70
VIn 0.2V
, f = 0 typ.(2) 4
Note:
1. At f = fmAx, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, TA = 25oC and not 100% tested.
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Rev. B3
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IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
®Long-term Support
World Class Quality
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 -10
Symbol Parameter Min. Max. Min. Max. Unit
tRc Read Cycle Time 8 10 ns
tAA Address Access Time 8 10 ns
tohA Output Hold Time 2 2 ns
tAcE CE Access Time 8 10 ns
tdoE OE Access Time 5.5 6.5 ns
thzoE(2) OE to High-Z Output 3 4 ns
tlzoE(2) OE to Low-Z Output 0 0 ns
thzcE(2 CE to High-Z Output 0 3 0 4 ns
tlzcE(2) CE to Low-Z Output 3 3 ns
tPU Power Up Time 0 0 ns
tPd Power Down Time 8 10 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
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Rev. B3
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IS61WV10248ALL
IS61WV10248BLL
IS64WV10248BLL
®Long-term Support
World Class Quality
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-20 ns
Symbol Parameter Min. Max. Unit
tRc Read Cycle Time 20 ns
tAA Address Access Time 20 ns
tohA Output Hold Time 2.5 ns
tAcE CE Access Time 20 ns
tdoE OE Access Time 8 ns
thzoE(2) OE to High-Z Output 0 8 ns
tlzoE(2) OE to Low-Z Output 0 ns
thzcE(2 CE to High-Z Output 0 8 ns
tlzcE(2) CE to Low-Z Output 3 ns
tPU Power Up Time 0 ns
tPd Power Down Time 20 ns
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
Vdd-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
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IS61WV10248BLL
IS64WV10248BLL
®Long-term Support
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t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z DATA VALID
CE_RD2.eps
ADDRESS
OE
CE
D
OUT
t
HZCE
READ CYCLE NO. 2(1,3) (CE and OE Controlled)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIl.
3. Address is valid prior to or coincident with CE LOW transitions.
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIl)
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WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 -10
Symbol Parameter Min. Max. Min. Max. Unit
twc Write Cycle Time 8 10 ns
tScE CE to Write End 6.5 8 ns
tAw Address Setup Time 6.5 8 ns
to Write End
thA Address Hold from Write End 0 0 ns
tSA Address Setup Time 0 0 ns
tPwE1 WE Pulse Width
(OE = HIGH)
6.5 8 ns
tPwE2 WE Pulse Width (OE = LOW) 8.0 10 ns
tSd Data Setup to Write End 5 6 ns
thd Data Hold from Write End 0 0 ns
thzwE(2) WE LOW to High-Z Output 3.5 5 ns
tlzwE(2) WE HIGH to Low-Z Output 2 2 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a
Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising
or falling edge of the signal that terminates the write. Shaded area product in development
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IS61WV10248BLL
IS64WV10248BLL
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WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-20 ns
Symbol Parameter Min. Max. Unit
twc Write Cycle Time 20 ns
tScE CE to Write End 12 ns
tAw Address Setup Time 12 ns
to Write End
thA Address Hold from Write End 0 ns
tSA Address Setup Time 0 ns
tPwE1 WE Pulse Width (OE = HIGH) 12 ns
tPwE2 WE Pulse Width (OE = LOW) 17 ns
tSd Data Setup to Write End 9 ns
thd Data Hold from Write End 0 ns
thzwE(3) WE LOW to High-Z Output 9 ns
tlzwE(3) WE HIGH to Low-Z Output 3 ns
Notes:
1. Test conditions assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input
pulse levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not
100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup
and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
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AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
DATA UNDEFINED
t WC
VALID ADDRESS
t SCE
t PWE1
t PWE2
t AW
t HA
HIGH-Z
t HD
t SA
t HZWE
ADDRESS
CE
WE
D
OUT
D
IN DATA
IN
VALID
t LZWE
t SD
CE_WR1.eps
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DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR2.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > VIh.
AC WAVEFORMS
WRITE CYCLE NO. 2(1,2) (WE Controlled: OE is HIGH During Write Cycle)
t
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AC WAVEFORMS
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
DOUT
DIN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR3.eps
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DATA RETENTION WAVEFORM (CE Controlled)
V
DD
CE V
DD
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
1.65V
1.4V
Data Retention Mode
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Min. Max. Unit
VdR Vdd for Data Retention See Data Retention Waveform 1.2 3.6 V
IdR Data Retention Current Vdd = 1.2V, CE Vdd – 0.2V Ind. 25 mA
Auto. 70
typ.(1) 4
tSdR Data Retention Setup Time See Data Retention Waveform 0 ns
tRdR Recovery Time See Data Retention Waveform tRc ns
Note:
1. Typical values are measured at Vdd = 3.0V, TA = 25oC and not 100% tested.
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ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
Speed (ns) Order Part No. Package
10 (81) IS61WV10248BLL-10MI 48 mini BGA (9mm x 11mm)
IS61WV10248BLL-10MLI 48 mini BGA (9mm x 11mm), Lead-free
IS61WV10248BLL-10TI TSOP (Type II)
IS61WV10248BLL-10TLI TSOP (Type II), Lead-free
Note:
1. Speed = 8ns for Vdd = 3.3V + 5%. Speed = 10ns for Vdd = 2.4V to 3.3V.
Industrial Range: -40°C to +85°C
Voltage Range: 1.65V to 2.2V
Speed (ns) Order Part No. Package
20 IS61WV10248ALL-20MI 48 mini BGA (9mm x 11mm)
IS61WV10248ALL-20MLI 48 mini BGA (9mm x 11mm), Lead-free
IS61WV10248ALL-20TI TSOP (Type II)
Automotive Range: -40°C to +125°C
Voltage Range: 2.4V to 3.6V
Speed (ns) Order Part No. Package
10 IS64WV10248BLL-10MA3 48 mini BGA (9mm x 11mm)
IS64WV10248BLL-10TA3 TSOP (Type II)
IS64WV10248BLL-10CTLA3 TSOP (Type II), Lead-free,
Copper Leadframe
FED 5mm 33:0 omfioum ’5de fin: 3 Am.» mHEL
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2. Reference document : JEDEC MO-207
1. CONTROLLING DIMENSION : MM .
NOTE :
08/21/2008
make 5mm NdOmH =Eoov Avv mqhww mmmmmmmmmmmmmmmmmmmmmm mmmmmmmmmmmmmmmmmmmmmm F ‘
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2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
1. CONTROLLING DIMENSION : MM
NOTE :
06/04/2008
Package Outline

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