IR2520D(S) (PbF) Datasheet by Infineon Technologies

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International ISBR Rectifier
Data Sheet No. PD60212 revC
Features
600V Half Bridge Driver
Integrated Bootstrap FET
Adaptive zero-voltage switching (ZVS)
Internal Crest Factor Over-Current Protection
0 to 6VDC Voltage Controlled Oscillator
Programmable minimum frequency
Micropower Startup Current (80uA)
Internal 15.6V zener clamp on Vcc
Small DIP8/SO8 Package
Also available LEAD-FREE (PbF)
Description
The IR2520D(S) is a complete adaptive ballast controller and 600V half-bridge driver integrated into a single
IC for fluorescent lighting applications. The IC includes adaptive zero-voltage switching (ZVS), internal crest
factor over-current protection, as well as an integrated bootstrap FET. The heart of this IC is a voltage con-
trolled oscillator with externally programmable minimum frequency. All of the necessary ballast features are
integrated in a small 8-pin DIP or SOIC package.
ADAPTIVE BALLAST CONTROL IC
IR2520D(S) & (PbF)
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Typical Application Diagram
Packages
8 Lead SOIC
IR2520DS
8-Lead PDIP
IR2520D
1
2
3
4
IR2520D
VCC
COM
VCO LO
VS
HO
VB
8
7
6
5
FMIN
MHS
CBS
CVCC
RFMIN
F1
CBUS
RSUPPLY
DCP2
DCP1
LRES
CRES
CSNUB
CVCO
BR1
LF
CF
MLS
CDC
SPIRAL
CFL
L1
L2
\mernafiono 1911 Recmfier
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Symbol Definition Min. Max. Units
VBHigh side floating supply voltage -0.3 625
VSHigh side floating supply offset voltage VB - 25 VB + 0.3
VHO High side floating output voltage VS - 0.3 VB + 0.3
VLO Low side output voltage -0.3 VCC + 0.3
IVCO Voltage controlled oscillator input current (Note 1) -5 + 5 mA
ICC Supply current (Note 2) -25 25 mA
dVS/dt Allowable offset voltage slew rate -50 50 V/ns
PDPackage power dissipation @ TA +25°C 8-Lead PDIP 1
PD=(TJMAX-TA)RthJA 8-Lead SOIC 0.625
RthJA Thermal resistance, junction to ambient 8-Lead PDIP 125
8-Lead SOIC 200
TJJunction temperature -55 150
TSStorage temperature -55 150
TLLead temperature (soldering, 10 seconds) 300
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance
and power dissipation ratings are measured under board mounted and still air conditions.
V
°C
W
°C/W
Note 1: This IC contains a zener clamp structure between the chip VCO and COM, which has a nominal breakdown voltage
of 6V. Please note that this pin should not be driven by a DC, low impedance power source greater than 6V.
Note 2: This IC contains a zener clamp structure between the chip VCC and COM, which has a nominal breakdown voltage
of 15.6V. Please note that this supply pin should not be driven by a DC, low impedance power source greater than the
VCLAMP specified in the Electrical Characteristics section.
Note 3: Enough current should be supplied into the VCC pin to keep the internal 15.6V zener clamp diode on this pin
regulating its voltage, VCLAMP.
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Symbol Definition Min. Max. Units
VBS High side floating supply voltage VCC - 0.7 VCLAMP
VSSteady state high side floating supply offset voltage -1 600
VCC Supply voltage VCCUV+ VCLAMP
ICC Supply current Note 3 10 mA
RFMIN Minimum frequency setting resistance 20 140 k
VVCO VCO pin voltage 0 5 V
TJJunction temperature -25 125 °C
V
nto’na‘ono Rcctma'
IR2520D(S) & (PbF)
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Electrical Characteristics
VCC = VBS = VBIAS = 14V +/- 0.25V, CLO=CHO=1000pF, RFMIN = 82k and TA = 25°C unless otherwise specified.
Symbol Definition Min. Typ. Max. Units Test Conditions
VCCUV+ VCC and VBS supply undervoltage positive going 11.4 12.6 13.8 VCC rising from OV
threshold
VCCUV- VCC and VBS supply undervoltage negative going 9.0 10.0 11.0
threshold
VUVHYS VCC supply undervoltage lockout hysteresis 2.7
IQCCUV UVLO quiescent current 45 80 VCC = 10V
IQCCFLT Fault mode quiescent current 100
ICCHF VCC supply current f=85KHz 4.5 VVCO=0V
ICCLF VCC supply current f=35KHz 2.0 VVCO=6V
VCLAMP VCC Zener clamp voltage 14.4 15.4 V ICC = 10mA
IQBS0Quiescent VBS supply current 80 150 VCC=10V, VBS=14V
IQBSUV Quiescent VBS supply current 20 40 VCC=10V, VBS=7V
VBSUV+ VBS supply undervoltage positive going threshold 7.7 9.0 10.3 V
VBSUV- VBS supply undervoltage negative going threshold 6.8 8.0 9.2 V
ILK Offset supply leakage current 50 µAV
B = VS = 600V
f(min) Minimum oscillator frequency (Note 4) 29.6 34 38.2 VVCO=6V
f(max) Maximum oscillator frequency (Note 4) 67 86 96 VVCO=0V
D Oscillator duty cycle 50 %
DTLO LO output deadtime 2.0
DTHO HO output deadtime 2.0
IVCOQS IVCO quick start 50 VVCO=0V
IVCOFS IVCO frequency sweep 0.8 1.3 1.7 VVCO=2V
IVCO_5V IVCO when VCO is at 5V 1.1
VVCO_max Maximum VCO voltage 6 V
VLO=LOW LO output voltage when LO is low COM —
VHO=LOW HO output voltage when HO is low COM —
VLO=HIGH LO output voltage when LO is high VCC —
VHO=HIGH HO output voltage when HO is high VCC —
TRISE Turn on rise time 150 230
TFALL Turn off fall time 75 120
IO+ Output source short circuit pulsed current 140 mA
IO- Output sink short circuit pulse current 230 mA
Note 4: Frequency shown is nominal for RFMIN=82k. Frequency can be programmed higher or lower with the value of RFMIN.
µS
kHz
µA
V
µA
mA
nS
mV
µA
Supply Characteristics
Floating Supply Characteristics
Oscillator I/O Characteristics
Gate Driver Output Characteristics
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IR2520D(S)& (PbF)
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Lead Definitions
Symbol Description
VCC Supply voltage
COM IC power and signal ground
FMIN Minimum frequency setting
VCO Voltage controlled oscillator input
LO Low-side gate driver output
VS High-side floating return
HO High-side gate driver output
VB High-side gate driver floating supply
1
2
3
4
IR2520D(S)
VCC
COM
VCO LO
VS
HO
VB
8
7
6
5
FMIN
Electrical Characteristics
VCC = VBS = VBIAS = 14V +/- 0.25V, CLO=CHO=1000pF, RFMIN = 82k and TA = 25°C unless otherwise specified.
Symbol Definition Min. Typ. Max. Units Test Conditions
VVCO_RUN VCO voltage when entering run mode 4.8 V
CSCF Crest factor peak-to-average fault factor 5.0 N/A VS offset = 0.5V
VS_ Maximum crest factor VS offset voltage 3.0 V
OFFSET_MAX
VVCOSD VVCO shutdown voltage 0.74 0.82 0.91 V
VFMIN FMIN lead voltage during normal operation 4.8 5.1 5.4 V
VFMINFLT FMIN lead voltage during fault mode 0 V
IBS1 VB current 30 70 CBS=0.1uF,
VS=0V
IBS2 VB current 10 20 VBS = 10V
Bootstrap FET
Minimum Frequency Setting Characteristics
Protection Characteristics
mA
\mernafiono 1911 Recmfier
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Block Diagram
All values are typical
LO
VCC
5
HO
7
6
8
VS
VB
Bootstrap
FET
Control
Bootstrap
FET
High-Voltage Well
UVLO
Level-Shift
FETs
QS
R2
R1
VCO
FMIN
4
3
Driver
Logic
5V
5V
IFMIN
IFMAX
IDT
RRFMIN
IFMIN=
CT
5V
Fault
Logic QS1
R2 Q
S2
R1
SET
RST
1V
0.8V
4.8V UVLO
VCC
COM
1
2
15.6V
300ns
PGEN
Q
S
RQ
5.1V
120uA
Q
T
RQ
Level
Shift
PGEN
HIN
LIN
VS-Sensing
FET
Averaging
Circuit
x 5
VCC
IQS
IVCO
1us
blank
\mernafiono 1911 Recmfier
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State Diagram
All values are typical
Power Turned
On
VCCUV Mode
VCC > 12.6V
(VCCUV+)
VCC < 10V
(VCCUV-)
V = 0V
VCC < 10V
(VCCUV-)
IQCC 45
-Bridge Off
1/2
Crest Factor > 5.0
(CSCF)
or
V < 0.82V
(V )
V = 0V
Frequency Sweep Mode
VCO ramps up, frequency ramps down
Crest Factor Disabled
V = 5.1V
RUN Mode
V = 6.0V, Frequency = fmin
Crest Factor Enabled
ZVS Enabled
If non-ZVS detected then V decreases
and frequency increases to maintain ZVS
FAULT
Mode
V = 0V
ZVS Disabled
VCO
VCO
FMIN
FMIN
VCO
FMIN
VCO
VCOSD
µA
V >4.8V
VCO
(V _RUN)
VCO
-Bridge Off
1
/2
V = 0V
VCO
100
QCCFLT
IµA
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Functional Description
Under-voltage Lock-Out Mode
The under-voltage lock-out mode (UVLO) is defined as the
state the IR2520D is in when VCC is below the turn-on
threshold of the IC. The IR2520D UVLO is designed to main-
tain an ultra-low supply current (IQCCUV<80uA), and to
guarantee that the IR2520D is fully functional before the
high- and low-side output gate drivers are activated. The
VCC capacitor, CVCC, is charged by current through sup-
ply resistor, RSUPPLY, minus the start-up current drawn by
the IR2520D (Figure 1). This resistor is chosen to provide
sufficient current to supply the IR2520D from the DC bus.
Once the capacitor voltage on VCC reaches the start-up
threshold, VCCUV+, the IR2520D turns on and HO and LO
start oscillating. Capacitor CVCC should be large enough to
hold the voltage at VCC above the VCCUV+ threshold for
one half-cycle of the line voltage or until the external auxil-
iary supply can maintain the required supply voltage and
current to the IC.
An internal bootstrap MOSFET between VCC and VB and
external supply capacitor, CBS, determine the supply volt-
age for the high-side driver circuitry. An external charge
pump circuit consisting of capacitor CSNUB and diodes DCP1
and DCP2, comprises the auxiliary supply voltage for the
low-side driver circuitry. To guarantee that the high-side
supply is charged up before the first pulse on pin HO, the
first pulse from the output drivers comes from the LO pin.
LO may oscillate several times until VB-VS exceeds the
high-side UVLO rising threshold, VBSUV+ (9 Volts), and the Fig. 2 Frequency sweep circuitry mode circuitry
Fig. 1 Start-up circuitry
VCC
COM
VCO LO
VS
HO
VB
FMIN
MHS
CBS
CVCC
RFMIN
RSUPPLY
DCP2
DCP1
CSNUB
CVCO MLS
DCBUS(+)
DCBUS(-)
8
7
6
5
1
2
3
4
TO LOAD
LOAD RETURN
15.6V
CLAMP
High-
and
Low-
side
Driver
Bootstrap
FET
Driver
UVLO
VCC
high-side driver is enabled. During UVLO mode, the high- and
low-side gate driver outputs, HO and LO, are both low and
pin VCO is pulled down to COM for resetting the starting
frequency to the maximum.
Frequency Sweep Mode
When VCC exceeds VCCUV+ threshold, the IR2520D enters
frequency sweep mode. An internal current source (Figure
2) charges the external capacitor on pin VCO, CVCO, and
the voltage on pin VCO starts ramping up linearly. An addi-
tional quick-start current (IVCOQS) is also connected to the
VCO pin and charges the VCO pin initially to 0.85V. When the
VCO voltage exceeds 0.85V, the quick-start current is then
disconnected internally and the VCO voltage continues to
charge up with the normal frequency sweep current source
(IVCOFS) (Figure 3). This quick-start brings the VCO voltage
quickly to the internal range of the VCO. The frequency ramps
down towards the resonance frequency of the high-Q bal-
last output stage causing the lamp voltage and load current to
increase. The voltage on pin VCO continues to increase and
the frequency keeps decreasing until the lamp ignites. If the
lamp ignites successfully, the voltage on pin VCO continues
to increase until it internally limits at 6V (VVCO_MAX). The
frequency stops decreasing and stays at the minimum fre-
quency as programmed by an external resistor, RFMIN, on
pin FMIN. The minimum frequency should be set below the
high-Q resonance frequency of the ballast output stage to
ensure that the frequency ramps through resonance for lamp
ignition (Figure 4). The desired preheat time can be set by
adjusting the slope of the VCO ramp with the external capaci-
tor CVCO.
VCC
COM
VCO LO
VS
HO
VB
FMIN
MHS
CBS
CVCC
RFMIN
RSUPPLY
DCP2
DCP1
CSNUB
CVCO MLS
DCBUS(+)
DCBUS(-)
8
7
6
5
1
2
3
4
TO LOAD
LOAD RETURN
15.6V
CLAMP
High-
and
Low-
side
Driver
Bootstrap
FET
Driver
VCO
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VVCO
4.8V
0.85V
6V
Freq
fmax
fmin
Frequency Sweep Mode Run Mode
Fig. 3 IR2520D Frequency sweep mode timing
diagram.
High -Q
Low -Q
Start
Ignition
Run
Vout
Vin
Frequency
Preheat
fmaxfmin
Fig. 4 Resonant tank Bode plot with lamp operating
points.
Run Mode
The IR2520D enters RUN mode when the voltage on pin
VCO exceeds 4.8V (VVCO_RUN). The lamp has ignited and
the ballast output stage becomes a low-Q, series-L, paral-
lel-RC circuit. Also, the VS sensing and fault logic blocks
(Figure 5) both become enabled for protection against non-
ZVS and over-current fault conditions. The voltage on the
VCO pin continues to increase and the frequency deceases
further until the VCO pin voltage limits at 6V (VVCO_MAX)
and the minimum frequency is reached. The resonant in-
ductor, resonant capacitor, DC bus voltage and minimum
frequency determine the running lamp power. The IC stays
at this minimum frequency unless non-ZVS occurs at the
VS pin, a crest factor over-current condition is detected at
the VS pin, or VCC decreases below the UVLO- threshold
(see State Diagram).
VCC
COM
VCO LO
VS
HO
VB
FMIN
MHS
CBS
CVCC
RFMIN
RSUPPLY
DCP2
DCP1
CSNUB
CVCO MLS
DCBUS(+)
DCBUS(-)
8
7
6
5
1
2
3
4
TO LOAD
LOAD RETURN
15.6V
CLAMP
High-
and
Low-
side
Driver
Bootstrap
FET
Driver
VCO
Fault
Logic VS
Sense
Fig. 5 IR2520D Run mode circuitry.
Non Zero-Voltage Switching (ZVS) Protection
During run mode, if the voltage at the VS pin has not slewed
entirely to COM during the dead-time such that there is
voltage between the drain and source of the external low-
side half-bridge MOSFET when LO turns-on, then the system
is operating too close to, or, on the capacitive side of,
resonance. The result is non-ZVS capacitive-mode
switching that causes high peak currents to flow in the
half-bridge MOSFETs that can damage or destroy them
(Figure 6). This can occur due to a lamp filament failure(s),
\mernafiono 1911 Recmfier
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VLO
VHO
IMLS
Too close to resonance.
Hard-switching and high
peak MOSFET currents!
!
IMHS
VVS
IL
VVCO
Frequency shifted higher
to maintain ZVS.
!
!
lamp removal (open circuit), a dropping DC bus during a
mains brown-out or mains interrupt, lamp variations over
time, or component variations. To protect against this, an
internal high-voltage MOSFET is turned on at the turn-off of
HO and the VS-sensing circuit measures VS at each rising
edge of LO. If the VS voltage is non-zero, a pulse of current
is sinked from the VCO pin (Figures 5 and 6) to slightly
discharge the external capacitor, CVCO, causing the
frequency to increase slightly. The VCO capacitor then
charges up during the rest of the cycle slowly due to the
internal current source.
Fig. 6 IR2520D non-ZVS protection timing diagram.
The frequency is trying to decrease towards resonance
by charging the VCO capacitor and the adaptive ZVS cir-
cuit “nudges” the frequency back up slightly above reso-
nance each time non-ZVS is detected at the turn-on of LO.
The internal high-voltage MOSFET is then turned off at the
turn-off of LO and it withstands the high-voltage when VS
slews up to the DC bus potential. The circuit then remains in
this closed-loop adaptive ZVS mode during running and
maintains ZVS operation with changing line conditions, com-
ponent tolerance variations and lamp/load variations. Dur-
ing a lamp removal or filament failure, the lamp resonant
tank will be interrupted causing the half-bridge output to go
open circuit (Figure 7). This will cause capacitive switching
(hard-switching) resulting in high peak MOSFET currents
that can damage them. The IR2520D will increase the fre-
quency in attempt to satisfy ZVS until the VCO pin de-
creases below 0.82V (VVCOSD). The IC will enter Fault
Mode and latch the LO and HO gate driver outputs ‘low’ for
turning the half-bridge off safely before any damage can
occur to the MOSFETs.
VLO
VHO
VVS
IMLS
IMHS
!
Capacitive switching. Hard-switching
and high peak MOSFET currents!
VVCO
Frequency shifted higher
until VCO < 0.82V. LO and
HO are latched low before
damage occurs to MOSFETs.
!
!
RUN MODE FAULT MODE
0.85V
Crest Factor Over-current Protection
During normal lamp ignition, the frequency sweeps through
resonance and the output voltage increases across the
resonant capacitor and lamp until the lamp ignites. If the
lamp fails to ignite, the resonant capacitor voltage, the inductor
voltage and inductor current will continue to increase until
the inductor saturates or the output voltage exceeds the
maximum voltage rating of the resonant capacitor or inductor.
The ballast must shutdown before damage occurs. To
protect against a lamp non-strike fault condition, the IR2520D
uses the VS-sensing circuitry (Figure 5) to also measure
the low-side half-bridge MOSFET current for detecting an
Fig. 7 Lamp removal or open filament fault
condition timing diagram
\mernafiono 1911 Recmfier <:>
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over-current fault. By using the RDSon of the external low-
side MOSFET for current sensing and the VS-sensing
circuitry, the IR2520D eliminates the need for an additional
current sensing resistor, filter and current-sensing pin. To
cancel changes in the RDSon value due to temperature and
MOSFET variations, the IR2520D performs a crest factor
measurement that detects when the peak current exceeds
the average current by a factor of 5 (CSCF). Measuring the
crest factor is ideal for detecting when the inductor saturates
due to excessive current that occurs in the resonant tank
when the frequency sweeps through resonance and the
lamp does not ignite. When the VCO voltage ramps up for
the first time from zero, the resonant tank current and
voltages increase as the frequency decreases towards
resonance (Figure 8). If the lamp does not ignite, the inductor
current will eventually saturate but the crest factor fault
protection is not active until the VCO voltage exceeds 4.8V
(VVCO_RUN) for the first time. The frequency will continue
decreasing to the capacitive side of resonance towards
the minimum frequency setting and the resonant tank current
and voltages will decrease again. When the VCO voltage
exceeds 4.8V (VVCO_RUN), the IC enters Run Mode and
the non-ZVS protection and crest factor protection are both
enabled. The non-ZVS protection will increase the
frequency again cycle-by-cycle towards resonance from
the capacitive side. The resonant tank current will increase
again as the frequency nears resonance until the inductor
saturates again.
The crest factor protection is now enabled and measures
the instantaneous voltage at the VS pin only during the time
when LO is ‘high’ and after an initial 1us blank time from the
rising edge of LO. The blank time is necessary to prevent
the crest factor protection circuit from reacting to a non-
ZVS condition. An internal averaging circuit averages the
instantaneous voltage at the VS pin over 10 to 20 switching
cycles of LO. During Run Mode, the first time the inductor
saturates when LO is ‘high’ (after the 1us blank time) and
the peak current exceeds the average by 5 (CSCF), the
IR2520D will enter Fault Mode and both LO and HO outputs
will be latched ‘low’. The half-bridge will be safely disabled
before any damage can occur to the ballast components.
The crest factor peak-to-average fault factor varies as a
function of the internal average (Figure 20). The maximum
internal average should be below 3.0 volts. Should the
average exceed this amount, the multiplied average voltage
can exceed the maximum limit of the VS sensing circuit and
the VS sensing circuit will no longer detect crest factor
LO
IL
VVCO
4.6V
INDUCTIVE SIDE
OF RESONANCE
CAPACITIVE SIDE
OF RESONANCE
FREQUENCY SWEEP MODE RUN MODE FAULT MODE
IMLS
AVG*5 Inductor
saturation
Fig. 8 Crest factor protection timing diagram
FAULT MODE
During Run Mode, should the VCO voltage decrease below
0.82V (VVCOSD) or a crest factor fault occur, the IR2520D
will enter Fault Mode (see State Diagram). The LO and HO
gate driver outputs are both latched ‘low’ so that the half-
bridge is disabled. The VCO pin is pulled low to COM and
the FMIN pin decreases from 5V to COM. VCC draws
micro-power current (ICCFLT) so that VCC stays at the
clamp voltage and the IC remains in Fault Mode without the
need for the charge-pump auxiliary supply. To exit Fault
Mode and return to Frequency Sweep Mode, VCC must be
cycled below the UVLO- threshold and back above the
UVLO+ threshold.
faults. This can occur when a half-bridge MOSFET is
selected that has an RDSon that is too large for the application
causing the internal average to exceed the maximum limit.
\mernafiono 1911 Recmfier “A:
IR2520D(S) & (PbF)
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0
10
20
30
40
50
-25 0 25 50 75 100 125
Temperature(C)
IQCCUV(uA
Fig. 9 VCCUV+/- vs TEMP Fig. 10 IQCCUV vs TEMP
VCC=10V, VCO=0V
Fig. 11 VBSUV+/- vs TEMP Fig. 12 IQBSUV vs TEMP
6
8
10
12
14
16
-2 5 0 2 5 50 75 10 0 12 5
Temperature(°C)
VCCUV+,-(V
VCCUV+
VCCUV-
6
8
10
12
-25 0 25 50 75 100 125
Temperature(°C)
VBSUV+,-(V)
VBSUV+
VBSUV-
0
20
40
60
80
10 0
-25 0 25 50 75 100 125
Temperature(°C)
IQBSUV(uA)
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0
10
20
30
40
50
60
70
80
90
-2 5 0 25 50 75 100 12 5
Temperature(C)
Freq(KHz
)
20
40
60
80
100
120
140
Fig. 16 FREQ VS VCC vs TEMP
VVCO=0V
Fig. 15 FREQ VS VVCO vs TEMP
VCC=14V
Fig. 14 Frequency vs RFMIN vs TEMP
VVCO=6V
Fig. 13 Frequency vs TEMP
REMIN=82K
0
10
20
30
40
50
60
70
80
90
10 0
-2 5 0 2 5 50 75 10 0 12 5
Temperature(C)
Frequency(kHz
)
VVCO=0V
VVCO=5V
0
10
20
30
40
50
60
70
80
90
10 0
1234 56
VCO(V)
Frequency(kHz
-2 5
25
75
12 5
86
87
88
89
90
91
92
93
12 13 14 15 16
Temperature(C)
Frequency(kHz)
-2 5
25
75
12 5
K
K
K
K
K
K
K
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0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-25 0 2 5 50 75 100 125
Temperature(°C)
IVCOFS(uA
Fig. 19 VVCOMAX vs TEMP Fig. 20 CSCF vs OFFSET
Fig. 17 DTHO, DTLO vs TEMP
VCO=0V
Fig. 18 IVCO_FS vs TEMP
5
5.5
6
6.5
7
-25 0 2 5 50 75 10 0 125
Temperature(C)
VVCO_MAX (V)
0
1
2
3
4
5
6
7
8
9
10
0.20.40.60.81
V S OFFSET( V )
VCSC
0
0.5
1
1.5
2
2.5
-25 0 2 5 50 75 100 125
Temperature(°C)
TD (uS
)
TDHO
TDLO
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Fig. 24 IBS1 vs TEMP
0
20
40
60
80
10 0
-25 0 2 5 50 75 10 0 125
Temperature(°C)
IBS1(mA)
Fig. 21 CSCF vs TEMP
VS_OFFSET=0.5V
Fig. 22 VVCO_SD vs TEMP
Fig. 23 VFMIN vs TEMP
VCO=0V, RFMIN=82K
0
0.25
0.5
0.75
1
1.25
1.5
-25 0 2 5 50 75 10 0 12 5
Temperature (°C)
VVCO_SD (V)
0
1
2
3
4
5
6
-25 0 25 50 75 100 125
Temperature(C)
VFMIN(V
()
0
2
4
6
8
10
-25 0 25 50 75 100 125
Temperature(°C)
CSC
F
\mernafiono 1911 Recmfier
IR2520D(S) & (PbF)
www.irf.com 15
Fig. 26 IBS2 vs TEMP
0
5
10
15
20
25
30
-25 0 2 5 50 75 100 125
Temperature(°C)
IBS2(mA)
\mernafiono 1911 Recmfier ‘_; Y j 1" A , — [k _ » <':| _-,,="" ,="" y="" .="" v="" ,="" ff="" a="" l="" a="" h="" hhhh="" 1="" %j="" c,="" ;="" j="" l="" j="" ,="" um[.au4]="">
IR2520D(S)& (PbF)
16 www.irf.com
IR2520DS 8-Lead SOIC 01-6027
01-0021 11 (MS-012AA)
87
5
65
D B
E
A
e
6X
H
0.25 [.010] A
6
4312
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
NOTES:
1. DIMENSIONING & TOLERANC ING PER ASME Y14.5M-1994.
2. CONTROLLING DIMENSION: MILLIMETER
3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].
7
K x 45°
8X L 8X c
y
FOOTPRINT
8X 0.72 [.028]
6.46 [.255]
3X 1.27 [.050] 8X 1.78 [.070]
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MO LD PROTRUSIONS NO T TO EXC EED 0.25 [.010].
7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
A SUBSTRATE.
MO LD PROTRUSIONS NO T TO EXC EED 0.15 [.006].
0.25 [.010] CAB
e1
A
A1
8X b
C
0.10 [.004]
e1
D
E
y
b
A
A1
H
K
L
.189
.1497
.013
.050 BASIC
.0532
.0040
.2284
.0099
.016
.1968
.1574
.020
.0688
.0098
.2440
.0196
.050
4.80
3.80
0.33
1.35
0.10
5.80
0.25
0.40
1.27 BASIC
5.00
4.00
0.51
1.75
0.25
6.20
0.50
1.27
MIN MAX
MILLIMETERSIN C H E S
MIN MAX
DIM
e
c .0075 .0098 0.19 0.25
.025 BASIC 0.635 BASIC
01-6014
01-3003 01 (MS-001AB)
IR2520D 8-Lead PDIP
Case outlines
\mernafiono 1911 Recmfier Internationcfl ISDR Rectifier
IR2520D(S) & (PbF)
www.irf.com 17
Leadfree Part
8-Lead PDIP IR2520D order IR2520DPbF
8-Lead SOIC IR2520DS order IR2520DSPbF
LEADFREE PART MARKING INFORMATION
ORDER INFORMATION
Lead Free Released
Non-Lead Free
Released
Part number
Date code
IRxxxxxx
YWW?
?XXXX
Pin 1
Identifier
IR logo
Lot Code
(Prod mode - 4 digit SPN code)
Assembly site code
Per SCOP 200-002
P
?MARKING CODE
Basic Part (Non-Lead Free)
8-Lead PDIP IR2520D order IR2520D
8-Lead SOIC IR2520DS order IR2520DS
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
This product has been qualified per industrial level MSL-3
Data and specifications subject to change without notice. 3/1/2005

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