MCIMX25(3,7,8)(C,D)(J,V)M4 Datasheet by NXP USA Inc.

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Freescale Semiconductor
Data Sheet: Technical Data
Document Number: IMX25CEC
Rev. 10, 07/2013
MCIMX25
Package Information
Plastic package
Case 5284 17 x 17 mm, 0.8 mm Pitch
Case 2107 12 x 12 mm, 0.5 mm Pitch
Ordering Information
See Table 1 on page 3 for ordering information.
© 2009-2013 Freescale Semiconductor, Inc. All rights reserved.
1 Introduction
The i.MX25 multimedia applications processor has
the right mix of high performance, low power, and
integration to support the growing needs of the
industrial and general embedded markets.
At the core of the i.MX25 is Freescale's fast,
proven, power-efficient implementation of the
ARM® 926EJ-S™ core, with speeds of up to
400 MHz. The i.MX25 includes support for up to
133 MHz DDR2 memory, integrated 10/100
Ethernet MAC, and two on-chip USB PHYs. The
device is suitable for a wide range of applications,
including the following:
Graphical remote controls
Human Machine Interface (HMI)
Residential and commercial control panels
Residential gateway (smart metering)
Handheld scanners and printers
Electronic point-of-sale terminals
Patient-monitoring devices
i.MX25 Applications
Processor for
Consumer and
Industrial Products
Silicon Version 1.2
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1. Special Signal Considerations . . . . . . . . . . . . . . . . 9
3. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1. i.MX25 Chip-Level Conditions . . . . . . . . . . . . . . . . 11
3.2. Supply Power-Up/Power-Down Requirements and
Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . 18
3.4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . 20
3.5. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6. AC Electrical Characteristics . . . . . . . . . . . . . . . . 24
3.7. Module Timing and Electrical Parameters . . . . . . 41
4. Package Information and Contact Assignment . . . . . . 124
4.1. 400 MAPBGA—Case 17x17 mm, 0.8 mm Pitch . 124
4.2. Ground, Power, Sense, and Reference Contact
Assignments Case 17x17 mm, 0.8 mm Pitch . . . 125
4.3. Signal Contact Assignments—17 x 17 mm, 0.8 mm
Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.4. i.MX25 17x17 Package Ball Map . . . . . . . . . . . . 135
4.5. 347 MAPBGA—Case 12 x 12 mm, 0.5 mm Pitch 138
4.6. Ground, Power, Sense, and Reference Contact
Assignments Case 12x12 mm, 0.5 mm Pitch . . . 139
4.7. Signal Contact Assignments12 x 12 mm, 0.5 mm
Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
4.8. i.MX25 12x12 Package Ball Map . . . . . . . . . . . . 148
5. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
2Freescale Semiconductor
Features of the i.MX25 processor include the following:
Advanced power management—The heart of the device is a level of power management
throughout the IC that enables the multimedia features and peripherals to achieve minimum system
power consumption in active and various low-power modes. Power management techniques allow
the designer to deliver a feature-rich product that requires levels of power far lower than typical
industry expectations.
Multimedia powerhouse—The multimedia performance of the i.MX25 processor is boosted by a
16 KB L1 instruction and data cache system and further enhanced by an LCD controller (with
alpha blending), a CMOS image sensor interface, an A/D controller (integrated touchscreen
controller), and a programmable Smart DMA (SDMA) controller.
128 Kbytes on-chip SRAM—The additional 128 Kbyte on-chip SRAM makes the device ideal for
eliminating external RAM in applications with small footprint RTOS. The on-chip SRAM allows
the designer to enable an ultra low power LCD refresh.
Interface flexibility—The device interface supports connection to all common types of external
memories: MobileDDR, DDR, DDR2, NOR Flash, PSRAM, SDRAM and SRAM, NAND Flash,
and managed NAND.
Increased security—Because the need for advanced security for tethered and untethered devices
continues to increase, the i.MX25 processor delivers hardware-enabled security features that
enable secure e-commerce, Digital Rights Management (DRM), information encryption, robust
tamper detection, secure boot, and secure software downloads.
On-chip PHY—The device includes an HS USB OTG PHY and FS USB HOST PHY.
Fast Ethernet—For rapid external communication, a Fast Ethernet Controller (FEC) is included.
i.MX25 only supports Little Endian mode.
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 3
1.1 Ordering Information
Table 1 provides ordering information for the i.MX25.
Table 1. Ordering Information
Description Part Number Silicon
Version
Projected
Temperature
Range (°C)
Package Ballmap
i.MX253 MCIMX253DVM4 1.1 –20 to +70 17 x 17 mm, 0.8 mm pitch,
MAPBGA-400
Table 103
i.MX257 MCIMX257DVM4 1.1 –20 to +70 17 x 17 mm, 0.8 mm pitch,
MAPBGA-400
Table 103
i.MX253 MCIMX253CVM4 1.1 –40 to +85 17 x 17 mm, 0.8 mm pitch,
MAPBGA-400
Table 103
i.MX257 MCIMX257CVM4 1.1 –40 to +85 17 x 17 mm, 0.8 mm pitch,
MAPBGA-400
Table 103
i.MX258 MCIMX258CVM4 1.1 –40 to +85 17 x 17 mm, 0.8 mm pitch,
MAPBGA-400
Table 103
i.MX253 MCIMX253DJM4 1.1 –20 to +70 17 x 17 mm, 0.8 mm pitch,
MAPBGA-400
Table 103
i.MX257 MCIMX257DJM4 1.1 –20 to +70 17 x 17 mm, 0.8 mm pitch,
MAPBGA-400
Table 103
i.MX253 MCIMX253CJM4 1.1 –40 to +85 17 x 17 mm, 0.8 mm pitch,
MAPBGA-400
Table 103
i.MX257 MCIMX257CJM4 1.1 –40 to +85 17 x 17 mm, 0.8 mm pitch,
MAPBGA-400
Table 103
i.MX258 MCIMX258CJM4 1.1 –40 to +85 17 x 17 mm, 0.8 mm pitch,
MAPBGA-400
Table 103
i.MX253 MCIMX253DJM4A 1.2 –20 to +70 17 x 17 mm, 0.8 mm pitch,
MAPBGA-400
Table 103
i.MX257 MCIMX257DJM4A 1.2 –20 to +70 17 x 17 mm, 0.8 mm pitch,
MAPBGA-400
Table 103
i.MX257 MCIMX257DJM4AR2 1.2 –20 to +70 17 x 17 mm, 0.8 mm pitch,
MAPBGA-400
Table 103
i.MX253 MCIMX253CJM4A 1.2 –40 to +85 17 x 17 mm, 0.8 mm pitch,
MAPBGA-400
Table 103
i.MX257 MCIMX257CJM4A 1.2 –40 to +85 17 x 17 mm, 0.8 mm pitch,
MAPBGA-400
Table 103
i.MX258 MCIMX258CJM4A 1.2 –40 to +85 17 x 17 mm, 0.8 mm pitch,
MAPBGA-400
Table 103
i.MX257 MCIMX257CJN4A 1.2 –40 to +85 12 x 12mm, 0.5mm pitch,
MAPBGA-347
Table 107
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
4Freescale Semiconductor
Table 2 shows the functional differences between the different parts in the i.MX25 family.
Table 2. i.MX25 Parts Functional Differences
Features MCIMX253 MCIMX257 MCIMX258
Core ARM 926EJ-S ARM 926EJ-S ARM 926EJ-S
CPU Speed 400 MHz 400 MHz 400 MHz
L1 I/D Cache 16K I/D 16K I/D 16K I/D
On-chip SRAM 128 KB 128 KB 128 KB
PATA/C E-ATA Yes Yes Yes
LCD Controller Yes Yes Yes
Touchscreen — Yes Yes
CSI — Yes Yes
FlexCAN (2) Yes Yes
ESAI — Yes Yes
SIM (2) Yes Yes
Security — Yes
10/100 Ethernet Yes Yes Yes
HS USB 2.0 OTG + PHY Yes Yes Yes
HS USB 2.0 Host + PHY Yes Yes Yes
12-bit ADC Yes Yes Yes
SD/SDIO/MMC (2) Yes Yes Yes
External Memory Controller Yes Yes Yes
I2C (3) Yes Yes Yes
SSI/I2S (2) Yes Yes Yes
CSPI (2) Yes Yes Yes
UART (5) Yes Yes Yes
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 5
1.2 Block Diagram
Figure 1 shows the simplified interface block diagram.
Figure 1. i.MX25 Simplified Interface Block Diagram
ARM Processor Domain (AP)
External Memory
Interface (EMI)
Smart
DMA
SDMA Peripherals
ARM Peripherals
ARM9
Internal
Memory
DDR2 /
MDDR
NOR
Flash/ NAND
Flash
Audio/Power
Management
ARM926EJ-S
SPBA
CSPI(2)
UART(3)
Platform
Bluetooth MMC/SDIO Keypad
MAX
AIPS(2)
JTAG Access.
Conn.
LCD Display 1
Ext. Graphics
Accelerator
Timers
GPT(4)
RTC
WDOG
1-WIRE
I
2
C(3)
PWM(4)
KPP
UART(2)
Fusebox
Shared
Domain
PSRAM
or WLAN
SCC
FlexCAN(2)
HS USB OTG
ATA IIM
CSPI
RTICv3
eSDHC(2)
AUDMUX
L1 I/D cache
ETM
AVIC
RNGB
EPIT(2)
ECT
IOMUX
FEC
HS USB OTG PHY
HS USB Host
SSI(1)
SSI
GPIO(3)
ECT
LCDC /
CSI
CSI SLCDC
Camera
Sensor
ADC/TSC
DRYICE
ESAI
SIM(2)
FS USB Host PHY
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
6Freescale Semiconductor
2Features
Table 3 describes the digital and analog modules of the device.
Table 3. i.MX25 Digital and Analog Modules
Block
Mnemonic Block Name Subsystem Brief Description
1-WIRE 1-Wire
Interface
Connectivity
peripherals
1-Wire support provided for interfacing with an on-board EEPROM, and
smart battery interfaces, for example: Dallas DS2502.
ARM9 or
ARM926
ARM926
platform and
memory
ARM The ARM926 Platform consists of the ARM 926EJ-S core, the ETM real-time
debug modules, a 5x5 Multi-Layer AHB crossbar switch, and a “primary
AHB” complex. It contains the 16 Kbyte L1 instruction cache, 16 Kbyte L1
data cache, 32 Kbyte ROM and 128 Kbyte RAM.
ATA ATA module Connectivity
peripherals
The ATA module is an AT attachment host interface. Its main use is to
interface with IDE hard disc drives and ATAPI optical disc drives. It interfaces
with the ATA device over a number of ATA signals.
AUDMUX Digital audio
mux
Multimedia
peripherals
The AUDMUX is a programmable interconnect for voice, audio, and
synchronous data routing between host serial interfaces (SSIs) and
peripheral serial interfaces (audio codecs). The AUDMUX has two sets of
interfaces: internal ports to on-chip peripherals, and external ports to off-chip
audio devices. Data is routed by configuring the appropriate internal and
external ports.
CCM Clock control
module
Clocks This block generates all clocks for the iMX25 system. The CCM also
manages the ARM926 Platform's low-power modes (wait, stop, and doze) by
disabling peripheral clocks appropriately for power conservation.
CSPI(3) Configurable
serial
peripheral
interface
Connectivity
peripherals
This module is a serial interface equipped with data FIFOs. Each
master/slave-configurable SPI module is capable of interfacing to both serial
port interface master and slave devices. The CSPI ready (SPI_RDY) and
Slave Select (SS) control signals enable fast data communication with fewer
software interrupts.
DRYICE DryIce module Security DryIce provides volatile key storage for Point-of-Sale (POS) terminals, and a
trusted time source for Digital Rights Management (DRM) schemes. Several
tamper-detect circuits are also provided to support key erasure and time
invalidation in the event of tampering. Alarms and/or interrupts can also
assert if tampering is detected. DryIce also includes a Real Time clock (RTC)
that can be used in secure and non-secure applications.
EMI External
memory
interface
Connectivity
peripherals
The External Memory Interface (EMI) module provides access to external
memory for the ARM and other masters. It is composed of four main
submodules:
M3IF provides arbitration between multiple masters requesting access to
the external memory.
Enhanced SDRAM/LPDDR memory controller (ESDCTL) interfaces to
DDR2 and SDR interfaces.
NAND Flash controller (NFC) provides an interface to NAND Flash
memories.
Wireless External Interface Memory controller (WEIM) interfaces to NOR
Flash and PSRAM.
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 7
EPIT(2) Enhanced
periodic
interrupt timer
Timer
peripherals
Each Enhanced Periodic Interrupt Timer (EPIT) is a 32-bit set-and-forget
timer that starts counting after the EPIT is enabled by software. It is capable
of providing precise interrupts at regular intervals with minimal processor
intervention. It has a 12-bit prescaler to adjust the input clock frequency to
the required time setting for the interrupts, and the counter value can be
programmed on the fly.
ESAI Enhanced
serial audio
interface
Connectivity
peripherals
ESAI provides a full-duplex serial port for serial communication with a variety
of serial devices, including industry-standard codecs, SPDIF transceivers,
and other DSPs. The ESAI consists of independent transmitter and receiver
sections, each section with its own clock generator.
eSDHC(2) Enhanced
multimedia
card/
secure digital
host controller
Connectivity
peripherals
The features of the eSDHC module, when serving as host, include the
following:
Conforms to the SD host controller standard specification version 2.0
Compatible with the JEDEC MMC system specification version 4.2
Compatible with the SD memory card specification version 2.0
Compatible with the SDIO specification version 1.2
Designed to work with SD memory, miniSD memory, SDIO, miniSDIO, SD
combo, MMC and MMC RS cards
Configurable to work in one of the following modes:
—SD/SDIO 1-bit, 4-bit
—MMC 1-bit, 4-bit, 8-bit
Full-/high-speed mode
Host clock frequency variable between 32 kHz and 52 MHz
Up to 200-Mbps data transfer for SD/SDIO cards using four parallel data
lines
Up to 416-Mbps data transfer for MMC cards using eight parallel data lines
FEC Fast ethernet
controller
Connectivity
peripherals
The Ethernet Media Access Controller (MAC) is designed to support both 10-
and 100-Mbps Ethernet networks compliant with IEEE 802.3® standard. An
external transceiver interface and transceiver function are required to
complete the interface to the media
FlexCAN(2) Controller
area network
module
Connectivity
peripherals
The Controller Area Network (CAN) protocol is primarily designed to be used
as a vehicle serial data bus running at 1 MBps.
GPIO(4) General
purpose I/O
modules
System control
peripherals
Used for general purpose input/output to external ICs. Each GPIO module
supports 32 bits of I/O.
GPT(4) General
purpose
timers
Timer
peripherals
Each GPT is a 32-bit free-running or set-and-forget mode timer with
programmable prescaler and compare and capture register. A timer counter
value can be captured using an external event and can be configured to
trigger a capture event on either the leading or trailing edges of an input
pulse. When the timer is configured to operate in set-and-forget mode, it is
capable of providing precise interrupts at regular intervals with minimal
processor intervention. The counter has output compare logic to provide the
status and interrupt at comparison. This timer can be configured to run either
on an external clock or on an internal clock.
Table 3. i.MX25 Digital and Analog Modules (continued)
Block
Mnemonic Block Name Subsystem Brief Description
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
8Freescale Semiconductor
I2C(3) I2C module Connectivity
peripherals
Inter-IC Communication (I2C) is an industry-standard, bidirectional serial bus
that provides a simple, efficient method of data exchange, minimizing the
interconnection between devices. I2C is suitable for applications requiring
occasional communications over a short distance between many devices.
The interface operates up to 100 kbps with maximum bus loading and timing.
The I2C system is a true multiple-master bus, including arbitration and
collision detection that prevents data corruption if multiple devices attempt to
control the bus simultaneously. This feature supports complex applications
with multiprocessor control and can be used for rapid testing and alignment
of end products through external connections to an assembly-line computer.
IIM IC
Identification
Module
Security The IIM provides the primary user-visible mechanism for interfacing with
on-chip fuse elements. Among the uses for the fuses are unique chip
identifiers, mask revision numbers, cryptographic keys, and various control
signals requiring a fixed value.
IOMUX I/O multiplexer Pins Each I/O multiplexer provides a flexible, scalable multiplexing solution:
Up to eight output sources multiplexed per pin
Up to four destinations for each input pin
Unselected input paths are held at constant level for reduced power
consumption
KPP Keypad port Connectivity
peripherals
KPP can be used for either keypad matrix scanning or general purpose I/O.
LCDC LCD
Controller
Multimedia
peripherals
LCDC provides display data for external gray-scale or color LCD panels.
LCDC is capable of supporting black-and-white, gray-scale, passive-matrix
color (passive color or CSTN), and active-matrix color (active color or TFT)
LCD panels.
MAX ARM platform
multilayer
AHB crossbar
switch
ARM platform MAX concurrently supports up to five simultaneous connections between
master ports and slave ports. MAX allows for concurrent transactions to
occur from any master port to any slave port.
PWM(4) Pulse width
modulation
Connectivity
peripherals
The Pulse-Width Modulator (PWM) has a 16-bit counter and is optimized to
generate sound from stored sample audio images. It can also generate
tones. The PWM uses 16-bit resolution and a 4x16 data FIFO to generate
sound.
SDMA Smart DMA
engine
System control The SDMA provides DMA capabilities inside the processor. It is a shared
module that implements 32 DMA channels.
SIM(2) Subscriber
identity
module
interface
Connectivity
peripherals
The SIM is an asynchronous interface designed to facilitate communication
with SIM cards or pre-paid phone cards. This module was designed based
on the ISO7816 standard; however, the module does require an external
companion controller to allow communication to certain smart cards or to
pass certain certifications, such as EMV.
The SIM supports only 11 and 12ETU cards and can communicate at the
default rate, which is obtained at Fi/Di=372/1. An external companion
controller is required to support cards aligned on 10.8 or 11.8ETU and to
support other rates, such as those obtained at Fi/Di=372/2 and Fi/Di=372/4.
SJC Secure JTAG
interface
System control
peripherals
The System JTAG Controller (SJC) provides debug and test control with
maximum security.
Table 3. i.MX25 Digital and Analog Modules (continued)
Block
Mnemonic Block Name Subsystem Brief Description
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 9
2.1 Special Signal Considerations
Special signal considerations are listed in Table 4. The package contact assignment is found in Section 4,
“Package Information and Contact Assignment.” Signal descriptions are provided in the reference manual.
.
SLCD Smart LCD
controller
Multimedia
peripherals
The SLCDC module transfers data from the display memory buffer to the
external display device.
SPBA Shared
peripheral bus
arbiter
System control The SPBA controls access to the shared peripherals. It supports shared
peripheral ownership and access rights to an owned peripheral.
SSI(2) I2S/SSI/AC97
interface
Connectivity
peripherals
The SSI is a full-duplex serial port that allows the processor to communicate
with a variety of serial protocols, including the Freescale Semiconductor SPI
standard and the inter-IC sound bus standard (I2S). The SSIs
interface to the AUDMUX for flexible audio routing.
TSC (and ADC) Touchscreen
controller (and
A/D converter)
Multimedia
peripherals
The touchscreen controller and associated Analog-to-Digital Converter
(ADC) together provide a resistive touchscreen solution. The module
implements simultaneous touchscreen control and auxiliary ADC operation
for temperature, voltage, and other measurement functions.
UART(5) UART
interface
Connectivity
peripherals
Each of the UART modules supports the following serial data
transmit/receive protocols and configurations:
7- or 8-bit data words, one or two stop bits, programmable parity (even,
odd, or none)
Programmable baud rates up to 4 MHz. This is a higher maximum baud
rate than the 1.875 MHz specified by the TIA/EIA-232-F standard and
previous Freescale UART modules. 32-byte FIFO on Tx and 32 half-word
FIFO on Rx supporting auto-baud
IrDA-1.0 support (up to SIR speed of 115200 bps)
Option to operate as 8-pins full UART, DCE, or DTE
USBOTG
USBHOST
High-speed
USB
on-the-go
Connectivity
peripherals
The USB module provides high-performance USB On-The-Go (OTG) and
host functionality (up to 480 Mbps), compliant with the USB 2.0 specification,
the OTG supplement, and the ULPI 1.0 Low Pin Count specification. The
module has DMA capabilities for handling data transfer between internal
buffers and system memory. An OTG HS PHY and HOST FS PHY are also
integrated.
Table 4. Signal Considerations
Signal Description
BAT_VDD DryIce backup power supply input.
CLK0 Clock-out pin; renders the internal clock visible to users for debugging. The clock source is controllable
through CRM registers. This pin can also be configured (through muxing) to work as a normal GPIO.
CLK_SEL Used to select the ARM clock source from MPLL out or from external EXT_ARMCLK. In normal operation,
CLK_SEL should be connected to GND.
EXT_ARMCLK Primarily for Freescale factory use. There is no internal on-chip pull-up/down on this pin, so it must be
externally connected to GND or VDD. Aside from factory use, this pin can also be configured (through
muxing) to work as a normal GPIO.
Table 3. i.MX25 Digital and Analog Modules (continued)
Block
Mnemonic Block Name Subsystem Brief Description
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
10 Freescale Semiconductor
MESH_C, MESH_D Wire-mesh tamper detect pins that can be routed at the PCB board to detect attempted tampering of a
protected wire. When security measures are implemented, MESH_C should be pulled-up or connected to
NVCC_DRYICE and triggers a tamper event when floating or when connected to MESH_D. MESH_D
should be pulled-down or connected to GND and triggers an event when floating or connected to
MESH_C. These pins can be left unconnected if the DryIce security features are not being used.
NVCC_DRYICE This is the DryIce power supply output. The supply source is QVDD when the i.MX25 is in run mode. When
i.MX25 is in reduced power mode, the DryIce supply source is the BATT_VDD supply. This pin can be
used to power external DryIce components (external tamper detect, wire-mesh tamper detect). In order
to guarantee the power-loss protection feature which guarantees that RTC and/or secure keys be
maintained after power-off an external capacitor no less than 4 µF must be connected to this supply output
pin. A 4.7 µF capacitor is recommended.
OSC_BYP The 32 kHz oscillator bypass-control pin. If this signal is pulled down, then OSC32K_EXTAL and
OSC32K_XTAL analog pins should be tied to the external 32.768 kHz crystal circuit. If on the other hand
the signal is pulled up, then the external 32 kHz oscillator output clock must be connected to
OSC32K_EXTAL analog pin, and OSC32K_XTAL can be no connect (NC).
OSC32K_EXTAL
OSC32K_XTAL
These analog pins are connected to an external 32 kHz CLK circuit depending on the state of OSC_BYP
pin (see the description of OSC_BYP under the preceding bullet). The 32 kHz reference CLK is required
for normal operation.
POWER_FAIL An interrupt from PMIC, which should be connected to a low-battery detection circuit. This signal is
internally connected to an on-chip 100 kΩ pull-down device. If there is no low-battery detection, then users
can tie this pin to GND through a pull-down resistor, or leave the signal as NC. This pin can also be
configured to work as a normal GPIO.
REF External ADC reference voltage. REF may be tied to GND if the user plans to only use the internally
generated 2.5 V reference supply.
SJC_MOD Must be externally connected to GND for normal operation. Termination to GND through an external
pull-down resistor (such as 1 kΩ) is allowed, but the value should be much smaller than the on-chip 100
kΩ pull-up.
TAMPER_A,
TAMPER _B
DryIce external tamper detect pins, active high. If TAMPER_A or TAMPER_B is connected to
NVCC_DRYICE, then external tampering is detected. These pins can be left unconnected if the DryIce
security features are not being used.
TEST_MODE For Freescale factory use only. This signal is internally connected to an on-chip pull-down device. Users
must either float this signal or tie it to GND.
UPLL_BYPCLK Primarily for Freescale factory use. There is no internal on-chip pull-up/down on this pin, so it must be
externally connected to GND or VDD. Aside from factory use, this pin can also be configured (through
muxing) to work as a normal GPIO.
USBPHY1_RREF Determines the reference current for the USB PHY1 bandgap reference. An external 10 kΩ 1% resistor to
GND is required.
USBPHY2_DM
USBPHY2_DP
The output impedance of these signals is expected at 10 Ω. It is recommended to also have on-board 33 Ω
series resistors (close to the pins).
Table 4. Signal Considerations (continued)
Signal Description
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 11
3 Electrical Characteristics
This section provides the device-level and module-level electrical characteristics for the i.MX25.
3.1 i.MX25 Chip-Level Conditions
This section provides the chip-level electrical characteristics for the IC.
3.1.1 DC Absolute Maximum Ratings
Table 5 provides the DC absolute maximum operating conditions.
CAUTION
Stresses beyond those listed under Table 5 may cause permanent
damage to the device.
Exposure to absolute-maximum-rated conditions for extended periods
may affect device reliability.
Table 5 gives stress ratings only—functional operation of the device is
not implied beyond the conditions indicated in Table 6.
3.1.2 DC Operating Conditions
Table 6 provides the DC recommended operating conditions.
Table 5. DC Absolute Maximum Ratings
Parameter Symbol Min. Max. Units
Supply voltage QVDD –0.5 1.52 V
Supply voltage (level shift i/o) VDDIOmax –0.5 3.6 V
ESD damage immunity: Vesd V
Human body model (HBM) 2500
Charge device model (CDM) 400
Machine model (MM) 200
Input voltage range VImax –0.5 NVDD + 0.3 V
Storage temperature range Tstorage –40 105 oC
Table 6. DC Operating Conditions
Parameter Symbol Min. Typ. Max. Units
Core supply voltage (at 266 MHz) QVDD 1.15 1.34 1.52 V
Core supply voltage (at 400 MHz) QVDD 1.38 1.45 1.52 V
Coin battery1
BAT_VDD
VDD_BAT 1.15 — 1.55 V
I/O supply voltage, GPIO
NFC,CSI,SDIO
NVDD_GPIO1 1.75 — 3.6 V
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
12 Freescale Semiconductor
I/O supply voltage, GPIO
CRM,LCDC,JTAG,MISC
NVDD_GPIO2 3.0 3.3 3.6 —
I/O supply voltage DDR (Mobile DDR mode)
EMI1, EMI2
NVDD_MDDR 1.75 — 1.95 V
I/O supply voltage DDR (DDR2 mode)
EMI1,EMI2
NVDD_DDR2 1.75 — 1.9 V
I/O supply voltage DDR (SDRAM mode)
EMI1,EMI2
NVDD_SDRAM 1.75 — 3.6 V
Supply of USBPHY1 (HS)
USBPHY1_VDDA_BIAS, USBPHY1_UPLL_VDD,USBPHY1_VDDA
VDD_usbphy1 3.17 3.3 3.43 V
Supply of USBPHY2 (FS)
USBPHY2_VDD
VDD_usbphy2 3.0 3.3 3.6 V
Supply of OSC24M
OSC24M_VDD
VDD_OSC24M 3.0 3.3 3.6 V
Supply of PLL
MPLL_VDD,UPLL_VDD
VDD_PLL 1.4 1.65 V
Supply of touchscreen ADC
NVCC_ADC
VDD_tsc 3.0 3.3 3.6 V
External reference of touchscreen ADC
Ref
Vref 2.5 VDD_tsc VDD_tsc V
Fusebox program supply voltage
FUSE_VDD2
FUSEVDD
(program mode)
3.3 ± 5% 3.6 V
Supply output3
NVCC_DRYICE
VDD_ 1.0 1.55 V
Operating ambient temperature TA–40 — 85 oC
1VDD_BAT must always be powered by battery in security application. In non-security case, VDD_BAT can be connected to
QVDD.
2The fusebox read supply is connected to supply of the full speed USBPHY2_VDD. FUSE_VDD is only used for programming.
It is recommended that FUSE_VDD be connected to ground when not being used for programming. See Table 7 for current
parameters.
3NVCC_DRYICE is a supply output. An external capacitor no less than 4 µF must be connected to it. A 4.7 µF capacitor is
recommended.
Table 6. DC Operating Conditions (continued)
Parameter Symbol Min. Typ. Max. Units
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 13
3.1.3 Fusebox Supply Current Parameters
Table 7 lists the fusebox supply current parameters.
3.1.4 Interface Frequency Limits
Table 8 provides information for interface frequency limits.
Table 9 provides the recommended external crystal specifications.
Table 10 provides the recommended external reference clock oscillator specifications (when reference is
used from an external clock source).
Table 7. Fusebox Supply Current Parameters
Parameter Symbol Min. Typ. Max. Units
eFuse program current1
Current to program one eFuse bit
The associated VDD_FUSE supply = 3.6 V
1The current Iprogram is during program time (tprogram).
Iprogram 26 35 62 mA
eFuse read current2
Current to read an 8-bit eFuse word
2The current Iread is present for approximately 50 ns of the read access to the 8-bit word.
Iread 12.5 15 mA
Table 8. Interface Frequency Limits
Parameter Min. Typ. Max. Units
JTAG: TCK Frequency of Operation DC 5 10 MHz
OSC24M_XTAL Oscillator 24 MHz
OSC32K_XTAL Oscillator 32.768 kHz
Table 9. Recommended External Crystal Specifications
24 MHz 32.768 kHz
Frequency Tolerance <= ± 30 ppm <= ± 30 ppm
ESR < 80 Ω50 K~60 K
Load Capacitor 8 pF–12 pF 6 pF–8 pF (12 pF–16 pF on each pin)
Shunt Capacitor < 7 pF 1 pF
Drive Level > 150 µW > 1 µW
Table 10. Recommended External Reference Clock Specifications
24 MHz 32.768 kHz
VOH min = 0.7* VDD min = 0.7* VDD
VOL max = 0.3* VDD max = 0.3* VDD
Frequency Tolerance = 30 ppm = 30 ppm
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
14 Freescale Semiconductor
3.1.5 USB_PHY Current Consumption
Table 11 provides information for USB_PHY current consumption.
3.1.6 Power Modes
Table 12 describes the core, clock, and module settings for the different power modes of the processor.
TRISE 1% TCLOCK 1% TCLOCK
TFALL 1% TCLOCK 1% TCLOCK
Duty Cycle 50% 50%
Table 11. USB PHY Current Consumption1
1Values must be verified
Parameter Conditions Typ.
(@Typ. Temp)
Max.
(@Max. Temp) Unit
Analog supply
USBPHY1_VDDA_BIAS, USBPHY1_UPLL_VDD,
USBPHY1_VDDA (3.3 V)
Full speed
Rx 11.4
mA
Tx 22,6
High speed
Rx 21.5
Tx 33.8
Suspend — 0.6 μA
Analog supply
USBPHY2_VDD (3.3 V) Full Speed
Rx 120 μA
Tx 25 mA
Low Speed
Rx 252 μA
Tx 5.5 mA
All supplies Suspend 50 100 μA
Table 12. i.MX25 Power Mode Settings
Core/Clock/Module
Power Mode
Doze Wait Stop/Sleep1Run (266 MHz) Run (400 MHz)
ARM core Platform clock is off In wait-for-interrupt mode Active @
266 MHz
Active @
400 MHz
Well bias On Off On Off Off
MCU PLL On On Off On On
USB PLL Off Off Off On On
OSC24M On On Off On On
OSC32K On On On On On
Other modules Off Off Off On On
Table 10. Recommended External Reference Clock Specifications (continued)
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 15
Table 13 shows typical current consumption for the various power supplies under the various power
modes.
In the reduced power mode, shown in Table 14, the i.MX25 is powered down, while the RTC clock and
the secure keys (in secure-use case), remain operational. BAT_VDD is tied to a battery while all other
supplies are turned off.
NOTE
In this low-power mode, i.MX25 cannot be woken up with an interrupt; it
must be powered back up before it can detect any events.
1Sleep mode differs from stop mode in that the core voltage is reduced to 1 V.
Table 13. i.MX25 Power Mode Current Consumption
Power Group Power Supplies Voltage
Setting
Current Consumption for Power Modes1
1Values are typical, under typical use conditions.
Doze Wait Stop Sleep
NVCC_EMI NVCC_EMI1
NVCC_EMI2
3.0 V 5 μA3.15 μA3.51μA3.61μA
NVCC_CRM NVCC_CRM 3.0 V 1.15 μA4.31μΑ 0.267 μΑ 0.32 μΑ
NVCC_
OTHER
NVCC_SDIO
NVCC_CSI
NVCC_NFC
NVCC_JTAG
NVCC_LCDC
NVCC_MISC
3.0 V 31.2 μA29.5μΑ 31.7 μA32.1μΑ
NVCC_ADC NVCC_ADC 3.0 V 163 μA3.25μΑ 1.14 μΑ 0.871 μΑ
OSC24M OSC24M_
VDD
3.0 V 906 μA903μΑ 10.2 μΑ mA 10.5 μΑ
PLL_VDD MPLL_VDD
UPLL_VDD
1.4 V 6.83 mA 6.83 mΑ38.9 μΑ 39.1 μΑ
QVDD QVDD 1.15 V 8.79 mA 11.28 mA 842 μA 665 μA
USBPHY1_
VDDA
USBPHY1_
VDDA
3.17 V 240 μA240μΑ 241 μΑ 242 μΑ
USBPHY1_
VDDA_VBIAS
USBPHY1_
VDDA_VBIAS
3.17 V 0.6 μΑ 1.46 μΑ 0.328 μΑ 0.231 μΑ
USBPHY1_
UPLL_VDD
USBPHY1_
UPLL_VDD
3.17 V 201 μΑ 201 μΑ 191 μΑ 191 μΑ
USBPHY2 USBPHY2_
VDD
3.0 V 158 μA 0158 μΑ 164 μΑ 164 μΑ
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
16 Freescale Semiconductor
3.2 Supply Power-Up/Power-Down Requirements and Restrictions
Any i.MX25 board design must comply with the power-up and power-down sequence guidelines given in
this section to ensure reliable operation of the device. Recommended power-up and power-down
sequences are given in the following subsections.
CAUTION
Deviations from the guidelines in this section may result in the following
situations:
Excessive current during power-up phase
Prevention of the device from booting
Irreversible damage to the i.MX25 (worst-case scenario)
NOTE
For security applications, the coin battery must be connected during both
power-up and power-down sequences to ensure that security keys are not
unintentionally erased.
3.2.1 Power-Up Sequence
For those users that are not using DryIce/SRTC, the following power-up sequence is recommended:
1. Assert power on reset (POR).
2. Turn on QVDD digital logic domain supplies.
3. Turn on NVCCx digital I/O power supplies after QVDD is stable.
4. Turn on all other analog power supplies, including USBPHY1_VDDA_BIAS,
USBPHY1_UPLL_VDD, USBPHY1_VDDA, USBPHY2_VDD, OSC24M_VDD,
MPPLL_VDD, UPLL_VDD, NVCC_ADC, and FUSEVDD (FUSEVDD is tied to GND if fuses
are not programmed), after all NVCCx digital I/O supplies are stable.
5. Negate the POR signal.
Table 14. iMX25 Reduced Power Mode Current Consumption
Power Group Power Supply Voltage Setting Typical Current Consumption
BAT_VDD BAT_VDD 1.15 V 9.95 μA
1.55 V 12.6 μA
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 17
NOTE
The user is advised to connect FUSEVDD to GND except when fuses
are programmed, to prevent unintentional blowing of fuses.
Other power-up sequences may be possible; however, the above
sequence has been verified and is recommended.
There is a 1 ms minimum time between supplies coming up, and a 1 ms
minimum time between POR_B assert and de-assert.
The dV/dT should be no faster than 0.25 V/μs for all power supplies, to
avoid triggering ESD circuit.
Figure 2 shows the power-up sequence diagram. After POR_B is asserted, Core VDD and NVDDx can be
powered up. After Core VDD and NVDDx are stable, the analog supplies can be powered up.
Figure 2. Power-Up Sequence Diagram
3.2.2 Power-Down Sequence
There are no special requirements for the power-down sequence. All power supplies can be shut down at
the same time.
3.2.3 SRTC DryIce Power-Up/Down Sequence
In order to guarantee DryIce power-loss protection, including retention of SRTC time data during power
down, users must do the following:
Place a proper capacitor on the NVCC_DRYICE output pin, and
Implement the below power-up/down sequence
1. Assert power on reset (POR).
2. Turn on NVCC_CRM.
3. Turn on QVDD digital logic domain supplies for not less than 1 ms and not more than 32 ms, after
NVCC_CRM reaches 90% of 3.3 V.
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
18 Freescale Semiconductor
NOTE
This is to guarantee that POR is stable already at NVCC_CRM/QVDD
power domain interface before QVDD is turned on, and POR instantly
propagates to QVDD domain after QVDD is turned on.
4. Turn on other NVCCx digital I/O power supplies for not less than 1 ms and not more than 32 ms,
after QVDD reaches 90% of 1.2 V.
5. Turn on all other analog power supplies, including USBPHY1_VDDA_BIAS,
USBPHY1_UPLL_VDD, USBPHY1_VDDA, USBPHY2_VDD, NVCC_ADC,
OSC24M_VDD, MPPLL_VDD, UPLL_VDD, and FUSEVDD (FUSEVDD is tied to GND if
fuses are not programmed) for not less than 1 ms and not more than 32 ms, after NVCCx reaches
90% of 3.3 V.
NOTE
This is to guarantee that analog peripherals can get properly initialized
(reset) values from QVDD domain and NVCCx domain.
6. Negate the POR signal for at least 90 μs after all previous steps.
NOTE
This is to guarantee that both POR logic and clocks are stable inside the
i.MX25 chip, before POR is removed.
The dV/dT should be no faster than 0.25 V/us for all power supplies, to
avoid triggering ESD circuit.
In addition, the following power-down sequence is recommended:
1. Turn off power for analog parts, including USBPHY1_VDDA_BIAS, USBPHY1_UPLL_VDD,
USBPHY1_VDDA, USBPHY2_VDD, NVCC_ADC, and FUSEVDD (FUSEVDD is tied to GND
if fuses are not programmed).
2. Turn off QVDD.
3. Turn off NVCCx, PLL, OSC, and other powers.
NOTE
The power-down steps can be executed simultaneously, or very shortly one
after another.
3.3 Power Characteristics
Table 15 shows values representing maximum current numbers for the i.MX25 under worst case voltage
and temperature conditions. These values are derived from the i.MX25 with core clock speed up to
400 MHz. Additionally, no power saving techniques such as clock gating were implemented when
measuring these values. Common supplies are bundled according to the i.MX25 power-up sequence
requirements. Peak numbers are provided for system designers so that the i.MX25 power supply
requirements are satisfied during startup and transient conditions. Freescale recommends that system
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 19
current measurements are taken with customer-specific use-cases to reflect the normal operating
conditions in the end system.
The method for obtaining the maximum current is as follows:
1. Measure the worst case power consumption on individual rails using directed test on i.MX25.
2. Correlate the worst case power consumption power measurements with the worst case power
consumption simulations.
3. Combine common voltage rails based on the power supply sequencing requirements (add the
worst case power consumption on each rail within some test cases from several test cases run, to
maximize different rails in the power group).
4. Guard the worst case numbers for temperature and process variation.
5. The sum of individual rails is greater than the real world power consumption, since a real system
does not typically maximize the power consumption on all peripherals simultaneously.
6. BATT_VDD current is measured when the system is in reduced power mode maintaining the
RTC. When the system is in run mode, QVDD is used to supply the DryIce, so this current
becomes negligible. See Table 12, for more details on the power modes.
NOTE
The values mentioned above should not be taken as a typical max run data
for specific use cases. These values are Absolute MAX data. Freescale
recommends that the system current measurements are taken with
customer-specific use-cases to reflect normal operating conditions in the
end system.
Table 15. Power Consumption
Power Supply Voltage (V) Max Current (mA)
QVDD 1.52 360
NVCC_EMI1, NVCC_EMI2 1.9 30
NVCC_CRM, NVCC_SDIO, NVCC_CSI,
NVCC_NFC, NVCC_JTAG, NVCC_LCDC,
NVCC_MISC
3.6 110
MPLL_VDD, UPLL_VDD 1.65 20
USBPHY1_VDDA_BIAS, USBPHY1_UPLL_VDD,
USBPHY1_VDDA, USBPHY2_VDD,
OSC24M_VDD, NVCC_ADC
3.3 40
FUSE_VDD1
1The FUSE_VDD rail is connected to ground. it only needs a voltage if the system fuse burning is needed.
3.6 62
BATT_VDD 1.55 0.030
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
20 Freescale Semiconductor
3.4 Thermal Characteristics
The thermal resistance characteristics for the device are given in Table 16. These values are measured
under the following conditions:
Two-layer substrate
Substrate solder mask thickness: 0.025 mm
Substrate metal thicknesses: 0.016 mm
Substrate core thickness: 0.200 mm
Core through I.D: 0.118 mm, Core through plating 0.016 mm.
Flag: Trace style with ground balls under the die connected to the flag
Die Attach: 0.033 mm non-conductive die attach, k = 0.3 W/m K
Mold compound: Generic mold compound; k = 0.9 W/m K
3.5 I/O DC Parameters
This section includes the DC parameters of the following I/O types:
DDR I/O: Mobile DDR (mDDR), double data rate (DDR2), or synchronous dynamic random
access memory (SDRAM)
General purpose I/O (GPIO)
Table 16. Thermal Resistance Data
Rating Condition Symbol Value Unit
Junction to ambient1 natural convection
1Junction-to-ambient thermal resistance determined per JEDC JESD51-3 and JESD51-6. Thermal test board meets JEDEC
specification for this package.
Single layer board (1s) ReJA 55 °C/W
Junction to ambient1 natural convection Four layer board (2s2p) ReJA 33 °C/W
Junction to ambient1 (@200 ft/min) Single layer board (1s) ReJMA 46 °C/W
Junction to ambient1 (@200 ft/min) Four layer board (2s2p) ReJMA 29 °C/W
Junction to boards2
2Junction-to-board thermal resistance determined per JEDC JESD51-8. Thermal test board meets JEDEC specification for
this package.
—R
eJB 22 °C/W
Junction to case (top)3
3Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
—R
eJCtop 13 °C/W
Junction to package top4
4Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, this thermal characterization parameter is written
as Psi-JT.
Natural convection ΨJT C/W
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 21
NOTE
The term ‘OVDD’ in this section refers to the associated supply rail of an
input or output. The association is shown in the “Signal Multiplexing”
chapter of the reference manual.
3.5.1 DDR I/O DC Parameters
The DDR pad type is configured by the IOMUXC_SW_PAD_CTL_GRP_DDRTYPE register (see the
External Signals and Pin Multiplexing chapter of the i.MX25 Reference Manual for details).
3.5.1.1 DDR_TYPE = 00 Standard Setting DDR I/O DC Parameters
Table 17 shows the I/O parameters for mobile DDR. These settings are suitable for mDDR and DDR2
1.8V (± 5%) applications.
Table 17. Mobile DDR I/O DC Electrical Characteristics
DC Electrical Characteristics Symbol Test Conditions Min. Typ. Max. Units
High-level output voltage Voh IOH = –1mA
IOH = Specified Drive
OVDD – 0.08
0.8 × OVDD
——V
Low-level output voltage Vol IOL = 1mA
IOL = Specified Drive
——0.08
0.2 × OVDD
V
High-level output current I
Ioh
Voh = 0.8 × OVDDV
Standard Drive
High Drive
Max. Drive
–3.6
–7.2
–10.8
——
mA
Low-level output current I
Iol
Vol = 0.2 × OVDDV
Standard Drive
High Drive
Max. Drive
3.6
7.2
10.8
——
mA
High-level DC CMOS input voltage VIH 0.7 × OVDD OVDD OVDD+0.3 V
Low-level DC CMOS input voltage VIL –0.3 0 0.3 × OVDD V
Differential receiver VTH+ VTH+ 100 mV
Differential receiver VTH- VTH- –100 mV
Input current (no pull-up/down) IIN VI = 0
VI = OVDD
——110
60
nA
High-impedance I/O supply current Icc-ovdd VI = OVDD or 0 990 nA
High-impedance core supply current Icc-vddi VI = VDD or 0 1220 nA
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
22 Freescale Semiconductor
3.5.1.2 DDR_TYPE = 01 SDRAM I/O DC Parameters
Table 18 shows the DC I/O parameters for SDRAM.
3.5.1.3 DDR_TYPE = 10 Max Setting DDR I/O DC Parameters
Table 19 shows the I/O parameters for DDR2 (SSTL_18).
Table 18. SDRAM DC Electrical Characteristics
DC Electrical Characteristics Symbol Test Conditions Min. Typ. Max. Units
High-level output voltage Voh Ioh = Specified Drive
(Ioh = –4, –8, –12, –16mA)
2.4 — V
Low-level output voltage Vol Ioh = Specified Drive
(Ioh = 4, 8, 12, 16mA)
——0.4V
High-level output current I
Ioh
Standard Drive
High Drive
Max. Drive
–4.0
–8.0
–12.0
——mA
Low-level output current I
Iol
Standard Drive
High Drive
Max. Drive
4.0
8.0
12.0
——mA
High-level DC input voltage VIH 2.0 3.6 V
Low-level DC input voltage VIL –0.3 V 0.8 V
Input current (no pull-up/down) IIN VI = 0
VI = OVDD
——150
80
nA
High-impedance I/O supply current Icc-ovdd VI = OVDD or 0 1180 nA
High-impedance core supply current Icc-vddi VI = VDD or 0 1220 nA
Table 19. DDR2 (SSTL_18) I/O DC Electrical Characteristics
DC Electrical Characteristics Symbol Test Conditions Min. Typ. Max. Units
High-level output voltage Voh OVDD – 0.28 V
Low-level output voltage Vol 0.28 V
Output min. source current1IIoh –13.4 — mA
Output min. sink current2IIol 13.4 — mA
DC input logic high VIH(dc) OVDD/2 + 0.125 OVDD + 0.3 V
DC input logic low VIL(dc) –0.3 V OVDD/2 – 0.125 V
DC input signal voltage3 (for differential
signal)
Vin(dc) –0.3 OVDD + 0.3 V
DC differential input voltage4Vid(dc) 0.25 OVDD+0.6 V
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 23
3.5.2 GPIO I/O DC Parameters
Table 20 shows the I/O parameters for GPIO.
Termination voltage5Vtt OVDD/2 – 0.04 OVDD/2 OVDD/2 + 0.04
Input current6(no pull-up/down) IIN VI = 0
VI = OVDD
— 110
60
nA
High-impedance I/O supply current6Icc-ovdd VI = OVDD or 0 980 nA
High-impedance core supply current6Icc-vddi VI = VDD or 0 1210 nA
1OVDD = 1.7 V; Vout = 1.42 V. (Vout-OVDD)/IOH must be less than 21 W for values of Vout between OVDD and OVDD-0.28 V.
2OVDD = 1.7 V; Vout = 280 mV. Vout/IOL must be less than 21 W for values of Vout between 0 V and 280 mV. Simulation circuit
for parameters Voh and Vol for I/O cells is below.
3Vin(dc) specifies the allowable DC excursion of each differential input.
4Vid(dc) specifies the input differential voltage required for switching. The minimum value is equal to Vih(dc) - Vil(dc).
5Vtt is expected to track OVDD/2.
6Minimum condition: BCS model, 1.95 V, and –40 °C. Typical condition: typical model, 1.8 V, and 25 °C. Maximum condition:
wcs model, 1.65 V, and 105 °C.
Table 20. GPIO DC Electrical Characteristics
DC Electrical Characteristics Symbol Test Conditions Min. Typ. Max. Units
High-level output voltage1Voh Ioh=–1mA
Ioh = Specified Drive
OVDD – 0.15
0.8 × OVDD
——V
Low-level output voltage1Vol Iol=1mA
Iol=Specified Drive
— 0.15
0.2 × OVDD
V
High-level output current for slow mode I
Ioh
Voh=0.8 × OVDD
Standard Drive
High Drive
Max. Drive
–2.0
–4.0
–8.0
——mA
High-level output current for fast mode I
Ioh
Voh=0.8 × OVDD
Standard Drive
High Drive
Max. Drive
–4.0
–6.0
–8.0
——mA
Low-level output current for slow mode I
Iol
Voh=0.2 × OVDD
Standard Drive
High Drive
Max. Drive
2.0
4.0
8.0
——mA
Low-level output current for fast mode I
Iol
Voh=0.2 × OVDD
Standard Drive
High Drive
Max. Drive
4.0
6.0
8.0
——mA
High-level DC input voltage VIH 0.7 × OVDD — OVDD V
Low-level DC input voltage VIL –0.3 V 0.3 × OVDD V
Table 19. DDR2 (SSTL_18) I/O DC Electrical Characteristics (continued)
DC Electrical Characteristics Symbol Test Conditions Min. Typ. Max. Units
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
24 Freescale Semiconductor
3.6 AC Electrical Characteristics
This section provides the AC parameters for slow and fast I/O.
Input hysteresis VHYS OVDD = 3.3 V
OVDD = 1.8V
370
290
— 420
320
mV
Schmitt trigger VT+1VT+ 0.5 × OVDD — V
Schmitt trigger VT–1VT– 0.5 × OVDD V
Pull-up resistor (22 kΩ PU) Rpu Vi=0 18.5 22 25.6 kΩ
Pull-up resistor (47 kΩ PU) Rpu Vi=0 41 47 55 kΩ
Pull-up resistor (100 kΩ PU) Rpu Vi=0 85 100 120 kΩ
Pull-down resistor (100 kΩ PD) Rpd VI = OVDD 85 100 120 kΩ
Input current (no pull-up/down) IIN VI = 0, OVDD = 3.3 V
VI = OVDD = 3.3 V
VI = 0, OVDD = 1.8 V
VI = OVDD = 1.8 V
— 100
60
77
50
nA
Input current (22 kΩ PU) IIN VI = 0, OVDD = 3.3 V
VI = OVDD = 3.3 V
VI = 0, OVDD = 1.8 V
VI = OVDD = 1.8 V
117
0.0001
64
0.0001
— 184
0.0001
104
0.0001
μA
Input current (47 kΩ PU) IIN VI = 0, OVDD = 3.3 V
VI = OVDD = 3.3 V
VI = 0, OVDD = 1.8 V
VI = OVDD = 1.8 V
54
0.0001
30
0.0001
—88
0.0001
49
0.0001
μA
Input current (100 kΩ PU) IIN VI = 0, OVDD = 3.3 V
VI = OVDD = 3.3 V
VI = 0, OVDD = 1.8 V
VI = OVDD = 1.8 V
25
0.0001
14
0.0001
—42
0.0001
23
0.0001
μA
Input current (100 kΩ PD) IIN VI = 0, OVDD = 3.3 V
VI = OVDD = 3.3 V
VI = 0, OVDD = 1.8 V
VI = OVDD = 1.8 V
25
0.0001
14
0.0001
—42
0.001
23
0.0001
μA
High-impedance I/O supply current Icc–ovdd VI = 0, OVDD = 3.3 V
VI = OVDD = 3.3 V
VI = 0, OVDD = 1.8 V
VI = OVDD = 1.8 V
— 688
688
560
560
nA
High-impedance core supply current Icc–vddi VI = 0, OVDD = 3.3 V
VI = OVDD = 3.3 V
VI = 0, OVDD = 1.8 V
VI = OVDD = 1.8 V
— 490
490
410
410
nA
1Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
Table 20. GPIO DC Electrical Characteristics (continued)
DC Electrical Characteristics Symbol Test Conditions Min. Typ. Max. Units
«+1 7777777
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 25
Figure 3 shows the load circuit for output. Figure 4 through Figure 6 show the output transition time and
propagation waveforms.
Figure 3. Load Circuit for Output
Figure 4. Output Pad Transition Time Waveform
Figure 5. Output Pad Propagation and Transition Time Waveform
Figure 6. Output Enable to Output Valid
Test Point
From Output
Under Test
CL
CL includes package, probe and jig capacitance
0V
OVDD
20%
80% 80%
20%
PA 1 PA1
Output (at pad)
tPHL
tPLH
0V
OVDD
50%
50%
50%
20%
80% 80%
20%
tTLH tTHL
Output (at pad)
Input from core 0V
VDD
50%
(1 ns transition times)
VDD
50%
50%
signal open from core
tpv
OVDD
Output (at pad)
signal “1” pdat from core
signal “0” pdat from core
VDD
0
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
26 Freescale Semiconductor
3.6.1 Slow I/O AC Parameters
Table 21 shows the slow I/O AC parameters.
Table 21. Slow I/O AC Parameters
Parameter Symbol Test Voltage Test
Capacitance
Min.
Rise/Fall
Typ.
Rise/Fall
Max.
Rise/Fall Units
Duty cycle Fduty 40 60 %
Output pad transition times1 (max.
drive)
tpr 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
0.95/0.84
1.58/1.37
2.70/2.50
3.40/3.20
1.36/1.11
2.19/1.77
1.80/1.40
2.80/2.14
2.06/1.60
3.20/2.47
3.01/2.37
4.63/3.38
ns
Output pad transition times1 (high
drive)
tpr 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
1.60/1.39
2.94/2.51
1.85/1.48
2.93/2.37
2.23/1.79
4.05/3.17
2.90/2.17
4.56/3.40
3.26/2.50
5.72/4.27
4.75/3.43
7.33/5.26
Output pad transition times1
(standard drive)
tpr 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
3.07/2.62
5.82/4.95
3.04/2.47
5.37/4.40
4.22/3.30
7.94/6.19
4.73/3.50
7.70/8.10
6.03/4.48
11.28/8.28
3.01/2.36
4.63/3.38
Output pad propagation delay1
(max. drive), 50%–50%
tpo 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
1.92/2.1
2.44/2.53
2.05/2.27
2.71/2.84
2.96/2.96
3.7/3.64
3.32/3.67
4.39/4.51
4.47/4.38
5.54/5.31
5.27/5.85
7.00/7.15
ns
Output pad propagation delay1
(high drive), 50%–50%
tpo 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
2.35/2.49
3.31/3.43
2.58/2.69
3.62/3.60
3.58/3.61
4.9/4.786
4.17/4.27
5.86/5.61
5.35/5.24
7.19/6.8
6.64/6.74
9.34/8.76
Output pad propagation delay1
(standard drive), 50%–50%
tpo 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
3.39/3.51
5.28/5.35
3.71/3.68
5.52/5.32
5.03/4.89
7.6/7.14
6.03/5.75
8.80/7.96
7.39/6.95
10.97/9.45
9.64/8.97
13.9/11.3
Output pad propagation delay1
(max. drive), 40%–60%
tpo 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
1.942/2.04
2.378/2.48
2.03/2.28
2.59/2.73
2.923/2.95
3.541/3.53
3.19/3.59
4.10/4.33
4.33/4.3
5.29/5.09
4.97/5.64
6.43/6.77
ns
Output pad propagation delay1
(high drive), 40%–60%
tpo 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
2.29/2.44
3.05/3.20
2.45/2.62
3.36/3.39
3.42/3.49
4.46/4.45
3.86/4.07
5.34/5.22
5.05/5.02
6.53/6.3
6.02/6.35
8.40/8.08
Output pad propagation delay1
(standard drive), 40%–60%
tpo 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
3.12/3.26
4.60/4.73
3.43/3.46
4.89/4.79
4.58/4.53
6.61/6.32
5.48/5.34
7.75/7.16
6.69/6.42
9.5/8.32
8.65/8.26
12.2/9.97
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 27
Output enable to output valid
delay1 (max. drive), 50%–50%
tpv 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
2.13/2.01
2.65/2.46
2.31/2.45
2.95/3.01
3.3/3.045
4.038/3.639
3.76/4.00
4.81/4.82
5.072/4.609
6.142/5.423
6.11/6.47
7.81/7.73
ns
Output enable to output valid
delay1 (high drive), 50%–50%
tpv 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
2.56/2.43
3.55/3.21
2.85/2.90
3.87/3.78
3.91/3.604
5.21/4.598
4.65/4.64
6.31/5.95
5.937/5.36
7.776/6.694
7.58/7.44
10.3/9.43
Output enable to output valid
delay1 (standard drive), 50%–50%
tpv 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
3.60/3.28
5.50/4.81
4.04/3.94
5.85/5.56
5.35/4.70
7.93/6.603
6.65/6.21
9.47/8.49
7.97/6.836
11.58/9.338
10.9/9.22
15.5/13.3
Output enable to output valid
delay1 (max. drive), 40%–60%
tpv 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
2.152/1.7
2.6/2.07
2.28/2.46
2.83/2.93
3.25/2.68
3.88/3.17
3.62/3.92
4.50/4.62
4.93/4.162
5.842/4.846
5.77/6.24
7.20/7.32
ns
Output enable to output valid
delay1 (high drive), 40%–60%
tpv 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
2.497/2.036
3.254/2.647
2.71/2.81
3.59/3.56
3.75/3.135
4.8/3.9
4.31/4.23
5.75/5.54
5.633/4.782
7.117/5.84
6.89/7.01
9.23/8.71
Output enable to output valid
delay1 (standard drive), 40%–60%
tpv 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
3.326/2.7
4.81/3.85
3.73/3.69
5.16/4.99
4.9/3.9
6.9/5.4
6.04/5.77
8.28/7.61
7.269/5.95
10.12/7.86
9.81/9.11
13.4/11.8
Output pad slew rate2 (max. drive) tps 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
0.79/1.12
0.49/0.73
0.30/0.42
0.20/0.29
1.30/1.77
0.84/1.23
0.54/0.73
0.35/0.50
2.02/2.58
1.19/1.58
0.91/1.20
0.60/0.80
V/ns
Output pad slew rate2 (high drive) tps 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
0.48/0.72
0.27/0.42
0.19/0.28
0.12/0.18
0.76/1.10
0.41/0.62
0.34/0.49
0.34/0.49
1.17/1.56
0.63/0.86
0.58/0/79
0.36/0.49
Output pad slew rate2 (standard
drive)
tps 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
0.25/0.40
0.14/0.21
0.12/0.18
0.07/0.11
0.40/0.59
0.21/0.32
0.20/0.30
0.11/0.17
0.60/0.83
0.32/0.44
0.34/0.47
0.20/0.27
Table 21. Slow I/O AC Parameters (continued)
Parameter Symbol Test Voltage Test
Capacitance
Min.
Rise/Fall
Typ.
Rise/Fall
Max.
Rise/Fall Units
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
28 Freescale Semiconductor
Output pad dI/dt3 (max. drive) tdit 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
15
16
7
7
36
38
21
22
76
80
56
58
mA
/ns
Output pad dI/dt3 (high drive) tdit 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
8
9
5
5
20
21
14
15
45
47
38
40
Output pad dI/dt3 (standard
drive)
tdit 3.0–3.6 V
3.0–3.6 V
1.65–1.95 V
1.65–1.95 V
25 pF
50 pF
25 pF
50 pF
4
4
2
2
10
10
7
7
22
23
18
19
Input pad propagation delay
without hysteresis, 50%–50%4
tpi 1.6 pF 0.82/0.47
0.74/1
1.1/0.76
1.1/1.5
1.6/1.04
1.75/2.16
ns
Input pad propagation delay with
hysteresis, 50%–50%4
tpi 1.6 pF 1.1/1.3
1.75/1.63
1.43/1.6
2.67/2.22
2/2
2.92/3
Input pad propagation delay
without hysteresis, 40%–60%4
tpi 1.6 pF 1.62/1.28
1.82/1.55
1.9/1.56
2.28/1.87
2.38/1.82
2.95/2.54
Input pad propagation delay with
hysteresis, 40%–60%4
tpi 1.6 pF 1.88/2.1
2.4/2.6
2.2/2.4
3/3.07
2.7/2.75
3.77/3.71
Input pad transition times without
hysteresis4
trfi 1.6 pF 0.16/0.12 0.23/0.18 0.33/0.29
Input pad transition times with
hysteresis4
trfi 1.6 pF 0.16/0.13 0.22/0.18 0.33/0.29
Maximum input transition times5trm 25 ns
1Maximum condition for tpr, tpo, and tpv: wcs model, 1.1 V, I/O 3.0 V (3.0–3.6 V range) or 1.65 V (1.65–1.95 V range), and 105
°C. Minimum condition for tpr, tpo, and tpv: bcs model, 1.3 V, I/O 3.6 V (3.0–3.6 V range) or 1.95 V (1.65–1.95 V range), and
–40 °C. Input transition time from core is 1 ns (20%–80%).
2Minimum condition for tps: wcs model, 1.1 V, I/O 3.0 V (3.0–3.6 V range) or 1.65 V (1.65–1.95 V range), and 105 °C. tps is
measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.
3Maximum condition for tdit: bcs model, 1.3 V, I/O 3.6 V (3.0–3.6 V range) or 1.95 V (1.65–1.95 V range), and –40 °C.
4Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 3.0 V (3.0–3.6 V range) or 1.65 V (1.65–1.95 V range), and 105 °C.
Minimum condition for tpi and trfi: bcs model, 1.3 V, I/O 3.6 V or 1.95 V (1.65–1.95 V range), and –40 °C. Input transition time
from pad is 5 ns (20%–80%).
5Hysteresis mode is recommended for input with transition time greater than 25 ns.
Table 21. Slow I/O AC Parameters (continued)
Parameter Symbol Test Voltage Test
Capacitance
Min.
Rise/Fall
Typ.
Rise/Fall
Max.
Rise/Fall Units
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 29
3.6.2 Fast I/O AC Parameters
Table 22 shows the fast I/O AC parameters for OVDD = 1.65–1.95 V.
Table 22. Fast I/O AC Parameters for OVDD = 1.651.95 V
Parameter Symbol Test
Condition
Min.
Rise/Fall Typ. Max.
Rise/Fall Units
Duty cycle Fduty 40 60 %
Output pad transition times1 (max. drive) tpr 25 pF
50 pF
0.88/0.77
1.45/1.24
1.36/1.10
2.20/1.80
2.10/1.70
3.50/2.70
ns
Output pad transition times1 (high drive) tpr 25 pF
50 pF
1.10/0.92
1.84/1.54
1.65/1.33
2.80/2.20
2.64/2.10
4.40/3.30
ns
Output pad transition times1 (standard drive) tpr 25 pF
50 pF
1.60/1.35
2.74/2.26
2.47/1.95
4.20/3.20
3.99/3.10
6.56/4.86
ns
Output pad propagation delay1 (max. drive),
50%–50%
tpo 25 pF
50 pF
1.64/1.53
2.15/2.01
2.68/2.41
3.47/3.08
4.25/3.74
5.50/4.77
ns
Output pad propagation delay1 (high drive),
50%–50%
tpo 25 pF
50 pF
1.82/1.71
2.46/2.29
2.98/2.66
3.96/3.49
4.74/4.13
6.27/5.37
ns
Output pad propagation delay1 (standard drive),
50%–50%
tpo 25 pF
50 pF
2.24/2.06
3.17/2.92
3.63/3.15
5.09/4.41
5.73/4.84
8.06/6.75
ns
Output pad propagation delay1 (max. drive),
40%–60%
tpo 25 pF
50 pF
1.67/1.58
2.09/1.98
2.63/2.38
3.30/2.97
4.06/3.63
5.14/4.51
ns
Output pad propagation delay1 (high drive),
40%–60%
tpo 25 pF
50 pF
1.94/1.73
2.34/2.22
2.89/2.61
3.69/3.30
4.49/3.97
5.76/5.01
ns
Output pad propagation delay1 (standard drive),
40%–60%
tpo 25 pF
50 pF
2.15/1.99
2.94/2.74
3.39/2.99
4.65/4.07
5.28/4.53
7.28/6.13
ns
Output enable to output valid delay1 (max. drive),
50%–50%
tpv 25 pF
50 pF
1.87/1.70
2.36/2.16
3.06/2.71
3.83/3.37
4.97/4.30
6.18/5.30
ns
Output enable to output valid delay1 (high drive),
50%–50%
tpv 25 pF
50 pF
2.05/1.88
2.68/2.45
3.67/2.98
4.32/3.78
5.46/4.72
6.98/5.92
ns
Output enable to output valid delay1 (standard
drive), 50%–50%
tpv 25 pF
50 pF
2.49/2.25
3.40/3.08
4.06/3.50
5.50/4.73
6.57/5.49
8.88/7.37
ns
Output enable to output valid delay1 (max. drive),
40%–60%
tpv 25 pF
50 pF
1.90/1.74
2.30/2.13
3.00/2.69
3.65/3.24
4.76/4.18
5.79/5.02
ns
Output enable to output valid delay1 (high drive),
40%–60%
tpv 25 pF
50 pF
2.06/1.90
2.56/2.37
3.28/2.33
4.04/3.59
5.21/4.54
6.43/5.54
ns
Output enable to output valid delay1 (standard
drive), 40%–60%
tpv 25 pF
50 pF
2.39/2.18
3.16/2.89
3.80/3.18
5.03/4.37
6.05/5.14
8.02/6.72
ns
Output pad slew rate2 (max. drive) tps 25 pF
50 pF
0.40/0.57
0.25/0.36
0.72/0.97
0.43/0.61
1.2/1.5
0.72/0.95
V/ns
Output pad slew rate2 (high drive) tps 25 pF
50 pF
0.38/0.48
0.20/0.30
0.59/0.81
0.34/0.50
0.98/1.27
0.56/0.72
V/ns
Output pad slew rate2 (standard drive) tps 25 pF
50 pF
0.23/0.32
0.13/0.20
0.40/0.55
0.23/0.34
0.66/0.87
0.38/0.52
V/ns
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
30 Freescale Semiconductor
Table 23 shows the fast I/O AC parameters for OVDD = 3.0–3.6 V.
Output pad dI/dt3 (max. drive) tdit 25 pF
50 pF
7
7
43
46
112
118
mA/ns
Output pad dI/dt3 (high drive) tdit 25 pF
50 pF
11
12
31
33
81
85
mA/ns
Output pad dI/dt3 (standard
drive)
tdit 25 pF
50 pF
9
10
27
28
71
74
mA/ns
Input pad propagation delay without hysteresis,
50%–50%4
tpi 1.6 pF 0.74/1 1.1/1.5 1.75/2.16 ns
Input pad propagation delay with hysteresis,
50%–50%4
tpi 1.6 pF 1.75/1.63 2.67/2.22 2.92/3 ns
Input pad propagation delay without hysteresis,
40%–60%4
tpi 1.6 pF 1.82/1.55 2.28/1.87 2.95/2.54 ns
Input pad propagation delay with hysteresis,
40%–60%4
tpi 1.6 pF 2.4/2.6 3/3.07 3.77/3.71 ns
Input pad transition times without hysteresis4trfi 1.6 pF 0.16/0.12 0.30/0.18 0.33/0.29 ns
Input pad transition times with hysteresis4trfi 1.6 pF 0.16/0.13 0.30/0.18 0.33/0.29 ns
Maximum input transition times5trm 25 ns
1Maximum condition for tpr, tpo, and tpv: wcs model, 1.1 V, I/O 1.65 V, and 105 °C. Minimum condition for tpr, tpo, and tpv: bcs
model, 1.3 V, I/O 1.95 V, and –40 °C. Input transition time from core is 1 ns (20%–80%).
2Minimum condition for tps: wcs model, 1.1 V, I/O 1.65 V and 105 °C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
3Maximum condition for tdit: bcs model, 1.3 V, I/O 1.95 V and –40 °C.
4Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.65 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V,
I/O 1.95 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).
5Hysteresis mode is recommended for input with transition time greater than 25 ns.
Table 23. Fast I/O AC Parameters for OVDD = 3.03.6 V
Parameter Symbol Test
Condition
Min.
Rise/Fall Typ. Max.
Rise/Fall Units
Duty Cycle Fduty 40 60 %
Output Pad Transition Times1 (Max Drive) tpr 25 pF
50 pF
0.80/0.70
1.40/1.60
1.12/2.51
1.60/2.39
1.64/1.32
2.84/2.10
ns
Output Pad Transition Times1 (High Drive) tpr 25 pF
50 pF
1.00/0.90
1.95/1.66
1.43/1.16
2.66/2.09
2.05/1.60
3.70/2.80
ns
Output Pad Transition Times1 (Standard Drive) tpr 25 pF
50 pF
1.50/1.30
2.90/2.50
2.09/1.67
3.40/3.09
3.00/2.30
5.56/4.12
ns
Output Pad Propagation Delay1 (Max Drive),
50%–50%
tpo 25 pF
50 pF
1.20/1.28
1.67/1.75
1.74/1.73
2.39/2.32
2.67/2.52
3.58/3.33
ns
Table 22. Fast I/O AC Parameters for OVDD = 1.651.95 V (continued)
Parameter Symbol Test
Condition
Min.
Rise/Fall Typ. Max.
Rise/Fall Units
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 31
Output Pad Propagation Delay1 (High Drive),
50%–50%
tpo 25 pF
50 pF
1.35/1.42
1.98/2.04
1.95/1.91
2.81/2.68
2.96/2.76
4.16/3.78
ns
Output Pad Propagation Delay1 (Standard Drive),
50%–50%
tpo 25 pF
50 pF
1.77/1.85
2.70/2.78
2.54/2.48
3.82/3.62
3.80/3.60
5.62/5.10
ns
Output Pad Propagation Delay1 (Max Drive),
40%–60%
tpo 25 pF
50 pF
1.37/1.50
1.74/1.88
1.94/2.05
2.46/2.55
2.95/3.07
3.71/3.75
ns
Output Pad Propagation Delay1 (High Drive),
40%–60%
tpo 25 pF
50 pF
1.48/1.61
1.98/2.10
2.11/2.19
2.78/2.81
3.19/3.26
4.14/4.09
ns
Output Pad Propagation Delay1 (Standard Drive),
40%–60%
tpo 25 pF
50 pF
1.84/1.97
2.58/2.71
2.61/2.67
3.62/3.58
3.95/3.95
5.36/5.15
ns
Output Enable to Output Valid Delay1 (Max Drive),
50%–50%
tpv 25 pF
50 pF
1.34/1.32
1.81/1.79
1.91/1.81
2.56/2.40
2.92/2.67
3.83/3.47
ns
Output Enable to Output Valid Delay1 (High Drive),
50%–50%
tpv 25 pF
50 pF
1.48/1.47
2.12/2.1
2.12/2.00
2.98/2.76
3.21/2.92
4.41/3.94
ns
Output Enable to Output Valid Delay1 (Standard
Drive), 50%–50%
tpv 25 pF
50 pF
1.90/1.90
2.85/2.83
2.70/2.60
4.00/3.70
4.07/3.74
5.86/5.24
ns
Output Enable to Output Valid Delay1 (Max Drive),
40%–60%
tpv 25 pF
50 pF
1.55/1.42
1.93/1.81
2.25/2.08
2.77/2.58
3.50/3.31
4.24/3.99
ns
Output Enable to Output Valid Delay1 (High Drive),
40%–60%
tpv 25 pF
50 pF
1.67/1.54
2.16/2.03
2.41/2.23
3.08/2.86
3.74/3.51
4.66/4.34
ns
Output Enable to Output Valid Delay1 (Standard
Drive), 40%–60%
tpv 25 pF
50 pF
2.02/1.90
2.76/2.63
2.91/2.71
3.91/3.62
4.48/4.21
5.85/5.39
ns
Output Pad Slew Rate2 (Max Drive) tps 25 pF
50 pF
0.96/1.40
0.54/0.83
1.54/2.10
0.85/1.24
2.30/3.00
1.26/1.70
V/ns
Output Pad Slew Rate2 (High Drive) tps 25 pF
50 pF
0.76/1.10
0.41/0.64
1.19/1.71
0.63/0.95
1.78/2.39
0.95/1.30
V/ns
Output Pad Slew Rate2 (Standard Drive) tps 25 pF
50 pF
0.52/0.78
0.28/0.44
0.80/1.19
0.43/0.64
1.20/1.60
0.63/0.87
V/ns
Output Pad di/dt3 (Max Drive) didt 25 pF
50 pF
46
49
108
113
250
262
mA/ns
Output Pad di/dt3 (High Drive) didt 25 pF
50 pF
35
37
82
86
197
207
mA/ns
Output Pad di/dt3 (Standard Drive) didt 25 pF
50 pF
22
23
52
55
116
121
mA/ns
Input Pad Propagation Delay without Hysteresis,
50%–50%4
tpi 1.6pF 0.729/0.458 0.97/0.0649 1.404/0.97 ns
Input Pad Propagation Delay with Hysteresis,
50%–50%4
tpi 1.6pF 1.203/0.938 1.172/1.187 1.713/1.535 ns
Input Pad Propagation Delay without Hysteresis,
40%–60%4tpi 1.6pF 0.879/0.977 1.434/1.12 1.854/1.427 ns
Table 23. Fast I/O AC Parameters for OVDD = 3.03.6 V (continued)
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
32 Freescale Semiconductor
3.6.3 DDR I/O AC Parameters
The DDR pad type is configured by the IOMUXC_SW_PAD_CTL_GRP_DDRTYPE register (see
Chapter 4, “External Signals and Pin Multiplexing,” in the i.MX25 Multimedia Applications Processor
Reference Manual).
3.6.3.1 DDR_TYPE = 00 Standard Setting I/O AC Parameters and Requirements
Table 24 shows AC parameters for mobile DDR I/O. These settings are suitable for mDDR and DDR2
1.8V (± 5%) applications.
Input Pad Propagation Delay with Hysteresis,
40%–60%4
tpi 1.6pF 1.353/1.457 1.637/1.659 2.163/1.991 ns
Input Pad Transition Times without Hysteresis4trfi 1.6pF 0.16/0.12 0.23/0.18 0.33/0.29 ns
Input Pad Transition Times with Hysteresis4trfi 1.6pF 0.16/0.13 0.22/0.18 0.33/0.29 ns
Maximum Input Transition Times5trm — ns
1Maximum condition for tpr, tpo, and tpv: wcs model, 1.1 V, IO 3.0 V and 105 °C. Minimum condition for tpr, tpo, and tpv: bcs
model, 1.3 V, IO 3.6 V and –40 °C. Input transition time from core is 1ns (20%–80%).
2Minimum condition for tps: wcs model, 1.1 V, IO 3.0 V and 105 °C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
3Maximum condition for tdit: bcs model, 1.3 V, IO 3.6 V and –40 °C.
4Maximum condition for tpi and trfi: wcs model, 1.1 V, IO 3.0 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V,
IO 3.6 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).
5Hysteresis mode is recommended for input with transition time greater than 25 ns.
Table 24. AC Parameters for Mobile DDR I/O
Parameter Symbol Load
Condition
Min.
Rise/Fall Typ. Max.
Rise/Fall Units
Duty cycle Fduty 40 50 60 %
Clock frequency1f 133 MHz
Output pad transition times1 (max. drive) tpr 25 pF
50 pF
0.52/0.51
0.98/0.96
0.79/0.72
1.49/1.34
1.25/1.09
2.31/1.98
ns
Output pad transition times1 (high drive) tpr 25 pF
50 pF
1.13/1.10
2.15/2.10
1.74/1.55
3.28/2.92
2.71/2.30
5.11/4.31
ns
Output pad transition times1 (standard drive) tpr 25 pF
50 pF
2.26/2.19
4.30/4.18
3.46/3.07
6.59/5.79
5.39/4.56
10.13/8.55
ns
Output pad propagation delay1 (max. drive),
50%–50%
tpo 15 pF
35 pF
0.80/1.03
1.06/1.32
1.36/1.50
1.76/1.90
2.21/2.40
2.83/2.82
ns
Output pad propagation delay1 (high drive),
50%–50%
tpo 15 pF
35 pF
1.04/1.27
1.63/1.90
1.74/1.83
2.63/2.69
2.79/2.70
4.18/3.86
ns
Output pad propagation delay1 (standard drive),
50%–50%
tpo 15 pF
35 pF
1.55/1.80
2.72/3.06
2.53/2.57
4.31/4.29
4.03/3.76
6.80/6.19
ns
Output pad propagation delay1 (max. drive),
40%–60%
tpo 15 pF
35 pF
0.80/0.91
1.06/1.12
1.44/1.59
1.76/1.91
2.24/2.29
2.74/2.75
ns
Table 23. Fast I/O AC Parameters for OVDD = 3.03.6 V (continued)
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 33
Output pad propagation delay1 (high drive),
40%–60%
tpo 15 pF
35 pF
1.04/1.09
1.63/1.56
1.73/1.83
2.43/2.52
2.69/2.62
3.79/3.62
ns
Output pad propagation delay1 (standard drive),
40%–60%
tpo 15 pF
35 pF
1.50/1.74
2.73/2.42
2.36/2.41
3.77/3.78
3.67/3.46
5.86/5.37
ns
Output enable to output valid delay1 (max. drive),
50%–50%
tpv 15 pF
35 pF
1.17/1.01
1.43/1.30
1.93/1.61
2.33/2.00
3.06/2.55
3.69/3.13
ns
Output enable to output valid delay1 (high drive),
50%–50%
tpv 15 pF
35 pF
1.38/1.28
1.97/1.92
2.25/1.99
3.16/2.86
3.58/3.10
5.01/4.39
ns
Output enable to output valid delay1 (standard
drive), 50%–50%
tpv 15 pF
35 pF
1.92/1.57
3.12/3.16
3.11/2.79
4.97/4.59
4.98/4.13
7.97/6.98
ns
Output enable to output valid delay1 (max. drive),
40%–60%
tpv 15 pF
35 pF
1.28/1.12
1.49/1.36
2.01/1.70
2.33/2.01
3.09/2.60
3.60/3.06
ns
Output enable to output valid delay1 (high drive),
40%–60%
tpv 15 pF
35 pF
1.43/1.33
1.90/1.84
2.24/1.99
2.96/2.68
3.47/3.02
4.59/4.03
ns
Output enable to output valid delay1 (standard
drive), 40%–60%
tpv 15 pF
35 pF
1.85/1.78
2.80/2.81
2.91/2.62
4.37/4.53
4.54/3.96
6.88/6.05
ns
Output pad slew rate2 (max. drive) tps 25 pF
50 pF
0.80/0.92
0.43/0.50
1.35/1.50
0.72/0.81
2.23/2.27
1.66/1.68
V/ns
Output pad slew rate2 (high drive) tps 25 pF
50 pF
0.37/0.43
0.19/0.23
0.62/0.70
0.33/0.37
1.03/1.05
0.75/0.77
V/ns
Output pad slew rate2 (standard drive) tps 25 pF
50 pF
0.18/0.22
0.10/0.12
0.31/0.35
0.16/0.18
0.51/0.53
0.38/0.39
V/ns
Output pad dI/dt3 (max. drive) tdit 25 pF
50 pF
64
69
171
183
407
432
mA/ns
Output pad dI/dt3 (high drive) tdit 25 pF
50 pF
37
39
100
106
232
246
mA/ns
Output pad di/dt3 (standard drive) tdit 25 pF
50 pF
18
20
50
52
116
123
mA/ns
Input pad transition times4trfi 1.0 pF 0.07/0.08 0.11/0.13 0.16/0.20 ns
Input pad propagation delay, 50%–50%4tpi 1.0 pF 0.77/1.00 1.22/1.45 1.89/2.21 ns
Input pad propagation delay, 40%–60%4tpi 1.0 pF 1.59/1.82 2.04/2.27 2.69/3.01 ns
1Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1.65 V, and 105 °C. Minimum condition for tpr, tpo, and tpv:
bcs model, 1.3 V, I/O 1.95 V and –40 °C. Input transition time from core is 1 ns (20%–80%).
2Minimum condition for tps: wcs model, 1.1 V, I/O 1.65 V, and 105 °C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
3Maximum condition for tdit: bcs model, 1.3 V, I/O 1.95 V, and –40 °C.
4Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.65 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V,
I/O 1.95 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).
Table 24. AC Parameters for Mobile DDR I/O (continued)
Parameter Symbol Load
Condition
Min.
Rise/Fall Typ. Max.
Rise/Fall Units
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
34 Freescale Semiconductor
Table 25 shows the AC parameters for mobile DDR pbijtov18_33_ddr_clk I/O.
Table 25. AC Parameters for Mobile DDR pbijtov18_33_ddr_clk I/O
Parameter Symbol Load
Condition
Min.
Rise/Fall Typ. Max.
Rise/Fall Units
Duty cycle Fduty 40 50 60 %
Clock frequency1f 133 MHz
Output pad transition times1 (max. drive) tpr 25 pF
50 pF
0.52/0.51
0.98/0.96
0.79/0.72
1.49/1.34
1.25/1.09
2.31/1.98
ns
Output pad transition times1 (high drive) tpr 25 pF
50 pF
1.13/1.10
2.15/2.10
1.74/1.55
3.28/2.92
2.71/2.30
5.11/4.31
ns
Output pad transition times1 (standard drive) tpr 25 pF
50 pF
2.26/2.19
4.30/4.18
3.46/3.07
6.59/5.79
5.39/4.56
10.13/8.55
ns
Output pad propagation delay1 (max. drive),
50%–50% input signals and crossing of output
signals
tpo 15 pF
35 pF
1.28/1.19
1.56/1.47
1.97/1.83
2.37/2.23
2.98/2.78
3.57/3.37
ns
Output pad propagation delay1 (high drive),
50%–50% input signals and crossing of output
signals
tpo 15 pF
35 pF
1.54/1.43
2.14/2.04
2.34/2.20
3.22/3.08
3.54/3.33
4.85/4.65
ns
Output pad propagation delay1 (standard drive),
50%–50% input signals and crossing of output
signals
tpo 15 pF
35 pF
2.05/1.94
3.27/3.16
3.11/2.96
4.86/4.72
4.70/4.50
7.33/7.12
ns
Output pad propagation delay1 (max. drive),
40%–60% input signals and crossing of output
signals
tpo 15 pF
35 pF
1.45/1.36
1.73/1.64
2.13/2.00
2.53/2.40
3.14/2.94
3.74/3.54
ns
Output pad propagation delay1 (high drive),
40%–60% input signals and crossing of output
signals
tpo 15 pF
35 pF
1.70/1.60
2.31/2.21
2.51/2.37
3.38/3.24
3.70/3.50
5.02/4.82
ns
Output pad propagation delay1 (standard drive),
40%–60% input signals and crossing of output
signals
tpo 15 pF
35 pF
2.22/2.11
3.43/3.32
3.27/3.13
5.02/4.88
4.87/4.66
7.49/7.29
ns
Output enable to output valid delay1 (max. drive),
50%–50%
tpv 15 pF
35 pF
1.16/1.12
1.42/1.41
1.91/1.81
2.31/2.20
3.10/2.89
3.72/3.47
ns
Output enable to output valid delay1 (high drive),
50%–50%
tpv 15 pF
35 pF
1.39/1.39
1.98/2.02
2.28/2.18
3.18/3.04
3.69/3.43
5.08/4.69
ns
Output enable to output valid delay1 (standard
drive), 50%–50%
tpv 15 pF
35 pF
1.90/1.94
3.07/3.20
3.09/2.94
4.88/4.66
4.95/4.55
7.73/7.05
ns
Output enable to output valid delay1 (max. drive),
40%–60%
tpv 15 pF
35 pF
1.28/1.24
1.49/1.47
2.00/1.90
2.32/2.21
3.14/2.93
3.64/3.41
ns
Output enable to output valid delay1 (high drive),
40%–60%
tpv 15 pF
35 pF
1.45/1.44
1.92/1.95
2.28/2.19
2.99/2.87
3.60/3.36
4.69/4.36
ns
Output enable to output valid delay1 (standard
drive), 40%–60%
tpv 15 pF
35 pF
1.85/1.88
2.78/2.88
2.92/2.79
4.34/4.16
4.5894.25
6.79/6.24
ns
Output pad slew rate2 (max. drive) tps 25 pF
50 pF
0.37/0.45
0.30/0.36
0.64/0.79
0.52/0.61
1.14/1.36
0.90/1.02
V/ns
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 35
Table 26 shows the AC requirements for mobile DDR I/O.
Output pad slew rate2 (high drive) tps 25 pF
50 pF
0.30/0.37
0.21/0.25
0.51/0.63
0.36/0.42
091/1.06
0.63/0.67
V/ns
Output pad slew rate2 (standard drive) tps 25 pF
50 pF
0.22/0.26
0.13/0.16
0.37/0.44
0.23/0.26
0.65/0.72
0.39/0.40
V/ns
Output pad dI/dt3 (max. drive) tdit 25 pF
50 pF
65
70
171
183
426
450
mA/ns
Output pad dI/dt3 (high drive) tdit 25 pF
50 pF
31
33
82
87
233
245
mA/ns
Output pad dI/dt3 (standard drive) tdit 25 pF
50 pF
16
17
43
46
115
120
mA/ns
Input pad transition times4trfi 1.0 pF 0.07/0.08 0.11/0.13 0.16/0.20 ns
Input pad propagation delay, 50%–50%4tpi 1.0 pF 0.84/0.84 1.40/1.34 2.25/2.16 ns
Input pad propagation delay, 40%–60%4tpi 1.0 pF 1.66/1.66 2.22/2.16 3.06/2.97 ns
1Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1.65 V, and 105 °C. Minimum condition for tpr, tpo, and tpv:
bcs model, 1.3 V, I/O 1.95 V and –40 °C. Input transition time from core is 1 ns (20%–80%).
2Minimum condition for tps: wcs model, 1.1 V, I/O 1.65 V, and 105 °C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
3Maximum condition for tdit: bcs model, 1.3 V, I/O 1.95 V, and –40 °C.
4Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.65 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V,
I/O 1.95 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).
Table 26. AC Requirements for Mobile DDR I/O
Parameter Symbol Min. Max. Units
AC input logic high VIH(ac) 0.8 × OVDD OVDD+0.3 V
AC input logic low VIL(ac) –0.3 0.2 × OVDD V
AC differential input voltage Vid(ac) 0.6 × OVDD OVDD+0.6 V
AC differential cross point voltage for input Vix(ac) 0.4 × OVDD OVDD+0.6 V
Table 25. AC Parameters for Mobile DDR pbijtov18_33_ddr_clk I/O (continued)
Parameter Symbol Load
Condition
Min.
Rise/Fall Typ. Max.
Rise/Fall Units
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
36 Freescale Semiconductor
3.6.3.2 DDR_TYPE = 01 SDRAM I/O AC Parameters and Requirements
Table 27 shows AC parameters for SDRAM I/O.
Table 27. AC Parameters for SDRAM I/O
Parameter Symbol Load
Condition
Min.
Rise/Fall Typ. Max.
Rise/Fall Units
Duty cycle Fduty 40 50 60 %
Clock frequency1f 133 MHz
Output pad transition times1 (max. drive) tpr 25 pF
50 pF
0.82/0.87
1.56/1.67
1.14/1.13
2.13/2.09
1.62/1.50
3.015/2.7
7
ns
Output pad transition times1 (high drive) tpr 25 pF
50 pF
1.23/1.31
2.31/2.47
1.71/1.68
3.22/3.12
2.39/2.22
4.53/4.16
ns
Output pad transition times1 (standard drive) tpr 25 pF
50 pF
2.44/2.60
4.65/4.99
3.38/3.27
6.38/6.23
4.73/4.38
9.05/8.23
ns
Output pad propagation delay1 (max. drive),
50%–50%
tpo 15 pF
35 pF
0.97/1.19
2.85/3.21
1.69/0.75
2.02/2.30
2.17/2.46
2.93/3.27
ns
Output pad propagation delay1 (high drive),
50%–50%
tpo 15 pF
35 pF
1.15/1.39
3.57/3.91
1.72/1.93
2.54/2.85
2.51/2.77
3.66/3.97
ns
Output pad propagation delay1 (standard drive),
50%–50%
tpo 15 pF
35 pF
2.01/1.57
5.73/6.05
2.45/2.69
4.10/4.51
3.54/3.77
5.84/6.13
ns
Output pad propagation delay1 (max. drive),
40%–60%
tpo 15 pF
35 pF
1.06/1.26
1.38/1.38
1.53/1.73
1.96/2.23
2.18/2.47
2.78/3.12
ns
Output pad propagation delay1 (high drive),
40%–60%
tpo 15 pF
35 pF
1.15/1.20
1.75/1.67
1.72/1.93
2.37/2.66
2.45/2.71
3.35/3.67
ns
Output pad propagation delay1 (standard drive),
40%–60%
tpo 15 pF
35 pF
1.91/2.01
2.88/2.56
2.30/2.52
3.59/3.97
3.26/3.50
5.06/5.36
ns
Output enable to output valid delay1 (max. drive),
50%–50%
tpv 15 pF
35 pF
0.90/1.27
1.07/1.77
1.44/1.89
1.66/2.51
2.19/2.87
2.51/3.69
ns
Output enable to output valid delay1 (high drive),
50%–50%
tpv 15 pF
35 pF
1.01/1.48
1.37/2.33
1.58/2.16
2.06/3.09
2.38/3.23
3.06/4.46
ns
Output enable to output valid delay1 (standard drive),
50%–50%
tpv 15 pF
35 pF
1.32/2.14
2.04/3.67
2.02/3.00
3.00/4.91
3.01/4.36
4.40/6.90
ns
Output enable to output valid delay1 (max. drive),
40%–60%
tpv 15 pF
35 pF
1.03/1.34
1.16/1.74
1.54/1.94
1.74/2.44
2.26/2.88
2.55/3.54
ns
Output enable to output valid delay1 (high drive),
40%–60%
tpv 15 pF
35 pF
1.11/1.51
1.39/2.10
1.65/2.15
2.03/2.89
2.43/3.16
2.95/4.13
ns
Output enable to output valid delay1 (standard drive),
40%–60%
tpv 15 pF
35 pF
1.35/2.03
1.91/3.23
1.99/2.83
2.76/4.30
2.89/4.03
3.98/6.01
ns
Output pad slew rate2 (max. drive) tps 25 pF
50 pF
1.11/1.20
0.97/0.65
1.74/1.75
0.92/0.94
2.42/2.46
1.39/1.30
V/ns
Output pad slew rate2 (high drive) tps 25 pF
50 pF
0.76/0.80
0.40/0.43
1.16/1.19
0.61/0.63
1.76/1.66
0.93/0.87
V/ns
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 37
Table 28 shows AC parameters for SDRAM pbijtov18_33_ddr_clk I/O.
Output pad slew rate2 (standard drive) tps 25 pF
50 pF
0.38/0.41
0.20/0.22
0.59/0.60
0.31/0.32
0.89/0.82
0.47/0.43
V/ns
Output pad dI/dt3 (max. drive) tdit 25 pF
50 pF
89
94
198
209
398
421
mA/ns
Output pad dI/dt3 (high drive) tdit 25 pF
50 pF
59
62
132
139
265
279
mA/ns
Output pad dI/dt3 (standard drive) tdit 25 pF
50 pF
29
31
65
69
132
139
mA/ns
Input pad transition times4trfi 1.0 pF 0.07/0.08 0.11/0.12 0.16/0.20 ns
Input pad propagation delay, 50%–50%4tpi 1.0 pF 0.35/1.17 0.63/1.53 1.16/2.04 ns
Input pad propagation delay, 40%–60%4tpi 1.18/1.99 1.45/2.35 1.97/2.85
1Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 3.0 V, and 105 °C. Minimum condition for tpr, tpo, and tpv:
bcs model, 1.3 V, I/O 3.6 V and –40 °C. Input transition time from core is 1 ns (20%–80%).
2Minimum condition for tps: wcs model, 1.1 V, I/O 3.0 V, and 105 °C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
3Maximum condition for tdit: bcs model, 1.3 V, I/O 3.6 V, and –40 °C.
4Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 3.0 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V,
I/O 3.6 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).
Table 28. AC Parameters for SDRAM pbijtov18_33_ddr_clk I/O
Parameter Symbol Load
Condition
Min.
Rise/Fall Typ. Max.
Rise/Fall Units
Duty cycle Fduty 40 50 60 %
Clock frequency1f 133 MHz
Output pad transition times1 (max. drive) tpr 25 pF
50 pF
0.82/0.87
1.56/1.67
1.14/1.13
2.13/2.09
1.62/1.50
3.015/2.7
7
ns
Output pad transition times1 (high drive) tpr 25 pF
50 pF
1.23/1.31
2.31/2.47
1.71/1.68
3.22/3.12
2.39/2.22
4.53/4.16
ns
Output pad transition times1 (standard drive) tpr 25 pF
50 pF
2.44/2.60
4.65/4.99
3.38/3.27
6.38/6.23
4.73/4.38
9.05/8.23
ns
Output pad propagation delay1 (max. drive),
50%–50% input signals and crossing of output signals
tpo 15 pF
35 pF
1.50/1.40
1.95/1.85
2.23/2.07
2.81/2.66
3.28/3.04
4.06/3.82
ns
Output pad propagation delay1 (high drive),
50%–50% input signals and crossing of output signals
tpo 15 pF
35 pF
1.69/1.59
2.35/2.25
2.48/2.32
3.35/3.19
3.63/3.38
4.80/4.56
ns
Output pad propagation delay1 (standard drive),
50%–50% input signals and crossing of output signals
tpo 15 pF
35 pF
2.26/2.15
3.59/3.49
3.24/3.08
4.98/4.82
4.66/4.42
7.00/6.75
ns
Output pad propagation delay1 (max. drive),
40%–60% input signals and crossing of output signals
tpo 15 pF
35 pF
1.67/1.57
2.11/2.02
2.39/2.24
2.97/2.82
3.45/3.21
4.23/3.99
ns
Table 27. AC Parameters for SDRAM I/O (continued)
Parameter Symbol Load
Condition
Min.
Rise/Fall Typ. Max.
Rise/Fall Units
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
38 Freescale Semiconductor
Output pad propagation delay1 (high drive),
40%–60% input signals and crossing of output signals
tpo 15 pF
35 pF
1.85/1.75
2.52/2.42
2.65/2.49
3.51/3.36
3.79/3.55
4.97/4.72
ns
Output pad propagation delay1 (standard drive),
40%–60% input signals and crossing of output signals
tpo 15 pF
35 pF
2.42/2.32
3.76/3.66
3.40/3.25
5.15/4.99
4.83/4.59
7.17/6.92
ns
Output enable to output valid delay1 (max. drive),
50%–50%
tpv 15 pF
35 pF
1.37/1.34
1.77/1.83
2.22/2.02
2.77/2.63
3.53/3.12
4.30/3.92
ns
Output enable to output valid delay1 (high drive),
50%–50%
tpv 15 pF
35 pF
1.55/1.56
2.15/2.29
2.46/2.30
3.28/3.21
3.87/3.47
5.02/4.67
ns
Output enable to output valid delay1 (standard drive),
50%–50%
tpv 15 pF
35 pF
2.07/2.18
3.28/3.65
3.20/3.08
4.84/4.90
4.92/4.50
7.21/6.89
ns
Output enable to output valid delay1 (max. drive),
40%–60%
tpv 15 pF
35 pF
1.46/1.42
1.77/1.81
2.28/2.07
2.71/2.56
3.54/3.13
4.15/3.78
ns
Output enable to output valid delay1 (high drive),
40%–60%
tpv 15 pF
35 pF
1.60/1.59
2.07/2.18
2.47/2.30
3.12/3.02
3.82/3.41
4.72/4.37
ns
Output enable to output valid delay1 (standard drive),
40%–60%
tpv 15 pF
35 pF
2.01/2.09
2.96/3.26
3.05/2.91
4.34/4.37
4.64/4.23
6.45/6.13
ns
Output pad slew rate2 (max. drive) tps 25 pF
50 pF
1.11/1.20
0.60/0.65
1.74/1.75
0.93/0.95
2.63/2.48
1.39/1.29
V/ns
Output pad slew rate2 (high drive) tps 25 pF
50 pF
0.75/0.81
0.40/0.43
1.16/1.18
0.62/0.64
1.76/1.65
094/0.87
V/ns
Output pad slew rate2 (standard drive) tps 25 pF
50 pF
0.38/0.41
0.20/0.22
0.59/0.61
0.31/0.32
0.89/0.83
0.47/0.43
V/ns
Output pad dI/dt3 (max. drive) tdit 25 pF
50 pF
89
95
202
213
435
456
mA/ns
Output pad dI/dt3 (high drive) tdit 25 pF
50 pF
60
63
135
142
288
302
mA/ns
Output pad dI/dt3 (standard drive) tdit 25 pF
50 pF
29
31
67
70
144
150
mA/ns
Input pad transition times4trfi 1.0 pF 0.07/0.08 0.11/0.12 0.16/0.20 ns
Input pad propagation delay, 50%–50%4tpi 1.0 pF 0.56/0.69 0.87/1.08 1.37/1.62 ns
Input pad propagation delay, 40%–60%4tpi 1.38/1.51 1.68/1.89 2.18/2.42
1Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 3.0 V, and 105 °C. Minimum condition for tpr, tpo, and tpv:
bcs model, 1.3 V, I/O 3.6 V and –40 °C. Input transition time from core is 1 ns (20%–80%).
2Minimum condition for tps: wcs model, 1.1 V, I/O 3.0 V, and 105 °C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
3Maximum condition for tdit: bcs model, 1.3 V, I/O 3.6 V, and –40 °C.
4Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 3.0 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V,
I/O 3.6 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).
Table 28. AC Parameters for SDRAM pbijtov18_33_ddr_clk I/O (continued)
Parameter Symbol Load
Condition
Min.
Rise/Fall Typ. Max.
Rise/Fall Units
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 39
3.6.3.3 DDR_TYPE = 10 Max Setting I/O AC Parameters and Requirements
Table 29 shows AC parameters for DDR2 I/O.
Table 30 shows AC parameters for DDR2 pbijtov18_33_ddr_clk I/O.
Table 29. AC Parameters for DDR2 I/O
Parameter Symbol Load
Condition
Min.
Rise/Fall Typ. Max.
Rise/Fall Units
Duty cycle Fduty 40 50 60 %
Clock frequency f 133 MHz
Output pad transition times1
1Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1. V, and 105 °C. Minimum condition for tpr, tpo, and tpv: bcs
model, 1.3 V, I/O 1.9 V and –40 °C. Input transition time from core is 1 ns (20%–80%).
tpr 25 pF
50 pF
0.53/0.52
1.01/0.98
0.80/0.72
1.49/1.34
1.19/1.04
2.21/1.90
ns
Output pad propagation delay, 50%–50%1tpo 25 pF
50 pF
0.93/1.25
1.26/1.54
1.56/1.70
2.07/2.19
2.52/2.53
3.29/3.24
ns
Output pad propagation delay, 40%–60%1tpo 25 pF
50 pF
1.01/1.17
1.27/1.53
1.60/1.75
2.00/2.14
2.49/2.52
3.11/3.10
ns
Output enable to output valid delay, 50%–50%1tpv 25 pF
50 pF
1.30/1.19
1.62/1.54
2.17/1.81
2.56/2.29
3.35/2.84
3.35/2.54
ns
Output enable to output valid delay, 40%–60%1tpv 25 pF
50 pF
1.39/1.27
1.64/1.55
2.13/1.86
2.62/2.23
3.38/2.83
4.14/2.38
ns
Output pad slew rate2
2Minimum condition for tps: wcs model, 1.1 V, I/O 1.7 V, and 105 °C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
tps 25 pF
50 pF
0.86/0.98
0.46/054
1.35/1.5
0.72/0.81
2.15/2.19
1.12/1.16
V/ns
Output pad dI/dt3
3Maximum condition for tdit: bcs model, 1.3 V, I/O 1.9 V, and –40 °C.
tdit 25 pF
50 pF
65
70
157
167
373
396
mA/ns
Input pad transition times4
4Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.7 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V,
I/O 1.9 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).
trfi 1.0 pF 0.07/0.08 0.10/0.12 0.17/0.20 ns
Input pad propagation delay, 50%–50%4tpi 1.0 pF 0.83/0.99 1.23/1.49 1.79/2.04 ns
Input pad propagation delay, 40%–60%4tpi 1.0 pF 1.65/1.81 2.05/2.31 2.60/2.84 ns
Table 30. AC Parameters for DDR2 pbijtov18_33_ddr_clk I/O
Parameter Symbol Load
Condition
Min.
Rise/Fall Typ. Max.
Rise/Fall Units
Duty cycle Fduty 40 50 60 %
Clock frequency f 133 MHz
Output pad transition times1tpr 25 pF
50 pF
0.53/0.52
1.01/0.98
0.80/0.72
1.49/1.34
1.19/1.04
2.21/1.90
ns
Output pad propagation delay1, 50%–50% input
signals and crossing of output signals
tpo 25 pF
50 pF
1.3/1.21
1.59/1.5
1.97/1.84
2.37/2.24
2.91/2.71
3.48/3.28
ns
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
40 Freescale Semiconductor
Table 31 shows the AC requirements for DDR2 I/O.
Output pad propagation delay1, 40%–60% input
signals and crossing of output signals
tpo 25 pF
50 pF
1.47/1.38
1.75/1.67
2.13/2.00
2.54/2.40
3.072/2.87
3.65/3.45
ns
Output enable to output valid delay, 50%–50%1tpv 25 pF
50 pF
1.32/1.28
1.66/1.65
2.11/2.00
2.61/2.50
3.31/3.12
4.06/3.81
ns
Output enable to output valid delay, 40%–60%1tpv 25 pF
50 pF
1.40/1.37
1.67/1.66
2.16/2.06
2.56/2.45
3.30/3.13
3.89/3.67
ns
Output pad slew rate2tps 25 pF
50 pF
0.86/0.98
0.46/054
1.35/1.5
0.72/0.81
2.15/2.19
1.12/1.16
V/ns
Output pad dI/dt3tdit 25 pF
50 pF
72
77
172
183
400
422
mA/ns
Input pad transition times4trfi 1.0 pF 0.07/0.08 0.10/0.12 0.17/0.20 ns
Input pad propagation delay, 50%–50%4tpi 1.0 pF 0.89/0.87 1.41/1.37 2.16/2.07 ns
Input pad propagation delay, 40%–60%4tpi 1.0 pF 1.71/1.69 2.22/2.18 2.98/2.88 ns
1Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1. V, and 105 °C. Minimum condition for tpr, tpo, and tpv: bcs
model, 1.3 V, I/O 1.9 V and –40 °C. Input transition time from core is 1 ns (20%–80%).
2Minimum condition for tps: wcs model, 1.1 V, I/O 1.7 V, and 105 °C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
3Maximum condition for tdit: bcs model, 1.3 V, I/O 1.9 V, and –40 °C.
4Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.7 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V,
I/O 1.9 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).
Table 31. AC Requirements for DDR2 I/O
Parameter1
1The Jedec SSTL_18 specification (JESD8-15a) for an SSTL interface for class II operation supersedes any specification in
this document.
Symbol Min. Max. Units
AC input logic high VIH(ac) OVDD/2 + 0.25 OVDD + 0.3 V
AC input logic low VIL(ac) –0.3 OVDD/2 – 0.25 V
AC differential input voltage2
2Vid(ac) specifies the input differential voltage |Vtr–Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The minimum value is equal to Vih(ac)–Vil(ac)
Vid(ac) 0.5 OVDD + 0.6 V
AC differential cross point voltage for input3
3The typical value of Vix(ac) is expected to be about 0.5 × OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
Vix(ac) OVDD/2–0.175 OVDD/2 + 0.175 V
AC differential cross point voltage for output4
4The typical value of Vox(ac) is expected to be about 0.5 × OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac)
indicates the voltage at which differential output signal must cross. Cload = 25 pF.
Vox(ac) OVDD/2–0.125 OVDD/2 + 0.125 V
Table 30. AC Parameters for DDR2 pbijtov18_33_ddr_clk I/O (continued)
Parameter Symbol Load
Condition
Min.
Rise/Fall Typ. Max.
Rise/Fall Units
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 41
3.7 Module Timing and Electrical Parameters
This section contains the timing and electrical parameters for i.MX25 modules.
3.7.1 1-Wire Timing Parameters
Figure 7 shows the reset and presence pulses (RPP) timing for 1-Wire.
Figure 7. 1-Wire RPP Timing Diagram
Table 32 lists the RPP timing parameters.
Figure 8 shows write 0 sequence timing, and Table 33 describes the timing parameters (OW5–OW6) that
are shown in the figure.
Figure 8. Write 0 Sequence Timing Diagram
Table 32. RPP Sequence Delay Comparisons Timing Parameters
ID Parameters Symbol Min. Typ. Max. Units
OW1 Reset Time Low tRSTL 480 511 μs
OW2 Presence Detect High tPDH 15 — 60 μs
OW3 Presence Detect Low tPDL 60 — 240 μs
OW4 Reset Time High tRSTH 480 512 μs
Table 33. WR0 Sequence Timing Parameters
ID Parameter Symbol Min. Typ. Max. Units
OW5 Write 0 Low Time tWR0_low 60 100 120 μs
OW6 Transmission Time Slot tSLOT OW5 117 120 μs
OW5
OW6
1-Wire bus
(OWIRE_LINE)
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
42 Freescale Semiconductor
Figure 9 and Figure 10 show write 1 and read sequence timing, respectively. Table 34 describes the timing
parameters (OW7–OW8) that are shown in the figure.
Figure 9. Write 1 Sequence Timing Diagram
Figure 10. Read Sequence Timing Diagram
Table 34. WR1 /RD Timing Parameters
ID Parameter Symbol Min. Typ. Max. Units
OW7 Write 1 / read low time tLOW1 1515 μs
OW8 Transmission time slot tSLOT 60 117 120 μs
OW9 Release time tRELEASE 15 — 45 μs
OW7
OW8
1-Wire bus
(OWIRE_LINE)
OW7
OW8
OW9
1-Wire bus
(OWIRE_LINE)
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 43
3.7.2 ATA Timing Parameters
Table 35 shows parameters used to specify the ATA timing. These parameters depend on the
implementation of the ATA interface on silicon, the bus buffer used, the cable delay and cable skew.
Table 35. Timing Parameters
Name Description Value/Contributing Factor
T Bus clock period Peripheral clock frequency
ti_ds Set-up time ata_data to ata_iordy edge (UDMA-in only)
UDMA0
UDMA1
UDMA2,UDMA3
UDMA4
UDMA5
15 ns
10 ns
7ns
5ns
4ns
ti_dh Hold time ata_iordy edge to ata_data (UDMA-in only)
UDMA0,UDMA1,UDMA2,UDMA3,UDMA4
UDMA5
5.0 ns
4.6 ns
tco Propagation delay bus clock L-to-H to
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data, ata_buffer_en
12.0 ns
tsu Set-up time ata_data
to bus clock L-to-H 8.5 ns
tsui Set-up time ata_iordy to bus clock H-to-L 8.5 ns
thi Hold time ata_iordy
to bus clock H-to-L 2.5 ns
tskew1 Maximum difference in propagation delay bus clock L-to-H to any of the
following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow,
ata_dmack, ata_data (write), ata_buffer_en
7ns
tskew2 Maximum difference in buffer propagation delay for any of the following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow,
ata_dmack, ata_data (write), ata_buffer_en
Transceiver
tskew3 Maximum difference in buffer propagation delay for any of the following signals
ata_iordy, ata_data (read)
Transceiver
tbuf Maximum buffer propagation delay Transceiver
tcable1 cable propagation delay for ata_data Cable
tcable2 cable propagation delay for control signals ata_dior, ata_diow, ata_iordy,
ata_dmack
Cable
tskew4 Maximum difference in cable propagation delay between ata_iordy and
ata_data (read)
Cable
tskew5 Maximum difference in cable propagation delay between (ata_dior, ata_diow,
ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0,
ata_data(write)
Cable
tskew6 Maximum difference in cable propagation delay without accounting for ground
bounce
Cable
|§ m #1
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
44 Freescale Semiconductor
3.7.2.1 PIO Mode Timing Parameters
Figure 11 shows a timing diagram for PIO read mode.
Figure 11. PIO Read Mode Timing
To meet PIO read mode timing requirements, a number of timing parameters must be controlled. Table 36
shows timing parameters and their determining relations, and indicates parameters that can be adjusted to
meet required conditions.
Table 36. Timing Parameters for PIO Read Mode
ATA
Parameter
PIO Read
Mode Timing
Parameter1
1See Figure 11.
Relation Adjustable Parameter
t1 t1 t1(min.) = time_1 × T – (tskew1 + tskew2 + tskew5) time_1
t2 t2r t2(min.) = time_2r × T – (tskew1 + tskew2 + tskew5) time_2r
t9 t9 t9(min.) = time_9 × T – (tskew1 + tskew2 + tskew6) time_9
t5 t5 t5(min.) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 If not met, increase time_2
t6 t6 0
tA tA tA(min.) = (1.5 + time_ax) × T – (tco + tsui + tcable2 + tcable2 + 2 × tbuf) time_ax
trd trd1 trd1(max.) = (–trd) + (tskew3 + tskew4)
trd1(min.) = (time_pio_rdx – 0.5) × T – (tsu + thi)
(time_pio_rdx – 0.5) × T > tsu + thi + tskew3 + tskew4
time_pio_rdx
t0 t0(min.) = (time_1 + time_2 + time_9) × T time_1, time_2r, time_9
ADDR
(See note 1)
DIOR
READ Data(15:0)
IORDY
IORDY
t1 t2r t9
tA
t5
t6
trd1
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor 45
Figure 12 gives timing waveforms for PIO write mode.
Figure 12. PIO Write Mode Timing
To meet PIO write mode timing requirements, a number of timing parameters must be controlled. Table 37
shows timing parameters and their determining relations, and indicates parameters that can be adjusted to
meet required conditions.
Table 37. Timing Parameters for PIO Write Mode
ATA
Parameter
PIO Write
Mode Timing
Parameter1
1See Figure 12.
Relation Adjustable Parameter(s)
t1 t1 t1(min.) = time_1 × T – (tskew1 + tskew2 + tskew5) time_1
t2 t2w t2(min.) = time_2w × T – (tskew1 + tskew2 + tskew5) time_2w
t9 t9 t9(min.) = time_9 × T – (tskew1 + tskew2 + tskew6) time_9
t3 t3(min.) = (time_2w – time_on) × T – (tskew1 + tskew2 +tskew5) if not met, increase time_2w
t4 t4 t4(min.) = time_4 × T tskew1 time_4
tA tA tA = (1.5 + time_ax) × T – (tco + tsui + tcable2 + tcable2 + 2 × tbuf) time_ax
t0 t0(min.) = (time_1 + time_2 + time_9) × T time_1, time_2r, time_9
Avoid bus contention when switching buffer on by making ton long
enough
Avoid bus contention when switching buffer off by making toff long
enough
ADDR
(See note 1)
DIOW
Write Data(15:0)
IORDY
IORDY
t1 t2w t9
tA
buffer_en
ton
t4 tofftB
DIOR
t1
mar é 1 fi [3 H IHH 31 % fl
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
46 Freescale Semiconductor
3.7.2.2 Multiword DMA (MDMA) Mode Timing
Figure 13 and Figure 14 show the timing for MDMA read and write modes, respectively.
Figure 13. MDMA Read Mode Timing
Figure 14. MDMA Write Mode Timing
ADDR
(See note 1)
DIOR
READ Data(15:0)
DMARQ
DMACK
tm td tk tkjn
tgr tfr
tk1
te
ADDR
(See note 1)
DIOW
Write Data(15:0)
DMARQ
DMACK
tkjn
tk1
buffer_en
tm ton td1 tk td toff
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To meet timing requirements, a number of timing parameters must be controlled. See Table 38 for details
on timing parameters for MDMA read and write modes.
3.7.2.3 Ultra DMA (UDMA) Mode Timing
UDMA mode timing is more complicated than PIO mode or MDMA mode. In this section, timing
diagrams for UDMA in- and out-transfers are provided.
Table 38. Timing Parameters for MDMA Read and Write Modes
ATA
Parameter
MDMA Read1
and Write2
Timing
Parameters
1See Figure 13.
2See Figure 14.
Relation Adjustable
Parameter(s)
tm, ti tm tm(min.) = ti(min.) = time_m × T – (tskew1 + tskew2 + tskew5) time_m
td td, td1 td1(min.) = td(min.) = time_d × T – (tskew1 + tskew2 + tskew6) time_d
tk tk tk(min.) = time_k × T – (tskew1 + tskew2 + tskew6) time_k
t0 t0(min.) = (time_d + time_k) × T time_d, time_k
tg(read) tgr tgr(min.–read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2
tgr(min.–drive) = td – te(drive)
time_d
tf(read) tfr tfr(min.–drive) =0 k
tg(write) tg(min.–write) = time_d × T –(tskew1 + tskew2 + tskew5) time_d
tf(write) tf(min.–write) = time_k × T – (tskew1 + tskew2 + tskew6) time_k
tL tL(max.) = (time_d + time_k–2) × T – (tsu + tco + 2 × tbuf + 2 × tcable2) time_d, time_k3
3tk1 in the UDMA figures equals (tk –2 × T).
tn, tj tkjn tn= tj= tkjn = (max.(time_k,. time_jn) × T – (tskew1 + tskew2 + tskew6) time_jn
—ton
toff
ton = time_on × Ttskew1
toff = time_off × T tskew1
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48 Freescale Semiconductor
3.7.2.3.1 UDMA In-Transfer Timing
Figure 15 shows the timing for UDMA in-transfer start.
Figure 15. Timing for UDMA In-Transfer Start
Figure 16 shows the timing for host-terminated UDMA in-transfer.
Figure 16. Timing for Host-Terminated UDMA In-Transfer
DMARQ
ADDR
DIOR
DIOW
IORDY
DATA READ
DMACK
tack
tenv
tds tdh
tc1 tc1
DMARQ
ADDR
DIOR
DIOW
IORDY
DATA READ
DMACK
tds tdh
tc1 tc1
DATA WRITE
buffer_en
tack
trp
tx1
tzah
tzah ton tdzfs tcvh toff
tmli
tmli
X:X>CX a
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Freescale Semiconductor 49
Figure 17 shows timing for device-terminated UDMA in-transfer.
Figure 17. Timing for Device-Terminated UDMA Transfer
Timing parameters for UDMA in-burst are listed in Table 39.
Table 39. Timing Parameters for UDMA In-Burst
ATA
Parameter
Spec.
Parameter Value Required Conditions
tack tack tack(min.) = (time_ack × T) – (tskew1 + tskew2) time_ack
tenv tenv tenv(min.) = (time_env × T) – (tskew1 + tskew2)
tenv(max.) = (time_env × T) + (tskew1 + tskew2)
time_env
tds tds1 tds – (tskew3) – ti_ds > 0 tskew3, ti_ds, ti_dh
should be low enough
tdh tdh1 tdh – (tskew3) –ti_dh > 0
tcyc tc1 (tcyc – tskew) > T T big enough
trp trp trp(min.) = time_rp × T – (tskew1 + tskew2 + tskew6) time_rp
—tx1
1
1There is a special timing requirement in the ATA host that requires the internal DIOW to go only high three clocks after the last
active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.
Make ton and toff big enough to avoid bus contention.
(time_rp × T) – (tco + tsu + 3T + 2 × tbuf + 2 × tcable2) > trfs (drive) time_rp
tmli tmli1 tmli1(min.) = (time_mlix + 0.4) × T time_mlix
tzah tzah tzah(min.) = (time_zah + 0.4) × T time_zah
tdzfs tdzfs tdzfs = (time_dzfs × T) – (tskew1 + tskew2) time_dzfs
tcvh tcvh tcvh = (time_cvh × T) – (tskew1 + tskew2) time_cvh
—ton
toff
ton = time_on × T – tskew1
toff = time_off × T – tskew1
DMARQ
ADDR
DIOR
DIOW
IORDY
DATA READ
DMACK
tds tdh
tc1 tc1
DATA WRITE
buffer_en
tack
tss1
tzah ton tdzfs tcvh toff
tzah
tmli
tmli
tli5
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3.7.2.4 UDMA Out-Transfer Timing
Figure 18 shows the timing for start of UDMA out-transfer.
Figure 18. Timing for UDMA Out-Transfer Start
Figure 19 shows timing for host-terminated UDMA out-transfer.
Figure 19. Timing for Host-Terminated UDMA Out-Transfer
DMARQ
ADDR
DIOW
DIOR
IORDY
DATA WRITE
DMACK
tack
tenv
buffer_en
ton tdzfs tdvs tdvh tdvs
tcyc tcyc
trfs1
tli1
DMARQ
ADDR
DIOW
DIOR
DMACK
DATA WRITE
buffer_en
tack
tcvh toff
tss
tcyc
IORDY
tli2
tli3
tdzfs_mlitcyc1
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Timing parameters for UDMA out-bursts are listed in Table 40.
3.7.3 Digital Audio Mux (AUDMUX) Timing
The AUDMUX provides a programmable interconnect logic for voice, audio, and data routing between
internal serial interfaces (SSI and SAP) and external serial interfaces (audio and voice codecs). The AC
timing of AUDMUX external pins is governed by the SSI modules. For more information, see
Section 3.7.17, “Synchronous Serial Interface (SSI) Timing.”
3.7.4 CMOS Sensor Interface (CSI) Timing
The CSI enables the chip to connect directly to external CMOS image sensors, which are classified as
dumb or smart as follows:
Dumb sensors only support traditional sensor timing (vertical sync (VSYNC) and horizontal sync
(HSYNC)) and output-only Bayer and statistics data.
Smart sensors support CCIR656 video decoder formats and perform additional processing of the
image (for example, image compression, image pre-filtering, and various data output formats).
The following subsections describe the CSI timing in gated and ungated clock modes.
Table 40. Timing Parameters UDMA Out-Bursts
ATA
Parameter
Spec
Parameter Value How to Meet?
tack tack tack(min.) = (time_ack × T) – (tskew1 + tskew2) time_ack
tenv tenv tenv(min.) = (time_env × T) – (tskew1 + tskew2)
tenv(max.) = (time_env × T) + (tskew1 + tskew2)
time_env
tdvs tdvs tdvs = (time_dvs × T) – (tskew1 + tskew2) time_dvs
tdvh tdvh tdvs = (time_dvh × T) – (tskew1 + tskew2) time_dvh
tcyc tcyc tcyc = time_cyc × T – (tskew1 + tskew2) time_cyc
t2cyc t2cyc = time_cyc × 2 × T time_cyc
trfs1 trfs trfs = 1.6 × T + tsui + tco + tbuf + tbuf
tdzfs tdzfs = time_dzfs × T – (tskew1) time_dzfs
tss tss tss = time_ss × T – (tskew1 + tskew2) time_ss
tmli tdzfs_mli tdzfs_mli =max.(time_dzfs, time_mli) × T – (tskew1 + tskew2)
tli tli1 tli1 > 0
tli tli2 tli2 > 0
tli tli3 tli3 > 0
tcvh tcvh tcvh = (time_cvh × T) – (tskew1 + tskew2) time_cvh
—ton
toff
ton = time_on × T – tskew1
toff = time_off × T – tskew1
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3.7.4.1 Gated Clock Mode Timing
Figure 20 and Figure 21 shows the gated clock mode timings for CSI, and Table 41 describes the timing
parameters (P1–P7) shown in the figures. A frame starts with a rising/falling edge on VSYNC, then
HSYNC is asserted and holds for the entire line. The pixel clock is valid as long as HSYNC is asserted.
Figure 20. CSI Gated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge
Figure 21. CSI Gated Clock Mode—Sensor Data at Rising Edge, Latch Data at Falling Edge
PIXCLK
VSYNC
DATA[15:0]
P5
P1
P3 P4
HSYNC
P2 P6
P7
PIXCLK
VSYNC
DATA[15:0]
P6
P1
P3 P4
HSYNC
P2 P5
P7
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3.7.4.2 Ungated Clock Mode Timing
Figure 22 shows the ungated clock mode timings of CSI, and Table 42 describes the timing parameters
(P1–P6) that are shown in the figure. In ungated mode the VSYNC and PIXCLK signals are used, and the
HSYNC signal is ignored.
Figure 22. CSI Ungated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge
Table 41. CSI Gated Clock Mode Timing Parameters
ID Parameter Symbol Min. Max. Units
P1 CSI VSYNC to HSYNC time tV2H 67.5 ns
P2 CSI HSYNC setup time tHsu 1 ns
P3 CSI DATA setup time tDsu 1 ns
P4 CSI DATA hold time tDh 1.2 ns
P5 CSI pixel clock high time tCLKh 10 ns
P6 CSI pixel clock low time tCLKl 10 ns
P7 CSI pixel clock frequency fCLK 48 ± 10% MHz
Table 42. CSI Ungated Clock Mode Timing Parameters
ID Parameter Symbol Min. Max. Units
P1 CSI VSYNC to pixel clock time tVSYNC 67.5 ns