MCP8641(D) Datasheet by NXP USA Inc.

freescale“

Freescale Semiconductor

Technical Data

Freescale reserves the right to change the detail specifications as may be required

to permit improvements in the design of its products.

1 Overview

The MPC8641 processor family integrates either one or two

Power Architecture® e600 processor cores with system

logic required for networking, storage, wireless

infrastructure, and general-purpose embedded applications.

The MPC8641 integrates one e600 core while the

MPC8641D integrates two cores.

This section provides a high-level overview of the MPC8641

and MPC8641D features. When referring to the MPC8641

throughout the document, the functionality described applies

to both the MPC8641 and the MPC8641D. Any differences

specific to the MPC8641D are noted.

Figure 1 shows the major functional units within the

MPC8641 and MPC8641D. The major difference between

the MPC8641 and MPC8641D is that there are two cores on

the MPC8641D.

Contents

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6

3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14

4. Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 20

6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 21

7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8. Ethernet: Enhanced Three-Speed Ethernet (eTSEC),

MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

9. Ethernet Management Interface Electrical

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

11. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

13. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 59

14. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

15. Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

16. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

17. Signal Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

18. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

19. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

20. System Design Information . . . . . . . . . . . . . . . . . . 116

21. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 126

22. Document Revision History . . . . . . . . . . . . . . . . . . 128

MPC8641 and MPC8641D

Integrated Host Processor

Hardware Specifications

Document Number: MPC8641D

Rev. 3, 05/2014

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

2Freescale Semiconductor

Overview

Figure 1. MPC8641 and MPC8641D

AND 1x/4x SRIO (2.5 GB/s) ]

[ x1/x2/x4/x8 PCI Exp (4 GB/s)

OR [2-x1/x2/x4/x8 PCI Express

(8 GB/S) ]

32-Kbyte

L1 Instruction Cache

e600 Core

32-Kbyte

L1 Data Cache

e600 Core Block

Local Bus Controller

Multiprocessor

Programmable Interrupt

DDR SDRAM Controller

SDRAM

IRQs

External

Control

DDR SDRAM Controller

(LBC)

Controller

(MPIC)

SDRAM

ROM,

GPIO

Dual Universal

Asynchronous

Receiver/Transmitter

(DUART)

Serial

I2C ControllerI2C

Enhanced TSEC

Controller

10/100/1Gb

Enhanced TSEC

Controller

10/100/1Gb

Enhanced TSEC

Controller

10/100/1Gb

PCI Express

Interface

Four-Channel

DMA Controller

Enhanced TSEC

Controller

10/100/1Gb

OCeaN

Switch

Fabric

MPX Coherency Module (MCM)

1-Mbyte

L2 Cache

Platform

MPX Bus

RMII, GMII,

MII, RGMII,

TBI, RTBI

RMII, GMII,

MII, RGMII,

TBI, RTBI

RMII, GMII,

MII, RGMII,

TBI, RTBI

RMII, GMII,

MII, RGMII,

TBI, RTBI

Platform Bus

e600 Core

e600 Core Block

L2 Cache

32-Kbyte

L1 Instruction Cache

32-Kbyte

L1 Data Cache

1-Mbyte

Serial RapidIO

Interface

PCI Express

Interface

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 3

Overview

1.1 Key Features

The following lists an overview of the MPC8641 key feature set:

• Major features of the e600 core are as follows:

— High-performance, 32-bit superscalar microprocessor that implements the PowerPC ISA

— Eleven independent execution units and three register files

– Branch processing unit (BPU)

– Four integer units (IUs) that share 32 GPRs for integer operands

– 64-bit floating-point unit (FPU)

– Four vector units and a 32-entry vector register file (VRs)

– Three-stage load/store unit (LSU)

— Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions,

respectively, in a cycle.

— Rename buffers

— Dispatch unit

— Completion unit

— Two separate 32-Kbyte instruction and data level 1 (L1) caches

— Integrated 1-Mbyte, eight-way set-associative unified instruction and data level 2 (L2) cache

with ECC

— 36-bit real addressing

— Separate memory management units (MMUs) for instructions and data

— Multiprocessing support features

— Power and thermal management

— Performance monitor

— In-system testability and debugging features

— Reliability and serviceability

• MPX coherency module (MCM)

— Ten local address windows plus two default windows

— Optional low memory offset mode for core 1 to allow for address disambiguation

• Address translation and mapping units (ATMUs)

— Eight local access windows define mapping within local 36-bit address space

— Inbound and outbound ATMUs map to larger external address spaces

— Three inbound windows plus a configuration window on PCI Express

— Four inbound windows plus a default window on serial RapidIO

— Four outbound windows plus default translation for PCI Express

— Eight outbound windows plus default translation for serial RapidIO with segmentation and

sub-segmentation support

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

4Freescale Semiconductor

Overview

• DDR memory controllers

— Dual 64-bit memory controllers (72-bit with ECC)

— Support of up to a 300-MHz clock rate and a 600-MHz DDR2 SDRAM

— Support for DDR, DDR2 SDRAM

— Up to 16 Gbytes per memory controller

— Cache line and page interleaving between memory controllers.

• Serial RapidIO interface unit

— Supports RapidIO Interconnect Specification, Revision 1.2

— Both 1x and 4x LP-Serial link interfaces

— Transmission rates of 1.25-, 2.5-, and 3.125-Gbaud (data rates of 1.0-, 2.0-, and 2.5-Gbps) per

lane

— RapidIO–compliant message unit

— RapidIO atomic transactions to the memory controller

• PCI Express interface

— PCI Express 1.0a compatible

— Supports x1, x2, x4, and x8 link widths

— 2.5 Gbaud, 2.0 Gbps lane

• Four enhanced three-speed Ethernet controllers (eTSECs)

— Three-speed support (10/100/1000 Mbps)

— Four IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab-compatible controllers

— Support of the following physical interfaces: MII, RMII, GMII, RGMII, TBI, and RTBI

— Support a full-duplex FIFO mode for high-efficiency ASIC connectivity

—TCP/IP off-load

— Header parsing

— Quality of service support

— VLAN insertion and deletion

— MAC address recognition

— Buffer descriptors are backward compatible with PowerQUICC II and PowerQUICC III

programming models

— RMON statistics support

— MII management interface for control and status

• Programmable interrupt controller (PIC)

— Programming model is compliant with the OpenPIC architecture

— Supports 16 programmable interrupt and processor task priority levels

— Supports 12 discrete external interrupts and 48 internal interrupts

— Eight global high resolution timers/counters that can generate interrupts

— Allows processors to interrupt each other with 32b messages

RTS m

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 5

Overview

— Support for PCI-Express message-shared interrupts (MSIs)

• Local bus controller (LBC)

— Multiplexed 32-bit address and data operating at up to 133 MHz

— Eight chip selects support eight external slaves

• Integrated DMA controller

— Four-channel controller

— All channels accessible by both the local and the remote masters

— Supports transfers to or from any local memory or I/O port

— Ability to start and flow control each DMA channel from external 3-pin interface

• Device performance monitor

— Supports eight 32-bit counters that count the occurrence of selected events

— Ability to count up to 512 counter-specific events

— Supports 64 reference events that can be counted on any of the 8 counters

— Supports duration and quantity threshold counting

— Burstiness feature that permits counting of burst events with a programmable time between

bursts

— Triggering and chaining capability

— Ability to generate an interrupt on overflow

• Dual I2C controllers

— Two-wire interface

— Multiple master support

— Master or slave I2C mode support

— On-chip digital filtering rejects spikes on the bus

• Boot sequencer

— Optionally loads configuration data from serial ROM at reset via the I2C interface

— Can be used to initialize configuration registers and/or memory

— Supports extended I2C addressing mode

— Data integrity checked with preamble signature and CRC

• DUART

— Two 4-wire interfaces (SIN, SOUT, RTS, CTS)

— Programming model compatible with the original 16450 UART and the PC16550D

• IEEE 1149.1-compatible, JTAG boundary scan

• Available as 1023 pin Hi-CTE flip chip ceramic ball grid array (FC-CBGA)

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

6Freescale Semiconductor

Electrical Characteristics

2 Electrical Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the

MPC8641. The MPC8641 is currently targeted to these specifications.

2.1 Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

2.1.1 Absolute Maximum Ratings

Table 1 provides the absolute maximum ratings.

Table 1. Absolute Maximum Ratings1

Characteristic Symbol Absolute Maximum

Value Unit Notes

Cores supply voltages VDD_Core0,

VDD_Core1

–0.3 to 1.21 V V 2

Cores PLL supply AVDD_Core0,

AVDD_Core1

–0.3 to 1.21 V V —

SerDes Transceiver Supply (Ports 1 and 2) SVDD –0.3 to 1.21 V V —

SerDes Serial I/O Supply Port 1 XVDD_SRDS1 –0.3 to 1.21V V —

SerDes Serial I/O Supply Port 2 XVDD_SRDS2 –0.3 to 1.21 V V —

SerDes DLL and PLL supply voltage for Port 1 and Port 2 AVDD_SRDS1,

AVDD_SRDS2

–0.3 to 1.21V V —

Platform Supply voltage VDD_PLAT –0.3 to 1.21V V —

Local Bus and Platform PLL supply voltage AVDD_LB,

AVDD_PLAT

–0.3 to 1.21V V —

DDR and DDR2 SDRAM I/O supply voltages D1_GVDD,

D2_GVDD

–0.3 to 2.75 V V 3

–0.3 to 1.98 V V 3

eTSEC 1 and 2 I/O supply voltage LVDD –0.3 to 3.63 V V 4

–0.3 to 2.75 V V 4

eTSEC 3 and 4 I/O supply voltage TVDD –0.3 to 3.63 V V 4

–0.3 to 2.75 V V 4

Local Bus, DUART, DMA, Multiprocessor Interrupts, System

Control & Clocking, Debug, Test, Power management, I2C, JTAG

and Miscellaneous I/O voltage

OVDD –0.3 to 3.63 V V —

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 7

Electrical Characteristics

2.1.2 Recommended Operating Conditions

Table 2 provides the recommended operating conditions for the MPC8641. Note that the values in Table 2

are the recommended and tested operating conditions. Proper device operation outside of these conditions

is not guaranteed. For details on order information and specific operating conditions for parts, see

Section 21, “Ordering Information.”

Input voltage DDR and DDR2 SDRAM signals Dn_MVIN – 0.3 to (Dn_GVDD +

0.3)

DDR and DDR2 SDRAM reference Dn_MVREF – 0.3 to (Dn_GVDD/2 +

0.3)

V—

Three-speed Ethernet signals LVIN

TVIN

GND to (LVDD+ 0.3)

GND to (TVDD+ 0.3)

V 5

DUART, Local Bus, DMA,

Multiprocessor Interrupts, System

Control & Clocking, Debug, Test,

Power management, I2C, JTAG and

Miscellaneous I/O voltage

OVIN GND to (OVDD+ 0.3) V 5

Storage temperature range TSTG –55 to 150 °C —

Notes:

1. Functional and tested operating conditions are given in Ta b le 2 . Absolute maximum ratings are stress ratings only, and

functional operation at the maxima is not guaranteed. Stresses beyond those listed may affect device reliability or cause

permanent damage to the device.

2. Core 1 characteristics apply only to MPC8641D. If two separate power supplies are used for VDD_Core0 and VDD_Core1,

they must be kept within 100 mV of each other during normal run time.

3. The –0.3 to 2.75 V range is for DDR and –0.3 to 1.98 V range is for DDR2.

4. The 3.63V maximum is only supported when the port is configured in GMII, MII, RMII, or TBI modes; otherwise the 2.75V

maximum applies. See Section 8.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications,” for details on

the recommended operating conditions per protocol.

5. During run time (M,L,T,O)VIN and Dn_MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown

in Figure 2.

Table 2. Recommended Operating Conditions

Characteristic Symbol Recommended

Value Unit Notes

Cores supply voltages VDD_Core0,

VDD_Core1

1.10 ± 50 mV V 1, 2, 8

1.05 ± 50 mV 1, 2, 7

0.95 ± 50 mV 1, 2, 12

Cores PLL supply AVDD_Core0,

AVDD_Core1

1.10 ± 50 mV V 8, 13

1.05 ± 50 mV 7, 13

0.95 ± 50 mV 12, 13

SerDes Transceiver Supply (Ports 1 and 2) SVDD 1.10 ± 50 mV V 8, 11

1.05 ± 50 mV 7, 11

Table 1. Absolute Maximum Ratings1 (continued)

Characteristic Symbol Absolute Maximum

Value Unit Notes

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

8Freescale Semiconductor

Electrical Characteristics

SerDes Serial I/O Supply Port 1 XVDD_SRDS1 1.10 ± 50 mV V 8

1.05 ± 50 mV 7

SerDes Serial I/O Supply Port 2 XVDD_SRDS2 1.10 ± 50 mV V 8

1.05 ± 50 mV 7

SerDes DLL and PLL supply voltage for Port 1 and Port 2 AVDD_SRDS1,

AVDD_SRDS2

1.10 ± 50 mV V 8

1.05 ± 50 mV 7

Platform Supply voltage VDD_PLAT 1.10 ± 50 mV V 8

1.05 ± 50 mV 7

Local Bus and Platform PLL supply voltage AVDD_LB,

AVDD_PLAT

1.10 ± 50 mV V 8

1.05 ± 50 mV 7

DDR and DDR2 SDRAM I/O supply voltages D1_GVDD,

D2_GVDD

2.5 V ± 125 mV V 9

1.8 V ± 90 mV V 9

eTSEC 1 and 2 I/O supply voltage LVDD 3.3 V ± 165 mV V 10

2.5 V ± 125 mV V 10

eTSEC 3 and 4 I/O supply voltage TVDD 3.3 V ± 165 mV V 10

2.5 V ± 125 mV V 10

Local Bus, DUART, DMA, Multiprocessor Interrupts, System

Control & Clocking, Debug, Test, Power management, I2C,

JTAG and Miscellaneous I/O voltage

OVDD 3.3 V ± 165 mV V 5

Input voltage DDR and DDR2 SDRAM signals Dn_MVIN GND to Dn_GVDD V3, 6

DDR and DDR2 SDRAM reference Dn_MVREF Dn_GVDD/2 ± 1% V

Three-speed Ethernet signals LVIN

TVIN

GND to LVDD

GND to TVDD

V4, 6

DUART, Local Bus, DMA,

Multiprocessor Interrupts, System

Control & Clocking, Debug, Test,

Power management, I2C, JTAG

and Miscellaneous I/O voltage

OVIN GND to OVDD V5,6

Table 2. Recommended Operating Conditions (continued)

Characteristic Symbol Recommended

Value Unit Notes

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 9

Electrical Characteristics

Junction temperature range TJ0 to 105 °C —

Notes:

1. Core 1 characteristics apply only to MPC8641D

2. If two separate power supplies are used for VDD_Core0 and VDD_Core1, they must be at the same nominal voltage and the

individual power supplies must be tracked and kept within 100 mV of each other during normal run time.

3. Caution: Dn_MVIN must meet the overshoot/undershoot requirements for Dn_GVDD as shown in Figure 2.

4. Caution: L/TVIN must meet the overshoot/undershoot requirements for L/TVDD as shown in Figure 2 during regular run time.

5. Caution: OVIN must meet the overshoot/undershoot requirements for OVDD as shown in Figure 2 during regular run time.

6. Timing limitations for M,L,T,O)VIN and Dn_MVREF during regular run time is provided in Figure 2

7. Applies to devices marked with a core frequency of 1333 MHz and below. Refer to Ta b l e 7 4 Part Numbering Nomenclature

to determine if the device has been marked for a core frequency of 1333 MHz and below.

8. Applies to devices marked with a core frequency above 1333 MHz. Refer to Ta bl e 7 4 Part Numbering Nomenclature to

determine if the device has been marked for a core frequency above 1333 MHz.

9. The 2.5 V ± 125 mV range is for DDR and 1.8 V ± 90 mV range is for DDR2.

10. See Section 8.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications,” for details on the recommended

operating conditions per protocol.

11. The PCI Express interface of the device is expected to receive signals from 0.175 to 1.2 V. For more information refer to

Section 14.4.3, “Differential Receiver (RX) Input Specifications.”

12. Applies to Part Number MC8641xxx1000NX only. VDD_Coren = 0.95 V and VDD_PLAT = 1.05 V devices. Refer to Ta bl e 7 4

Part Numbering Nomenclature to determine if the device has been marked for VDD_Coren = 0.95 V.

13. This voltage is the input to the filter discussed in Section 20.2, “Power Supply Design and Sequencing,” and not necessarily

the voltage at the AVDD_Coren pin, which may be reduced from VDD_Coren by the filter.

Table 2. Recommended Operating Conditions (continued)

Characteristic Symbol Recommended

Value Unit Notes

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

10 Freescale Semiconductor

Electrical Characteristics

Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8641.

Figure 2. Overshoot/Undershoot Voltage for Dn_M/O/L/TVIN

The MPC8641 core voltage must always be provided at nominal VDD_Coren (See Table 2 for actual

recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of

supply pins and must be provided at the voltages shown in Table 2. The input voltage threshold scales with

respect to the associated I/O supply voltage. OVDD and L/TVDD based receivers are simple CMOS I/O

circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a

single-ended differential receiver referenced to each externally supplied Dn_MVREF signal (nominally set

to Dn_GVDD/2) as is appropriate for the (SSTL-18 and SSTL-25) electrical signaling standards.

GND

GND – 0.3 V

GND – 0.7 V Not to Exceed 10%

L/T/Dn_G/O/X/SVDD + 20%

L/T/Dn_G/O/X/SVDD

L/T/Dn_G/O/X/SVDD + 5%

of tCLK1

1. tCLK references clocks for various functional blocks as follows:

VIH

VIL

Note:

DDRn = 10% of Dn_MCK period

eTSECn = 10% of ECn_GTX_CLK125 period

Local Bus = 10% of LCLK[0:2] period

I2C = 10% of SYSCLK

JTAG = 10% of SYSCLK

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 11

Electrical Characteristics

2.1.3 Output Driver Characteristics

Table 3 provides information on the characteristics of the output driver strengths. The values are

preliminary estimates.

2.2 Power Up/Down Sequence

The MPC8641 requires its power rails to be applied in a specific sequence in order to ensure proper device

operation.

NOTE

The recommended maximum ramp up time for power supplies is 20

milliseconds.

The chronological order of power up is as follows:

1. All power rails other than DDR I/O (Dn_GVDD, and Dn_MVREF).

Table 3. Output Drive Capability

Driver Type

Programmable

Output Impedance

(Ω)

Supply

Voltage Notes

DDR1 signal 18

36 (half strength mode)

Dn_GVDD = 2.5 V 4, 9

DDR2 signal 18

36 (half strength mode)

Dn_GVDD = 1.8 V 1, 5, 9

Local Bus signals 45

OVDD = 3.3 V 2, 6

eTSEC/10/100 signals 45 T/LVDD = 3.3 V 6

30 T/LVDD = 2.5 V 6

DUART, DMA, Multiprocessor Interrupts, System

Control & Clocking, Debug, Test, Power management,

JTAG and Miscellaneous I/O voltage

45 OVDD = 3.3 V 6

I2C150OV

DD = 3.3 V 7

SRIO, PCI Express 100 SVDD = 1.1/1.05 V 3, 8

Notes:

1. See the DDR Control Driver registers in the MPC8641D reference manual for more information.

2. Only the following local bus signals have programmable drive strengths: LALE, LAD[0:31], LDP[0:3], LA[27:31], LCKE,

LCS[1:2], LWE[0:3], LGPL1, LGPL2, LGPL3, LGPL4, LGPL5, LCLK[0:2]. The other local bus signals have a fixed drive

strength of 45 Ω. See the POR Impedance Control register in the MPC8641D reference manual for more information about

local bus signals and their drive strength programmability.

3. See Section 17, “Signal Listings,” for details on resistor requirements for the calibration of SDn_IMP_CAL_TX and

SDn_IMP_CAL_RX transmit and receive signals.

4. Stub Series Terminated Logic (SSTL-25) type pins.

5. Stub Series Terminated Logic (SSTL-18) type pins.

6. Low Voltage Transistor-Transistor Logic (LVTTL) type pins.

7. Open Drain type pins.

8. Low Voltage Differential Signaling (LVDS) type pins.

9. The drive strength of the DDR interface in half strength mode is at Tj = 105C and at Dn_GVDD (min).

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

12 Freescale Semiconductor

Electrical Characteristics

NOTE

There is no required order sequence between the individual rails for this

item (# 1). However, VDD_PLAT, AVDD_PLAT rails must reach 90% of

their recommended value before the rail for Dn_GVDD, and Dn_MVREF (in

next step) reaches 10% of their recommended value. AVDD type supplies

must be delayed with respect to their source supplies by the RC time

constant of the PLL filter circuit described in Section 20.2.1, “PLL Power

Supply Filtering.”

2. Dn_GVDD, Dn_MVREF

NOTE

It is possible to leave the related power supply (Dn_GVDD, Dn_MVREF)

turned off at reset for a DDR port that will not be used. Note that these power

supplies can only be powered up again at reset for functionality to occur on

the DDR port.

3. SYSCLK

The recommended order of power down is as follows:

1. Dn_GVDD, Dn_MVREF

2. All power rails other than DDR I/O (Dn_GVDD, Dn_MVREF).

NOTE

SYSCLK may be powered down simultaneous to either of item # 1 or # 2 in

the power down sequence. Beyond this, the power supplies may power

down simultaneously if the preservation of DDRn memory is not a concern.

See Figure 3 for more details on the Power and Reset Sequencing details.

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 13

Electrical Characteristics

Figure 3 illustrates the Power Up sequence as described above.

Figure 3. MPC8641 Power-Up and Reset Sequence

VDD_PLAT, AVDD_PLAT

L/T/OVDD

Time

2.5 V

3.3 V

1.2 V

DC Power Supply Voltage

Reset

Configuration Pins

HRESET (& TRST)

100 µs Platform PLL

Asserted for

100 μs after

Power Supply Ramp Up 2

Notes:

1. Dotted waveforms correspond to optional supply values for a specified power supply. See Ta b l e 2 .

2. The recommended maximum ramp up time for power supplies is 20 milliseconds.

3. Refer to Section 5, “RESET Initialization” for additional information on PLL relock and reset signal

assertion timing requirements.

4. Refer to Ta bl e 1 1 for additional information on reset configuration pin setup timing requirements. In

addition see Figure 68 regarding HRESET and JTAG connection details including TRST.

5. e600 PLL relock time is 100 microseconds maximum plus 255 MPX_clk cycles.

6. Stable PLL configuration signals are required as stable SYSCLK is applied. All other POR configuration

inputs are required 4 SYSCLK cycles before HRESET negation and are valid at least 2 SYSCLK cycles

after HRESET has negated (hold requirement). See Section 5, “RESET Initialization” for more

information on setup and hold time of reset configuration signals.

7. VDD_PLAT, AVDD_PLAT must strictly reach 90% of their recommended voltage before the rail for

Dn_GVDD, and Dn_MVREF reaches 10% of their recommended voltage.

8. SYSCLK must be driven only AFTER the power for the various power supplies is stable.

9. In device sleep mode, the reset configuration signals for DRAM types (TSEC2_TXD[4],TSEC2_TX_ER)

must be valid BEFORE HRESET is asserted.

e600

_LB, SV

, XV

_SRDSn

VDD_Coren, AVDD_Coren

AVDD_SRDSn

1.8 V

Dn_GVDD, = 1.8/2.5 V

Dn_MVREF

SYSCLK

(not drawn to scale)

Relock Time 3

L/TVDD=2.5 V 1

PLL

SYSCLK is functional 4

Cycles Setup and hold Time 6

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

14 Freescale Semiconductor

Power Characteristics

3 Power Characteristics

The power dissipation for the dual core MPC8641D device is shown in Table 4.

Table 4. MPC8641D Power Dissipation (Dual Core)

Power Mode Core Frequency

(MHz)

Platform

Frequency (MHz)

VDD_Coren,

VDD_PLAT

(Volts)

Junction

Temperature

Power

(Watts) Notes

Typical

1500 MHz 600 MHz 1.1 V

65 oC32.11, 2

Thermal

105 oC

43.4 1, 3

Maximum 49.9 1, 4

Typical

1333 MHz 533 MHz 1.05 V

65 oC23.91, 2

Thermal

105 oC

30.0 1, 3

Maximum 34.1 1, 4

Typical

1250 MHz

500 MHz

1.05 V

65 oC23.91, 2

Thermal

105 oC

30.0 1, 3

Maximum 34.1 1, 4

Typical

1000 MHz 400 MHz 1.05 V

65 oC23.91, 2

Thermal

105 oC

30.0 1, 3

Maximum 34.1 1, 4

Typical

1000 MHz 500 MHz 0.95 V,

1.05 V

65 oC 16.2 1, 2, 5

Thermal

105 oC

21.8 1, 3, 5

Maximum 25.0 1, 4, 5

Notes:

1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and

configurations. The values do not include power dissipation for I/O supplies.

2. Typical power is an average value measured at the nominal recommended core voltage (VDD_Coren) and 65°C junction

temperature (see Ta b l e 2 )while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz with one core

at 100% efficiency and the second core at 65% efficiency.

3. Thermal power is the average power measured at nominal core voltage (VDD_Coren) and maximum operating junction

temperature (see Ta bl e 2 ) while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz on both

cores and a typical workload on platform interfaces.

4. Maximum power is the maximum power measured at nominal core voltage (VDD_Coren) and maximum operating junction

temperature (see Ta bl e 2 ) while running a test which includes an entirely L1-cache-resident, contrived sequence of

instructions which keep all the execution units maximally busy on both cores.

5. These power numbers are for Part Number MC8641Dxx1000NX only. VDD_Coren = 0.95 V and VDD_PLAT = 1.05 V.

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 15

Power Characteristics

The maximum power dissipation for individual power supplies of the MPC8641D is shown in Table 5.

Table 5. MPC8641D Individual Supply Maximum Power Dissipation 1

Component Description Supply Voltage

(Volts)

Power

(Watts) Notes

Per Core voltage Supply VDD_Core0/VDD_Core1 = 1.1 V @ 1500 MHz 21.00

Per Core PLL voltage supply AVDD_Core0/AVDD_Core1 = 1.1 V @ 1500 MHz 0.0125

Per Core voltage Supply VDD_Core0/VDD_Core1 = 1.05 V @ 1333 MHz 17.00

Per Core PLL voltage supply AVDD_Core0/AVDD_Core1 = 1.05 V @ 1333 MHz 0.0125

Per Core voltage Supply VDD_Core0/VDD_Core1 = 0.95 V @ 1000 MHz 11.50 5

Per Core PLL voltage supply AVDD_Core0/AVDD_Core1 = 0.95 V @ 1000 MHz 0.0125 5

DDR Controller I/O voltage supply Dn_GVDD = 2.5 V @ 400 MHz 0.80 2

Dn_GVDD = 1.8 V @ 533 MHz 0.68 2

Dn_GVDD = 1.8 V @ 600 MHz 0.77 2

16-bit FIFO @ 200 MHz

eTsec 1&2/3&4 Voltage Supply

L/TVDD = 3.3 V 0.11 2, 3

non-FIFO eTsecn Voltage Supply L/TVDD = 3.3 V 0.08 2

x8 SerDes transceiver Supply SVDD = 1.1 V 0.70 2

x8 SerDes I/O Supply XVDD_SRDSn = 1.1 V 0.66 2

SerDes PLL voltage supply Port 1 or 2 AVDD_SRDS1/AVDD_SRDS2 = 1.1 V 0.10

Platform I/O Supply OVDD = 3.3 V 0.45 4

Platform source Supply VDD_PLAT = 1.1 V @ 600 MHz 12.00

Platform source Supply VDD_PLAT = 1.05 Vn @ 500 MHz 9.80 5

Platform source Supply VDD_PLAT = 1.05 Vn @ 400 MHz 7.70

Platform, Local Bus PLL voltage Supply AVDD_PLAT, AVDD_LB = 1.1 V 0.0125

Notes:

1. This is a maximum power supply number which is provided for power supply and board design information. The numbers are

based on 100% bus utilization for each component. The components listed are not expected to have 100% bus usage

simultaneously for all components. Actual numbers may vary based on activity.

2. Number is based on a per port/interface value.

3. This is based on one eTSEC port used. Since 16-bit FIFO mode involves two ports, the number will need to be multiplied by

two for the total. The other eTSEC protocols dissipate less than this number per port. Note that the power needs to be

multiplied by the number of ports used for the protocol for the total eTSEC port power dissipation.

4.This includes Local Bus, DUART, I2C, DMA, Multiprocessor Interrupts, System Control & Clocking, Debug, Test, Power

management, JTAG and Miscellaneous I/O voltage.

5. These power numbers are for Part Number MC8641xxx1000NX only. VDD_Coren = 0.95 V and VDD_PLAT = 1.05 V.

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

16 Freescale Semiconductor

Power Characteristics

The power dissipation for the MPC8641 single core device is shown in Table 6.

Table 6. MPC8641 Power Dissipation (Single Core)

Power Mode Core Frequency

(MHz)

Platform

Frequency (MHz)

VDD_Coren,

VDD_PLAT

(Volts)

Junction

Temperature

Power

(Watts) Notes

Typical

1500 MHz 600 MHz 1.1 V

65 oC20.31, 2

Thermal

105 oC

25.2 1, 3

Maxim 28.9 1, 4

Typical

1333 MHz 533 MHz 1.05 V

65 oC16.31, 2

Thermal

105 oC

20.2 1, 3

Maximum 23.2 1, 4

Typical

1250 MHz

500 MHz

1.05 V

65 oC16.31, 2

Thermal

105 oC

20.2 1, 3

Maximum 23.2 1, 4

Typical

1000 MHz 400 MHz 1.05 V

65 oC16.31, 2

Thermal

105 oC

20.2 1, 3

Maximum 23.2 1, 4

Typical

1000 MHz 500 MHz 0.95 V,

1.05 V

65 oC 11.6 1, 2, 5

Thermal

105 oC

14.4 1, 3, 5

Maximum 16.5 1, 4, 5

Notes:

1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and

configurations. The values do not include power dissipation for I/O supplies.

2. Typical power is an average value measured at the nominal recommended core voltage (VDD_Coren) and 65°C junction

temperature (see Ta bl e 2 )while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz.

3. Thermal power is the average power measured at nominal core voltage (VDD_Coren) and maximum operating junction

temperature (see Ta bl e 2 ) while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz and a typical

workload on platform interfaces.

4. Maximum power is the maximum power measured at nominal core voltage (VDD_Coren) and maximum operating junction

temperature (see Ta bl e 2 ) while running a test which includes an entirely L1-cache-resident, contrived sequence of

instructions which keep all the execution units maximally busy.

5. These power numbers are for Part Number MC8641xx1000NX only. VDD_Coren = 0.95 V and VDD_PLAT = 1.05 V.

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 17

Input Clocks

4 Input Clocks

Table 7 provides the system clock (SYSCLK) DC specifications for the MPC8641.

4.1 System Clock Timing

Table 8 provides the system clock (SYSCLK) AC timing specifications for the MPC8641.

4.1.1 SYSCLK and Spread Spectrum Sources

Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference

emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise

magnitude in order to meet industry and government requirements. These clock sources intentionally add

long-term jitter in order to diffuse the EMI spectral content. The jitter specification given in Table 8

considers short-term (cycle-to-cycle) jitter only and the clock generator’s cycle-to-cycle output jitter

Table 7. SYSCLK DC Electrical Characteristics (OVDD = 3.3 V ± 165 mV)

Parameter Symbol Min Max Unit

High-level input voltage VIH 2OV

DD + 0.3 V

Low-level input voltage VIL –0.3 0.8 V

Input current

(VIN 1 = 0 V or VIN = VDD)

IIN —±5μA

Note:

1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Ta bl e 1 and Ta bl e 2 .

Table 8. SYSCLK AC Timing Specifications

At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV.

Parameter/Condition Symbol Min Typical Max Unit Notes

SYSCLK frequency fSYSCLK 66 — 166.66 MHz 1

SYSCLK cycle time tSYSCLK 6——ns—

SYSCLK rise and fall time tKH, tKL 0.6 1.0 1.2 ns 2

SYSCLK duty cycle tKHK/tSYSCLK 40 — 60 % 3

SYSCLK jitter — — — 150 ps 4, 5

Notes:

1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the

resulting SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective

maximum or minimum operating frequencies. See Section 18.2, “MPX to SYSCLK PLL Ratio,” and Section 18.3,

“e600 to MPX clock PLL Ratio,” for ratio settings.

2. Rise and fall times for SYSCLK are measured at 0.4 V and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the short term jitter only and is guaranteed by design.

5. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to

allow cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter. Note that the

frequency modulation for SYSCLK reduces significantly for the spread spectrum source case. This is to guarantee

what is supported based on design.

iREFfCLK and SDrLREFiCLK

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

18 Freescale Semiconductor

Input Clocks

should meet the MPC8641 input cycle-to-cycle jitter requirement. Frequency modulation and spread are

separate concerns, and the MPC8641 is compatible with spread spectrum sources if the recommendations

listed in Table 9 are observed.

It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO frequencies

must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is

operated at its maximum rated e600 core frequency should avoid violating the stated limits by using

down-spreading only.

SDn_REF_CLK and SDn_REF_CLK was designed to work with a spread spectrum clock (+0 to 0.5%

spreading at 30–33kHz rate is allowed), assuming both ends have same reference clock. For better results

use a source without significant unintended modulation.

4.2 Real Time Clock Timing

The RTC input is sampled by the platform clock (MPX clock). The output of the sampling latch is then

used as an input to the counters of the PIC. There is no jitter specification. The minimum pulse width of

the RTC signal should be greater than 2x the period of the MPX clock. That is, minimum clock high time

is 2 × tMPX, and minimum clock low time is 2 × tMPX. There is no minimum RTC frequency; RTC may be

grounded if not needed.

4.3 eTSEC Gigabit Reference Clock Timing

Table 10 provides the eTSEC gigabit reference clocks (EC1_GTX_CLK125 and EC2_GTX_CLK125) AC

timing specifications for the MPC8641.

Table 9. Spread Spectrum Clock Source Recommendations

At recommended operating conditions. See Ta b l e 2 .

Parameter Min Max Unit Notes

Frequency modulation — 50 kHz 1

Frequency spread — 1.0 % 1, 2

Notes:

1. Guaranteed by design.

2. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO

frequencies, must meet the minimum and maximum specifications given in Ta b l e 8 .

Table 10. ECn_GTX_CLK125 AC Timing Specifications

Parameter/Condition Symbol Min Typical Max Unit Notes

ECn_GTX_CLK125 frequency fG125 — 125 ±100

ppm

—MHz3

ECn_GTX_CLK125 cycle time tG125 —8—ns—

ECn_GTX_CLK125 peak-to-peak jitter tG125J — — 250 ps 1

527 MHz x PQI-Express link width 2x . 12 x erialRaidl inleﬂacelre uenc x enalRaIdl Iinkwidlh

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 19

Input Clocks

NOTE

The phase between the output clocks TSEC1_GTX_CLK and

TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The phase

between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK

(ports 3 and 4) is no more than 100 ps.

4.4 Platform Frequency Requirements for PCI-Express and Serial

RapidIO

The MPX platform clock frequency must be considered for proper operation of the high-speed PCI

Express and Serial RapidIO interfaces as described below.

For proper PCI Express operation, the MPX clock frequency must be greater than or equal to:

527 MHz x (PCI-Express link width)

16 / (1 + cfg_plat_freq)

Note that at MPX = 400 MHz, cfg_plat_freq = 0 and at MPX > 400 MHz, cfg_plat_freq = 1. Therefore,

when operating PCI Express in x8 link width, the MPX platform frequency must be 400 MHz with

cfg_plat_freq = 0 or greater than or equal to 527 MHz with cfg_plat_freq = 1.

For proper Serial RapidIO operation, the MPX clock frequency must be greater than or equal to:

2 × (0.8512) × (Serial RapidIO interface frequency) × (Serial RapidIO link width)

4.5 Other Input Clocks

For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC,

see the specific section of this document.

ECn_GTX_CLK125 duty cycle

GMII, TBI

1000Base-T for RGMII, RTBI

tG125H/tG125

—

%1, 2

Notes:

1. Timing is guaranteed by design and characterization.

2. ECn_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation.

ECn_GTX_CLK125 duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle

generated by the eTSEC GTX_CLK. See Section 8.2.6, “RGMII and RTBI AC Timing Specifications,” for duty cycle

for 10Base-T and 100Base-T reference clock.

3. ±100 ppm tolerance on ECn_GTX_CLK125 frequency

Table 10. ECn_GTX_CLK125 AC Timing Specifications (continued)

Parameter/Condition Symbol Min Typical Max Unit Notes

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

20 Freescale Semiconductor

RESET Initialization

5 RESET Initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements of

the MPC8641. Table 11 provides the RESET initialization AC timing specifications.

Table 12 provides the PLL lock times.

Table 11. RESET Initialization Timing Specifications

Parameter/Condition Min Max Unit Notes

Required assertion time of HRESET 100 — μs—

Minimum assertion time for SRESET_0 & SRESET_1 3 — SYSCLKs 1

Platform PLL input setup time with stable SYSCLK

before HRESET negation

100 — μs2

Input setup time for POR configs (other than PLL

config) with respect to negation of HRESET

4 — SYSCLKs 1

Input hold time for all POR configs (including PLL

config) with respect to negation of HRESET

2 — SYSCLKs 1

Maximum valid-to-high impedance time for actively

driven POR configs with respect to negation of

HRESET

— 5 SYSCLKs 1

Notes:

1. SYSCLK is the primary clock input for the MPC8641.

2 This is related to HRESET assertion time. Stable PLL configuration inputs are required when a stable SYSCLK is

applied. See the MPC8641D Integrated Host Processor Reference Manual for more details on the power-on reset

sequence.

Table 12. PLL Lock Times

Parameter/Condition Min Max Unit Notes

(Platform and E600) PLL lock times — 100 μs1

Local bus PLL — 50 μs—

Note:

1.The PLL lock time for e600 PLLs require an additional 255 MPX_CLK cycles.

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 21

DDR and DDR2 SDRAM

6 DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the

MPC8641. Note that DDR SDRAM is Dn_GVDD(typ) = 2.5 V and DDR2 SDRAM is

Dn_GVDD(typ) = 1.8 V.

6.1 DDR SDRAM DC Electrical Characteristics

Table 13 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the

MPC8641 when Dn_GVDD(typ) = 1.8 V.

Table 14 provides the DDR2 capacitance when Dn_GVDD(typ) = 1.8 V.

Table 13. DDR2 SDRAM DC Electrical Characteristics for Dn_GVDD(typ) = 1.8 V

Parameter/Condition Symbol Min Max Unit Notes

I/O supply voltage Dn_GVDD 1.71 1.89 V 1

I/O reference voltage Dn_MVREF 0.49 ×Dn_GVDD 0.51 × Dn_GVDD V2

I/O termination voltage VTT Dn_MVREF –0.0

Dn_MVREF + 0.04 V 3

Input high voltage VIH Dn_MVREF+0.1

Dn_GVDD +0.3 V —

Input low voltage VIL –0.3 Dn_MVREF – 0.125 V —

Output leakage current IOZ –50 50 μA4

Output high current (VOUT = 1.420 V) IOH –13.4 — mA —

Output low current (VOUT = 0.280 V) IOL 13.4 — mA —

Notes:

1. Dn_GVDD is expected to be within 50 mV of the DRAM Dn_GVDD at all times.

2. Dn_MVREF is expected to be equal to 0.5 × Dn_GVDD, and to track Dn_GVDD DC variations as measured at the

receiver. Peak-to-peak noise on Dn_MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to Dn_MVREF

. This rail should track variations in the DC level of Dn_MVREF

4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ Dn_GVDD.

Table 14. DDR2 SDRAM Capacitance for Dn_GVDD(typ)=1.8 V

Parameter/Condition Symbol Min Max Unit Notes

Input/output capacitance: DQ, DQS, DQS CIO 68pF1

Delta input/output capacitance: DQ, DQS, DQS CDIO —0.5pF1

Note:

1. This parameter is sampled. Dn_GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA =25°C, V

OUT = Dn_GVDD/2, VOUT

(peak-to-peak) = 0.2 V.

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

22 Freescale Semiconductor

DDR and DDR2 SDRAM

Table 15 provides the recommended operating conditions for the DDR SDRAM component(s) when

Dn_GVDD(typ) = 2.5 V.

Table 16 provides the DDR capacitance when Dn_GVDD (typ)=2.5 V.

Table 17 provides the current draw characteristics for MVREF.

Table 15. DDR SDRAM DC Electrical Characteristics for Dn_GVDD (typ) = 2.5 V

Parameter/Condition Symbol Min Max Unit Notes

I/O supply voltage Dn_GVDD 2.375 2.625 V 1

I/O reference voltage Dn_MVREF 0.49 × Dn_GVDD 0.51 × Dn_GVDD V2

I/O termination voltage VTT Dn_MVREF – 0.04 Dn_MVREF + 0.04 V 3

Input high voltage VIH Dn_MVREF + 0.15 Dn_GVDD + 0.3 V —

Input low voltage VIL –0.3 Dn_MVREF– 0.15 V —

Output leakage current IOZ –50 50 μA4

Output high current (VOUT = 1.95 V) IOH –16.2 — mA —

Output low current (VOUT = 0.35 V) IOL 16.2 — mA —

Notes:

1. Dn_GVDD is expected to be within 50 mV of the DRAM Dn_GVDD at all times.

2. MVREF is expected to be equal to 0.5 × Dn_GVDD, and to track Dn_GVDD DC variations as measured at the receiver.

Peak-to-peak noise on Dn_MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to Dn_MVREF

. This rail should track variations in the DC level of Dn_MVREF

4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ Dn_GVDD.

Table 16. DDR SDRAM Capacitance for Dn_GVDD (typ) = 2.5 V

Parameter/Condition Symbol Min Max Unit Notes

Input/output capacitance: DQ, DQS CIO 68pF1

Delta input/output capacitance: DQ, DQS CDIO —0.5pF1

Note:

1. This parameter is sampled. Dn_GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = Dn_GVDD/2,

VOUT (peak-to-peak) = 0.2 V.

Table 17. Current Draw Characteristics for MVREF

Parameter / Condition Symbol Min Max Unit Note

Current draw for MVREF IMVREF — 500 μA1

1. The voltage regulator for MVREF must be able to supply up to 500 μA current.

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 23

DDR and DDR2 SDRAM

6.2 DDR SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR SDRAM interface.

6.2.1 DDR SDRAM Input AC Timing Specifications

Table 18 provides the input AC timing specifications for the DDR2 SDRAM when Dn_GVDD(typ)=1.8 V.

Table 19 provides the input AC timing specifications for the DDR SDRAM when Dn_GVDD(typ)=2.5 V.

Table 20 provides the input AC timing specifications for the DDR SDRAM interface.

Table 18. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

At recommended operating conditions

Parameter Symbol Min Max Unit Notes

AC input low voltage

400, 533 MHz

600 MHz

VIL

—Dn_MVREF – 0.25

Dn_MVREF – 0.20

V—

AC input high voltage

400, 533 MHz

600 MHz

VIH

Dn_MVREF + 0.25

Dn_MVREF + 0.20

—

V—

Table 19. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface

At recommended operating conditions.

Parameter Symbol Min Max Unit Notes

AC input low voltage VIL —Dn_MVREF – 0.31 V —

AC input high voltage VIH Dn_MVREF + 0.31 — V —

Table 20. DDR SDRAM Input AC Timing Specifications

At recommended operating conditions.

Parameter Symbol Min Max Unit Notes

Controller Skew for

MDQS—MDQ/MECC

tCISKEW —ps1, 2

600 MHz — –240 240 — 3

533 MHz — –300 300 — 3

400 MHz — –365 365 — —

Note:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding

bit that will be captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be

determined by the following equation: tDISKEW =+/–(T/4 – abs(tCISKEW)) where T is the clock period and

abs(tCISKEW) is the absolute value of tCISKEW.

3. Maximum DDR1 frequency is 400 MHz.

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

24 Freescale Semiconductor

DDR and DDR2 SDRAM

Figure 4 shows the DDR SDRAM input timing for the MDQS to MDQ skew measurement (tDISKEW).

Figure 4. DDR Input Timing Diagram for tDISKEW

6.2.2 DDR SDRAM Output AC Timing Specifications

Table 21. DDR SDRAM Output AC Timing Specifications

At recommended operating conditions.

Parameter Symbol 1Min Max Unit Notes

MCK[n] cycle time, MCK[n]/MCK[n] crossing tMCK 310ns2

MCK duty cycle

600 MHz

533 MHz

400 MHz

tMCKH/tMCK

47.5

52.5

ADDR/CMD output setup with respect to MCK tDDKHAS ns 3

600 MHz 1.10 — 7

533 MHz 1.48 — 7

400 MHz 1.95 —

ADDR/CMD output hold with respect to MCK tDDKHAX ns 3

600 MHz 1.10 — 7

533 MHz 1.48 — 7

400 MHz 1.95 —

MCS[n] output setup with respect to MCK tDDKHCS ns 3

600 MHz 1.10 — 7

533 MHz 1.48 — 7

400 MHz 1.95 —

MCK[n]

MCK[n] tMCK

MDQ[x]

MDQS[n]

tDISKEW

D1D0

tDISKEW

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 25

DDR and DDR2 SDRAM

MCS[n] output hold with respect to MCK tDDKHCX ns 3

600 MHz 1.10 — 7

533 MHz 1.48 — 7

400 MHz 1.95 —

MCK to MDQS Skew tDDKHMH –0.6 0.6 ns 4

MDQ/MECC/MDM output setup with respect

to MDQS

tDDKHDS,

tDDKLDS

ps 5

600 MHz 500 — 7

533 MHz 590 — 7

400 MHz 700 —

MDQ/MECC/MDM output hold with respect to

MDQS

tDDKHDX,

tDDKLDX

ps 5

600 MHz 500 — 7

533 MHz 590 — 7

400 MHz 700 —

MDQS preamble start tDDKHMP –0.5 × tMCK – 0.6 –0.5 × tMCK +0.6 ns 6

Table 21. DDR SDRAM Output AC Timing Specifications (continued)

At recommended operating conditions.

Parameter Symbol 1Min Max Unit Notes

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

26 Freescale Semiconductor

DDR and DDR2 SDRAM

NOTE

For the ADDR/CMD setup and hold specifications in Table 21, it is

assumed that the Clock Control register is set to adjust the memory clocks

by 1/2 applied cycle.

MDQS epilogue end tDDKHME –0.6 0.6 ns 6

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can

be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went

invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K)

goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR

timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data

output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.

4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR

timing (DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be

modified through control of the DQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This

will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in

the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8641

Integrated Processor Reference Manual for a description and understanding of the timing modifications enabled by

use of these bits.

5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ),

ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the

microprocessor.

6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows

the symbol conventions described in note 1.

7. Maximum DDR1 frequency is 400 MHz

8. Per the JEDEC spec the DDR2 duty cycle at 600 MHz is the average low and high cycle time values that are

defined as the average pulse widths calculated across any consecutive 200 pulses. Jitter can sometimes force

single low and high cycle times to drift from the average values. tJIT = ±125 ps.

9. Per the JEDEC spec the DDR2 duty cycle at 400 and 533 MHz is the low and high cycle time values.

Table 21. DDR SDRAM Output AC Timing Specifications (continued)

At recommended operating conditions.

Parameter Symbol 1Min Max Unit Notes

\ ‘ :47 Write A0

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 27

DDR and DDR2 SDRAM

Figure 5 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).

Figure 5. Timing Diagram for tDDKHMH

Figure 6 shows the DDR SDRAM output timing diagram.

Figure 6. DDR SDRAM Output Timing Diagram

MDQS

MCK[n]

tMCK

tDDKHMHmax) = 0.6 ns

tDDKHMH(min) = –0.6 ns

MDQS

ADDR/CMD

tDDKHAS ,tDDKHCS

tDDKHMH

tDDKLDS

tDDKHDS

MDQ[x]

MDQS[n]

MCK[n]

MCK[n] tMCK

tDDKLDX

tDDKHDX

D1D0

tDDKHAX ,tDDKHCX

Write A0 NOOP

tDDKHME

tDDKHMP

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

28 Freescale Semiconductor

DUART

Figure 7 provides the AC test load for the DDR bus.

Figure 7. DDR AC Test Load

7DUART

This section describes the DC and AC electrical specifications for the DUART interface of the MPC8641.

7.1 DUART DC Electrical Characteristics

Table 22 provides the DC electrical characteristics for the DUART interface.

7.2 DUART AC Electrical Specifications

Table 23 provides the AC timing parameters for the DUART interface.

Table 22. DUART DC Electrical Characteristics

Parameter Symbol Min Max Unit

High-level input voltage VIH 2OV

DD + 0.3 V

Low-level input voltage VIL –0.3 0.8 V

Input current

(VIN 1 = 0 V or VIN = VDD)

IIN —±5 μA

High-level output voltage

(OVDD = min, IOH = –100 μA)

VOH OVDD – 0.2 — V

Low-level output voltage

(OVDD = min, IOL = 100 μA)

VOL —0.2 V

Note:

1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Tabl e 1 and Ta b l e 2 .

Table 23. DUART AC Timing Specifications

Parameter Value Unit Notes

Minimum baud rate MPX clock/1,048,576 baud 1,2

Maximum baud rate MPX clock/16 baud 1,3

Oversample rate 16 — 1,4

Notes:

1. Guaranteed by design.

2. MPX clock refers to the platform clock.

3. Actual attainable baud rate will be limited by the latency of interrupt processing.

4. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are

sampled each 16th sample.

Output Z0 = 50 Ω

RL = 50 Ω

Dn_GVDD/2

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 29

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

8 Ethernet: Enhanced Three-Speed Ethernet (eTSEC),

MII Management

This section provides the AC and DC electrical characteristics for enhanced three-speed and MII

management.

8.1 Enhanced Three-Speed Ethernet Controller (eTSEC)

(10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI/RMII Electrical

Characteristics

The electrical characteristics specified here apply to all gigabit media independent interface (GMII), media

independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface

(RGMII), reduced ten-bit interface (RTBI), and reduced media independent interface (RMII) signals

except management data input/output (MDIO) and management data clock (MDC). The RGMII and RTBI

interfaces are defined for 2.5 V, while the GMII and TBI interfaces can be operated at 3.3 or 2.5 V. Whether

the GMII or TBI interface is operated at 3.3 or 2.5 V, the timing is compatible with IEEE 802.3. The

RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface (RGMII)

Specification Version 1.3 (12/10/2000). The RMII interface follows the RMII Consortium RMII

Specification Version 1.2 (3/20/1998). The electrical characteristics for MDIO and MDC are specified in

Section 9, “Ethernet Management Interface Electrical Characteristics.”

8.1.1 eTSEC DC Electrical Characteristics

All GMII, MII, TBI, RGMII, RMII and RTBI drivers and receivers comply with the DC parametric

attributes specified in Table 24 and Table 25. The potential applied to the input of a GMII, MII, TBI,

RGMII, RMII or RTBI receiver may exceed the potential of the receiver’s power supply (that is, a GMII

driver powered from a 3.6-V supply driving VOH into a GMII receiver powered from a 2.5-V supply).

Tolerance for dissimilar GMII driver and receiver supply potentials is implicit in these specifications. The

RGMII and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC

EIA/JESD8-5.

Table 24. GMII, MII, RMII, TBI and FIFO DC Electrical Characteristics

Parameter Symbol Min Max Unit Notes

Supply voltage 3.3 V LVDD

TVDD

3.135 3.465 V 1, 2

Output high voltage

(LVDD/TVDD = Min, IOH = –4.0 mA)

VOH 2.40 — V —

Output low voltage

(LVDD/TVDD = Min, IOL = 4.0 mA)

VOL —0.50 V—

Input high voltage VIH 2.0 — V —

Input low voltage VIL —0.90 V—

Input high current

(VIN = LVDD, VIN = TVDD)

IIH —40 μA1, 2,3

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

30 Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

8.2 FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing

Specifications

The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII and RTBI are presented in this

section.

8.2.1 FIFO AC Specifications

The basis for the AC specifications for the eTSEC’s FIFO modes is the double data rate RGMII and RTBI

specifications, since they have similar performance and are described in a source-synchronous fashion like

FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and

source clock in GMII fashion.

When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the

relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK,

while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit

Input low current

(VIN = GND)

IIL –600 — μA3

Notes:

1LVDD supports eTSECs 1 and 2.

2TVDD supports eTSECs 3 and 4.

3The symbol VIN, in this case, represents the LVIN and TVIN symbols referenced in Ta b l e 1 and Ta bl e 2 .

Table 25. GMII, RGMII, RTBI, TBI and FIFO DC Electrical Characteristics

Parameters Symbol Min Max Unit Notes

Supply voltage 2.5 V LVDD/TVDD 2.375 2.625 V 1,2

1LVDD supports eTSECs 1 and 2.

2TVDD supports eTSECs 3 and 4.

Output high voltage

(LVDD/TVDD = Min, IOH = –1.0 mA)

VOH 2.00 — V —

Output low voltage

(LVDD/TVDD = Min, IOL = 1.0 mA)

VOL —0.40V—

Input high voltage VIH 1.70 — V —

Input low voltage VIL —0.90V—

Input high current

(VIN = LVDD, VIN = TVDD)

IIH —10μA1, 2,3

3Note that the symbol VIN, in this case, represents the LVIN and TVIN symbols referenced in Ta b l e 1 and Ta b l e 2 .

Input low current

(VIN = GND)

IIL –15 — μA3

Note:

Table 24. GMII, MII, RMII, TBI and FIFO DC Electrical Characteristics (continued)

Parameter Symbol Min Max Unit Notes

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 31

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out

onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is

intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a

source-synchronous timing reference. Typically, the clock edge that launched the data can be used, since

the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is

relationship between the maximum FIFO speed and the platform speed. For more information see

Section 18.4.2, “Platform to FIFO Restrictions.”

NOTE

The phase between the output clocks TSEC1_GTX_CLK and

TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The phase

between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK

(ports 3 and 4) is no more than 100 ps.

A summary of the FIFO AC specifications appears in Table 26 and Table 27.

Table 26. FIFO Mode Transmit AC Timing Specification

At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.

Parameter/Condition Symbol Min Typ Max Unit

TX_CLK, GTX_CLK clock period (GMII mode) tFIT 7.0 8.0 100 ns

TX_CLK, GTX_CLK clock period (Encoded mode) tFIT 5.3 8.0 100 ns

TX_CLK, GTX_CLK duty cycle tFITH/tFIT 45 50 55 %

TX_CLK, GTX_CLK peak-to-peak jitter tFITJ ——250ps

Rise time TX_CLK (20%–80%) tFITR — — 0.75 ns

Fall time TX_CLK (80%–20%) tFITF — — 0.75 ns

FIFO data TXD[7:0], TX_ER, TX_EN setup time to GTX_CLK tFITDV 2.0 — — ns

GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time tFITDX 0.5 — 3.0 ns

Table 27. FIFO Mode Receive AC Timing Specification

At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.

Parameter/Condition Symbol Min Typ Max Unit

RX_CLK clock period (GMII mode) tFIR1

1±100 ppm tolerance on RX_CLK frequency

7.0 8.0 100 ns

RX_CLK clock period (Encoded mode) tFIR 15.3 8.0 100 ns

RX_CLK duty cycle tFIRH/tFIR 45 50 55 %

RX_CLK peak-to-peak jitter tFIRJ — — 250 ps

Rise time RX_CLK (20%–80%) tFIRR — — 0.75 ns

Fall time RX_CLK (80%–20%) tFIRF — — 0.75 ns

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK tFIRDV 1.5 — — ns

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK tFIRDX 0.5 — — ns

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

32 Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

Timing diagrams for FIFO appear in Figure 8 and Figure 9.

Figure 8. FIFO Transmit AC Timing Diagram

Figure 9. FIFO Receive AC Timing Diagram

8.2.2 GMII AC Timing Specifications

This section describes the GMII transmit and receive AC timing specifications.

8.2.2.1 GMII Transmit AC Timing Specifications

Table 28 provides the GMII transmit AC timing specifications.

Table 28. GMII Transmit AC Timing Specifications

At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.

Parameter/Condition Symbol 1Min Typ Max Unit

GMII data TXD[7:0], TX_ER, TX_EN setup time tGTKHDV 2.5 — — ns

GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay tGTKHDX 0.5 — 5.0 ns

GTX_CLK data clock rise time (20%-80%) tGTXR2——1.0ns

tFIT

tFITH

tFITF

tFITDX

TXD[7:0]

TX_EN

GTX_CLK

TX_ER

tFITDV

tFITR

tFIR

tFIRH tFIRF

tFIRR

RX_CLK

RXD[7:0]

RX_DV

RX_ER

valid data

tFIRDX

tFIRDV

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 33

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

Figure 10 shows the GMII transmit AC timing diagram.

Figure 10. GMII Transmit AC Timing Diagram

8.2.2.2 GMII Receive AC Timing Specifications

Table 29 provides the GMII receive AC timing specifications.

GTX_CLK data clock fall time (80%-20%) tGTXF2——1.0ns

Notes:

1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII

transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input

signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect

to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold

time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a

particular functional. For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times,

the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

Table 29. GMII Receive AC Timing Specifications

At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.

Parameter/Condition Symbol 1Min Typ Max Unit

RX_CLK clock period tGRX3—8.0— ns

RX_CLK duty cycle tGRXH/tGRX 40 — 60 ns

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK tGRDVKH 2.0 — — ns

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK tGRDXKH 0.5 — — ns

RX_CLK clock rise time (20%-80%) tGRXR2——1.0ns

Table 28. GMII Transmit AC Timing Specifications (continued)

At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.

Parameter/Condition Symbol 1Min Typ Max Unit

GTX_CLK

TXD[7:0]

tGTKHDX

tGTX

tGTXH

tGTXR

tGTXF

tGTKHDV

TX_EN

TX_ER

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

34 Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

Figure 11 provides the AC test load for eTSEC.

Figure 11. eTSEC AC Test Load

Figure 12 shows the GMII receive AC timing diagram.

Figure 12. GMII Receive AC Timing Diagram

RX_CLK clock fall time (80%-20%) tGRXF2——1.0ns

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII

receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock

reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to

the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time.

Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular

functional. For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

3. ±100 ppm tolerance on RX_CLK frequency

Table 29. GMII Receive AC Timing Specifications (continued)

At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.

Parameter/Condition Symbol 1Min Typ Max Unit

Output LVDD/2

RL = 50 Ω

Z0 = 50 Ω

RX_CLK

RXD[7:0]

tGRDXKH

tGRX

tGRXH

tGRXR

tGRXF

tGRDVKH

RX_DV

RX_ER

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 35

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

8.2.3 MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

8.2.3.1 MII Transmit AC Timing Specifications

Table 30 provides the MII transmit AC timing specifications.

Figure 13 shows the MII transmit AC timing diagram.

Figure 13. MII Transmit AC Timing Diagram

Table 30. MII Transmit AC Timing Specifications

At recommended operating conditions with L/TVDD of 3.3 V ± 5%.

Parameter/Condition Symbol 1Min Typ Max Unit

TX_CLK clock period 10 Mbps tMTX2—400— ns

TX_CLK clock period 100 Mbps tMTX —40—ns

TX_CLK duty cycle tMTXH/tMTX 35 — 65 %

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay tMTKHDX 1515ns

TX_CLK data clock rise time (20%-80%) tMTXR21.0 — 4.0 ns

TX_CLK data clock fall time (80%-20%) tMTXF21.0 — 4.0 ns

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII

transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in

general, the clock reference symbol representation is based on two to three letters representing the clock of a particular

functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

TX_CLK

TXD[3:0]

tMTKHDX

tMTX

tMTXH

tMTXR

tMTXF

TX_EN

TX_ER

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

36 Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

8.2.3.2 MII Receive AC Timing Specifications

Table 31 provides the MII receive AC timing specifications.

Figure 14 provides the AC test load for eTSEC.

Figure 14. eTSEC AC Test Load

Figure 15 shows the MII receive AC timing diagram.

Figure 15. MII Receive AC Timing Diagram

Table 31. MII Receive AC Timing Specifications

At recommended operating conditions with L/TVDD of 3.3 V ± 5%.

Parameter/Condition Symbol 1Min Typ Max Unit

RX_CLK clock period 10 Mbps tMRX2,3 —400— ns

RX_CLK clock period 100 Mbps tMRX3—40—ns

RX_CLK duty cycle tMRXH/tMRX 35 — 65 %

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK tMRDVKH 10.0 — — ns

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK tMRDXKH 10.0 — — ns

RX_CLK clock rise time (20%-80%) tMRXR21.0 — 4.0 ns

RX_CLK clock fall time (80%-20%) tMRXF21.0 — 4.0 ns

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive

timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K)

going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input

signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general,

the clock reference symbol representation is based on three letters representing the clock of a particular functional. For

example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used

with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

3. ±100 ppm tolerance on RX_CLK frequency

Output Z0 = 50 ΩLVDD/2

RL = 50 Ω

RX_CLK

RXD[3:0]

tMRDXKL

tMRX

tMRXH

tMRXR

tMRXF

RX_DV

RX_ER

tMRDVKH

Valid Data

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 37

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

8.2.4 TBI AC Timing Specifications

This section describes the TBI transmit and receive AC timing specifications.

8.2.4.1 TBI Transmit AC Timing Specifications

Table 32 provides the TBI transmit AC timing specifications.

Figure 16 shows the TBI transmit AC timing diagram.

Figure 16. TBI Transmit AC Timing Diagram

Table 32. TBI Transmit AC Timing Specifications

At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.

Parameter/Condition Symbol 1Min Typ Max Unit

TCG[9:0] setup time GTX_CLK going high tTTKHDV 2.0 — — ns

TCG[9:0] hold time from GTX_CLK going high tTTKHDX 1.0 — — ns

GTX_CLK rise time (20%–80%) tTTXR2——1.0ns

GTX_CLK fall time (80%–20%) tTTXF2——1.0ns

Notes:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI

transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid

state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high

(H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference

symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of

tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter:

R (rise) or F (fall).

2. Guaranteed by design.

GTX_CLK

TCG[9:0]

tTTXR

tTTX

tTTXH

tTTXR

tTTXF

tTTKHDV

tTTKHDX

tTTXF

«jﬁ

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

38 Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

8.2.4.2 TBI Receive AC Timing Specifications

Table 33 provides the TBI receive AC timing specifications.

Figure 17 shows the TBI receive AC timing diagram.

Figure 17. TBI Receive AC Timing Diagram

Table 33. TBI Receive AC Timing Specifications

At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.

Parameter/Condition Symbol 1Min Typ Max Unit

PMA_RX_CLK[0:1] clock period tTRX3— 16.0 — ns

PMA_RX_CLK[0:1] skew tSKTRX 7.5 — 8.5 ns

PMA_RX_CLK[0:1] duty cycle tTRXH/tTRX 40 — 60 %

RCG[9:0] setup time to rising PMA_RX_CLK tTRDVKH 2.5 — — ns

RCG[9:0] hold time to rising PMA_RX_CLK tTRDXKH 1.5 — — ns

PMA_RX_CLK[0:1] clock rise time (20%-80%) tTRXR20.7 — 2.4 ns

PMA_RX_CLK[0:1] clock fall time (80%-20%) tTRXF20.7 — 2.4 ns

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive

timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K) going

to the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with respect to the time data input signals

(D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state. Note that, in general, the clock reference

symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of

tTRX represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter:

R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX).

2. Guaranteed by design.

3. ±100 ppm tolerance on PMA_RX_CLK[0:1] frequency

PMA_RX_CLK1

RCG[9:0]

tTRX

tTRXH

tTRXR

tTRXF

tTRDVKH

PMA_RX_CLK0

tTRDXKH

tTRDVKH

tTRDXKH

tSKTRX

tTRXH

Valid Data Valid Data

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 39

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

8.2.5 TBI Single-Clock Mode AC Specifications

When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant

eTSEC interface. In single-clock TBI mode, when TBICON[CLKSEL] = 1 a 125-MHz TBI receive clock

is supplied on TSECn_RX_CLK pin (no receive clock is used on TSECn_TX_CLK in this mode, whereas

for the dual-clock mode this is the PMA1 receive clock). The 125-MHz transmit clock is applied on the

TSEC_GTX_CLK125 pin in all TBI modes.

A summary of the single-clock TBI mode AC specifications for receive appears in Table 34.

A timing diagram for TBI receive appears in Figure 18.

Figure 18. TBI Single-Clock Mode Receive AC Timing Diagram

8.2.6 RGMII and RTBI AC Timing Specifications

Table 35 presents the RGMII and RTBI AC timing specifications.

Table 34. TBI single-clock Mode Receive AC Timing Specification

At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.

Parameter/Condition Symbol Min Typ Max Unit

RX_CLK clock period tTRR1

1±100 ppm tolerance on RX_CLK frequency

7.5 8.0 8.5 ns

RX_CLK duty cycle tTRRH/tTRR 40 50 60 %

RX_CLK peak-to-peak jitter tTRRJ — — 250 ps

Rise time RX_CLK (20%–80%) tTRRR ——1.0ns

Fall time RX_CLK (80%–20%) tTRRF ——1.0ns

RCG[9:0] setup time to RX_CLK rising edge tTRRDVKH 2.0 — — ns

RCG[9:0] hold time to RX_CLK rising edge tTRRDXKH 1.0 — — ns

Table 35. RGMII and RTBI AC Timing Specifications

At recommended operating conditions with L/TVDD of 2.5 V ± 5%.

Parameter/Condition Symbol 1Min Typ Max Unit

Data to clock output skew (at transmitter) tSKRGT5–500 0 500 ps

Data to clock input skew (at receiver) 2tSKRGT 1.0 — 2.8 ns

tTRR

tTRRH tTRRF

tTRRR

RX_CLK

RCG[9:0]

valid data

tTRRDXKH

tTRRDVKH

C XXXX X

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

40 Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

Figure 19 shows the RGMII and RTBI AC timing and multiplexing diagrams.

Figure 19. RGMII and RTBI AC Timing and Multiplexing Diagrams

Clock period duration 3tRGT5,6 7.2 8.0 8.8 ns

Duty cycle for 10BASE-T and 100BASE-TX 3, 4 tRGTH/tRGT540 50 60 %

Rise time (20%–80%) tRGTR5— — 0.75 ns

Fall time (80%–20%) tRGTF5— — 0.75 ns

Notes:

1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent

RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note also that the

notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the

subscript is skew (SK) followed by the clock that is being skewed (RGT).

2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns

will be added to the associated clock signal.

3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long

as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned

between.

5. Guaranteed by characterization

6. ±100 ppm tolerance on RX_CLK frequency

Table 35. RGMII and RTBI AC Timing Specifications (continued)

At recommended operating conditions with L/TVDD of 2.5 V ± 5%.

Parameter/Condition Symbol 1Min Typ Max Unit

GTX_CLK

tRGT

tRGTH

tSKRGT

TX_CTL

TXD[8:5]

TXD[7:4]

TXD[9]

TXERR

TXD[4]

TXEN

TXD[3:0]

(At Transmitter)

TXD[8:5][3:0]

TXD[7:4][3:0]

TX_CLK

(At PHY)

RX_CTL

RXD[8:5]

RXD[7:4]

RXD[9]

RXERR

RXD[4]

RXDV

RXD[3:0]

RXD[8:5][3:0]

RXD[7:4][3:0]

RX_CLK

(At PHY)

tSKRGT

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 41

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

8.2.7 RMII AC Timing Specifications

This section describes the RMII transmit and receive AC timing specifications.

8.2.7.1 RMII Transmit AC Timing Specifications

The RMII transmit AC timing specifications are in Table 36.

Figure 20 shows the RMII transmit AC timing diagram.

Figure 20. RMII Transmit AC Timing Diagram

Table 36. RMII Transmit AC Timing Specifications

At recommended operating conditions with L/TVDD of 3.3 V ± 5%.

Parameter/Condition Symbol 1Min Typ Max Unit

REF_CLK clock period tRMT —20.0— ns

REF_CLK duty cycle tRMTH/tRMT 35 50 65 %

REF_CLK peak-to-peak jitter tRMTJ — — 250 ps

Rise time REF_CLK (20%–80%) tRMTR 1.0 — 2.0 ns

Fall time REF_CLK (80%–20%) tRMTF 1.0 — 2.0 ns

REF_CLK to RMII data TXD[1:0], TX_EN delay tRMTDX 1.0 — 10.0 ns

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII

transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in

general, the clock reference symbol representation is based on two to three letters representing the clock of a particular

functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

REF_CLK

TXD[1:0]

tRMTDX

tRMT

tRMTH

tRMTR

tRMTF

TX_EN

TX_ER

, a +

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

42 Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

8.2.7.2 RMII Receive AC Timing Specifications

Figure 21 provides the AC test load for eTSEC.

Figure 21. eTSEC AC Test Load

Figure 22 shows the RMII receive AC timing diagram.

Figure 22. RMII Receive AC Timing Diagram

Table 37. RMII Receive AC Timing Specifications

At recommended operating conditions with L/TVDD of 3.3 V ± 5%.

Parameter/Condition Symbol 1Min Typ Max Unit

REF_CLK clock period tRMR 15.0 20.0 25.0 ns

REF_CLK duty cycle tRMRH/tRMR 35 50 65 %

REF_CLK peak-to-peak jitter tRMRJ — — 250 ps

Rise time REF_CLK (20%–80%) tRMRR 1.0 — 2.0 ns

Fall time REF_CLK (80%–20%) tRMRF 1.0 — 2.0 ns

RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising

edge tRMRDV 4.0 — — ns

RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising

edge tRMRDX 2.0 — — ns

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive

timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going

to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals

(D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the

clock reference symbol representation is based on three letters representing the clock of a particular functional. For example,

the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the

appropriate letter: R (rise) or F (fall).

Output Z0 = 50 ΩLVDD/2

RL = 50 Ω

REF_CLK

RXD[1:0]

tRMRDX

tRMR

tRMRH

tRMRR

tRMRF

CRS_DV

RX_ER

tRMRDV

Valid Data

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 43

Ethernet Management Interface Electrical Characteristics

9 Ethernet Management Interface Electrical

Characteristics

The electrical characteristics specified here apply to MII management interface signals MDIO

(management data input/output) and MDC (management data clock). The electrical characteristics for

GMII, RGMII, RMII, TBI and RTBI are specified in “Section 8, “Ethernet: Enhanced Three-Speed

Ethernet (eTSEC), MII Management.”

9.1 MII Management DC Electrical Characteristics

The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics

for MDIO and MDC are provided in Table 38.

9.2 MII Management AC Electrical Specifications

Table 39 provides the MII management AC timing specifications.

Table 38. MII Management DC Electrical Characteristics

Parameter Symbol Min Max Unit

Supply voltage (3.3 V) OVDD 3.135 3.465 V

Output high voltage

(OVDD = Min, IOH = –1.0 mA)

VOH 2.10 — V

Output low voltage

(OVDD =Min, IOL = 1.0 mA)

VOL —0.50V

Input high voltage VIH 1.70 — V

Input low voltage VIL —0.90V

Input high current

(OVDD = Max, VIN 1 = 2.1 V)

IIH —40μA

Input low current

(OVDD = Max, VIN = 0.5 V)

IIL –600 — μA

Note:

1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Ta b l e 1 and Ta ble 2.

Table 39. MII Management AC Timing Specifications

At recommended operating conditions with OVDD is 3.3 V ± 5%.

Parameter/Condition Symbol 1Min Typ Max Unit Notes

MDC frequency fMDC 2.5 — 9.3 MHz 2, 4

MDC period tMDC 80 — 400 ns —

MDC clock pulse width high tMDCH 32 — — ns —

MDC to MDIO valid tMDKHDV 16*tMPXCLK ——ns5

MDC to MDIO delay tMDKHDX 10 — 16*tMPXCLK ns 3, 5

MDIO to MDC setup time tMDDVKH 5——ns—

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

44 Freescale Semiconductor

Ethernet Management Interface Electrical Characteristics

Figure 23 provides the AC test load for eTSEC.

Figure 23. eTSEC AC Test Load

NOTE

Output will see a 50-Ω load since what it sees is the transmission line.

Figure 24 shows the MII management AC timing diagram.

Figure 24. MII Management Interface Timing Diagram

MDIO to MDC hold time tMDDXKH 0——ns—

MDC rise time tMDCR — — 10 ns 4

MDC fall time tMDHF — — 10 ns 4

Notes:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX

symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are

invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input

signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For

rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the system clock speed. (The maximum frequency is the maximum platform frequency

divided by 64.)

3. This parameter is dependent on the system clock speed. (That is, for a system clock of 267 MHz, the maximum frequency

is 8.3 MHz and the minimum frequency is 1.2 MHz; for a system clock of 375 MHz, the maximum frequency is 11.7 MHz

and the minimum frequency is 1.7 MHz.)

4. Guaranteed by design.

5. tMPXCLK is the platform (MPX) clock

Table 39. MII Management AC Timing Specifications (continued)

At recommended operating conditions with OVDD is 3.3 V ± 5%.

Parameter/Condition Symbol 1Min Typ Max Unit Notes

Output Z0 = 50 ΩOVDD/2

RL = 50 Ω

MDC

tMDDXKH

tMDC

tMDCH

tMDCR

tMDCF

tMDDVKH

tMDKHDX

MDIO

(Input)

(Output)

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 45

Local Bus

10 Local Bus

This section describes the DC and AC electrical specifications for the local bus interface of the MPC8641.

10.1 Local Bus DC Electrical Characteristics

Table 40 provides the DC electrical characteristics for the local bus interface operating at OVDD = 3.3 V

DC.

10.2 Local Bus AC Electrical Specifications

Table 41 describes the timing parameters of the local bus interface at OVDD = 3.3 V with PLL enabled.

For information about the frequency range of local bus see Section 18.1, “Clock Ranges.”

Table 40. Local Bus DC Electrical Characteristics (3.3 V DC)

Parameter Symbol Min Max Unit

High-level input voltage VIH 2OV

DD + 0.3 V

Low-level input voltage VIL –0.3 0.8 V

Input current

(VIN 1 = 0 V or VIN = OVDD)

IIN —±5 μA

High-level output voltage

(OVDD = min, IOH = –2 mA)

VOH OVDD – 0.2 — V

Low-level output voltage

(OVDD = min, IOL = 2 mA)

VOL —0.2 V

Note:

1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Ta bl e 1 and Ta bl e 2 .

Table 41. Local Bus Timing Parameters (OVDD = 3.3 V)m - PLL Enabled

Parameter Symbol 1Min Max Unit Notes

Local bus cycle time tLBK 7.5 — ns 2

Local Bus Duty Cycle tLBKH/tLBK 45 55 % —

LCLK[n] skew to LCLK[m] or LSYNC_OUT tLBKSKEW — 150 ps 7, 8

Input setup to local bus clock (except LGTA/LUPWAIT) tLBIVKH1 1.8 — ns 3, 4

LGTA/LUPWAIT input setup to local bus clock tLBIVKH2 1.7 — ns 3, 4

Input hold from local bus clock (except LGTA/LUPWAIT) tLBIXKH1 1.0 — ns 3, 4

LGTA/LUPWAIT input hold from local bus clock tLBIXKH2 1.0 — ns 3, 4

LALE output transition to LAD/LDP output transition (LATCH hold

time)

tLBOTOT 1.5 — ns 6

Local bus clock to output valid (except LAD/LDP and LALE) tLBKHOV1 —2.0ns —

Local bus clock to data valid for LAD/LDP tLBKHOV2 —2.2ns —

Local bus clock to address valid for LAD tLBKHOV3 —2.3ns —

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

46 Freescale Semiconductor

Local Bus

Figure 25 provides the AC test load for the local bus.

Figure 25. Local Bus AC Test Load

Local bus clock to LALE assertion tLBKHOV4 —2.3ns 3

Output hold from local bus clock (except LAD/LDP and LALE) tLBKHOX1 0.7 — ns —

Output hold from local bus clock for LAD/LDP tLBKHOX2 0.7 — ns 3

Local bus clock to output high Impedance (except LAD/LDP and

LALE)

tLBKHOZ1 —2.5ns 5

Local bus clock to output high impedance for LAD/LDP tLBKHOZ2 —2.5ns 5

Note:

1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1

symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes

high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go

high (H), with respect to the output (O) going invalid (X) or output hold time.

2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.

3. All signals are measured from OVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL

bypass mode to 0.4 ×OVDD of the signal in question for 3.3-V signaling levels.

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is

programmed with the LBCR[AHD] parameter.

7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementary signals at BVDD/2.

8. Guaranteed by design.

Table 41. Local Bus Timing Parameters (OVDD = 3.3 V)m - PLL Enabled (continued)

Parameter Symbol 1Min Max Unit Notes

Output Z0 = 50 ΩOVDD/2

RL = 50 Ω

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 47

Local Bus

Figure 26 to Figure 31 show the local bus signals.

Figure 26. Local Bus Signals (PLL Enabled)

NOTE

PLL bypass mode is recommended when LBIU frequency is at or below

83 MHz. When LBIU operates above 83 MHz, LBIU PLL is recommended

to be enabled.

Table 42 describes the general timing parameters of the local bus interface at OVDD = 3.3 V with PLL

bypassed.

Table 42. Local Bus Timing Parameters—PLL Bypassed

Parameter Symbol 1Min Max Unit Notes

Local bus cycle time tLBK 12 — ns 2

Local bus duty cycle tLBKH/tLBK 45 55 % —

Internal launch/capture clock to LCLK delay tLBKHKT 2.3 3.9 ns 8

Input setup to local bus clock (except LGTA/LUPWAIT) tLBIVKH1 5.7 — ns 4, 5

LGTA/LUPWAIT input setup to local bus clock tLBIVKL2 5.6 — ns 4, 5

Input hold from local bus clock (except LGTA/LUPWAIT) tLBIXKH1 –1.8 — ns 4, 5

Output Signals:

LA[27:31]/LBCTL/LBCKE/LOE/

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

tLBKHOV1

tLBKHOV2

tLBKHOV3

LSYNC_IN

Input Signals:

LAD[0:31]/LDP[0:3]

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

Output (Address) Signal:

LAD[0:31]

LALE

tLBIXKH1

tLBIVKH1

tLBIVKH2

tLBIXKH2

tLBKHOX1

tLBKHOZ1

tLBKHOX2

tLBKHOZ2

Input Signal:

LGTA

tLBOTOT

tLBKHOZ2

tLBKHOX2

tLBKHOV4

LUPWAIT

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

48 Freescale Semiconductor

Local Bus

LGTA/LUPWAIT input hold from local bus clock tLBIXKL2 –1.3 — ns 4, 5

LALE output transition to LAD/LDP output transition (LATCH

hold time)

tLBOTOT 1.5 — ns 6

Local bus clock to output valid (except LAD/LDP and LALE) tLBKLOV1 — –0.3 ns

Local bus clock to data valid for LAD/LDP tLBKLOV2 — –0.1 ns 4

Local bus clock to address valid for LAD tLBKLOV3 —0ns4

Local bus clock to LALE assertion tLBKLOV4 —0ns4

Output hold from local bus clock (except LAD/LDP and LALE) tLBKLOX1 –3.2 — ns 4

Output hold from local bus clock for LAD/LDP tLBKLOX2 –3.2 — ns 4

Local bus clock to output high Impedance (except LAD/LDP

and LALE)

tLBKLOZ1 —0.2ns7

Local bus clock to output high impedance for LAD/LDP tLBKLOZ2 —0.2ns7

Notes:

1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus

timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case

for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect

to the output (O) going invalid (X) or output hold time.

2. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus

clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes LCLK

by tLBKHKT

3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementary signals at BVDD/2.

4. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 x BVDD of the signal

in question for 3.3-V signaling levels.

5. Input timings are measured at the pin.

6. The value of tLBOTOT is the measurement of the minimum time between the negation of LALE and any change in LAD

7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

8. Guaranteed by characterization.

Table 42. Local Bus Timing Parameters—PLL Bypassed (continued)

Parameter Symbol 1Min Max Unit Notes

LGTA

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 49

Local Bus

Figure 27. Local Bus Signals (PLL Bypass Mode)

NOTE

In PLL bypass mode, LCLK[n] is the inverted version of the internal clock

with the delay of tLBKHKT. In this mode, signals are launched at the rising edge

of the internal clock and are captured at falling edge of the internal clock,

with the exception of the LGTA/LUPWAIT signal, which is captured at the

rising edge of the internal clock.

Output Signals:

LA[27:31]/LBCTL/LBCKE/LOE/

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

tLBKLOV2

LCLK[n]

Input Signals:

LAD[0:31]/LDP[0:3]

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

LALE

tLBIXKH1

Input Signal:

LGTA

Output (Address) Signal:

LAD[0:31]

tLBIVKH1

tLBIXKL2

tLBIVKL2

tLBKLOX1

tLBKLOZ2

tLBOTOT

Internal launch/capture clock

tLBKLOX2

tLBKLOV1

tLBKLOV3

tLBKLOZ1

tLBKHKT

tLBKLOV4

LUPWAIT

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

50 Freescale Semiconductor

Local Bus

Figure 28. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (clock ratio of 4) (PLL Enabled)

LSYNC_IN

UPM Mode Input Signal:

LUPWAIT

tLBIXKH2

tLBIVKH2

tLBIVKH1

tLBIXKH1

tLBKHOZ1

Input Signals:

LAD[0:31]/LDP[0:3]

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

GPCM Mode Output Signals:

LCS[0:7]/LWE

tLBKHOV1

tLBKHOV1 tLBKHOZ1

GPCM Mode Input Signal:

LGTA

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 51

Local Bus

Figure 29. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (clock ratio of 4)

(PLL Bypass Mode)

tLBIVKH1

tLBIXKL2

Internal launch/capture clock

UPM Mode Input Signal:

LUPWAIT

Input Signals:

LAD[0:31]/LDP[0:3]

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

GPCM Mode Output Signals:

LCS[0:7]/LWE

tLBKLOV1

tLBKLOZ1

LCLK

tLBKLOX1

tLBIXKH1

GPCM Mode Input Signal:

LGTA

tLBIVKL2

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

52 Freescale Semiconductor

Local Bus

Figure 30. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 or 8 (clock ratio of 8 or 16)

(PLL Enabled)

LSYNC_IN

UPM Mode Input Signal:

LUPWAIT

tLBIXKH2

tLBIVKH2

tLBIVKH1

tLBIXKH1

tLBKHOZ1

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

GPCM Mode Output Signals:

LCS[0:7]/LWE

tLBKHOV1

tLBKHOV1 tLBKHOZ1

Input Signals:

LAD[0:31]/LDP[0:3]

GPCM Mode Input Signal:

LGTA

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 53

Local Bus

Figure 31. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 or 8 (clock ratio of 8 or 16)

(PLL Bypass Mode)

tLBIXKL2

tLBIVKH1

Internal launch/capture clock

UPM Mode Input Signal:

LUPWAIT

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

GPCM Mode Output Signals:

LCS[0:7]/LWE

Input Signals:

LAD[0:31]/LDP[0:3]

LCLK

tLBKLOV1

tLBKLOZ1

tLBKLOX1

tLBIXKH1

GPCM Mode Input Signal:

LGTA

tLBIVKL2

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

54 Freescale Semiconductor

JTAG

11 JTAG

This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of

the MPC8641/D.

11.1 JTAG DC Electrical Characteristics

Table 43 provides the DC electrical characteristics for the JTAG interface.

11.2 JTAG AC Electrical Specifications

Table 44 provides the JTAG AC timing specifications as defined in Figure 33 through Figure 35.

Table 43. JTAG DC Electrical Characteristics

Parameter Symbol Min Max Unit

High-level input voltage VIH 2OV

DD + 0.3 V

Low-level input voltage VIL – 0.3 0.8 V

Input current

(VIN 1 = 0 V or VIN = VDD)

IIN —±5 μA

High-level output voltage

(OVDD = min, IOH = –100 μA)

VOH OVDD – 0.2 — V

Low-level output voltage

(OVDD = min, IOL = 100 μA)

VOL —0.2 V

Note:

1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Tabl e 1 and Ta b l e 2 .

Table 44. JTAG AC Timing Specifications (Independent of SYSCLK) 1

At recommended operating conditions (see Ta b l e 3 ).

Parameter Symbol 2Min Max Unit Notes

JTAG external clock frequency of operation fJTG 033.3MHz—

JTAG external clock cycle time t JTG 30 — ns —

JTAG external clock pulse width measured at 1.4 V tJTKHKL 15 — ns —

JTAG external clock rise and fall times tJTGR & tJTGF 02ns6

TRST assert time tTRST 25 — ns 3

Input setup times:

Boundary-scan data

TMS, TDI

tJTDVKH

tJTIVKH

—

Input hold times:

Boundary-scan data

TMS, TDI

tJTDXKH

tJTIXKH

—

Valid times:

Boundary-scan data

TDO

tJTKLDV

tJTKLOV

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 55

JTAG

Figure 32 provides the AC test load for TDO and the boundary-scan outputs.

Figure 32. AC Test Load for the JTAG Interface

Figure 33 provides the JTAG clock input timing diagram.

Figure 33. JTAG Clock Input Timing Diagram

Output hold times:

Boundary-scan data

TDO

tJTKLDX

tJTKLOX

—

5, 6

JTAG external clock to output high impedance:

Boundary-scan data

TDO

tJTKLDZ

tJTKLOZ

5, 6

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.

The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 32).

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG

device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference

(K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input

signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock

reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

4. Non-JTAG signal input timing with respect to tTCLK.

5. Non-JTAG signal output timing with respect to tTCLK.

6. Guaranteed by design.

Table 44. JTAG AC Timing Specifications (Independent of SYSCLK) 1 (continued)

At recommended operating conditions (see Ta b l e 3 ).

Parameter Symbol 2Min Max Unit Notes

Output Z0 = 50 ΩOVDD/2

RL = 50 Ω

JTAG

tJTKHKL tJTGR

External Clock VMVMVM

tJTG tJTGF

VM = Midpoint Voltage (OVDD/2)

the TRST Input Data Valid

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

56 Freescale Semiconductor

I2C

Figure 34 provides the TRST timing diagram.

Figure 34. TRST Timing Diagram

Figure 35 provides the boundary-scan timing diagram.

Figure 35. Boundary-Scan Timing Diagram

12 I2C

This section describes the DC and AC electrical characteristics for the I2C interfaces of the MPC8641.

12.1 I2C DC Electrical Characteristics

Table 45 provides the DC electrical characteristics for the I2C interfaces.

Table 45. I2C DC Electrical Characteristics

At recommended operating conditions with OVDD of 3.3 V ± 5%.

Parameter Symbol Min Max Unit Notes

Input high voltage level VIH 0.7 × OVDD OVDD +0.3 V —

Input low voltage level VIL –0.3 0.3 × OVDD V—

Low level output voltage VOL 00.2 × OVDD V1

Pulse width of spikes which must be suppressed by

the input filter

tI2KHKL 050ns2

Input current each I/O pin (input voltage is between

0.1 × OVDD and 0.9 × OVDD(max)

II–10 10 μA3

TRST

VM = Midpoint Voltage (OVDD/2)

VM VM

tTRST

VM = Midpoint Voltage (OVDD/2)

VM VM

tJTDVKH

tJTDXKH

Boundary

Data Outputs

Boundary

Data Outputs

JTAG

External Clock

Boundary

Data Inputs

Output Data Valid

tJTKLDX

tJTKLDZ

tJTKLDV

Input

Data Valid

Output Data Valid

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 57

I2C

12.2 I2C AC Electrical Specifications

Table 46 provides the AC timing parameters for the I2C interfaces.

Capacitance for each I/O pin CI—10pF—

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. Refer to the MPC8641 Integrated Host Processor Reference Manual for information on the digital filter used.

3. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.

Table 46. I2C AC Electrical Specifications

All values refer to VIH (min) and VIL (max) levels (see Tab l e 4 5 ).

Parameter Symbol 1Min Max Unit

SCL clock frequency fI2C 0 400 kHz

Low period of the SCL clock tI2CL 4 1.3 — μs

High period of the SCL clock tI2CH 4 0.6 — μs

Setup time for a repeated START condition tI2SVKH 4 0.6 — μs

Hold time (repeated) START condition (after this period, the first

clock pulse is generated)

tI2SXKL 4 0.6 — μs

Data setup time tI2DVKH 4 100 — ns

Data input hold time:

CBUS compatible masters

I2C bus devices

tI2DXKL

—

0 2

—

—μs

Rise time of both SDA and SCL signals tI2CR 20 + 0.1 CB5300 ns

Fall time of both SDA and SCL signals tI2CF 20 + 0.1 Cb 5300 ns

Data output delay time tI2OVKL —0.9

3μs

Set-up time for STOP condition tI2PVKH 0.6 — μs

Bus free time between a STOP and START condition tI2KHDX 1.3 — μs

Noise margin at the LOW level for each connected device

(including hysteresis)

VNL 0.1 × OVDD —V

Table 45. I2C DC Electrical Characteristics (continued)

At recommended operating conditions with OVDD of 3.3 V ± 5%.

Parameter Symbol Min Max Unit Notes

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

58 Freescale Semiconductor

I2C

Figure 32 provides the AC test load for the I2C.

Figure 36. I2C AC Test Load

Noise margin at the HIGH level for each connected device

(including hysteresis)

VNH 0.2 × OVDD —V

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing

(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the

high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition

(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C

timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock

reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2. As a transmitter, the MPC8641 provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL

signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition.

When MPC8641 acts as the I2C bus master while transmitting, MPC8641 drives both SCL and SDA. As long as the load on

SCL and SDA are balanced, MPC8641 would not cause unintended generation of Start or Stop condition. Therefore, the 300

ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for

MPC8641 as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure both the

desired I2C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I2C SCL clock frequency

is 400 KHz and the Digital Filter Sampling Rate Register (I2CDFSRR) is programmed with its default setting of 0x10 (decimal

16):

I2C Source Clock Frequency 333 MHz 266 MHz 200 MHz 133 MHz

FDR Bit Setting 0x2A 0x05 0x26 0x00

Actual FDR Divider Selected 896 704 512 384

Actual I2C SCL Frequency Generated 371 KHz 378 KHz 390 KHz 346 KHz

For the detail of I2C frequency calculation, refer to the application note AN2919 “Determining the I2C Frequency Divider Ratio

for SCL”. Note that the I2C Source Clock Frequency is half of the MPX clock frequency for MPC8641.

3. The maximum tI2DXKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.

4. Guaranteed by design.

5. CB = capacitance of one bus line in pF.

Table 46. I2C AC Electrical Specifications (continued)

All values refer to VIH (min) and VIL (max) levels (see Tab l e 4 5 ).

Parameter Symbol 1Min Max Unit

Output Z0 = 50 ΩOVDD/2

RL = 50 Ω

and SDniTX SDniRX SDniTX SDniRX VSDan

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 59

High-Speed Serial Interfaces (HSSI)

Figure 37 shows the AC timing diagram for the I2C bus.

Figure 37. I2C Bus AC Timing Diagram

13 High-Speed Serial Interfaces (HSSI)

The MPC8641D features two Serializer/Deserializer (SerDes) interfaces to be used for high-speed serial

interconnect applications. The SerDes1 interface is dedicated for PCI Express data transfers. The SerDes2

can be used for PCI Express and/or Serial RapidIO data transfers.

This section describes the common portion of SerDes DC electrical specifications, which is the DC

requirement for SerDes Reference Clocks. The SerDes data lane’s transmitter and receiver reference

circuits are also shown.

13.1 Signal Terms Definition

The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms

used in the description and specification of differential signals.

Figure 38 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for

description. The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a

receiver input (SDn_RX and SDn_RX). Each signal swings between A Volts and B Volts where A > B.

Using this waveform, the definitions are as follows. To simplify illustration, the following definitions

assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling

environment.

1. Single-Ended Swing

The transmitter output signals and the receiver input signals SDn_TX, SDn_TX, SDn_RX and

SDn_RX each have a peak-to-peak swing of A – B Volts. This is also referred as each signal wire’s

Single-Ended Swing.

2. Differential Output Voltage, VOD (or Differential Output Swing):

The Differential Output Voltage (or Swing) of the transmitter, VOD, is defined as the difference of

the two complimentary output voltages: VSDn_TX – VSDn_TX. The VOD value can be either positive

or negative.

3. Differential Input Voltage, VID (or Differential Input Swing):

SrS

SDA

SCL

tI2CF

tI2SXKL

tI2CL

tI2CH

tI2DXKL

tI2DVKH

tI2SXKL

tI2SVKH

tI2KHKL

tI2PVKH

tI2CR

tI2CF

SDn7RX (SDniTX VSDniTX

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

60 Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

The Differential Input Voltage (or Swing) of the receiver, VID, is defined as the difference of the

two complimentary input voltages: VSDn_RX – VSDn_RX. The VID value can be either positive or

negative.

4. Differential Peak Voltage, VDIFFp

The peak value of the differential transmitter output signal or the differential receiver input signal

is defined as Differential Peak Voltage, VDIFFp = |A – B| Volts.

5. Differential Peak-to-Peak, VDIFFp-p

Since the differential output signal of the transmitter and the differential input signal of the receiver

each range from A – B to –(A – B) Volts, the peak-to-peak value of the differential transmitter

output signal or the differential receiver input signal is defined as Differential Peak-to-Peak

Voltage, VDIFFp-p = 2*VDIFFp = 2 * |(A – B)| Volts, which is twice of differential swing in

amplitude, or twice of the differential peak. For example, the output differential peak-peak voltage

can also be calculated as VTX-DIFFp-p = 2*|VOD|.

6. Differential Waveform

The differential waveform is constructed by subtracting the inverting signal (SDn_TX, for

example) from the non-inverting signal (SDn_TX, for example) within a differential pair. There is

only one signal trace curve in a differential waveform. The voltage represented in the differential

waveform is not referenced to ground. Refer to Figure 47 as an example for differential waveform.

7. Common Mode Voltage, Vcm

The Common Mode Voltage is equal to one half of the sum of the voltages between each conductor

of a balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out =

(VSDn_TX + VSDn_TX)/2 = (A + B) / 2, which is the arithmetic mean of the two complimentary

output voltages within a differential pair. In a system, the common mode voltage may often differ

from one component’s output to the other’s input. Sometimes, it may be even different between the

receiver input and driver output circuits within the same component. It is also referred as the DC

offset in some occasion.

Figure 38. Differential Voltage Definitions for Transmitter or Receiver

Differential Swing, VID or VOD = A - B

A Volts

B Volts

SDn_TX or

SDn_RX

SDn_TX or

SDn_RX

Differential Peak Voltage, VDIFFp = |A - B|

Differential Peak-Peak Voltage, VDIFFpp = 2*VDIFFp (not shown)

Vcm = (A + B) / 2

orﬁ SDrLREFicLK SDn7REF7CLK iREFfCLK or SDn7REF7CLK SDniREFiCLK

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 61

High-Speed Serial Interfaces (HSSI)

To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic)

transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing

that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD

or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since

the differential signaling environment is fully symmetrical, the transmitter output’s differential swing

(VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges

between 500 mV and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other

phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p)

is 1000 mV p-p.

13.2 SerDes Reference Clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by

the corresponding SerDes lanes. The SerDes reference clocks inputs are SDn_REF_CLK and

SDn_REF_CLK for PCI Express and Serial RapidIO.

The following sections describe the SerDes reference clock requirements and some application

information.

13.2.1 SerDes Reference Clock Receiver Characteristics

Figure 39 shows a receiver reference diagram of the SerDes reference clocks.

• The supply voltage requirements for XVDD_SRDSn are specified in Table 1 and Table 2.

• SerDes Reference Clock Receiver Reference Circuit Structure

— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as

shown in Figure 39. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a

50-Ω termination to SGND followed by on-chip AC-coupling.

— The external reference clock driver must be able to drive this termination.

— The SerDes reference clock input can be either differential or single-ended. Refer to the

Differential Mode and Single-ended Mode description below for further detailed requirements.

• The maximum average current requirement that also determines the common mode voltage range

— When the SerDes reference clock differential inputs are DC coupled externally with the clock

driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the

exact common mode input voltage is not critical as long as it is within the range allowed by the

maximum average current of 8 mA (refer to the following bullet for more detail), since the

input is AC-coupled on-chip.

— This current limitation sets the maximum common mode input voltage to be less than 0.4 V

(0.4 V/50 = 8 mA) while the minimum common mode input level is 0.1 V above SGND. For

example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven

by its current source from 0 mA to 16 mA (0–0.8 V), such that each phase of the differential

input has a single-ended swing from 0 V to 800 mV with the common mode voltage at 400 mV.

— If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 Ω to

SGND DC, or it exceeds the maximum input current limitations, then it must be AC-coupled

off-chip.

*X’T with SDnikEFicLK

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

62 Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

• The input amplitude requirement

— This requirement is described in detail in the following sections.

Figure 39. Receiver of SerDes Reference Clocks

13.2.2 DC Level Requirement for SerDes Reference Clocks

The DC level requirement for the MPC8641D SerDes reference clock inputs is different depending on the

signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described

below.

• Differential Mode

— The input amplitude of the differential clock must be between 400 mV and 1600 mV

differential peak-peak (or between 200 mV and 800 mV differential peak). In other words,

each signal wire of the differential pair must have a single-ended swing less than 800mV and

greater than 200 mV. This requirement is the same for both external DC-coupled or

AC-coupled connection.

— For external DC-coupled connection, as described in Section 13.2.1, “SerDes Reference

Clock Receiver Characteristics,” the maximum average current requirements sets the

requirement for average voltage (common mode voltage) to be between 100 mV and 400 mV.

Figure 40 shows the SerDes reference clock input requirement for DC-coupled connection

scheme.

— For external AC-coupled connection, there is no common mode voltage requirement for the

clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver

and the SerDes reference clock receiver operate in different command mode voltages. The

SerDes reference clock receiver in this connection scheme has its common mode voltage set to

SGND. Each signal wire of the differential inputs is allowed to swing below and above the

command mode voltage (SGND). Figure 41 shows the SerDes reference clock input

requirement for AC-coupled connection scheme.

• Single-ended Mode

— The reference clock can also be single-ended. The SDn_REF_CLK input amplitude

(single-ended swing) must be between 400 mV and 800 mV peak-peak (from Vmin to Vmax)

with SDn_REF_CLK either left unconnected or tied to ground.

Input

Amp

50 Ω

SDn_REF_CLK

or AC-coupled into the unused phase (SDnikEFicLK Vmin z 2 m m

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 63

High-Speed Serial Interfaces (HSSI)

—The SDn_REF_CLK input average voltage must be between 200 and 400 mV. Figure 42 shows

the SerDes reference clock input requirement for single-ended signaling mode.

— To meet the input amplitude requirement, the reference clock inputs might need to be DC or

AC-coupled externally. For the best noise performance, the reference of the clock could be DC

or AC-coupled into the unused phase (SDn_REF_CLK) through the same source impedance as

the clock input (SDn_REF_CLK) in use.

Figure 40. Differential Reference Clock Input DC Requirements (External DC-Coupled)

Figure 41. Differential Reference Clock Input DC Requirements (External AC-Coupled)

Figure 42. Single-Ended Reference Clock Input DC Requirements

SDn_REF_CLK

Vmax < 800 mV

Vmin > 0V

100 mV < Vcm < 400 mV

200 mV < Input Amplitude or Differential Peak < 800 mV

SDn_REF_CLK

Vcm

200 mV < Input Amplitude or Differential Peak < 800 mV

Vmax < Vcm + 400 mV

Vmin > Vcm - 400 mV

SDn_REF_CLK

400 mV < SDn_REF_CLK Input Amplitude < 800 mV

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

64 Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

13.2.3 Interfacing With Other Differential Signaling Levels

With on-chip termination to SGND, the differential reference clocks inputs are HCSL (High-Speed

Current Steering Logic) compatible DC-coupled.

Many other low voltage differential type outputs like LVDS (Low Voltage Differential Signaling) can be

used but may need to be AC-coupled due to the limited common mode input range allowed (100 to 400

mV) for DC-coupled connection.

LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock

driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to

AC-coupling.

NOTE

Figure 43 to Figure 46 below are for conceptual reference only. Due to the

fact that clock driver chip's internal structure, output impedance and

termination requirements are different between various clock driver chip

manufacturers, it is very possible that the clock circuit reference designs

provided by clock driver chip vendor are different from what is shown

below. They might also vary from one vendor to the other. Therefore,

Freescale Semiconductor can neither provide the optimal clock driver

reference circuits, nor guarantee the correctness of the following clock

driver connection reference circuits. The system designer is recommended

to contact the selected clock driver chip vendor for the optimal reference

circuits with the MPC8641D SerDes reference clock receiver requirement

provided in this document.

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 65

High-Speed Serial Interfaces (HSSI)

Figure 43 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It

assumes that the DC levels of the clock driver chip is compatible with MPC8641D SerDes reference clock

input’s DC requirement.

Figure 43. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)

Figure 44 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.

Since LVDS clock driver’s common mode voltage is higher than the MPC8641D SerDes reference clock

input’s allowed range (100 to 400 mV), AC-coupled connection scheme must be used. It assumes the

LVDS output driver features 50-Ω termination resistor. It also assumes that the LVDS transmitter

establishes its own common mode level without relying on the receiver or other external component.

Figure 44. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)

Figure 45 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.

Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with

50 Ω

SDn_REF_CLK

Clock Driver 100 Ω differential PWB trace

Clock driver vendor dependent

source termination resistor

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

HCSL CLK Driver Chip

33 Ω

Total 50 Ω. Assume clock driver’s

output impedance is about 16 Ω.

MPC8641D

CLK_Out

50 Ω

SDn_REF_CLK

Clock Driver 100 Ω differential PWB trace SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

LVDS CLK Driver Chip

10 nF

MPC8641D

\\\\\\\\\\\\\\\ r“ SDHJR \ \ \ \ \ 7 \ \ \ L \\\\\\\\\\\\\\

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

66 Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

MPC8641D SerDes reference clock input’s DC requirement, AC-coupling has to be used. Figure 45

assumes that the LVPECL clock driver’s output impedance is 50 Ω. R1 is used to DC-bias the LVPECL

outputs prior to AC-coupling. Its value could be ranged from 140 Ω to 240 Ω depending on clock driver

vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-Ω termination

resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8641D SerDes

reference clock’s differential input amplitude requirement (between 200 mV and 800 mV differential

peak). For example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference

clock input amplitude is selected as 600mV, the attenuation factor is 0.67, which requires R2 = 25 Ω.

Please consult clock driver chip manufacturer to verify whether this connection scheme is compatible with

a particular clock driver chip.

Figure 45. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)

50 Ω

SDn_REF_CLK

Clock Driver 100 Ω differential PWB trace SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

LVPECL CLK

Driver Chip

MPC8641D

10nF

riiiiiiiiiiiiw iiiiiiiii

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 67

High-Speed Serial Interfaces (HSSI)

Figure 46 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.

It assumes the DC levels of the clock driver are compatible with MPC8641D SerDes reference clock

input’s DC requirement.

Figure 46. Single-Ended Connection (Reference Only)

50 Ω

SDn_REF_CLK

100 Ω differential PWB trace SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

Single-Ended

CLK Driver Chip MPC8641D

33 Ω

Total 50 Ω. Assume clock driver’s

output impedance is about 16 Ω.

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

68 Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

13.2.4 AC Requirements for SerDes Reference Clocks

The clock driver selected should provide a high quality reference clock with low phase noise and

cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and

is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise

occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50 Ω to match the

transmission line and reduce reflections which are a source of noise to the system.

Table 47 describes some AC parameters common to PCI Express and Serial RapidIO protocols.

Figure 47. Differential Measurement Points for Rise and Fall Time

Table 47. SerDes Reference Clock Common AC Parameters

At recommended operating conditions with XVDD_SRDS1 or XVDD_SRDS2 = 1.1V ± 5% and 1.05V ± 5%.

Parameter Symbol Min Max Unit Notes

Rising Edge Rate Rise Edge Rate 1.0 4.0 V/ns 2, 3

Falling Edge Rate Fall Edge Rate 1.0 4.0 V/ns 2, 3

Differential Input High Voltage VIH +200 mV 2

Differential Input Low Voltage VIL — –200 mV 2

Rising edge rate (SDn_REF_CLK) to falling edge rate

(SDn_REF_CLK) matching

Rise-Fall

Matching

—20%1, 4

Notes:

1. Measurement taken from single ended waveform.

2. Measurement taken from differential waveform.

3. Measured from –200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The

signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered

on the differential zero crossing. See Figure 47.

4. Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a 200

mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median cross

point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate

of SDn_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed difference should not

exceed 20% of the slowest edge rate. See Figure 48.

VIH = +200 mV

VIL = –200 mV

0.0 V

SD_REF_CLKn –

SD_REF_CLKn

Fall Edge RateRise Edge Rate

TFALL TRISE x, ‘9 Vcnoss VEDIAN +10” "'V Vcnoss VEDIAN Venoss venuw " Vwoss MEDIAN ‘1”°'"V’""

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 69

PCI Express

Figure 48. Single-Ended Measurement Points for Rise and Fall Time Matching

The other detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol

based on application usage. Refer to the following sections for detailed information:

•Section 14.2, “AC Requirements for PCI Express SerDes Clocks”

•Section 15.2, “AC Requirements for Serial RapidIO SDn_REF_CLK and SDn_REF_CLK”

13.3 SerDes Transmitter and Receiver Reference Circuits

Figure 49 shows the reference circuits for SerDes data lane’s transmitter and receiver.

Figure 49. SerDes Transmitter and Receiver Reference Circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol section below

(PCI Express or Serial Rapid IO) in this document based on the application usage:”

•Section 14, “PCI Express”

•Section 15, “Serial RapidIO”

Note that external AC Coupling capacitor is required for the above two serial transmission protocols with

the capacitor value defined in specification of each protocol section.

14 PCI Express

This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8641.

SDn_REF_CLK

50 Ω

50 ΩReceiver

Transmitter

SD1_TXn or

SD2_TXn

SD1_TXn or

SD2_TXn

SD1_RXn or

SD2_RXn

SD1_RXn or

SD2_RXn

50 Ω

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

70 Freescale Semiconductor

PCI Express

14.1 DC Requirements for PCI Express SDn_REF_CLK and

SDn_REF_CLK

For more information, see Section 13.2, “SerDes Reference Clocks.”

14.2 AC Requirements for PCI Express SerDes Clocks

Table 48 lists AC requirements.

14.3 Clocking Dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)

of each other at all times. This is specified to allow bit rate clock sources with a +/– 300 ppm tolerance.

14.4 Physical Layer Specifications

The following is a summary of the specifications for the physical layer of PCI Express on this device. For

further details as well as the specifications of the Transport and Data Link layer please use the PCI

EXPRESS Base Specification. REV. 1.0a document.

14.4.1 Differential Transmitter (TX) Output

Table 49 defines the specifications for the differential output at all transmitters (TXs). The parameters are

specified at the component pins.

Table 48. SDn_REF_CLK and SDn_REF_CLK AC Requirements

Symbol Parameter Description Min Typical Max Units Notes

tREF REFCLK cycle time — 10 — ns —

tREFCJ REFCLK cycle-to-cycle jitter. Difference in the period of any two

adjacent REFCLK cycles

— — 100 ps —

tREFPJ Phase jitter. Deviation in edge location with respect to mean

edge location

–50 — 50 ps —

Table 49. Differential Transmitter (TX) Output Specifications

Symbol Parameter Min Nom Max Units Comments

UI Unit Interval 399.88 400 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not account for

Spread Spectrum Clock dictated variations. See Note

VTX-DIFFp-p Differential

Peak-to-Peak

Output Voltage

0.8 — 1.2 V VTX-DIFFp-p = 2*|VTX-D+ – VTX-D-| See Note 2.

VTX-DE-RATIO De- Emphasized

Differential

Output Voltage

(Ratio)

–3.0 –3.5 –4.0 dB Ratio of the VTX-DIFFp-p of the second and following

bits after a transition divided by the VTX-DIFFp-p of the

first bit after a transition. See Note 2.

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 71

PCI Express

TTX-EYE Minimum TX Eye

Width

0.70 — — UI The maximum Transmitter jitter can be derived as

TTX-MAX-JITTER = 1 – TTX-EYE= 0.3 UI.

See Notes 2 and 3.

TTX-EYE-MEDIAN-to-

MAX-JITTER

Maximum time

between the jitter

median and

maximum

deviation from

the median.

— — 0.15 UI Jitter is defined as the measurement variation of the

crossing points (VTX-DIFFp-p = 0 V) in relation to a

recovered TX UI. A recovered TX UI is calculated over

3500 consecutive unit intervals of sample data. Jitter

is measured using all edges of the 250 consecutive UI

in the center of the 3500 UI used for calculating the TX

UI. See Notes 2 and 3.

TTX-RISE, TTX-FALL D+/D– TX Output

Rise/Fall Time

0.125 — — UI See Notes 2 and 5

VTX-CM-ACp RMS AC Peak

Common Mode

Output Voltage

——20mVV

TX-CM-ACp = RMS(|VTXD+ + VTXD-|/2 – VTX-CM-DC)

VTX-CM-DC = DC(avg) of |VTX-D+ + VTX-D-|/2

See Note 2

VTX-CM-DC-ACTIVE-

IDLE-DELTA

Absolute Delta of

DC Common

Mode Voltage

During L0 and

Electrical Idle

0—100mV|V

TX-CM-DC (during L0) – VTX-CM-Idle-DC (During Electrical

Idle)|<=100 mV

VTX-CM-DC = DC(avg) of |VTX-D+ + VTX-D-|/2 [L0]

VTX-CM-Idle-DC = DC(avg) of |VTX-D+ + VTX-D-|/2

[Electrical Idle]

See Note 2.

VTX-CM-DC-LINE-DELTA Absolute Delta of

DC Common

Mode between

D+ and D–

0—25mV|V

TX-CM-DC-D+ – VTX-CM-DC-D-| <= 25 mV

VTX-CM-DC-D+ = DC(avg) of |VTX-D+|

VTX-CM-DC-D- = DC(avg) of |VTX-D-|

See Note 2.

VTX-IDLE-DIFFp Electrical Idle

differential Peak

Output Voltage

0—20mVV

TX-IDLE-DIFFp = |VTX-IDLE-D+ –VTX-IDLE-D-| <= 20 mV

See Note 2.

VTX-RCV-DETECT The amount of

voltage change

allowed during

Receiver

Detection

— — 600 mV The total amount of voltage change that a transmitter

can apply to sense whether a low impedance

Receiver is present. See Note 6.

VTX-DC-CM The TX DC

Common Mode

Voltage

0 — 3.6 V The allowed DC Common Mode voltage under any

conditions. See Note 6.

ITX-SHORT TX Short Circuit

Current Limit

— — 90 mA The total current the Transmitter can provide when

shorted to its ground

TTX-IDLE-MIN Minimum time

spent in

Electrical Idle

50 — — UI Minimum time a Transmitter must be in Electrical Idle

Utilized by the Receiver to start looking for an

Electrical Idle Exit after successfully receiving an

Electrical Idle ordered set

Table 49. Differential Transmitter (TX) Output Specifications (continued)

Symbol Parameter Min Nom Max Units Comments

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

72 Freescale Semiconductor

PCI Express

TTX-IDLE-SET-TO-IDLE Maximum time to

transition to a

valid Electrical

idle after sending

an Electrical Idle

ordered set

— — 20 UI After sending an Electrical Idle ordered set, the

Transmitter must meet all Electrical Idle Specifications

within this time. This is considered a debounce time

for the Transmitter to meet Electrical Idle after

transitioning from L0.

TTX-IDLE-TO-DIFF-DATA Maximum time to

transition to valid

TX specifications

after leaving an

Electrical idle

condition

— — 20 UI Maximum time to meet all TX specifications when

transitioning from Electrical Idle to sending differential

data. This is considered a debounce time for the TX to

meet all TX specifications after leaving Electrical Idle

RLTX-DIFF Differential

Return Loss

12 — — dB Measured over 50 MHz to 1.25 GHz. See Note 4

RLTX-CM Common Mode

Return Loss

6 — — dB Measured over 50 MHz to 1.25 GHz. See Note 4

ZTX-DIFF-DC DC Differential

TX Impedance

80 100 120 ΩTX DC Differential mode Low Impedance

ZTX-DC Transmitter DC

Impedance

40 — — ΩRequired TX D+ as well as D- DC Impedance during

all states

LTX-SKEW Lane-to-Lane

Output Skew

— — 500 +

2 UI

ps Static skew between any two Transmitter Lanes within

a single Link

CTX AC Coupling

Capacitor

75 — — nF All Transmitters shall be AC coupled. The AC coupling

is required either within the media or within the

transmitting component itself. See Note 8.

Tcrosslink Crosslink

Random

Timeout

0 — — ms This random timeout helps resolve conflicts in

crosslink configuration by eventually resulting in only

one Downstream and one Upstream Port. See Note 7.

Notes:

1. No test load is necessarily associated with this value.

2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 52 and measured over

any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 50)

3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the

Transmitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total

TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean.

The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed

to the averaged time value.

4. The Transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode

return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement

applies to all valid input levels. The reference impedance for return loss measurements is 50 Ω to ground for both the D+ and

D- line (that is, as measured by a Vector Network Analyzer with 50 ohm probes—see Figure 52). Note that the series

capacitors CTX is optional for the return loss measurement.

5. Measured between 20-80% at transmitter package pins into a test load as shown in Figure 52 for both VTX-D+ and VTX-D-.

6. See Section 4.3.1.8 of the PCI Express Base Specifications Rev 1.0a

7. See Section 4.2.6.3 of the PCI Express Base Specifications Rev 1.0a

8. MPC8641D SerDes transmitter does not have CTX built-in. An external AC Coupling capacitor is required.

Table 49. Differential Transmitter (TX) Output Specifications (continued)

Symbol Parameter Min Nom Max Units Comments

/—’ TX-TOTAL-MAX)

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 73

PCI Express

14.4.2 Transmitter Compliance Eye Diagrams

The TX eye diagram in Figure 50 is specified using the passive compliance/test measurement load (see

Figure 52) in place of any real PCI Express interconnect + RX component.

There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in

time using the jitter median to locate the center of the eye diagram. The different eye diagrams will differ

in voltage depending whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level

of the de-emphasized bit will always be relative to the transition bit.

The eye diagram must be valid for any 250 consecutive UIs.

A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is

created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX

UI.

NOTE

It is recommended that the recovered TX UI is calculated using all edges in

the 3500 consecutive UI interval with a fit algorithm using a minimization

merit function (that is, least squares and median deviation fits).

Figure 50. Minimum Transmitter Timing and Voltage Output Compliance Specifications

VTX-DIFF = 0 mV

(D+ D– Crossing Point)

[De-Emphasized Bit]

0.07 UI = UI – 0.3 UI (JTX-TOTAL-MAX)

566 mV (3 dB ) >=

TX-DIFFp-p-MIN

>= 505 mV (4 dB )

[Transition Bit]

TX-DIFFp-p-MIN

= 800 mV

VRX-DIFF = 0 mV

(D+ D– Crossing Point)

[Transition Bit]

TX-DIFFp-p-MIN

= 800 mV

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

74 Freescale Semiconductor

PCI Express

14.4.3 Differential Receiver (RX) Input Specifications

Table 50 defines the specifications for the differential input at all receivers (RXs). The parameters are

specified at the component pins.

Table 50. Differential Receiver (RX) Input Specifications

Symbol Parameter Min Nom Max Units Comments

UI Unit Interval 399.88 400 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not

account for Spread Spectrum Clock dictated

variations. See Note 1.

VRX-DIFFp-p Differential

Peak-to-Peak

Output Voltage

0.175 — — V VRX-DIFFp-p = 2*|VRX-D+ – VRX-D-|

See Note 2.

TRX-EYE Minimum

Receiver Eye

Width

0.4 — — UI The maximum interconnect media and

Transmitter jitter that can be tolerated by the

Receiver can be derived as TRX-MAX-JITTER =

1 – TRX-EYE= 0.6 UI.

See Notes 2 and 3.

TRX-EYE-MEDIAN-to-MAX

-JITTER

Maximum time

between the jitter

median and

maximum

deviation from

the median.

— — 0.3 UI Jitter is defined as the measurement variation

of the crossing points (VRX-DIFFp-p = 0 V) in

relation to a recovered TX UI. A recovered TX

UI is calculated over 3500 consecutive unit

intervals of sample data. Jitter is measured

using all edges of the 250 consecutive UI in

the center of the 3500 UI used for calculating

the TX UI. See Notes 2, 3 and 7.

VRX-CM-ACp AC Peak

Common Mode

Input Voltage

—— 150mVV

RX-CM-ACp = |VRXD+ – VRXD-|/2 – VRX-CM-DC

VRX-CM-DC = DC(avg) of |VRX-D+ – VRX-D-|/2

See Note 2

RLRX-DIFF Differential

Return Loss

15 — — dB Measured over 50 MHz to 1.25 GHz with the

D+ and D– lines biased at +300 mV and –300

mV, respectively.

See Note 4

RLRX-CM Common Mode

Return Loss

6 — — dB Measured over 50 MHz to 1.25 GHz with the

D+ and D– lines biased at 0 V. See Note 4

ZRX-DIFF-DC DC Differential

Input Impedance

80 100 120 ΩRX DC Differential mode impedance. See

Note 5

ZRX-DC DC Input

Impedance

40 50 60 ΩRequired RX D+ as well as D– DC

Impedance (50 ± 20% tolerance). See Notes

2 and 5.

ZRX-HIGH-IMP-DC Powered Down

DC Input

Impedance

200 k — — ΩRequired RX D+ as well as D– DC

Impedance when the Receiver terminations

do not have power. See Note 6.

VRX-IDLE-DET-DIFFp-p Electrical Idle

Detect Threshold

65 — — mV VRX-IDLE-DET-DIFFp-p = 2*|VRX-D+ –VRX-D-|

Measured at the package pins of the Receiver

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 75

PCI Express

14.5 Receiver Compliance Eye Diagrams

The RX eye diagram in Figure 51 is specified using the passive compliance/test measurement load (see

Figure 52) in place of any real PCI Express RX component.

Note: In general, the minimum Receiver eye diagram measured with the compliance/test measurement

load (see Figure 52) will be larger than the minimum Receiver eye diagram measured over a range of

systems at the input Receiver of any real PCI Express component. The degraded eye diagram at the input

Receiver is due to traces internal to the package as well as silicon parasitic characteristics which cause the

real PCI Express component to vary in impedance from the compliance/test measurement load. The input

Receiver eye diagram is implementation specific and is not specified. RX component designer should

TRX-IDLE-DET-DIFF-

ENTERTIME

Unexpected

Electrical Idle

Enter Detect

Threshold

Integration Time

— — 10 ms An unexpected Electrical Idle (VRX-DIFFp-p <

VRX-IDLE-DET-DIFFp-p) must be recognized no

longer than TRX-IDLE-DET-DIFF-ENTERING to

signal an unexpected idle condition.

LTX-SKEW Total Skew — — 20 ns Skew across all lanes on a Link. This includes

variation in the length of SKP ordered set (for

example, COM and one to five Symbols) at

the RX as well as any delay differences

arising from the interconnect itself.

Notes:

1. No test load is necessarily associated with this value.

2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 52 should be used as

the RX device when taking measurements (also refer to the Receiver compliance eye diagram shown in Figure 51). If the clocks

to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used

as a reference for the eye diagram.

3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and

interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in

which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any

250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point

in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the

clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must

be used as the reference for the eye diagram.

4. The Receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to

300 mV and the D- line biased to -300 mV and a common mode return loss greater than or equal to 6 dB (no bias required)

over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference

impedance for return loss measurements for is 50 Ω to ground for both the D+ and D- line (that is, as measured by a Vector

Network Analyzer with 50 ohm probes - see Figure 52). Note: that the series capacitors CTX is optional for the return loss

measurement.

5. Impedance during all LTSSM states. When transitioning from a Fundamental Reset to Detect (the initial state of the LTSSM)

there is a 5 ms transition time before Receiver termination values must be met on all un-configured Lanes of a Port.

6. The RX DC Common Mode Impedance that exists when no power is present or Fundamental Reset is asserted. This helps

ensure that the Receiver Detect circuit will not falsely assume a Receiver is powered on when it is not. This term must be

measured at 300 mV above the RX ground.

7. It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm

using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated

data.

Table 50. Differential Receiver (RX) Input Specifications (continued)

Symbol Parameter Min Nom Max Units Comments

Crossing Point) (D+ D— Crossin

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

76 Freescale Semiconductor

PCI Express

provide additional margin to adequately compensate for the degraded minimum Receiver eye diagram

(shown in Figure 51) expected at the input Receiver based on some adequate combination of system

simulations and the Return Loss measured looking into the RX package and silicon. The RX eye diagram

must be aligned in time using the jitter median to locate the center of the eye diagram.

The eye diagram must be valid for any 250 consecutive UIs.

A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is

created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX

UI.

NOTE

The reference impedance for return loss measurements is 50Ω to ground for

both the D+ and D- line (that is, as measured by a Vector Network Analyzer

with 50Ω probes—see Figure 52). Note that the series capacitors, CTX, are

optional for the return loss measurement.

Figure 51. Minimum Receiver Eye Timing and Voltage Compliance Specification

14.5.1 Compliance Test and Measurement Load

The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2

inches of the package pins, into a test/measurement load shown in Figure 52.

NOTE

The allowance of the measurement point to be within 0.2 inches of the

package pins is meant to acknowledge that package/board routing may

benefit from D+ and D– not being exactly matched in length at the package

pin boundary.

VRX-DIFF = 0 mV

(D+ D– Crossing Point)

VRX-DIFF = 0 mV

(D+ D– Crossing Point)

RX-DIFFp-p-MIN

> 175 mV

0.4 UI = TRX-EYE-MIN

\\\\\\\\\

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 77

Serial RapidIO

Figure 52. Compliance Test/Measurement Load

15 Serial RapidIO

This section describes the DC and AC electrical specifications for the RapidIO interface of the MPC8641,

for the LP-Serial physical layer. The electrical specifications cover both single and multiple-lane links.

Two transmitter types (short run and long run) on a single receiver are specified for each of three baud

rates, 1.25, 2.50, and 3.125 GBaud.

Two transmitter specifications allow for solutions ranging from simple board-to-board interconnect to

driving two connectors across a backplane. A single receiver specification is given that will accept signals

from both the short run and long run transmitter specifications.

The short run transmitter specifications should be used mainly for chip-to-chip connections on either the

same printed circuit board or across a single connector. This covers the case where connections are made

to a mezzanine (daughter) card. The minimum swings of the short run specification reduce the overall

power used by the transceivers.

The long run transmitter specifications use larger voltage swings that are capable of driving signals across

backplanes. This allows a user to drive signals across two connectors and a backplane. The specifications

allow a distance of at least 50 cm at all baud rates.

All unit intervals are specified with a tolerance of +/– 100 ppm. The worst case frequency difference

between any transmit and receive clock will be 200 ppm.

To ensure interoperability between drivers and receivers of different vendors and technologies, AC

coupling at the receiver input must be used.

15.1 DC Requirements for Serial RapidIO SDn_REF_CLK and

SDn_REF_CLK

For more information, see Section 13.2, “SerDes Reference Clocks.”

15.2 AC Requirements for Serial RapidIO SDn_REF_CLK and

SDn_REF_CLK

Table 51 lists AC requirements.

Silicon

+ Package

C = CTX

R = 50 ΩR = 50 Ω

D+ Package

D– Package

D+ Package

andﬁ E

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

78 Freescale Semiconductor

Serial RapidIO

15.3 Signal Definitions

LP-Serial links use differential signaling. This section defines terms used in the description and

specification of differential signals. Figure 53 shows how the signals are defined. The figures show

waveforms for either a transmitter output (TD and TD) or a receiver input (RD and RD). Each signal

swings between A Volts and B Volts where A > B. Using these waveforms, the definitions are as follows:

1. The transmitter output signals and the receiver input signals TD, TD, RD and RD each have a

peak-to-peak swing of A – B Volts

2. The differential output signal of the transmitter, VOD, is defined as VTD–VTD

3. The differential input signal of the receiver, VID, is defined as VRD–VRD

4. The differential output signal of the transmitter and the differential input signal of the receiver

each range from A – B to –(A – B) Volts

5. The peak value of the differential transmitter output signal and the differential receiver input

signal is A – B Volts

6. The peak-to-peak value of the differential transmitter output signal and the differential receiver

input signal is 2 * (A – B) Volts

Figure 53. Differential Peak-Peak Voltage of Transmitter or Receiver

To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic)

transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing

that goes between 2.5V and 2.0V. Using these values, the peak-to-peak voltage swing of the signals TD

and TD is 500 mV p-p. The differential output signal ranges between 500 mV and –500 mV. The peak

differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mV p-p.

Table 51. SDn_REF_CLK and SDn_REF_CLK AC Requirements

Symbol Parameter Description Min Typical Max Units Comments

tREF REFCLK cycle time — 10(8) — ns 8 ns applies only to serial RapidIO

with 125-MHz reference clock

tREFCJ REFCLK cycle-to-cycle jitter. Difference in the

period of any two adjacent REFCLK cycles

——80ps —

tREFPJ Phase jitter. Deviation in edge location with

respect to mean edge location

–40 — 40 ps —

Differential Peak-Peak = 2 * (A-B)

A Volts TD or RD

TD or RD

B Volts

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 79

Serial RapidIO

15.4 Equalization

With the use of high speed serial links, the interconnect media will cause degradation of the signal at the

receiver. Effects such as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss

can be large enough to degrade the eye opening at the receiver beyond what is allowed in the specification.

To negate a portion of these effects, equalization can be used. The most common equalization techniques

that can be used are:

• A passive high pass filter network placed at the receiver. This is often referred to as passive

equalization.

• The use of active circuits in the receiver. This is often referred to as adaptive equalization.

15.5 Explanatory Note on Transmitter and Receiver Specifications

AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at

three baud rates (a total of six cases) are described.

The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified

in Clause 47 of IEEE 802.3ae-2002.

XAUI has similar application goals to serial RapidIO, as described in Section 8.1. The goal of this standard

is that electrical designs for serial RapidIO can reuse electrical designs for XAUI, suitably modified for

applications at the baud intervals and reaches described herein.

15.6 Transmitter Specifications

LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section.

The differential return loss, S11, of the transmitter in each case shall be better than

• –10 dB for (Baud Frequency)/10 < Freq(f) < 625 MHz, and

• –10 dB + 10log(f/625 MHz) dB for 625 MHz ≤ Freq(f) ≤ Baud Frequency

The reference impedance for the differential return loss measurements is 100 Ohm resistive. Differential

return loss includes contributions from on-chip circuitry, chip packaging and any off-chip components

related to the driver. The output impedance requirement applies to all valid output levels.

It is recommended that the 20%–80% rise/fall time of the transmitter, as measured at the transmitter output,

in each case have a minimum value 60 ps.

It is recommended that the timing skew at the output of an LP-Serial transmitter between the two signals

that comprise a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50 GB and 15 ps at 3.125 GB.

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

80 Freescale Semiconductor

Serial RapidIO

Table 52. Short Run Transmitter AC Timing Specifications—1.25 GBaud

Characteristic Symbol

Range

Unit Notes

Min Max

Output Voltage, VO–0.40 2.30 Volts Voltage relative to COMMON

of either signal comprising a

differential pair

Differential Output Voltage VDIFFPP 500 1000 mV p-p —

Deterministic Jitter JD— 0.17 UI p-p —

Total Jitter JT— 0.35 UI p-p —

Multiple output skew SMO — 1000 ps Skew at the transmitter output

between lanes of a multilane

link

Unit Interval UI 800 800 ps +/– 100 ppm

Table 53. Short Run Transmitter AC Timing Specifications—2.5 GBaud

Characteristic Symbol

Range

Unit Notes

Min Max

Output Voltage, VO–0.40 2.30 Volts Voltage relative to COMMON

of either signal comprising a

differential pair

Differential Output Voltage VDIFFPP 500 1000 mV p-p —

Deterministic Jitter JD— 0.17 UI p-p —

Total Jitter JT— 0.35 UI p-p —

Multiple Output skew SMO — 1000 ps Skew at the transmitter output

between lanes of a multilane

link

Unit Interval UI 400 400 ps +/– 100 ppm

Table 54. Short Run Transmitter AC Timing Specifications—3.125 GBaud

Characteristic Symbol

Range

Unit Notes

Min Max

Output Voltage, VO–0.40 2.30 Volts Voltage relative to COMMON

of either signal comprising a

differential pair

Differential Output Voltage VDIFFPP 500 1000 mV p-p —

Deterministic Jitter JD— 0.17 UI p-p —

Total Jitter JT— 0.35 UI p-p —

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 81

Serial RapidIO

Multiple output skew SMO — 1000 ps Skew at the transmitter output

between lanes of a multilane

link

Unit Interval UI 320 320 ps +/– 100 ppm

Table 55. Long Run Transmitter AC Timing Specifications—1.25 GBaud

Characteristic Symbol

Range

Unit Notes

Min Max

Output Voltage, VO–0.40 2.30 Volts Voltage relative to COMMON

of either signal comprising a

differential pair

Differential Output Voltage VDIFFPP 800 1600 mV p-p —

Deterministic Jitter JD— 0.17 UI p-p —

Total Jitter JT— 0.35 UI p-p —

Multiple output skew SMO — 1000 ps Skew at the transmitter output

between lanes of a multilane

link

Unit Interval UI 800 800 ps +/– 100 ppm

Table 56. Long Run Transmitter AC Timing Specifications—2.5 GBaud

Characteristic Symbol

Range

Unit Notes

Min Max

Output Voltage, VO–0.40 2.30 Volts Voltage relative to COMMON

of either signal comprising a

differential pair

Differential Output Voltage VDIFFPP 800 1600 mV p-p —

Deterministic Jitter JD— 0.17 UI p-p —

Total Jitter JT— 0.35 UI p-p —

Multiple output skew SMO — 1000 ps Skew at the transmitter output

between lanes of a multilane

link

Unit Interval UI 400 400 ps +/– 100 ppm

Table 54. Short Run Transmitter AC Timing Specifications—3.125 GBaud (continued)

Characteristic Symbol

Range

Unit Notes

Min Max

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

82 Freescale Semiconductor

Serial RapidIO

For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the

transmitter shall fall entirely within the unshaded portion of the Transmitter Output Compliance Mask

shown in Figure 54 with the parameters specified in Table 58 when measured at the output pins of the

device and the device is driving a 100 Ω +/–5% differential resistive load. The output eye pattern of an

LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol

interference) need only comply with the Transmitter Output Compliance Mask when pre-emphasis is

disabled or minimized.

Figure 54. Transmitter Output Compliance Mask

Table 57. Long Run Transmitter AC Timing Specifications—3.125 GBaud

Characteristic Symbol

Range

Unit Notes

Min Max

Output Voltage, VO–0.40 2.30 Volts Voltage relative to COMMON

of either signal comprising a

differential pair

Differential Output Voltage VDIFFPP 800 1600 mV p-p —

Deterministic Jitter JD— 0.17 UI p-p —

Total Jitter JT— 0.35 UI p-p —

Multiple output skew SMO — 1000 ps Skew at the transmitter output

between lanes of a multilane

link

Unit Interval UI 320 320 ps +/– 100 ppm

VDIFF min

VDIFF max

-VDIFF min

-VDIFF max

0B1-B1

Time in UI

Transmitter Differential Output Voltage

A1-A

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 83

Serial RapidIO

15.7 Receiver Specifications

LP-Serial receiver electrical and timing specifications are stated in the text and tables of this section.

Receiver input impedance shall result in a differential return loss better that 10 dB and a common mode

return loss better than 6 dB from 100 MHz to (0.8)*(Baud Frequency). This includes contributions from

on-chip circuitry, the chip package and any off-chip components related to the receiver. AC coupling

components are included in this requirement. The reference impedance for return loss measurements is

100 Ohm resistive for differential return loss and 25 Ohm resistive for common mode.

Table 58. Transmitter Differential Output Eye Diagram Parameters

Transmitter Type VDIFFmin

(mV)

VDIFFmax

(mV) A (UI) B (UI)

1.25 GBaud short range 250 500 0.175 0.39

1.25 GBaud long range 400 800 0.175 0.39

2.5 GBaud short range 250 500 0.175 0.39

2.5 GBaud long range 400 800 0.175 0.39

3.125 GBaud short range 250 500 0.175 0.39

3.125 GBaud long range 400 800 0.175 0.39

Table 59. Receiver AC Timing Specifications—1.25 GBaud

Characteristic Symbol

Range

Unit Notes

Min Max

Differential Input Voltage VIN 200 1600 mV p-p Measured at receiver

Deterministic Jitter Tolerance JD0.37 — UI p-p Measured at receiver

Combined Deterministic and Random

Jitter Tolerance

JDR 0.55 — UI p-p Measured at receiver

Total Jitter Tolerance1JT0.65 — UI p-p Measured at receiver

Multiple Input Skew SMI — 24 ns Skew at the receiver input

between lanes of a multilane

link

Bit Error Rate BER — 10–12 ——

Unit Interval UI 800 800 ps +/– 100 ppm

Note:

1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 55. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

84 Freescale Semiconductor

Serial RapidIO

Table 60. Receiver AC Timing Specifications—2.5 GBaud

Characteristic Symbol

Range

Unit Notes

Min Max

Differential Input Voltage VIN 200 1600 mV p-p Measured at receiver

Deterministic Jitter Tolerance JD0.37 — UI p-p Measured at receiver

Combined Deterministic and Random

Jitter Tolerance

JDR 0.55 — UI p-p Measured at receiver

Total Jitter Tolerance1JT0.65 — UI p-p Measured at receiver

Multiple Input Skew SMI — 24 ns Skew at the receiver input

between lanes of a multilane

link

Bit Error Rate BER — 10–12 ——

Unit Interval UI 400 400 ps +/– 100 ppm

Note:

1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 55. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

Table 61. Receiver AC Timing Specifications—3.125 GBaud

Characteristic Symbol

Range

Unit Notes

Min Max

Differential Input Voltage VIN 200 1600 mV p-p Measured at receiver

Deterministic Jitter Tolerance JD0.37 — UI p-p Measured at receiver

Combined Deterministic and Random

Jitter Tolerance

JDR 0.55 — UI p-p Measured at receiver

Total Jitter Tolerance1JT0.65 — UI p-p Measured at receiver

Multiple Input Skew SMI — 22 ns Skew at the receiver input

between lanes of a multilane

link

Bit Error Rate BER — 10-12 ——

Unit Interval UI 320 320 ps +/– 100 ppm

Note:

1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 55. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 85

Serial RapidIO

Figure 55. Single Frequency Sinusoidal Jitter Limits

15.8 Receiver Eye Diagrams

For each baud rate at which an LP-Serial receiver is specified to operate, the receiver shall meet the

corresponding Bit Error Rate specification (Table 59, Table 60, Table 61) when the eye pattern of the

receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the Receiver

Input Compliance Mask shown in Figure 56 with the parameters specified in Table . The eye pattern of the

receiver test signal is measured at the input pins of the receiving device with the device replaced with a

100 Ω +/– 5% differential resistive load.

8.5 UI p-p

0.10 UI p-p

Sinusoidal

Jitter

Amplitude

22.1 kHz 1.875 MHz 20 MHz

Frequency

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

86 Freescale Semiconductor

Serial RapidIO

Figure 56. Receiver Input Compliance Mask

15.9 Measurement and Test Requirements

Since the LP-Serial electrical specification are guided by the XAUI electrical interface specified in Clause

47 of IEEE 802.3ae-2002, the measurement and test requirements defined here are similarly guided by

Clause 47. In addition, the CJPAT test pattern defined in Annex 48A of IEEE 802.3ae-2002 is specified as

the test pattern for use in eye pattern and jitter measurements. Annex 48B of IEEE 802.3ae-2002 is

recommended as a reference for additional information on jitter test methods.

15.9.1 Eye Template Measurements

For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point

at (Baud Frequency)/1667 is applied to the jitter. The data pattern for template measurements is the

Table 62. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter

Receiver Type VDIFFmin (mV) VDIFFmax (mV) A (UI) B (UI)

1.25 GBaud 100 800 0.275 0.400

2.5 GBaud 100 800 0.275 0.400

3.125 GBaud 100 800 0.275 0.400

VDIFF max

-VDIFF max

VDIFF min

-VDIFF min

Time (UI)

Receiver Differential Input Voltage

AB 1-B1-A

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 87

Serial RapidIO

Continuous Jitter Test Pattern (CJPAT) defined in Annex 48A of IEEE 802.3ae. All lanes of the LP-Serial

link shall be active in both the transmit and receive directions, and opposite ends of the links shall use

asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane

implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. The

amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10-12.

The eye pattern shall be measured with AC coupling and the compliance template centered at 0 Volts

differential. The left and right edges of the template shall be aligned with the mean zero crossing points of

the measured data eye. The load for this test shall be 100 Ω resistive +/– 5% differential to 2.5 GHz.

15.9.2 Jitter Test Measurements

For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (Baud

Frequency)/1667 is applied to the jitter. The data pattern for jitter measurements is the Continuous Jitter

Test Pattern (CJPAT) pattern defined in Annex 48A of IEEE 802.3ae. All lanes of the LP-Serial link shall

be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous

clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane implementations

shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be measured

with AC coupling and at 0 Volts differential. Jitter measurement for the transmitter (or for calibration of a

jitter tolerance setup) shall be performed with a test procedure resulting in a BER curve such as that

described in Annex 48B of IEEE 802.3ae.

15.9.3 Transmit Jitter

Transmit jitter is measured at the driver output when terminated into a load of 100 Ω resistive +/– 5%

differential to 2.5 GHz.

15.9.4 Jitter Tolerance

Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first

producing the sum of deterministic and random jitter defined in Section 8.6 and then adjusting the signal

amplitude until the data eye contacts the 6 points of the minimum eye opening of the receive template

shown in Figure 8-4 and Table 8-11. Note that for this to occur, the test signal must have vertical waveform

symmetry about the average value and have horizontal symmetry (including jitter) about the mean zero

crossing. Eye template measurement requirements are as defined above. Random jitter is calibrated using

a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade roll-off below this. The

required sinusoidal jitter specified in Section 8.6 is then added to the signal and the test load is replaced

by the receiver being tested.

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

88 Freescale Semiconductor

Package

16 Package

This section details package parameters and dimensions.

16.1 Package Parameters for the MPC8641

The package parameters are as provided in the following list. The package type is 33 mm × 33 mm, 1023

pins. There are two package options: high-lead Flip Chip-Ceramic Ball Grid Array (FC-CBGA), and

lead-free (FC-CBGA).

For all package types:

Die size 12.1 mm × 14.7 mm

Package outline 33 mm × 33 mm

Interconnects 1023

Pitch 1 mm

Total Capacitor count 43 caps; 100 nF each

For high-lead FC-CBGA (package option: HCTE1 HX)

Maximum module height 2.97 mm

Minimum module height 2.47 mm

Solder Balls 89.5% Pb 10.5% Sn

Ball diameter (typical2) 0.60 mm

For RoHS lead-free FC-CBGA (package option: HCTE1 VU) and lead-free FC-CBGA (package option:

HCTE1 VJ)

Maximum module height 2.77 mm

Minimum module height 2.27 mm

Solder Balls 95.5% Sn 4.0% Ag 0.5% Cu

Ball diameter (typical2) 0.60 mm

1 High-coefficient of thermal expansion

2 Typical ball diameter is before reflow

ama- m INDEX SEATING PLANE 7 72’) W 4X CAP ZONES 2x 107 W 2x 7.855 W .x H w 2x 905 W — TOP V‘EW as 5 09 a g u a: . , “075 : 4x 0 55 : a 5 mx . __ ‘ : Y32 297 m AI some»! my BOTTOM VIEW S‘DE V‘EW

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 89

Package

16.2 Mechanical Dimensions of the MPC8641 FC-CBGA

The mechanical dimensions and bottom surface nomenclature of the MPC8641D (dual core) and

MPC8641 (single core) high-lead FC-CBGA (package option: HCTE HX) and lead-free FC-CBGA

(package option: HCTE VU) are shown respectfully in Figure 57 and Figure 58.

Figure 57. MPC8641D High-Head FC-CBGA Dimensions

NOTES for Figure 57

1. All dimensions are in millimeters.

2. Dimensions and tolerances per ASME Y14.5M-1994.

3. Maximum solder ball diameter measured parallel to datum A.

4. Datum A, the seating plane, is defined by the spherical crowns of the solder balls.

5. Capacitors may not be present on all devices.

6. Caution must be taken not to short capacitors or expose metal capacitor pads on package top.

7. All dimensions symmetrical about centerlines unless otherwise specified.

E 1025XE- us 0 2X 9 as MAX y ﬂv—I 1 510.3» l‘ * -777 7.395 MAX SEA'HNG/ PLANE / l A A A g M wuzx IJ 1 7‘; CAP ZONES \i— 3 . __ _' __ 7 / i 3 7 725 MAX V l ! 7X 575 MAX I 33 E3 * 7 X 7 ~ L + f H 9 . 7725 W 2X 565 MIN 1 F 3 ¢ 7 ‘ a _____ ___._ _ ____9_ 2X H MAX ; 4X5 3 —. 2X ‘4 MAX r.— 3 [Q a 2x 10 7 MIN \e : TOP VIEW . (3‘) 3 3l)( ‘ j m _ fin L . tG : i“: E 3 AC ‘5“ 9 v v" : r (it) : D I ~ u " 3 x5 L j u L : r i . :C ’ 832* z 055 A 0,65 ‘ “ "u 35 ‘ 3 5 7 a u u va w z 212527 29 m “‘02“ a .55 4X 06f-‘—‘_L32 24sswwuwuamzzzozﬁuwu$¢g4®ABM MAX mo BOTTOM VIEW ¢ 02® A 2-77 W’ * S‘DE VIE

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

90 Freescale Semiconductor

Package

8. Note that for MPC8641 (single core) the solder balls for the following signals/pins are not populated in the package:

VDD_Core1 (R16, R18, R20, T17, T19, T21, T23, U16, U18, U22, V17, V19, V21, V23, W16, W18, W20, W22, Y17,

Y19, Y21, Y23, AA16, AA18, AA20, AA22, AB23, AC24) and SENSEVDD_Core1 (U20).

Figure 58. MPC8641D Lead-Free FC-CBGA Dimensions

NOTES for Figure 58

1. All dimensions are in millimeters.

2. Dimensions and tolerances per ASME Y14.5M-1994.

3. Maximum solder ball diameter measured parallel to datum A.

4. Datum A, the seating plane, is defined by the spherical crowns of the solder balls.

5. Capacitors may not be present on all devices.

6. Caution must be taken not to short capacitors or expose metal capacitor pads on package top.

7. All dimensions symmetrical about centerlines unless otherwise specified.

8. Note that for MPC8641 (single core) the solder balls for the following signals/pins are not populated in the package:

VDD_Core1 (R16, R18, R20, T17, T19, T21, T23, U16, U18, U22, V17, V19, V21, V23, W16, W18, W20, W22, Y17,

Y19, Y21, Y23, AA16, AA18, AA20, AA22, AB23, AC24) and SENSEVDD_Core1 (U20).

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 91

Signal Listings

17 Signal Listings

Table 63 provides the pin assignments for the signals. Notes for the signal changes on the single core

device (MPC8641) are italicized and prefixed by “S”.

Table 63. MPC8641 Signal Reference by Functional Block

Name1Package Pin Number Pin Type Power Supply Notes

DDR Memory Interface 1 Signals2,3

D1_MDQ[0:63] D15, A14, B12, D12, A15, B15, B13, C13,

C11, D11, D9, A8, A12, A11, A9, B9, F11,

G12, K11, K12, E10, E9, J11, J10, G8, H10,

L9, L7, F10, G9, K9, K8, AC6, AC7, AG8,

AH9, AB6, AB8, AE9, AF9, AL8, AM8,

AM10, AK11, AH8, AK8, AJ10, AK10, AL12,

AJ12, AL14, AM14, AL11, AM11, AM13,

AK14, AM15, AJ16, AK18, AL18, AJ15,

AL15, AL17, AM17

I/O D1_GVDD —

D1_MECC[0:7] M8, M7, R8, T10, L11, L10, P9, R10 I/O D1_GVDD —

D1_MDM[0:8] C14, A10, G11, H9, AD7, AJ9, AM12, AK16,

N10

OD1_GV

DD —

D1_MDQS[0:8] A13, C10, H12, J7, AE8, AM9, AK13, AK17,

I/O D1_GVDD —

D1_MDQS[0:8] D14, B10, H13, J8, AD8, AL9, AJ13, AM16,

P10

I/O D1_GVDD —

D1_MBA[0:2] AA8, AA10, T9 O D1_GVDD —

D1_MA[0:15] Y10, W8, W9, V7, V8, U6, V10, U9, U7, U10,

Y9, T6, T8, AE12, R7, P6

OD1_GV

DD —

D1_MWE AB11 O D1_GVDD —

D1_MRAS AB12 O D1_GVDD —

D1_MCAS AC10 O D1_GVDD —

D1_MCS[0:3] AB9, AD10, AC12, AD11 O D1_GVDD —

D1_MCKE[0:3] P7, M10, N8, M11 O D1_GVDD 23

D1_MCK[0:5] W6, E13, AH11, Y7, F14, AG10 O D1_GVDD —

D1_MCK[0:5] Y6, E12, AH12, AA7, F13, AG11 O D1_GVDD —

D1_MODT[0:3] AC9, AF12, AE11, AF10 O D1_GVDD —

D1_MDIC[0:1] E15, G14 IO D1_GVDD 27

D1_MVREF AM18 DDR Port 1

reference

voltage

D1_GVDD /2 3

DDR Memory Interface 2 Signals2,3

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

92 Freescale Semiconductor

Signal Listings

D2_MDQ[0:63] A7, B7, C5, D5, C8, D8, D6, A5, C4, A3, D3,

D2, A4, B4, C2, C1, E3, E1, H4, G1, D1, E4,

G3, G2, J4, J2, L1, L3, H3, H1, K1, L4, AA4,

AA2, AD1, AD2, Y1, AA1, AC1, AC3, AD5,

AE1, AG1, AG2, AC4, AD4, AF3, AF4, AH3,

AJ1, AM1, AM3, AH1, AH2, AL2, AL3, AK5,

AL5, AK7, AM7, AK4, AM4, AM6, AJ7

I/O D2_GVDD —

D2_MECC[0:7] H6, J5, M5, M4, G6, H7, M2, M1 I/O D2_GVDD —

D2_MDM[0:8] C7, B3, F4, J1, AB1, AE2, AK1, AM5, K6 O D2_GVDD —

D2_MDQS[0:8] B6, B1, F1, K2, AB3, AF1, AL1, AL6, L6 I/O D2_GVDD —

D2_MDQS[0:8] A6, A2, F2, K3, AB2, AE3, AK2, AJ6, K5 I/O D2_GVDD —

D2_MBA[0:2] W5, V5, P3 O D2_GVDD —

D2_MA[0:15] W1, U4, U3, T1, T2, T3, T5, R2, R1, R5, V4,

R4, P1, AH5, P4, N1

OD2_GV

DD —

D2_MWE Y4 O D2_GVDD —

D2_MRAS W3 O D2_GVDD —

D2_MCAS AB5 O D2_GVDD —

D2_MCS[0:3] Y3, AF6, AA5, AF7 O D2_GVDD —

D2_MCKE[0:3] N6, N5, N2, N3 O D2_GVDD 23

D2_MCK[0:5] U1, F5, AJ3, V2, E7, AG4 O D2_GVDD —

D2_MCK[0:5] V1, G5, AJ4, W2, E6, AG5 O D2_GVDD —

D2_MODT[0:3] AE6, AG7, AE5, AH6 O D2_GVDD —

D2_MDIC[0:1] F8, F7 IO D2_GVDD 27

D2_MVREF A18 DDR Port 2

reference

voltage

D2_GVDD /2 3

High Speed I/O Interface 1 (SERDES 1)4

SD1_TX[0:7] L26, M24, N26, P24, R26, T24, U26, V24 O SVDD —

SD1_TX[0:7] L27, M25, N27, P25, R27, T25, U27, V25 O SVDD —

SD1_RX[0:7] J32, K30, L32, M30, T30, U32, V30, W32 I SVDD —

SD1_RX[0:7] J31, K29, L31, M29, T29, U31, V29, W31 I SVDD —

SD1_REF_CLK N32 I SVDD —

SD1_REF_CLK N31 I SVDD —

SD1_IMP_CAL_TX Y26 Analog SVDD 19

SD1_IMP_CAL_RX J28 Analog SVDD 30

SD1_PLL_TPD U28 O SVDD 13, 17

Table 63. MPC8641 Signal Reference by Functional Block (continued)

Name1Package Pin Number Pin Type Power Supply Notes

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 93

Signal Listings

SD1_PLL_TPA T28 Analog SVDD 13, 18

SD1_DLL_TPD N28 O SVDD 13, 17

SD1_DLL_TPA P31 Analog SVDD 13, 18

High Speed I/O Interface 2 (SERDES 2)4

SD2_TX[0:3] Y24, AA27, AB25, AC27 O SVDD —

SD2_TX[4:7] AE27, AG27, AJ27, AL27 O SVDD 34

SD2_TX[0:3] Y25, AA28, AB26, AC28 O SVDD —

SD2_TX[4:7] AE28, AG28, AJ28, AL28 O SVDD 34

SD2_RX[0:3] Y30, AA32, AB30, AC32 I SVDD 32

SD2_RX[4:7] AH30, AJ32, AK30, AL32 I SVDD 32, 35

SD2_RX[0:3] Y29, AA31, AB29, AC31 I SVDD —

SD2_RX[4:7] AH29, AJ31, AK29, AL31 I SVDD 35

SD2_REF_CLK AE32 I SVDD —

SD2_REF_CLK AE31 I SVDD —

SD2_IMP_CAL_TX AM29 Analog SVDD 19

SD2_IMP_CAL_RX AA26 Analog SVDD 30

SD2_PLL_TPD AF29 O SVDD 13, 17

SD2_PLL_TPA AF31 Analog SVDD 13, 18

SD2_DLL_TPD AD29 O SVDD 13, 17

SD2_DLL_TPA AD30 Analog SVDD 13, 18

Special Connection Requirement pins

No Connects K24, K25, P28, P29, W26, W27, AD25,

AD26

—— 13

Reserved H30, R32, V28, AG32 — — 14

Reserved H29, R31, W28, AG31 — — 15

Reserved AD24, AG26 — — 16

Ethernet Miscellaneous Signals5

EC1_GTX_CLK125 AL23 I LVDD 39

EC2_GTX_CLK125 AM23 I TVDD 39

EC_MDC G31 O OVDD —

EC_MDIO G32 I/O OVDD —

eTSEC Port 1 Signals5

Table 63. MPC8641 Signal Reference by Functional Block (continued)

Name1Package Pin Number Pin Type Power Supply Notes

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

94 Freescale Semiconductor

Signal Listings

TSEC1_TXD[0:7]/

GPOUT[0:7]

AF25, AC23,AG24, AG23, AE24, AE23,

AE22, AD22

OLV

DD 6, 10

TSEC1_TX_EN AB22 O LVDD 36

TSEC1_TX_ER AH26 O LVDD —

TSEC1_TX_CLK AC22 I LVDD 40

TSEC1_GTX_CLK AH25 O LVDD 41

TSEC1_CRS AM24 I/O LVDD 37

TSEC1_COL AM25 I LVDD —

TSEC1_RXD[0:7]/

GPIN[0:7]

AL25, AL24, AK26, AK25, AM26, AF26,

AH24, AG25

ILV

DD 10

TSEC1_RX_DV AJ24 I LVDD —

TSEC1_RX_ER AJ25 I LVDD —

TSEC1_RX_CLK AK24 I LVDD 40

eTSEC Port 2 Signals5

TSEC2_TXD[0:3]/

GPOUT[8:15]

AB20, AJ23, AJ22, AD19 O LVDD 6, 10

TSEC2_TXD[4]/

GPOUT[12]

AH23 O LVDD 6,10, 38

TSEC2_TXD[5:7]/

GPOUT[13:15]

AH21, AG22, AG21 O LVDD 6, 10

TSEC2_TX_EN AB21 O LVDD 36

TSEC2_TX_ER AB19 O LVDD 6, 38

TSEC2_TX_CLK AC21 I LVDD 40

TSEC2_GTX_CLK AD20 O LVDD 41

TSEC2_CRS AE20 I/O LVDD 37

TSEC2_COL AE21 I LVDD —

TSEC2_RXD[0:7]/

GPIN[8:15]

AL22, AK22, AM21, AH20, AG20, AF20,

AF23, AF22

ILV

DD 10

TSEC2_RX_DV AC19 I LVDD —

TSEC2_RX_ER AD21 I LVDD —

TSEC2_RX_CLK AM22 I LVDD 40

eTSEC Port 3 Signals5

TSEC3_TXD[0:3] AL21, AJ21, AM20, AJ20 O TVDD 6

TSEC3_TXD[4]/ AM19 O TVDD —

TSEC3_TXD[5:7] AK21, AL20, AL19 O TVDD 6

Table 63. MPC8641 Signal Reference by Functional Block (continued)

Name1Package Pin Number Pin Type Power Supply Notes

MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor 95

Signal Listings

TSEC3_TX_EN AH19 O TVDD 36

TSEC3_TX_ER AH17 O TVDD —

TSEC3_TX_CLK AH18 I TVDD 40

TSEC3_GTX_CLK AG19 O TVDD 41

TSEC3_CRS AE15 I/O TVDD 37

TSEC3_COL AF15 I TVDD —

TSEC3_RXD[0:7] AJ17, AE16, AH16, AH14, AJ19, AH15,

AG16, AE19

ITV

DD —

TSEC3_RX_DV AG15 I TVDD —

TSEC3_RX_ER AF16 I TVDD —

TSEC3_RX_CLK AJ18 I TVDD 40

eTSEC Port 4 Signals5

TSEC4_TXD[0:3] AC18, AC16, AD18, AD17 O TVDD 6

TSEC4_TXD[4] AD16 O TVDD 25

TSEC4_TXD[5:7] AB18, AB17, AB16 O TVDD 6

TSEC4_TX_EN AF17 O TVDD 36

TSEC4_TX_ER AF19 O TVDD —

TSEC4_TX_CLK AF18 I TVDD 40

TSEC4_GTX_CLK AG17 O TVDD 41

TSEC4_CRS AB14 I/O TVDD 37

TSEC4_COL AC13 I TVDD —

TSEC4_RXD[0:7] AG14, AD13, AF13, AD14, AE14, AB15,

AC14, AE17

ITV

DD —

TSEC4_RX_DV AC15 I TVDD —

TSEC4_RX_ER AF14 I TVDD —

TSEC4_RX_CLK AG13 I TVDD 40

Local Bus Signals5

LAD[0:31] A30, E29, C29, D28, D29, H25, B29, A29,

C28, L22, M22, A28, C27, H26, G26, B27,

B26, A27, E27, G25, D26, E26, G24, F27,

A26, A25, C25, H23, K22, D25, F25, H22

I/O OVDD 6

LDP[0:3] A24, E24, C24,