MC9S12KT256 Datasheet by Freescale Semiconductor - NXP

View All Related Products | Download PDF Datasheet
NP O 9' freescale’“ semiconductor
HCS12
Microcontrollers
freescale.com
MC9S12KT256
Data Sheet
MC9S12KT256
Rev. 1.16
06/2010
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
A full list of family members and options is included in the appendices.
The following revision history table summarizes changes contained in this document.
This document contains information for all constituent modules, with the exception of the CPU. For CPU
information please refer to CPU12-1 in the CPU12 & CPU12X Reference Manual.
Revision History
Date Revision
Level Description
June, 2010 1.16
Change SCI from V1 to V2, Chagne ATD from V2 to V3.
Update TIM block guide.
Update mask set Table 1-7
Add S12FTS256K2ECC_V1 for the xL33V mask set
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 3
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1). . . . . . . .17
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1). . . . . . .73
Chapter 3 256 Kbyte ECC Flash Module (S12FTS256K2ECCV2). . . . . .117
Chapter 4 4 Kbyte EEPROM Module (S12EETS4KV2) . . . . . . . . . . . . . .161
Chapter 5 Port Integration Module (PIM9KT256V1) . . . . . . . . . . . . . . . .181
Chapter 6 Clocks and Reset Generator (CRGV4) . . . . . . . . . . . . . . . . . .221
Chapter 7 Pierce Oscillator (S12OSCLCPV1) . . . . . . . . . . . . . . . . . . . . .257
Chapter 8 Analog-to-Digital Converter (S12ATD10B8CV3) . . . . . . . . . .263
Chapter 9 Inter-Integrated Circuit (IICV2) . . . . . . . . . . . . . . . . . . . . . . . .291
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2).
315
Chapter 11 Serial Communications Interface (S12SCIV2) . . . . . . . . . . .371
Chapter 12 Serial Peripheral Interface (SPIV3) . . . . . . . . . . . . . . . . . . . . .401
Chapter 13 Pulse-Width Modulator (S12PWM8B8CV1) . . . . . . . . . . . . . .423
Chapter 14 Timer Module (TIM16B8CV1) . . . . . . . . . . . . . . . . . . . . . . . . .455
Chapter 15 Dual Output Voltage Regulator (VREG3V3V2) . . . . . . . . . . .487
Chapter 16 Background Debug Module (BDMV4) . . . . . . . . . . . . . . . . . .495
Chapter 17 Debug Module (DBGV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .521
Chapter 18 Interrupt (INTV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .555
Chapter 19 Multiplexed External Bus Interface (MEBIV3) . . . . . . . . . . . .563
Chapter 20 Module Mapping Control (MMCV4) . . . . . . . . . . . . . . . . . . . .593
Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .613
Appendix B Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . .647
Appendix C Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650
MC9S12KT256 Data Sheet, Rev. 1.16
4 Freescale Semiconductor
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 5
Chapter 1
MC9S12KT256 Device Overview (MC9S12KT256V1)
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.1.3 MC9S12KT256 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.2.1 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.2.2 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.2.3 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
1.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
1.3.1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.3.2 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1.3.3 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
1.4 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
1.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
1.5.1 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
1.5.2 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
1.5.3 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
1.6 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
1.6.1 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
1.6.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Chapter 2
256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
2.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
2.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2.5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
2.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
2.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
2.5.3 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
2.6 Flash Module Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
2.6.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
2.6.2 Unsecuring the Flash Module in Special Single-Chip Mode using BDM . . . . . . . . . . . 113
2.7 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
MC9S12KT256 Data Sheet, Rev. 1.16
6 Freescale Semiconductor
2.7.1 Flash Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
2.7.2 Reset While Flash Command Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
2.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
2.8.1 Description of Flash Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Chapter 3
256 Kbyte ECC Flash Module (S12FTS256K2ECCV2)
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
3.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
3.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
3.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
3.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
3.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
3.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
3.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
3.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
3.4.1 Flash Command Operations (NVM User Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
3.5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
3.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
3.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
3.5.3 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
3.6 Flash Module Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
3.6.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
3.6.2 Unsecuring the Flash Module in Special Single-Chip Mode using BDM . . . . . . . . . . . 157
3.7 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
3.7.1 Flash Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
3.7.2 Reset While Flash Command Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
3.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
3.8.1 Description of Flash Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Chapter 4
4 Kbyte EEPROM Module (S12EETS4KV2)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
4.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
4.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
4.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
4.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
4.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
4.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
4.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
4.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
4.4.1 Program and Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 7
4.5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
4.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
4.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
4.5.3 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
4.6 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Chapter 5
Port Integration Module (PIM9KT256V1)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
5.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
5.2.1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
5.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
5.3.1 Port T Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
5.3.2 Port S Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
5.3.3 Port M Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
5.3.4 Port P Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
5.3.5 Port H Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
5.3.6 Port J Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
5.4.1 I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
5.4.2 Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
5.4.3 Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
5.4.4 Reduced Drive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
5.4.5 Pull Device Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
5.4.6 Polarity Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
5.4.7 Pin Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
5.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
5.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
5.6.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
5.6.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
5.6.3 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Chapter 6
Clocks and Reset Generator (CRGV4) Block Description
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
6.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
6.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
6.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
6.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
6.2.1 VDDPLL, VSSPLL — PLL Operating Voltage, PLL Ground . . . . . . . . . . . . . . . . . . . . . . 223
MC9S12KT256 Data Sheet, Rev. 1.16
8 Freescale Semiconductor
6.2.2 XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
6.2.3 RESET — Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
6.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
6.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
6.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
6.4.1 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
6.4.2 System Clocks Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
6.4.3 Clock Monitor (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
6.4.4 Clock Quality Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
6.4.5 Computer Operating Properly Watchdog (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
6.4.6 Real-Time Interrupt (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
6.4.7 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
6.4.8 Low-Power Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
6.4.9 Low-Power Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
6.4.10 Low-Power Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
6.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
6.5.1 Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
6.5.2 Computer Operating Properly Watchdog (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 254
6.5.3 Power-On Reset, Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
6.6.1 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
6.6.2 PLL Lock Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
6.6.3 Self-Clock Mode Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Chapter 7
Pierce Oscillator (S12OSCLCPV1)
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
7.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
7.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
7.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins . . . . . . . . . . . . . . . . . . . . 258
7.2.2 EXTAL and XTAL — Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
7.2.3 XCLKS — Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
7.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
7.4.1 Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
7.4.2 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
7.4.3 Wait Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
7.4.4 Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 9
Chapter 8
Analog-to-Digital Converter (S12ATD10B8CV3)
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
8.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
8.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
8.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
8.2.1 ANx (x = 7, 6, 5, 4, 3, 2, 1, 0) — Analog Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
8.2.2 ETRIG3, ETRIG2, ETRIG1, and ETRIG0 — External Trigger Pins . . . . . . . . . . . . . . 264
8.2.3 VRH and VRL — High and Low Reference Voltage Pins . . . . . . . . . . . . . . . . . . . . . . . . 264
8.2.4 VDDA and VSSA — Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
8.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
8.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
8.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
8.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
8.5.1 Setting up and starting an A/D conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
8.5.2 Aborting an A/D conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
8.6 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
8.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Chapter 9
Inter-Integrated Circuit (IICV2) Block Description
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
9.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
9.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
9.2.1 IIC_SCL — Serial Clock Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
9.2.2 IIC_SDA — Serial Data Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
9.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
9.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
9.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
9.4.1 I-Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
9.4.2 Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
9.4.3 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
9.4.4 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
9.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
9.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
9.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
9.7.1 IIC Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
MC9S12KT256 Data Sheet, Rev. 1.16
10 Freescale Semiconductor
Chapter 10
Freescale’s Scalable Controller Area Network (S12MSCANV2)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
10.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
10.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
10.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
10.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
10.2.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
10.2.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
10.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
10.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
10.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
10.3.3 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
10.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
10.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
10.4.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
10.4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
10.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
10.4.6 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
10.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
10.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Chapter 11
Serial Communications Interface (S12SCIV2)
Block Description
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
11.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
11.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
11.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
11.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
11.2.1 TXD-SCI Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
11.2.2 RXD-SCI Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
11.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
11.4.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
11.4.2 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
11.4.3 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 11
11.4.4 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
11.4.5 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
11.4.6 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
11.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
11.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
11.5.2 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
11.5.3 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Chapter 12
Serial Peripheral Interface (SPIV3) Block Description
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
12.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
12.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
12.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
12.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
12.2.3 SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
12.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
12.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
12.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
12.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
12.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
12.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
12.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
12.4.7 Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
12.4.8 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
12.4.9 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
12.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
12.6.1 MODF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
12.6.2 SPIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
12.6.3 SPTEF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Chapter 13
Pulse-Width Modulator (S12PWM8B8CV1)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
13.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
13.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
MC9S12KT256 Data Sheet, Rev. 1.16
12 Freescale Semiconductor
13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
13.2.1 PWM7 — PWM Channel 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
13.2.2 PWM6 — PWM Channel 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
13.2.3 PWM5 — PWM Channel 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
13.2.4 PWM4 — PWM Channel 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
13.2.5 PWM3 — PWM Channel 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
13.2.6 PWM3 — PWM Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
13.2.7 PWM3 — PWM Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
13.2.8 PWM3 — PWM Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
13.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
13.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
13.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
13.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
13.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
Chapter 14
Timer Module (TIM16B8CV1) Block Description
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
14.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
14.2.1 IOC7 — Input Capture and Output Compare Channel 7 Pin . . . . . . . . . . . . . . . . . . . . 458
14.2.2 IOC6 — Input Capture and Output Compare Channel 6 Pin . . . . . . . . . . . . . . . . . . . . 458
14.2.3 IOC5 — Input Capture and Output Compare Channel 5 Pin . . . . . . . . . . . . . . . . . . . . 458
14.2.4 IOC4 — Input Capture and Output Compare Channel 4 Pin . . . . . . . . . . . . . . . . . . . . 458
14.2.5 IOC3 — Input Capture and Output Compare Channel 3 Pin . . . . . . . . . . . . . . . . . . . . 458
14.2.6 IOC2 — Input Capture and Output Compare Channel 2 Pin . . . . . . . . . . . . . . . . . . . . 459
14.2.7 IOC1 — Input Capture and Output Compare Channel 1 Pin . . . . . . . . . . . . . . . . . . . . 459
14.2.8 IOC0 — Input Capture and Output Compare Channel 0 Pin . . . . . . . . . . . . . . . . . . . . 459
14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
14.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
14.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
14.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
14.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
14.4.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
14.4.5 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
14.4.6 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
14.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
14.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 13
14.6.1 Channel [7:0] Interrupt (C[7:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
14.6.2 Pulse Accumulator Input Interrupt (PAOVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
14.6.3 Pulse Accumulator Overflow Interrupt (PAOVF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
14.6.4 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
Chapter 15
Dual Output Voltage Regulator (VREG3V3V2)
Block Description
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
15.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
15.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
15.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
15.2.1 VDDR — Regulator Power Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
15.2.2 VDDA, VSSA — Regulator Reference Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
15.2.3 VDD, VSS — Regulator Output1 (Core Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
15.2.4 VDDPLL, VSSPLL — Regulator Output2 (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
15.2.5 VREGEN — Optional Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
15.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
15.4.1 REG — Regulator Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
15.4.2 Full-Performance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
15.4.3 Reduced-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
15.4.4 LVD — Low-Voltage Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
15.4.5 POR — Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
15.4.6 LVR — Low-Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
15.4.7 CTRL — Regulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
15.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
15.5.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
15.5.2 Low-Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
15.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
15.6.1 LVI — Low-Voltage Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
Chapter 16
Background Debug Module (BDMV4) Block Description
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
16.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
16.2.1 BKGD — Background Interface Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
16.2.2 TAGHI — High Byte Instruction Tagging Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
16.2.3 TAGLO — Low Byte Instruction Tagging Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
MC9S12KT256 Data Sheet, Rev. 1.16
14 Freescale Semiconductor
16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
16.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
16.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
16.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
16.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
16.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
16.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
16.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
16.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
16.4.9 SYNC — Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
16.4.10Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
16.4.11Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
16.4.12Serial Communication Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
16.4.13Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
16.4.14Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
Chapter 17
Debug Module (DBGV1) Block Description
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
17.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
17.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
17.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
17.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
17.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
17.4.1 DBG Operating in BKP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
17.4.2 DBG Operating in DBG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
17.4.3 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
17.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
17.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
Chapter 18
Interrupt (INTV1) Block Description
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
18.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
18.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
18.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
18.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 15
18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
18.4.1 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
18.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
18.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
18.6.1 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
18.6.2 Highest Priority I-Bit Maskable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
18.6.3 Interrupt Priority Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
18.7 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
Chapter 19
Multiplexed External Bus Interface (MEBIV3)
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
19.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
19.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
19.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
19.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
19.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
19.4.1 Detecting Access Type from External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
19.4.2 Stretched Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
19.4.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
19.4.4 Internal Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
19.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
Chapter 20
Module Mapping Control (MMCV4) Block Description
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
20.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
20.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
20.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
20.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
20.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
20.4.1 Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
20.4.2 Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
20.4.3 Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
Appendix A
Electrical Characteristics
A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
MC9S12KT256 Data Sheet, Rev. 1.16
16 Freescale Semiconductor
A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
A.1.8 Power Dissipation and Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
A.2 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
A.3 Chip Power-up and LVI/LVR Graphical Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
A.4 Output Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
A.4.1 Resistive Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
A.4.2 Capacitive Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
A.5 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
A.5.1 ATD Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
A.5.2 Factors Influencing Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
A.5.3 ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
A.6 NVM, Flash and EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
A.6.1 NVM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
A.6.2 NVM Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
A.7 Reset, Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
A.7.1 Startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
A.7.2 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
A.7.3 Phase Locked Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
A.8 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
A.9 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
A.9.1 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
A.9.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
A.10 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
A.10.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
Appendix B
Recommended PCB Layout
Appendix C
Package Information
C.1 112-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
C.2 80-Pin QFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 17
Chapter 1
MC9S12KT256 Device Overview (MC9S12KT256V1)
1.1 Introduction
The MC9S12KT256 is a 112/80 pin 16-bit Flash-based microcontroller family targeted for high reliability
systems. The MC9S12KT256 has an increased performance in reliability over the life of the product due
to a built-in Error Checking and Correction Code (ECC) in the Flash memory. The program and erase
operations automatically generate six parity bits per word making ECC transparent to the user.
The MC9S12KT256 is comprised of standard on-chip peripherals including a 16-bit central processing
unit (CPU12), 256K bytes of Flash EEPROM, 4K bytes of EEPROM, 12K bytes of RAM, two
asynchronous serial communications interface (SCI), three serial peripheral interface (SPI), IIC-bus, an
8-channel IC/OC timer, two 8-channel 10-bit analog-to-digital converters (ADC), an 8-channel
pulse-width modulator (PWM), three CAN 2.0 A, B software compatible modules, 29 discrete digital I/O
channels (Port A, Port B, Port E and Port K), and 20 discrete digital I/O lines with interrupt and wakeup
capability. The MC9S12KT256 has full 16-bit data paths throughout, however, the external bus can operate
in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The
inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational
requirements.
1.1.1 Features
HCS12 Core
16-bit HCS12 CPU
Upward compatible with M68HC11 instruction set
Interrupt stacking and programmer’s model identical to M68HC11
Instruction queue
Enhanced indexed addressing
MEBI (Multiplexed External Bus Interface)
MMC (Memory Map and Interface)
INT (Interrupt Controller)
DBG (Debugger)
BDM (Background Debug Mode)
• Oscillator
4MHz to 16MHz frequency range
Pierce with amplitude loop control
Clock monitor
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
18 Freescale Semiconductor
Clock and Reset Generator (CRG)
Phase-locked loop clock frequency multiplier
Self Clock mode in absence of external clock
COP watchdog
Real Time interrupt (RTI)
• Memory
256K Byte Flash EEPROM
Internal program/erase voltage generation
Security and Block Protect bits
Hamming Error Correction Coding (ECC)
4K Byte EEPROM
12K Byte static RAM
Single-cycle misaligned word accesses without wait states
Analog-to-Digital Converters (ADC)
Two 8-channel modules with 10-bit resolution
External conversion trigger capability
8-channel Timer (TIM)
Programmable input capture or output compare channels
Simple PWM mode
Counter Modulo Reset
External Event Counting
Gated Time Accumulation
8-channel Pulse Width Modulator (PWM)
Programmable period and duty cycle per channel
8-bit 8-channel or 16-bit 4-channel
Edge and center aligned PWM signals
Emergency shutdown input
Three 1M bit per second, CAN 2.0 A, B software compatible modules
Five receive and three transmit buffers
Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
Four separate interrupt channels for Rx, Tx, error and wake-up
Low-pass filter wake-up function
Loop-back for self test operation
Serial interfaces
Two asynchronous serial communication interface (SCI)
Three synchronous serial peripheral interface (SPI)
Inter-IC Bus (IIC)
Internal 2.5V Regulator
Input voltage range from 3.15V to 5.5V
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 19
Low power mode capability
Low Voltage Reset (LVR) and Low Voltage Interrupt (LVI)
20 key wake up inputs
Rising or falling edge triggered interrupt capability
Digital filter to prevent short pulses from triggering interrupts
Programmable pull ups and pull downs
Operating frequency for ambient temperatures (TA -40°C to 125°C)
50MHz equivalent to 25MHz Bus Speed
112-Pin LQFP or 80-Pin QFP package
I/O lines with 3.3V/5V input and drive capability
3.3V/5V A/D converter inputs
1.1.2 Modes of Operation
Normal modes
Normal Single-Chip Mode
Normal Expanded Wide Mode
Normal Expanded Narrow Mode
Emulation Expanded Wide Mode
Emulation Expanded Narrow Mode
Special Operating Modes
Special Single-Chip Mode with active Background Debug Mode
Special Test Mode (Freescale use only)
Special Peripheral Mode (Freescale use only)
Each of the above modes of operation can be configured for three Low power submodes
Stop Mode
Pseudo Stop Mode
Wait Mode
Secure operation, preventing the unauthorized read and write of the memory contents.
g
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
20 Freescale Semiconductor
Table 1-1 shows a feature overview of the MC9S12KT256 members.
Figure 1-1 shows the part number coding based on the package and temperature options for the
MC9S12KT256.
Figure 1-1. Order Part number Coding
Table 1-1. List of MC9S12KT256 members
Device Temp Options1
1C: TA = 85˚C, f = 25MHz. V: TA=105˚C, f = 25MHz. M: TA= 125˚C, f = 25MHz
Flash RAM EEPROM Package CAN SCI SPI IIC A/D2
2Number of channels
PWM2TIM2I/O3
3I/O is the sum of ports capable to act as digital input or output.
MC9S12KT256 C, V, M 256K 12K 4K 112 LQFP 3 2 3 1 16 8 8 91
MC9S12KG256 C, V, M 256K 12K 4K 112 LQFP 2 2 3 1 16 8 8 91
80 QFP 2 2 3 1 8 7 8 59
MC9S12 KT256 C FU
Package Option
Temperature Option
Device Title
Controller Family
Temperature Options
C = -40˚C to 85˚C
V = -40˚C to 105˚C
M = -40˚C to 125˚C
Package Options
PV = 112LQFP
FU = 80QFP
:: Iii: ffifit
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 21
1.1.3 MC9S12KT256 Block Diagram
Figure 1-2. MC9S12KT256 Block Diagram
256K Byte Flash EEPROM
12K Byte RAM
RESET
EXTAL
XTAL
VDD1,2
VSS1,2
SCI0
BKGD
R/W
MODB
XIRQ
NOACC/XCLKS
System
Integration
Module
(SIM)
VDDR
CPU12
Periodic Interrupt
COP Watchdog
Clock Monitor
Single-wire BDM
Breakpoints
PLL
VSSPLL
XFC
VDDPLL
Multiplexed Address/Data Bus
ATD0
Multiplexed
Wide Bus
Multiplexed
VDDX
VSSX
Internal Logic 2.5V
Narrow Bus
PPAGE
V
DDPLL
VSSPLL
OSC/PLL 2.5V
IRQ
LSTRB
ECLK
MODA
PA4
PA3
PA2
PA1
PA0
PA7
PA6
PA5
TEST
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR15
ADDR14
ADDR13
DATA12
DATA11
DATA10
DATA9
DATA8
DATA15
DATA14
DATA13
PB4
PB3
PB2
PB1
PB0
PB7
PB6
PB5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
ADDR7
ADDR6
ADDR5
DATA4
DATA3
DATA2
DATA1
DATA0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DATA7
DATA6
DATA5
PE3
PE4
PE5
PE6
PE7
PE0
PE1
PE2
AN2
AN6
AN0
AN7
AN1
AN3
AN4
AN5
PAD03
PAD04
PAD05
PAD06
PAD07
PAD00
PAD01
PAD02
IOC2
IOC6
IOC0
IOC7
IOC1
IOC3
IOC4
IOC5
PT3
PT4
PT5
PT6
PT7
PT0
PT1
PT2
VRH
VRL
VDDA
VSSA
VRH
VRL
AN2
AN6
AN0
AN7
AN1
AN3
AN4
AN5
PAD11
PAD12
PAD13
PAD14
PAD15
PAD08
PAD09
PAD10
VDDA
VSSA
RXD
TXD
MISO
MOSI
PS3
PS4
PS5
PS0
PS1
PS2
SCI1 RXD
TXD
PWM2
PWM6
PWM0
PWM7
PWM1
PWM3
PWM4
PWM5
PP3
PP4
PP5
PP6
PP7
PP0
PP1
PP2
PIX2
PIX0
PIX1
PIX3
ECS
PK3
PK7
PK0
PK1
XADDR17
ECS
XADDR14
XADDR15
XADDR16
SCK
SS PS6
PS7
SPI0
IIC SDA
SCL PJ6
PJ7
CAN0 RxCAN
TxCAN PM1
PM0
PM2
PM3
PM4
PM5
PM6
PM7
KWH2
KWH6
KWH0
KWH7
KWH1
KWH3
KWH4
KWH5
PH3
PH4
PH5
PH6
PH7
PH0
PH1
PH2
KWJ0
KWJ1 PJ0
PJ1
I/O Driver 3.3V/5V
VDDA
VSSA
A/D Converter 3.3V/5V
DDRA DDRB
PTA PTB
DDRE
PTE
AD1
AD0
PTK
DDRK
PTT
DDRT
PTP
DDRP
PTS
DDRS
PTM
DDRM
PTH
DDRH
PTJ
DDRJ
PK2
CRG
Voltage Regulator
VSSR
VDD1,2
VSS1,2
VREGEN
VDDR
VSSR
Voltage Regulator 3.3V/5V
PIX4
PIX5 PK4
PK5 XADDR18
XADDR19
Voltage Reference
KWP2
KWP6
KWP0
KWP7
KWP1
KWP3
KWP4
KWP5
KWJ6
KWJ7
TIM
Signals shown in Bold are not available on n the 80-Pin Package
Module to
Port Routing
4K Byte EEPROM
PWM
MISO
MOSI
SCK
SS
SPI1
MISO
MOSI
SCK
SS
SPI2
CAN4 RxCAN
TxCAN
OSC
Debugger
CAN1 RxCAN
TxCAN
ATD1
VRH
VRL
VDDA
VSSA
VRH
VRL VDDA
VSSA
flflHflHflflflflflflflflflflflflflflflflflflflflflflfl flflflflflflflflflflflflflflflflflflflflflflflflflflflfl O UHUHUUUUUUUUUUUUUUUUUUUUUUUU UHUHUUUUUUUUUUUUUUUUUUUUUUUU ‘ ‘\“ \ ‘ \ ‘
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
22 Freescale Semiconductor
1.2 Signal Description
The MC9S12KT256 is available in a 112-pin low profile quad flat pack (LQFP) and a 80-pin quad flat pack
(QFP). Most pins perform two or more functions, as described in Section 1.2.1, “Signal Properties
Summary”.Figure 1-3 and Figure 1-4 show the pin assignments for different packages.
Figure 1-3. Pin Assignments for 112 LQFP
VRH
VDDA
PAD15/AN15
PAD07/AN07
PAD14/AN14
PAD06/AN06
PAD13/AN13
PAD05/AN05
PAD12/AN12
PAD04/AN04
PAD11/AN11
PAD03/AN03
PAD10/AN10
PAD02/AN02
PAD09/AN09
PAD01/AN01
PAD08/AN08
PAD00/AN00
VSS2
VDD2
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
PP4/KWP4/PWM4/MISO2
PP5/KWP5/PWM5/MOSI2
PP6/KWP6/PWM6/SS2
PP7/KWP7/PWM7/SCK2
PK7/ECS
VDDX
VSSX
PM0/RXCAN0
PM1/TXCAN0
PM2/RXCAN1/RXCAN0/MISO0
PM3/TXCAN1/TXCAN0/SS0
PM4/RXCAN0/RXCAN4/MOSI0
PM5/TXCAN0/TXCAN4/SCK0
PJ6/KWJ6/RXCAN4/SDA
PJ7/KWJ7/TXCAN4/SCL
VREGEN
PS7/SS0
PS6/SCK0
PS5/MOSI0
PS4/MISO0
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
PM6/RXCAN4
PM7/TXCAN4
VSSA
VRL
SS1/PWM3/KWP3/PP3
SCK1/PWM2/KWP2/PP2
MOSI1/PWM1/KWP1/PP1
MISO1/PWM0/KWP0/PP0
XADDR17/PK3
XADDR16/PK2
XADDR15/PK1
XADDR14/PK0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDD1
VSS1
IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
XADDR19/PK5
XADDR18/PK4
KWJ1/PJ1
KWJ0/PJ0
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
ADDR5/DATA5/PB5
ADDR6/DATA6/PB6
ADDR7/DATA7/PB7
SS2/KWH7/PH7
SCK2/KWH6/PH6
MOSI2/KWH5/PH5
MISO2/KWH4/PH4
XCLKS/NOACC/PE7
MODB/IPIPE1/PE6
MODA/IPIPE0/PE5
ECLK/PE4
VSSR
VDDR
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
SS1/KWH3/PH3
SCK1/KWH2/PH2
MOSI1/KWH1/PH1
MISO1/KWH0/PH0
LSTRB/TAGLO/PE3
R/W/PE2
IRQ/PE1
XIRQ/PE0
Signals shown in Bold are not available on the 80-pin package
MC9S12KT256
112LQFP
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
|( OK flflflflflflflflflflflflflflflflflflflfl HHHHHHHHHHHHHHHHHHHH O UUUUUUUUUUUUUUUUUUUU UUUUUUUUUUUUUUUUUUUU ‘ ‘\“
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 23
Figure 1-4. Pin Assignments for 80 QFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VRH
VDDA
PAD07/AN07
PAD06/AN06
PAD05/AN05
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
PAD00/AN00
VSS2
VDD2
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
PP4/KWP4/PWM4/MISO2
PP5/KWP5/PWM5/MOSI2
PP7/KWP7/PWM7/SCK2
VDDX
VSSX
PM0/RXCAN0
PM1/TXCAN0
PM2/RXCAN1/RXCAN0/MISO
0
PM3/TXCAN1/TXCAN0/SS0
PM4/RXCAN0/RXCAN4/MOSI
0
PM5/TXCAN0/TXCAN4/SCK0
PJ6/KWJ6/RXCAN4/SDA
PJ7/KWJ7/TXCAN4/SCL
VREGEN
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
VSSA
VRL
PWM3/KWP3/PP3
PWM2/KWP2/PP2
PWM1/KWP1/PP1
PWM0/KWP0/PP0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDD1
VSS1
IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
ADDR5/DATA5/PB5
ADDR6/DATA6/PB6
ADDR7/DATA7/PB7
XCLKS/NOACC/PE7
MODB/IPIPE1/PE6
MODA/IPIPE0/PE5
ECLK/PE4
VSSR
VDDR
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
LSTRB/TAGLO/PE3
R/W/PE2
IRQ/PE1
XIRQ/PE0
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
MC9S12KT256
80 QFP
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
24 Freescale Semiconductor
1.2.1 Signal Properties Summary
Table 1-2 summarizes the pin functionality. Signals shown in bold are not available in the 80-pin package.
Table 1-3 summarizes the power and ground pins.
Table 1-2. Signal Properties (Sheet 1 of 3)
Pin Name
Function 1 Pin Name
Function 2 Pin Name
Function 3 Pin Name
Function 4 Powered
by
Internal Pull
Resistor Description
CTRL Reset
State
EXTAL VDDPLL NA NA Oscillator Pins
XTAL VDDPLL NA NA
RESET VDDR None None External Reset
TEST NA NA NA Test Input
VREGEN VDDX NA NA Voltage Regulator Enable Input
XFC VDDPLL NA NA PLL Loop Filter
BKGD TAGHI MODC VDDR Always Up Up Background Debug, Tag High,
Mode Input
PAD[15:8] AN1[7:0] VDDA None None Port AD Input, Analog Inputs of
ATD1
PAD[7:0] AN0[7:0] VDDA None None Port AD Input, Analog Inputs of
ATD0
PA[7:0] ADDR[15:8]/
DATA[15:8] VDDR PUCR Disabled Port A I/O, Multiplexed
Address/Data
PB[7:0] ADDR[7:0]/
DATA[7:0] VDDR PUCR Disabled Port B I/O, Multiplexed
Address/Data
PE7 NOACC XCLKS VDDR PUCR Up Port E I/O, Access, Clock Select
PE6 IPIPE1 MODB VDDR While RESET
pin is low:
Down
Port E I/O, Pipe Status, Mode
Input
PE5 IPIPE0 MODA VDDR While RESET
pin is low:
Down
Port E I/O, Pipe Status, Mode
Input
PE4 ECLK VDDR PUCR Up Port E I/O, Bus Clock Output
PE3 LSTRB TAGLO VDDR PUCR Up Port E I/O, Byte Strobe, Tag Low
PE2 R/W VDDR PUCR Up Port E I/O, R/W in expanded
modes
PE1 IRQ VDDR PUCR Up Port E Input, Maskable Interrupt
PE0 XIRQ VDDR PUCR Up Port E Input, Non Maskable
Interrupt
PH7 KWH7 SS2 VDDR PERH/
PPSH Disabled Port H I/O, Interrupt, SS of SPI2
PH6 KWH6 SCK2 VDDR PERH/
PPSH Disabled Port H I/O, Interrupt, SCK of
SPI2
PH5 KWH5 MOSI2 VDDR PERH/
PPSH Disabled Port H I/O, Interrupt, MOSI of
SPI2
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 25
PH4 KWH4 MISO2 VDDR PERH/
PPSH Disabled Port H I/O, Interrupt, MISO of
SPI2
PH3 KWH3 SS1 VDDR PERH/
PPSH Disabled Port H I/O, Interrupt, SS of SPI1
PH2 KWH2 SCK1 VDDR PERH/
PPSH Disabled Port H I/O, Interrupt, SCK of
SPI1
PH1 KWH1 MOSI1 VDDR PERH/
PPSH Disabled Port H I/O, Interrupt, MOSI of
SPI1
PH0 KWH0 MISO1 VDDR PERH/
PPSH Disabled Port H I/O, Interrupt, MISO of
SPI1
PJ7 KWJ7 TXCAN4 SCL VDDX PERJ/
PPSJ Up Port J I/O, Interrupt, TX of CAN4,
SCL of IIC
PJ6 KWJ6 RXCAN4 SDA VDDX PERJ/
PPSJ Up Port J I/O, Interrupt, RX of CAN4,
SDA of IIC
PJ[1:0] KWJ[1:0] VDDX PERJ/
PPSJ Up Port J I/O, Interrupts
PK7 ECS ROMCTL VDDX PUCR Up Port K I/O, Emulation Chip
Select,
ROM On Enable
PK[5:0] XADDR[19:14] VDDX PUCR Up Port K I/O, Extended
Addresses
PM7 TXCAN4 VDDX PERM/
PPSM Disabled Port M I/O, CAN4 TX
PM6 RXCAN4 VDDX PERM/
PPSM Disabled Port M I/O, CAN4 RX
PM5 TXCAN0 TXCAN4 SCK0 VDDX PERM/
PPSM Disabled Port M I/O, CAN0 TX, CAN4 TX,
SPI0 SCK
PM4 RXCAN0 RXCAN4 MOSI0 VDDX PERM/
PPSM Disabled Port M I/O, CAN0 RX, CAN4 RX,
SPI0 MOSI
PM3 TXCAN1 TXCAN0 SS0 VDDX PERM/
PPSM Disabled Port M I/O, CAN1 TX, CAN0 TX,
SPI0 SS
PM2 RXCAN1 RXCAN0 MISO0 VDDX PERM/
PPSM Disabled Port M I/O, CAN1 RX, CAN0 RX,
SPI0 MISO
PM1 TXCAN0 VDDX PERM/
PPSM Disabled Port M I/O, CAN0 TX
PM0 RXCAN0 VDDX PERM/
PPSM Disabled Port M I/O, CAN0 RX
PP7 KWP7 PWM7 SCK2 VDDX PERP/
PPSP Disabled Port P I/O, Interrupt, PWM
Channel 7,
SCK of SPI2
PP6 KWP6 PWM6 SS2 VDDX PERP/
PPSP Disabled Port P I/O, Interrupt, PWM
Channel 6, SPI2 SS
Table 1-2. Signal Properties (Sheet 2 of 3)
Pin Name
Function 1 Pin Name
Function 2 Pin Name
Function 3 Pin Name
Function 4 Powered
by
Internal Pull
Resistor Description
CTRL Reset
State
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
26 Freescale Semiconductor
PP5 KWP5 PWM5 MOSI2 VDDX PERP/
PPSP Disabled Port P I/O, Interrupt, PWM
Channel 5,
SPI2 MOSI
PP4 KWP4 PWM4 MISO2 VDDX PERP/
PPSP Disabled Port P I/O, Interrupt, PWM
Channel 4, SPI2 MISO
PP3 KWP3 PWM3 SS1 VDDX PERP/
PPSP Disabled Port P I/O, Interrupt, PWM
Channel 3, SPI1 SS
PP2 KWP2 PWM2 SCK1 VDDX PERP/
PPSP Disabled Port P I/O, Interrupt, PWM
Channel 2, SPI1 SCK
PP1 KWP1 PWM1 MOSI1 VDDX PERP/
PPSP Disabled Port P I/O, Interrupt, PWM
Channel 1, SPI1 MOSI
PP0 KWP0 PWM0 MISO1 VDDX PERP/
PPSP Disabled Port P I/O, Interrupt, PWM
Channel 0, SPI1 MISO
PS7 SS0 VDDX PERS/
PPSS Up Port S I/O, SPI0 SS
PS6 SCK0 VDDX PERS/
PPSS Up Port S I/O, SPI0 SCK
PS5 MOSI0 VDDX PERS/
PPSS Up Port S I/O, SPI0 MOSI
PS4 MISO0 VDDX PERS/
PPSS Up Port S I/O, SPI0 MISO
PS3 TXD1 VDDX PERS/
PPSS Up Port S I/O, SCI1TXD
PS2 RXD1 VDDX PERS/
PPSS Up Port S I/O, SCI1RXD
PS1 TXD0 VDDX PERS/
PPSS Up Port S I/O, SCI0 TXD
PS0 RXD0 VDDX PERS/
PPSS Up Port S I/O, SCI0 RXD
PT[7:0] IOC[7:0] VDDX Up or
Down Disabled Port T I/O, Timer channels
Table 1-2. Signal Properties (Sheet 3 of 3)
Pin Name
Function 1 Pin Name
Function 2 Pin Name
Function 3 Pin Name
Function 4 Powered
by
Internal Pull
Resistor Description
CTRL Reset
State
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 27
NOTE
All VSS pins must be connected together in the application. Because fast
signal transitions place high, short-duration current demands on the power
supply, use bypass capacitors with high-frequency characteristics and place
them as close to the MCU as possible. Bypass requirements depend on
MCU pin load.
1.2.2 Detailed Signal Descriptions
1.2.2.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
1.2.2.2 RESET — External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up state,
and an output when an internal MCU function causes a reset.
1.2.2.3 TEST — Test Pin
This input only pin is reserved for test.
NOTE
The TEST pin must be tied to VSS in all applications.
Table 1-3. Power and Ground
Mnemonic Nominal
Voltage Description
VDD1 VDD2 2.5 V Internal power and ground generated by internal regulator. These also allow an external
source to supply the core VDD/VSS voltages and bypass the internal voltage regulator.
VSS1
VSS2 0V
VDDR 3.3/5.0 V External power and ground, supply to pin drivers and internal voltage regulator.
VSSR 0 V
VDDX 3.3/5.0 V External power and ground, supply to pin drivers.
VSSX 0 V
VDDA 3.3/5.0 V Operating voltage and ground for the analog-to-digital converter and the reference for the
internal voltage regulator, allows the supply voltage to the A/D to be bypassed
independently.
VSSA 0 V
VRH 3.3/5.0 V Reference voltage high for the ATD converter.
VRL 0 V Reference voltage low for the ATD converter.
VDDPLL 2.5 V Provides operating voltage and ground for the Phased-Locked Loop. This allows the supply
voltage to the PLL to be bypassed independently. Internal power and ground generated by
internal regulator.
VSSPLL 0 V
#3 || ||
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
28 Freescale Semiconductor
1.2.2.4 VREGEN — Voltage Regulator Enable Pin
This input only pin enables or disables the on-chip voltage regulator.
1.2.2.5 XFC — PLL Loop Filter Pin
PLL loop filter. Please ask your Freescale representative for the interactive application note to compute
PLL loop filter elements. Any current leakage on this pin must be avoided.
Figure 1-5. PLL Loop Filter Connections
1.2.2.6 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET.
1.2.2.7 PAD[15:8] / AN1[7:0] — Port AD Input Pins [15:8]
PAD15 - PAD8 are general purpose input pins and analog inputs of the analog to digital converter with 8
channels (ATD1).
1.2.2.8 PAD[7:0] / AN0[7:0] — Port AD Input Pins [7:0]
PAD7–PAD0 are general purpose input pins and analog inputs of the analog to digital converter with 8
channels (ATD0).
1.2.2.9 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA7–PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
1.2.2.10 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB7–PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
MCU
XFC
R
CS
CP
VDDPLLVDDPLL
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 29
1.2.2.11 PE7 / NOACC / XCLKS — Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal
will assert when the CPU is not using the bus.
The XCLKS is an input signal which controls whether a crystal in combination with the internal Loop
Controlled Pierce (low power) oscillator is used or whether Full Swing Pierce oscillator/external clock
circuitry is used. The state of this pin is latched at the rising edge of RESET. If the input is a logic low the
EXTAL pin is configured for an external clock drive or Full Swing Pierce Oscillator. If input is a logic high
a Loop Controlled Pierce oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input
with a pull-up device during reset, if the pin is left floating, the default configuration is a Loop Controlled
Pierce oscillator circuit on EXTAL and XTAL.
Figure 1-6. Loop Controlled Pierce Oscillator Connections (PE7 = 1)
Figure 1-7. Full Swing Pierce Oscillator Connections (PE7 = 0)
Table 1-4. Clock Selection Based on PE7 During Reset
PE7 Description
1 Loop Controlled Pierce Oscillator selected
0 Full Swing Pierce Oscillator or external clock selected
MCU
EXTAL
XTAL
VSSPLL
CRYSTAL OR
CERAMIC
C8
C7
RESONATOR
* Rs can be zero (shorted) when use with higher frequency crystals.
Refer to manufacturer’s data.
MCU
EXTAL
XTAL RS*
RB
VSSPLL
C8
C7
CRYSTAL OR
CERAMIC
RESONATOR
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
30 Freescale Semiconductor
Figure 1-8. External Clock Connections (PE7 = 0)
1.2.2.12 PE6 / MODB / IPIPE1 — Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE1.
1.2.2.13 PE5 / MODA / IPIPE0 — Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE0.
1.2.2.14 PE4 / ECLK — Port E I/O Pin 4
PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK.
ECLK can be used as a timing reference.
1.2.2.15 PE3 / LSTRB / TAGLO — Port E I/O Pin 3
PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB can be used
for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on,
TAGLO is used to tag the low half of the instruction word being read into the instruction queue.
1.2.2.16 PE2 / R/W Port E I/O Pin 2
PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the
read/write output signal for the external bus. It indicates the direction of data on the external bus.
1.2.2.17 PE1 / IRQ — Port E Input Pin 1
PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
MCU
EXTAL
XTAL
CMOS-COMPATIBLE
EXTERNAL OSCILLATOR
NOT CONNECTED
(VDDPLL-LEVEL)
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 31
1.2.2.18 PE0 / XIRQ — Port E Input Pin 0
PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
1.2.2.19 PH7 / KWH7 / SS2 — Port H I/O Pin 7
PH7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface 2
(SPI2).
1.2.2.20 PH6 / KWH6 / SCK2 — Port H I/O Pin 6
PH6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral
Interface 2 (SPI2).
1.2.2.21 PH5 / KWH5 / MOSI2 — Port H I/O Pin 5
PH5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input
pin (during slave mode) MOSI of the Serial Peripheral Interface 2 (SPI2).
1.2.2.22 PH4 / KWH4 / MISO2 — Port H I/O Pin 2
PH4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output
(during slave mode) pin MISO of the Serial Peripheral Interface 2 (SPI2).
1.2.2.23 PH3 / KWH3 / SS1 — Port H I/O Pin 3
PH3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface 1
(SPI1).
1.2.2.24 PH2 / KWH2 / SCK1 — Port H I/O Pin 2
PH2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral
Interface 1 (SPI1).
1.2.2.25 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1
PH1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input
pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
32 Freescale Semiconductor
1.2.2.26 PH0 / KWH0 / MISO1 — Port H I/O Pin 0
PH0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output
(during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1).
1.2.2.27 PJ7 / KWJ7 / TXCAN4 / SCL — PORT J I/O Pin 7
PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the transmit pin TXCAN for the Scalable Controller
Area Network controller 4 (CAN4) or the serial clock pin SCL of the IIC module.
1.2.2.28 PJ6 / KWJ6 / RXCAN4 / SDA — PORT J I/O Pin 6
PJ6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the receive pin RXCAN for the Scalable Controller
Area Network controller 4 (CAN4) or the serial data pin SDA of the IIC module.
1.2.2.29 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0]
PJ1 and PJ0 are general purpose input or output pins. They can be configured to generate an interrupt
causing the MCU to exit STOP or WAIT mode.
1.2.2.30 PK7 / ECS / ROMCTL — Port K I/O Pin 7
PK7 is a general purpose input or output pin. During MCU expanded modes of operation, this pin is used
as the emulation chip select output (ECS). During MCU expanded modes of operation, this pin is used to
enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the
state of this pin is latched to the ROMON bit.
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 33
For all other modes the reset state of the ROMON bit is as follows:
Special single: ROMCTL = 1
Normal single: ROMCTL = 1
Emulation expanded wide: ROMCTL = 0
Emulation expanded narrow: ROMCTL = 0
Special test: ROMCTL = 0
Peripheral test: ROMCTL = 1
1.2.2.31 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0]
PK5-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins
provide the expanded address XADDR[19:14] for the external bus.
1.2.2.32 PM7 / TXCAN4 — Port M I/O Pin 7
PM7 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Scalable Controller Area Network controllers 4 (CAN4).
1.2.2.33 PM6 / RXCAN4 — Port M I/O Pin 6
PM6 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Scalable Controller Area Network controllers 4 (CAN4).
1.2.2.34 PM5 / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5
PM5 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Scalable Controller Area Network controllers 0 or 4 (CAN0 or CAN4). It can be configured as the serial
clock pin SCK of the Serial Peripheral Interface 0 (SPI0).
1.2.2.35 PM4 / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4
PM4 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Scalable Controller Area Network controllers 0 or 4 (CAN0 or CAN4). It can be configured as the master
output (during master mode) or slave input pin (during slave mode) MOSI for the Serial Peripheral
Interface 0 (SPI0).
1.2.2.36 PM3 / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3
PM3 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as the slave
select pin SS of the Serial Peripheral Interface 0 (SPI0).
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
34 Freescale Semiconductor
1.2.2.37 PM2 / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2
PM2 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as the master
input (during master mode) or slave output pin (during slave mode) MISO for the Serial Peripheral
Interface 0 (SPI0).
1.2.2.38 PM1 / TXCAN0 — Port M I/O Pin 1
PM1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Scalable Controller Area Network controller 0 (CAN0).
1.2.2.39 PM0 / RXCAN0 — Port M I/O Pin 0
PM0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Scalable Controller Area Network controller 0 (CAN0).
1.2.2.40 PP7 / KWP7 / PWM7 / SCK2 — Port P I/O Pin 7
PP7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output. It
can be configured as serial clock pin SCK of the Serial Peripheral Interface 2 (SPI2).
1.2.2.41 PP6 / KWP6 / PWM6 / SS2 — Port P I/O Pin 6
PP6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output. It
can be configured as slave select pin SS of the Serial Peripheral Interface 2 (SPI2).
1.2.2.42 PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5
PP5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 5 output. It
can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of
the Serial Peripheral Interface 2 (SPI2).
1.2.2.43 PP4 / KWP4 / PWM4 / MISO2 — Port P I/O Pin 4
PP4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 4 output. It
can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of
the Serial Peripheral Interface 2 (SPI2).
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 35
1.2.2.44 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3
PP3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output. It
can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1).
1.2.2.45 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2
PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output. It
can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1).
1.2.2.46 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1
PP1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 1 output. It
can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of
the Serial Peripheral Interface 1 (SPI1).
1.2.2.47 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0
PP0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output. It
can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of
the Serial Peripheral Interface 1 (SPI1).
1.2.2.48 PS7 / SS0 — Port S I/O Pin 7
PS6 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial
Peripheral Interface 0 (SPI0).
1.2.2.49 PS6 / SCK0 — Port S I/O Pin 6
PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial
Peripheral Interface 0 (SPI0).
1.2.2.50 PS5 / MOSI0 — Port S I/O Pin 5
PS5 is a general purpose input or output pin. It can be configured as master output (during master mode)
or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
1.2.2.51 PS4 / MISO0 — Port S I/O Pin 4
PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or
slave output pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
36 Freescale Semiconductor
1.2.2.52 PS3 / TXD1 — Port S I/O Pin 3
PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 1 (SCI1).
1.2.2.53 PS2 / RXD1 — Port S I/O Pin 2
PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 1 (SCI1).
1.2.2.54 PS1 / TXD0 — Port S I/O Pin 1
PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 0 (SCI0).
1.2.2.55 PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 0 (SCI0).
1.2.2.56 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0]
PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC7-IOC0 of the Timer (TIM).
1.2.3 Power Supply Pins
MC9S12KT256 power and ground pins are described below.
NOTE
All VSS pins must be connected together in the application.
1.2.3.1 VDDX,VSSX — Power Supply Pins for I/O Drivers
External power and ground for I/O drivers. Because fast signal transitions place high, short-duration
current demands on the power supply, use bypass capacitors with high-frequency characteristics and place
them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are
loaded.
1.2.3.2 VDDR, VSSR — Power Supply Pins for I/O Drivers & for Internal Voltage
Regulator
External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal
transitions place high, short-duration current demands on the power supply, use bypass capacitors with
high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements
depend on how heavily the MCU pins are loaded.
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 37
1.2.3.3 VDD1, VDD2, VSS1, VSS2 — Power Supply Pins for Internal Logic
Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high,
short-duration current demands on the power supply, use bypass capacitors with high-frequency
characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the
internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is
turned off, if VREGEN is tied to ground.
NOTE
No load allowed except for bypass capacitors.
1.2.3.4 VDDA, VSSA — Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to
digital converter. It also provides the reference for the internal voltage regulator. This allows the supply
voltage to the ATD and the reference voltage to be bypassed independently.
1.2.3.5 VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
1.2.3.6 VDDPLL, VSSPLL — Power Supply Pins for PLL
Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the
supply voltage to the Oscillator and PLL to be bypassed independently. This 2.5V voltage is generated by
the internal voltage regulator.
NOTE
No load allowed except for bypass capacitors.
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
38 Freescale Semiconductor
1.3 Memory Map and Register Definition
1.3.1 Device Memory Map
Table 1-5 shows the device register map of the MC9S12KT256 after reset.
Table 1-5. MC9S12KT256 Device Memory Map
Address Module Size
0x0000–0x0017 CORE (Ports A, B, E, Modes, Inits, Test) 24
0x0018 Reserved 1
0x0019 Voltage Regulator (VREG) 1
0x001A–0x001B Device ID register (PARTID) 2
0x001C–0x001F CORE (MEMSIZ, IRQ, HPRIO) 4
0x0020–0x002F CORE (DBG) 16
0x0030–0x0033 CORE (PPAGE, Port K) 4
0x0034–0x003F Clock and Reset Generator (PLL, RTI, COP) 12
0x0040–0x006F Standard Timer 16-bit 8 channels (TIM) 48
0x0070–0x007F Reserved 16
0x0080–0x009F Analog to Digital Converter 10-bit 8 channels (ATD0) 32
0x00A0–0x00C7 Reserved 40
0x00C8–0x00CF Serial Communications Interface 0 (SCI0) 8
0x00D0–0x00D7 Serial Communications Interface 1 (SCI1) 8
0x00D8–0x00DF Serial Peripheral Interface 0 (SPI0) 8
0x00E0–0x00E7 Inter Integrated Circuit Bus (IIC) 8
0x00E8–0x00EF Reserved 8
0x00F0–0x00F7 Serial Peripheral Interface 1 (SPI1) 8
0x00F8–0x00FF Serial Peripheral Interface 2 (SPI2) 8
0x0100–0x010F Flash Control Register 16
0x0110- 0x011B EEPROM Control Register 12
0x011C–0x011F Reserved 4
0x0120–0x013F Analog to Digital Converter 10-bit 8 channels (ATD1) 32
0x0140–0x017F Scalable Controller Area Network 0 (CAN0) 64
0x0180–0x01BF Scalable Controller Area Network 1 (CAN1) 64
0x01C0–0x023F Reserved 128
0x0240–0x027F Port Integration Module (PIM) 64
0x0280–0x02BF Scalable Controller Area Network 4 (CAN4) 64
0x02C0–0x02E7 Pulse Width Modulator 8-bit 8 channels (PWM) 40
0x02E8–0x03FF Reserved 280
VECTORS <‘ 0="" v,‘="" ,vectory="">
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 39
Figure 1-9 illustrates the full user configurable device memory map of MC9S12KT256.
Figure 1-9. MC9S12KT256 Memory Map
The figure shows a useful map, which is not the map out of reset. After reset the map is:
0x0000–0x03FF: Register Space
0x1000–0x3FFF: 12K RAM
0x0000–0x0FFF: 4K EEPROM (1K hidden behind Register Space)
0x0000
0xFFFF
0xC000
0x8000
0x4000
0x0400
0x1000
0xFF00
EXT
NORMAL
SINGLE CHIP EXPANDED SPECIAL
SINGLE CHIP
VECTORSVECTORS VECTORS
0xFF00
0xFFFF
BDM
(If Active)
0xC000
0xFFFF
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
0x8000
0xBFFF
16K Page Window
sixteen * 16K Flash EEPROM Pages
0x4000
0x7FFF 16K Fixed Flash EEPROM
0.5K, 1K, 2K or 4K Protected Sector
0x1000
0x3FFF
12K Bytes RAM
Mappable to any 16K Boundary
0x0000
0x0FFF
4K Bytes EEPROM
Mappable to any 4K Boundary
0x0000
0x03FF
1K Register Space
Mappable to any 2K Boundary
and alignable to top or bottom
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
40 Freescale Semiconductor
1.3.2 Detailed Register Map
The following tables show the detailed register map of the MC9S12KT256.
0x0000–0x000F MEBI Map 1 of 3 (HCS12 Multiplexed External Bus Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0000 PORTA RBit 7 6 5 4 3 2 1 Bit 0
W
0x0001 PORTB RBit 7 6 5 4 3 2 1 Bit 0
W
0x0002 DDRA RBit 7 6 5 4 3 2 1 Bit 0
W
0x0003 DDRB RBit 7 6 5 4 3 2 1 Bit 0
W
0x0004 Reserved R00000000
W
0x0005 Reserved R00000000
W
0x0006 Reserved R00000000
W
0x0007 Reserved R00000000
W
0x0008 PORTE RBit 7 6 5 4 3 2 Bit 1 Bit 0
W
0x0009 DDRE RBit 7 6 5 4 3 Bit 2 00
W
0x000A PEAR RNOACCE 0PIPOE NECLK LSTRE RDWE 00
W
0x000B MODE RMODC MODB MODA 0IVIS 0EMK EME
W
0x000C PUCR RPUPKE 00
PUPEE 00
PUPBE PUPAE
W
0x000D RDRIV RRDPK 00
RDPE 00
RDPB RDPA
W
0x000E EBICTL R0000000
ESTR
W
0x000F Reserved R00000000
W
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 41
0x0010–0x0014 MMC Map 1 of 4 (HCS12 Module Mapping Control)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0010 INITRM RRAM15 RAM14 RAM13 RAM12 RAM11 00
RAMHAL
W
0x0011 INITRG R0 REG14 REG13 REG12 REG11 000
W
0x0012 INITEE REE15 EE14 EE13 EE12 EE11 00
EEON
W
0x0013 MISC R0 0 0 0 EXSTR1 EXSTR0 ROMHM ROMON
W
0x0014 Reserved R00000000
W
0x0015–0x0016 INT Map 1 of 2 (HCS12 Interrupt)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0015 ITCR R0 0 0 WRINT ADR3 ADR2 ADR1 ADR0
W
0x0016 ITEST RINTE INTC INTA INT8 INT6 INT4 INT2 INT0
W
0x0017–0x0017 MMC Map 2 of 4 (HCS12 Module Mapping Control)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0017 Reserved R00000000
W
0x0018–0x0018 Miscellaneous Peripherals (Device Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0018 Reserved R00000000
W
0x0019–0x0019 VREG3V3 (Voltage Regulator)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0019 VREGCTRL R00000LVDS
LVIE LVIF
W
0x001A–0x001B Miscellaneous Peripherals (Device Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x001A PARTIDH R ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8
W
0x001B PARTIDL R ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
W
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
42 Freescale Semiconductor
0x001C–0x001D MMC Map 3 of 4 (HCS12 Module Mapping Control, Device Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x001C MEMSIZ0 R reg_sw0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_sw0
W
0x001D MEMSIZ1 R rom_sw1 rom_sw0 0 0 0 0 pag_sw1 pag_sw0
W
0x001E–0x001E MEBI Map 2 of 3 (HCS12 Multiplexed External Bus Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x001E INTCR RIRQE IRQEN 000000
W
0x001F–0x001F INT Map 2 of 2 (HCS12 Interrupt)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x001F HPRIO RPSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 0
W
0x0020–0x002F DBG Map 1 of 1 (HCS12 Debug)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0020 DBGC1 R DBGEN ARM TRGSEL BEGIN DBGBRK 0CAPMOD
—W
0x0021 DBGSC R AF BF CF 0 TRG
—W
0x0022 DBGTBH R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
—W
0x0023 DBGTBL R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
—W
0x0024 DBGCNT R TBF 0 CNT
—W
0x0025 DBGCCX R PAGSEL EXTCMP
—W
0x0026 DBGCCH R Bit 15 14 13 12 11 10 9 Bit 8
—W
0x0027 DBGCCL R Bit 7 6 5 4 3 2 1 Bit 0
—W
0x0028 DBGC2 R BKABEN FULL BDM TAGAB BKCEN TAGC RWCEN RWC
BKPCT0 W
0x0029 DBGC3 R BKAMBH BKAMBL BKBMBH BKBMBL RWAEN RWA RWBEN RWB
BKPCT1 W
0x002A DBGCAX R PAGSEL EXTCMP
BKP0X W
0x002B DBGCAH R Bit 15 14 13 12 11 10 9 Bit 8
BKP0H W
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 43
0x002C DBGCAL R Bit 7 6 5 4 3 2 1 Bit 0
BKP0L W
0x002D DBGCBX R PAGSEL EXTCMP
BKP1X W
0x002E DBGCBH R Bit 15 14 13 12 11 10 9 Bit 8
BKP1H W
0x002F DBGCBL R Bit 7 6 5 4 3 2 1 Bit 0
BKP1L W
0x0030–0x0031 MMC Map 4 of 4 (HCS12 Module Mapping Control)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0030 PPAGE R0 0 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0
W
0x0031 Reserved R00000000
W
0x0032–0x0033 MEBI Map 3 of 3 (HCS12 Multiplexed External Bus Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0032 PORTK RBit 7 6 5 4 3 2 1 Bit 0
W
0x0033 DDRK RBit 7 6 5 4 3 2 1 Bit 0
W
0x0034–0x003F CRG (Clock and Reset Generator)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0034 SYNR R0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0
W
0x0035 REFDV R0 0 0 0 REFDV3 REFDV2 REFDV1 REFDV0
W
0x0036 CTFLG
TEST ONLY
R TOUT7 TOUT6 TOUT5 TOUT4 TOUT3 TOUT2 TOUT1 TOUT0
W
0x0037 CRGFLG RRTIF PROF 0LOCKIF LOCK TRACK SCMIF SCM
W
0x0038 CRGINT RRTIE 00
LOCKIE 00
SCMIE 0
W
0x0039 CLKSEL RPLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI
W
0x003A PLLCTL RCME PLLON AUTO ACQ 0PRE PCE SCME
W
0x003B RTICTL R0 RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
W
0x0020–0x002F DBG Map 1 of 1 (HCS12 Debug) (continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
44 Freescale Semiconductor
0x003C COPCTL RWCOP RSBCK 000
CR2 CR1 CR0
W
0x003D FORBYP
TEST ONLY
RRTIBYP COPBYP 0PLLBYP 00
FCM 0
W
0x003E CTCTL
TEST ONLY
R TCTL7 TCTL6 TCTL5 TCTL4 TCLT3 TCTL2 TCTL1 TCTL0
W
0x003F ARMCOP R00000000
W Bit 7 6 5 4 3 2 1 Bit 0
0x0040–0x006FTIM (Timer 16 Bit 8 Channels) (Sheet 1 of 3)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0040 TIOS RIOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0
W
0x0041 CFORC R00000000
W FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0
0x0042 OC7M ROC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0
W
0x0043 OC7D ROC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0
W
0x0044 TCNT (hi) R Bit 15 14 13 12 11 10 9 Bit 8
W
0x0045 TCNT (lo) R Bit 7 6 5 4 3 2 1 Bit 0
W
0x0046 TSCR1 RTEN TSWAI TSFRZ TFFCA 0000
W
0x0047 TTOV RTOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0
W
0x0048 TCTL1 ROM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4
W
0x0049 TCTL2 ROM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0
W
0x004A TCTL3 REDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
W
0x004B TCTL4 REDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
W
0x004C TIE RC7I C6I C5I C4I C3I C2I C1I C0I
W
0x004D TSCR2 RTOI 000
TCRE PR2 PR1 PR0
W
0x004E TFLG1 RC7F C6F C5F C4F C3F C2F C1F C0F
W
0x004F TFLG2 RTOF 0000000
W
0x0034–0x003F CRG (Clock and Reset Generator) (continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 45
0x0050 TC0 (hi) RBit 15 14 13 12 11 10 9 Bit 8
W
0x0051 TC0 (lo) RBit 7 6 5 4 3 2 1 Bit 0
W
0x0052 TC1 (hi) RBit 15 14 13 12 11 10 9 Bit 8
W
0x0053 TC1 (lo) RBit 7 6 5 4 3 2 1 Bit 0
W
0x0054 TC2 (hi) RBit 15 14 13 12 11 10 9 Bit 8
W
0x0055 TC2 (lo) RBit 7 6 5 4 3 2 1 Bit 0
W
0x0056 TC3 (hi) RBit 15 14 13 12 11 10 9 Bit 8
W
0x0057 TC3 (lo) RBit 7 6 5 4 3 2 1 Bit 0
W
0x0058 TC4 (hi) RBit 15 14 13 12 11 10 9 Bit 8
W
0x0059 TC4 (lo) RBit 7 6 5 4 3 2 1 Bit 0
W
0x005A TC5 (hi) RBit 15 14 13 12 11 10 9 Bit 8
W
0x005B TC5 (lo) RBit 7 6 5 4 3 2 1 Bit 0
W
0x005C TC6 (hi) RBit 15 14 13 12 11 10 9 Bit 8
W
0x005D TC6 (lo) RBit 7 6 5 4 3 2 1 Bit 0
W
0x005E TC7 (hi) RBit 15 14 13 12 11 10 9 Bit 8
W
0x005F TC7 (lo) RBit 7 6 5 4 3 2 1 Bit 0
W
0x0060 PACTL R0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI
W
0x0061 PAFLG R000000
PAOVF PAIF
W
0x0062 PACNT (hi) RBit 7 6 5 4 3 2 1 Bit 0
W
0x0063 PACNT (lo) RBit 7 6 5 4 3 2 1 Bit 0
W
0x0064 Reserved R00000000
W
0x0065 Reserved R00000000
W
0x0066 Reserved R00000000
W
0x0040–0x006FTIM (Timer 16 Bit 8 Channels) (Sheet 2 of 3)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
46 Freescale Semiconductor
0x0067 Reserved R00000000
W
0x0068 Reserved R00000000
W
0x0069 Reserved R00000000
W
0x006A Reserved R00000000
W
0x006B Reserved R00000000
W
0x006C Reserved R00000000
W
0x006D Reserved R00000000
W
0x006E Reserved R00000000
W
0x006F Reserved R00000000
W
0x0070–0x007FReserved Space
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0070–
0x007F Reserved R00000000
W
0x0080–0x009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0080 ATD0CTL0 R00000
WRAP2 WRAP1 WRAP0
W
0x0081 ATD0CTL1 RETRIGSEL 0000
ETRIGCH2 ETRIGCH1 ETRIGCH0
W
0x0082 ATD0CTL2 RADPU AFFC AWAI ETRIGLE ETRIGP ETRIG ASCIE ASCIF
W
0x0083 ATD0CTL3 R0 S8C S4C S2C S1C FIFO FRZ1 FRZ0
W
0x0084 ATD0CTL4 RSRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
W
0x0085 ATD0CTL5 RDJM DSGN SCAN MULT 0CC CB CA
W
0x0086 ATD0STAT0 RSCF 0ETORF FIFOR 0 CC2 CC1 CC0
W
0x0087 Reserved R00000000
W
0x0040–0x006FTIM (Timer 16 Bit 8 Channels) (Sheet 3 of 3)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 47
0x0088 ATD0TEST0 R00000000
W
0x0089 ATD0TEST1 R0000000SC
W
0x008A Reserved R00000000
W
0x008B ATD0STAT1 R CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
W
0x008C Reserved R00000000
W
0x008D ATD0DIEN RIEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0
W
0x008E Reserved R00000000
W
0x008F PORTAD0 R PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
W
0x0090 ATD0DR0H R Bit 15 14 13 12 11 10 9 Bit 8
W
0x0091 ATD0DR0L R Bit 7 Bit 6 0 0 0 0 0 0
W
0x0092 ATD0DR1H R Bit 15 14 13 12 11 10 9 Bit 8
W
0x0093 ATD0DR1L R Bit 7 Bit 6 0 0 0 0 0 0
W
0x0094 ATD0DR2H R Bit 15 14 13 12 11 10 9 Bit 8
W
0x0095 ATD0DR2L R Bit 7 Bit 6 0 0 0 0 0 0
W
0x0096 ATD0DR3H R Bit 15 14 13 12 11 10 9 Bit 8
W
0x0097 ATD0DR3L R Bit 7 Bit 6 0 0 0 0 0 0
W
0x0098 ATD0DR4H R Bit 15 14 13 12 11 10 9 Bit 8
W
0x0099 ATD0DR4L R Bit 7 Bit 6 0 0 0 0 0 0
W
0x009A ATD0DR5H R Bit 15 14 13 12 11 10 9 Bit 8
W
0x009B ATD0DR5L R Bit 7 Bit 6 0 0 0 0 0 0
W
0x009C ATD0DR6H R Bit 15 14 13 12 11 10 9 Bit 8
W
0x0080–0x009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel) (continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
48 Freescale Semiconductor
0x009D ATD0DR6L R Bit 7 Bit 6 0 0 0 0 0 0
W
0x009E ATD0DR7H R Bit 15 14 13 12 11 10 9 Bit 8
W
0x009F ATD0DR7L R Bit 7 Bit 6 0 0 0 0 0 0
W
0x00A0–0x00C7 Reserved space
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x00A0–
0x00C7 Reserved R00000000
W
0x00C8–0x00CF SCI0 (Asynchronous Serial Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x00C8 SCI0BDH R0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8
W
0x00C9 SCI0BDL RSBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
W
0x00CA SCI0CR1 RLOOPS SCISWAI RSRC M WAKE ILT PE PT
W
0x00CB SCI0CR2 RTIE TCIE RIE ILIE TE RE RWU SBK
W
0x00CC SCI0SR1 R TDRE TC RDRF IDLE OR NF FE PF
W
0x00CD SCI0SR2 R00000
BRK13 TXDIR RAF
W
0x00CE SCI0DRH RR8 T8 000000
W
0x00CF SCI0DRL RR7R6R5R4R3R2R1R0
WT7T6T5T4T3T2T1T0
0x00D0–0x00D7 SCI1 (Asynchronous Serial Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x00D0 SCI1BDH R0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8
W
0x00D1 SCI1BDL RSBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
W
0x00D2 SCI1CR1 RLOOPS SCISWAI RSRC M WAKE ILT PE PT
W
0x00D3 SCI1CR2 RTIE TCIE RIE ILIE TE RE RWU SBK
W
0x0080–0x009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel) (continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 49
0x00D4 SCI1SR1 R TDRE TC RDRF IDLE OR NF FE PF
W
0x00D5 SCI1SR2 R00000
BRK13 TXDIR RAF
W
0x00D6 SCI1DRH RR8 T8 000000
W
0x00D7 SCI1DRL RR7R6R5R4R3R2R1R0
WT7T6T5T4T3T2T1T0
0x00D8–0x00DF SPI0 (Serial Peripheral Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x00D8 SPI0CR1 RSPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
W
0x00D9 SPI0CR2 R0 0 0MODFEN BIDIROE 0SPISWAI SPC0
W
0x00DA SPI0BR R0 SPPR2 SPPR1 SPPR0 0SPR2 SPR1 SPR0
W
0x00DB SPI0SR R SPIF 0 SPTEF MODF 0 0 0 0
W
0x00DC Reserved R00000000
W
0x00DD SPI0DR RBit 7 6 5 4 3 2 1 Bit 0
W
0x00DE Reserved R00000000
W
0x00DF Reserved R00000000
W
0x00E0–0x00E7 IIC (Inter IC Bus)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x00E0 IBAD RADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 0
W
0x00E1 IBFD RIBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0
W
0x00E2 IBCR RIBEN IBIE MS/SL TX/RX TXAK 00
IBSWAI
W RSTA
0x00E3 IBSR R TCF IAAS IBB IBAL 0SRW
IBIF RXAK
W
0x00E4 IBDR RD7 D6 D5 D4 D3 D2 D1 D 0
W
0x00D0–0x00D7 SCI1 (Asynchronous Serial Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
50 Freescale Semiconductor
0x00E5 Reserved R0 0 00 0 0 0 0
W
0x00E6 Reserved R00000000
W
0x00E7 Reserved R00000000
W
0x00E8–0x00EF Reserved Space
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x00E8–
0x00EF Reserved R00000000
W
0x00F0–0x00F7 SPI1 (Serial Peripheral Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x00F0 SPI1CR1 RSPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
W
0x00F1 SPI1CR2 R0 0 0MODFEN BIDIROE 0SPISWAI SPC0
W
0x00F2 SPI1BR R0 SPPR2 SPPR1 SPPR0 0SPR2 SPR1 SPR0
W
0x00F3 SPI1SR R SPIF 0 SPTEF MODF 0 0 0 0
W
0x00F4 Reserved R00000000
W
0x00F5 SPI1DR RBit 7 6 5 4 3 2 1 Bit 0
W
0x00F6 Reserved R00000000
W
0x00F7 Reserved R00000000
W
0x00F8–0x00FF SPI2 (Serial Peripheral Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x00F8 SPI2CR1 RSPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
W
0x00F9 SPI2CR2 R0 0 0MODFEN BIDIROE 0SPISWAI SPC0
W
0x00FA SPI2BR R0 SPPR2 SPPR1 SPPR0 0SPR2 SPR1 SPR0
W
0x00FB SPI2SR R SPIF 0 SPTEF MODF 0 0 0 0
W
0x00E0–0x00E7 IIC (Inter IC Bus)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 51
0x00FC Reserved R00000000
W
0x00FD SPI2DR RBit 7 6 5 4 3 2 1 Bit 0
W
0x00FE Reserved R00000000
W
0x00FF Reserved R00000000
W
0x0100–0x010F Flash Control Register
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0100 FCLKDIV R FDIVLD PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0
W
0x0101 FSEC R KEYEN RNV5 RNV4 RNV3 RNV2 SEC
W
0x0102 FTSTMOD R0 0 0 WRALL FDFD 000
W
0x0103 FCNFG RCBEIE CCIE KEYACC 0DFDIE 00
BKSEL
W
0x0104 FPROT RFPOPEN RNV6 FPHDIS FPHS FPLDIS FPLS
W
0x0105 FSTAT RCBEIF CCIF PVIOL ACCERR DFDIF BLANK 0 0
W
0x0106 FCMD R0 CMDB
W
0x0107 FCTL R NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0
W
0x0108 FADDRHI R FADDRHI
W
0x0109 FADDRLO R FADDRLO
W
0x010A FDATAHI R FDATAHI
W
0x010B FDATALO R FDATALO
W
0x010C Reserved R00000000
W
0x010D Reserved R00000000
W
0x010E Reserved R00000000
W
0x010F Reserved R00000000
W
0x00F8–0x00FF SPI2 (Serial Peripheral Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
52 Freescale Semiconductor
0x0110–0x011B EEPROM Control Register
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0110 ECLKDIV R EDIVLD PRDIV8 EDIV5 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0
W
0x0111 Reserved R00000000
W
0x0112 Reserved for
Factory Test
R00000000
W
0x0113 ECNFG RCBEIE CCIE 000000
W
0x0114 EPROT REPOPEN NV6 NV5 NV4 EPDIS EP2 EP1 EP0
W
0x0115 ESTAT RCBEIF CCIF PVIOL ACCERR 0BLANK 00
W
0x0116 ECMD R0 CMDB6 CMDB5 00
CMDB2 0CMDB0
W
0x0117 Reserved for
Factory Test
R00000000
W
0x0118 EADDRHI R00000
10 9 Bit 8
W
0x0119 EADDRLO RBit 7 6 5 4 3 2 1 Bit 0
W
0x011A EDATAHI RBit 15 14 13 12 11 10 9 Bit 8
W
0x011B EDATALO RBit 7 6 5 4 3 2 1 Bit 0
W
0x011C–0x011F Reserved Space
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x011C–
0x011F Reserved R00000000
W
0x0120–0x013F ATD1 (Analog-to-Digital Converter 10 Bit 8 Channel)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0120 ATD1CTL0 R00000
WRAP2 WRAP1 WRAP0
W
0x0121 ATD1CTL1 RETRIGSEL 0000
ETRIGCH2 ETRIGCH1 ETRIGCH0
W
0x0122 ATD1CTL2 RADPU AFFC AWAI ETRIGLE ETRIGP ETRIG ASCIE ASCIF
W
0x0123 ATD1CTL3 R0 S8C S4C S2C S1C FIFO FRZ1 FRZ0
W
0x0124 ATD1CTL4 RSRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
W
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 53
0x0125 ATD1CTL5 RDJM DSGN SCAN MULT 0CC CB CA
W
0x0126 ATD1STAT0 RSCF 0ETORF FIFOR 0 CC2 CC1 CC0
W
0x0127 Reserved R00000000
W
0x0128 ATD1TEST0 R00000000
W
0x0129 ATD1TEST1 R0000000SC
W
0x012A Reserved R00000000
W
0x012B ATD1STAT1 R CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
W
0x012C Reserved R00000000
W
0x012D ATD1DIEN RIEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0
W
0x012E Reserved R00000000
W
0x012F PORTAD1 R PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
W
0x0130 ATD1DR0H R Bit 15 14 13 12 11 10 9 Bit 8
W
0x0131 ATD1DR0L R Bit 7 Bit 6 0 0 0 0 0 0
W
0x0132 ATD1DR1H R Bit 15 14 13 12 11 10 9 Bit 8
W
0x0133 ATD1DR1L R Bit 7 Bit 6 0 0 0 0 0 0
W
0x0134 ATD1DR2H R Bit 15 14 13 12 11 10 9 Bit 8
W
0x0135 ATD1DR2L R Bit 7 Bit 6 0 0 0 0 0 0
W
0x0136 ATD1DR3H R Bit 15 14 13 12 11 10 9 Bit 8
W
0x0137 ATD1DR3L R Bit 7 Bit 6 0 0 0 0 0 0
W
0x0138 ATD1DR4H R Bit 15 14 13 12 11 10 9 Bit 8
W
0x0139 ATD1DR4L R Bit 7 Bit 6 0 0 0 0 0 0
W
0x013A ATD1DR5H R Bit 15 14 13 12 11 10 9 Bit 8
W
0x013B ATD1DR5L R Bit 7 Bit 6 0 0 0 0 0 0
W
0x0120–0x013F ATD1 (Analog-to-Digital Converter 10 Bit 8 Channel) (continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
54 Freescale Semiconductor
0x013C ATD1DR6H R Bit 15 14 13 12 11 10 9 Bit 8
W
0x013D ATD1DR6L R Bit 7 Bit 6 0 0 0 0 0 0
W
0x013E ATD1DR7H R Bit 15 14 13 12 11 10 9 Bit 8
W
0x013F ATD1DR7L R Bit 7 Bit 6 0 0 0 0 0 0
W
0x0140–0x017F CAN0 (MSCAN)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0140 CAN0CTL0 RRXFRM RXACT CSWAI SYNCH TIME WUPE SLPRQ INITRQ
W
0x0141 CAN0CTL1 RCANE CLKSRC LOOPB LISTEN 0WUPM SLPAK INITAK
W
0x0142 CAN0BTR0 RSJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
W
0x0143 CAN0BTR1 RSAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
W
0x0144 CAN0RFLG RWUPIF CSCIF RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF RXF
W
0x0145 CAN0RIER RWUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
W
0x0146 CAN0TFLG R00000
TXE2 TXE1 TXE0
W
0x0147 CAN0TIER R00000
TXEIE2 TXEIE1 TXEIE0
W
0x0148 CAN0TARQ R00000
ABTRQ2 ABTRQ1 ABTRQ0
W
0x0149 CAN0TAAK R 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0
W
0x014A CAN0TBSEL R00000
TX2 TX1 TX0
W
0x014B CAN0IDAC R0 0 IDAM1 IDAM0 0 IDHIT2 IDHIT1 IDHIT0
W
0x014C Reserved R00000000
W
0x014D Reserved R00000000
W
0x014E CAN0RXERR R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
W
0x014F CAN0TXERR R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
W
0x0120–0x013F ATD1 (Analog-to-Digital Converter 10 Bit 8 Channel) (continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 55
0x0150–
0x0153 CAN0IDAR0–
CAN0IDAR3
RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x0154–
0x0157 CAN0IDMR0–
CAN0IDMR3
RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x0158–
0x015B CAN0IDAR4–
CAN0IDAR7
RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x015C–
0x015F CAN0IDMR4–
CAN0IDMR7
RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x0160–
0x016F CAN0RXFG R FOREGROUND RECEIVE BUFFER (see Table 1-6)
W
0x0170–
0x017F CAN0TXFG RFOREGROUND TRANSMIT BUFFER (see Table 1-6)
W
Table 1-6. Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x00
Extended ID R ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
Standard ID R ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3
CANxRIDR0 W
0x01
Extended ID R ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15
Standard ID R ID2 ID1 ID0 RTR IDE=0
CANxRIDR1 W
0x02
Extended ID R ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7
Standard ID R
CANxRIDR2 W
0x03
Extended ID R ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR
Standard ID R
CANxRIDR3 W
0x04–
0x0B CANxRDSR0–
CANxRDSR7
R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
W
0x0C CANRxDLR RDLC3 DLC2 DLC1 DLC0
W
0x0D Reserved R
W
0x0E CANxRTSRH R TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8
W
0x0F CANxRTSRL R TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0
W
0x10
Extended ID R ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
CANxTIDR0 W
Standard ID R ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3
W
0x10
Extended ID R ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15
CANxTIDR1 W
Standard ID R ID2 ID1 ID0 RTR IDE=0
W
0x0140–0x017F CAN0 (MSCAN)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
56 Freescale Semiconductor
0x12
Extended ID R ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7
CANxTIDR2 W
Standard ID R
W
0x13
Extended ID R ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR
CANxTIDR3 W
Standard ID R
W
0x14–
0x1B CANxTDSR0–
CANxTDSR7
RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
W
0x1C CANxTDLR RDLC3 DLC2 DLC1 DLC0
W
0x1D CONxTTBPR RPRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0
W
0x1E CANxTTSRH R TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8
W
0x1F CANxTTSRL R TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0
W
0x0180–0x01BF CAN1 (MSCAN)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0180 CAN1CTL0 RRXFRM RXACT CSWAI SYNCH TIME WUPE SLPRQ INITRQ
W
0x0181 CAN1CTL1 RCANE CLKSRC LOOPB LISTEN 0WUPM SLPAK INITAK
W
0x0182 CAN1BTR0 RSJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
W
0x0183 CAN1BTR1 RSAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
W
0x0184 CAN1RFLG RWUPIF CSCIF RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF RXF
W
0x0185 CAN1RIER RWUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
W
0x0186 CAN1TFLG R00000
TXE2 TXE1 TXE0
W
0x0187 CAN1TIER R00000
TXEIE2 TXEIE1 TXEIE0
W
0x0188 CAN1TARQ R00000
ABTRQ2 ABTRQ1 ABTRQ0
W
0x0189 CAN1TAAK R 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0
W
0x018A CAN1TBSEL R00000
TX2 TX1 TX0
W
0x018B CAN1IDAC R0 0 IDAM1 IDAM0 0 IDHIT2 IDHIT1 IDHIT0
W
Table 1-6. Detailed MSCAN Foreground Receive and Transmit Buffer Layout (continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 57
0x018C Reserved R00000000
W
0x018D Reserved R00000000
W
0x018E CAN1RXERR R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
W
0x018F CAN1TXERR R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
W
0x0190 CAN1IDAR0 RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x0191 CAN1IDAR1 RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x0192 CAN1IDAR2 RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x0193 CAN1IDAR3 RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x0194 CAN1IDMR0 RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x0195 CAN1IDMR1 RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x0196 CAN1IDMR2 RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x0197 CAN1IDMR3 RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x0198 CAN1IDAR4 RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x0199 CAN1IDAR5 RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x019A CAN1IDAR6 RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x019B CAN1IDAR7 RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x019C CAN1IDMR4 RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x019D CAN1IDMR5 RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x019E CAN1IDMR6 RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x019F CAN1IDMR7 RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x01A0–
0x01AF CAN1RXFG R FOREGROUND RECEIVE BUFFER (see Table 1-6)
W
0x01B0–
0x01BF CAN1TXFG RFOREGROUND TRANSMIT BUFFER (see Table 1-6)
W
0x0180–0x01BF CAN1 (MSCAN)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
58 Freescale Semiconductor
0x01C0–0x023F Reserved Space
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x01C0–
0x023F Reserved R00000000
W
0x0240–0x027F PIM (Port Integration Module) (Sheet 1 of 3)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0240 PTT RPTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0
W
0x0241 PTIT R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0
W
0x0242 DDRT RDDRT7 DDRT7 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
W
0x0243 RDRT RRDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0
W
0x0244 PERT RPERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0
W
0x0245 PPST RPPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0
W
0x0246 Reserved R00000000
W
0x0247 Reserved R00000000
W
0x0248 PTS RPTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0
W
0x0249 PTIS R PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0
W
0x024A DDRS RDDRS7 DDRS7 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0
W
0x024B RDRS RRDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0
W
0x024C PERS RPERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0
W
0x024D PPSS RPPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0
W
0x024E WOMS RWOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0
W
0x024F Reserved R00000000
W
0x0250 PTM RPTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0
W
0x0251 PTIM R PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0
W
0x0252 DDRM RDDRM7 DDRM7 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0
W
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 59
0x0253 RDRM RRDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0
W
0x0254 PERM RPERM7 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0
W
0x0255 PPSM RPPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0
W
0x0256 WOMM RWOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
W
0x0257 MODRR R0MODRR6 MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0
W
0x0258 PTP RPTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
W
0x0259 PTIP R PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0
W
0x025A DDRP RDDRP7 DDRP7 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
W
0x025B RDRP RRDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0
W
0x025C PERP RPERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0
W
0x025D PPSP RPPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSS0
W
0x025E PIEP RPIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0
W
0x025F PIFP RPIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0
W
0x0260 PTH RPTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0
W
0x0261 PTIH R PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0
W
0x0262 DDRH RDDRH7 DDRH7 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0
W
0x0263 RDRH RRDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0
W
0x0264 PERH RPERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0
W
0x0265 PPSH RPPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0
W
0x0266 PIEH RPIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0
W
0x0267 PIFH RPIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0
W
0x0268 PTJ RPTJ7 PTJ6 0000
PTJ1 PTJ0
W
0x0269 PTIJ R PTIJ7 PTIJ6 0 0 0 0 PTIJ1 PTIJ0
W
0x0240–0x027F PIM (Port Integration Module) (Sheet 2 of 3)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
60 Freescale Semiconductor
0x026A DDRJ RDDRJ7 DDRJ7 0000
DDRJ1 DDRJ0
W
0x026B RDRJ RRDRJ7 RDRJ6 0000
RDRJ1 RDRJ0
W
0x026C PERJ RPERJ7 PERJ6 0000
PERJ1 PERJ0
W
0x026D PPSJ RPPSJ7 PPSJ6 0000
PPSJ1 PPSJ0
W
0x026E PIEJ RPIEJ7 PIEJ6 0000
PIEJ1 PIEJ0
W
0x026F PIFJ RPIFJ7 PIFJ6 0000
PIFJ1 PIFJ0
W
0x0270–
0x027F Reserved R
0x0280–0x02BF CAN4 (MSCAN)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0280 CAN4CTL0 RRXFRM RXACT CSWAI SYNCH TIME WUPE SLPRQ INITRQ
W
0x0281 CAN4CTL1 RCANE CLKSRC LOOPB LISTEN 0WUPM SLPAK INITAK
W
0x0282 CAN4BTR0 RSJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
W
0x0283 CAN4BTR1 RSAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
W
0x0284 CAN4RFLG RWUPIF CSCIF RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF RXF
W
0x0285 CAN4RIER RWUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
W
0x0286 CAN4TFLG R00000
TXE2 TXE1 TXE0
W
0x0287 CAN4TIER R00000
TXEIE2 TXEIE1 TXEIE0
W
0x0288 CAN4TARQ R00000
ABTRQ2 ABTRQ1 ABTRQ0
W
0x0289 CAN4TAAK R 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0
W
0x028A CAN4TBSEL R00000
TX2 TX1 TX0
W
0x028B CAN4IDAC R0 0 IDAM1 IDAM0 0 IDHIT2 IDHIT1 IDHIT0
W
0x028C Reserved R00000000
W
0x028D Reserved R00000000
W
0x0240–0x027F PIM (Port Integration Module) (Sheet 3 of 3)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 61
0x028E CAN4RXERR R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
W
0x028F CAN4TXERR R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
W
0x0290 CAN4IDAR0 RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x0291 CAN4IDAR1 RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x0292 CAN4IDAR2 RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x0293 CAN4IDAR3 RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x0294 CAN4IDMR0 RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x0295 CAN4IDMR1 RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x0296 CAN4IDMR2 RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x0297 CAN4IDMR3 RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x0298 CAN4IDAR4 RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x0299 CAN4IDAR5 RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x029A CAN4IDAR6 RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x029B CAN4IDAR7 RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x029C CAN4IDMR4 RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x029D CAN4IDMR5 RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x029E CAN4IDMR6 RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x029F CAN4IDMR7 RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x02A0–
0x02AF CAN4RXFG R FOREGROUND RECEIVE BUFFER (see Table 1-6)
W
0x02B0–
0x02BF CAN4TXFG RFOREGROUND TRANSMIT BUFFER (see Table 1-6)
W
0x0280–0x02BF CAN4 (MSCAN) (continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
62 Freescale Semiconductor
0x02C0–0x02E7 PWM (Pulse Width Modulator 8 Bit 8 Channel)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x02C0 PWME RPWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0
W
0x02C1 PWMPOL RPPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0
W
0x02C2 PWMCLK RPCLK7 PCLK6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0
W
0x02C3 PWMPRCLK R0 PCKB2 PCKB1 PCKB0 0PCKA2 PCKA1 PCKA0
W
0x02C4 PWMCAE RCAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0
W
0x02C5 PWMCTL RCON67 CON45 CON23 CON01 PSWAI PFRZ 00
W
0x02C6 PWMTST
Test Only
R00000000
W
0x02C7 PWMPRSC R00000000
W
0x02C8 PWMSCLA RBit 7 6 5 4 3 2 1 Bit 0
W
0x02C9 PWMSCLB RBit 7 6 5 4 3 2 1 Bit 0
W
0x02CA PWMSCNTA R00000000
W
0x02CB PWMSCNTB R00000000
W
0x02CC PWMCNT0 R Bit 7 6 5 4 3 2 1 Bit 0
W00000000
0x02CD PWMCNT1 R Bit 7 6 5 4 3 2 1 Bit 0
W00000000
0x02CE PWMCNT2 R Bit 7 6 5 4 3 2 1 Bit 0
W00000000
0x02CF PWMCNT3 R Bit 7 6 5 4 3 2 1 Bit 0
W00000000
0x02D0 PWMCNT4 R Bit 7 6 5 4 3 2 1 Bit 0
W00000000
0x02D1 PWMCNT5 R Bit 7 6 5 4 3 2 1 Bit 0
W00000000
0x02D2 PWMCNT6 R Bit 7 6 5 4 3 2 1 Bit 0
W00000000
0x02D3 PWMCNT7 R Bit 7 6 5 4 3 2 1 Bit 0
W00000000
0x02D4 PWMPER0 RBit 7 6 5 4 3 2 1 Bit 0
W
0x02D5 PWMPER1 RBit 7 6 5 4 3 2 1 Bit 0
W
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 63
0x02D6 PWMPER2 RBit 7 6 5 4 3 2 1 Bit 0
W
0x02D7 PWMPER3 RBit 7 6 5 4 3 2 1 Bit 0
W
0x02D8 PWMPER4 RBit 7 6 5 4 3 2 1 Bit 0
W
0x02D9 PWMPER5 RBit 7 6 5 4 3 2 1 Bit 0
W
0x02DA PWMPER6 RBit 7 6 5 4 3 2 1 Bit 0
W
0x02DB PWMPER7 RBit 7 6 5 4 3 2 1 Bit 0
W
0x02DC PWMDTY0 RBit 7 6 5 4 3 2 1 Bit 0
W
0x02DD PWMDTY1 RBit 7 6 5 4 3 2 1 Bit 0
W
0x02DE PWMDTY2 RBit 7 6 5 4 3 2 1 Bit 0
W
0x02DF PWMDTY3 RBit 7 6 5 4 3 2 1 Bit 0
W
0x02E0 PWMDTY4 RBit 7 6 5 4 3 2 1 Bit 0
W
0x02E1 PWMDTY5 RBit 7 6 5 4 3 2 1 Bit 0
W
0x02E2 PWMDTY6 RBit 7 6 5 4 3 2 1 Bit 0
W
0x02E3 PWMDTY7 RBit 7 6 5 4 3 2 1 Bit 0
W
0x02E4 PWMSDN RPWMIF PWMIE PWMRSTRT PWMLVL 0PWM7IN PWM7INL PWM7ENA
W
0x02E5 Reserved R00000000
W
0x02E6 Reserved R00000000
W
0x02E7 Reserved R00000000
W
0x02E8–0x03FF Reserved Space
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x02E8–
0x03FF Reserved R00000000
W
0x02C0–0x02E7 PWM (Pulse Width Modulator 8 Bit 8 Channel) (continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
64 Freescale Semiconductor
1.3.3 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B after
reset. The read-only value is a unique part ID for each revision of the chip. Table 1-7 shows the assigned
part ID number. Chapter 2, “256 Kbyte ECC Flash Module (S12FTS256K2ECCV1) is for the xL33V
mask set. Chapter 3, “256 Kbyte ECC Flash Module (S12FTS256K2ECCV2) is for the 0M17D mas set.
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses 0x001C
and 0x001D after reset). Table 1-8 shows the read-only values of these registers. Refer to HCS12 Module
Mapping and Control (MMC) block description chapter for further details.
Table 1-7. Assigned Part ID Numbers
Device Mask Set Number Part ID1
1The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-8: Minor family identifier
Bit 7-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor - non full - mask set revision
MC9S12KT256 0L33V 0x7000
MC9S12KT256 1L33V 0x7001
MC9S12KT256 2L33V 0x7002
MC9S12KT256 3L33V 0x7003
MC9S12KT256 0M17D 0x7010
Table 1-8. Memory Size Registers
Device Register Name Value
MC9S12KT256 MEMSIZ0 0x25
MC9S12KT256 MEMSIZ1 0x81
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 65
1.4 System Clock Description
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 1-10 shows the clock connections from the CRG to all modules. Consult the CRG Block Guide for
details on clock generation.
Figure 1-10. Clock Connections
1.5 Modes of Operation
Eight possible modes determine the operating configuration of the MC9S12KT256. Each mode has an
associated default memory map and external bus configuration controlled by a further pin.
Three low power modes exist for the device.
1.5.1 Chip Configuration Summary
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (Table 1-9). The MODC, MODB, and MODA bits in the MODE register show the current operating
mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting
of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory
CRG BUS CLOCK
CORE CLOCK
EXTAL
XTAL
OSCILLATOR CLOCK
HCS12 CORE
Flash
BDM
OSC
CPU
MEBI MMC
INT DBG
IIC
RAM
SCI0, SCI1
PWM
ATD
EEPROM
TIM
SPI0, SPI1, SPI2
CAN0, CAN1, CAN4
PIM
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
66 Freescale Semiconductor
map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched
into the ROMON bit in the MISC register on the rising edge of the reset signal.
For further explanation on the modes refer to the HCS12 MEBI block description chapter.
Table 1-9. Mode Selection
BKGD =
MODC PE6 =
MODB PE5 =
MODA PK7 =
ROMCTL ROMON
Bit Mode Description
0 0 0 X 1 Special Single Chip, BDM allowed and ACTIVE. BDM is
allowed in all other modes but a serial command is
required to make BDM active.
00101Emulation Expanded Narrow, BDM allowed
10
0 1 0 X 0 Special Test (Expanded Wide), BDM allowed
01101Emulation Expanded Wide, BDM allowed
10
1 0 0 X 1 Normal Single Chip, BDM allowed
10100Normal Expanded Narrow, BDM allowed
11
1 1 0 X 1 Peripheral; BDM allowed but bus operations would cause
bus conflicts (must not be used)
11100Normal Expanded Wide, BDM allowed
11
Table 1-10. Clock Selection Based on PE7
PE7 = XCLKS Description
1 Loop Controlled Pierce Oscillator selected
0 Full Swing Pierce Oscillator or external clock selected
Table 1-11. Voltage Regulator VREGEN
VREGEN Description
1 Internal Voltage Regulator enabled
0 Internal Voltage Regulator disabled, VDD1,2 and
VDDPLL must be supplied externally with 2.5V
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 67
1.5.2 Security
The device will make available a security feature preventing the unauthorized read and write of the
memory contents. This feature allows:
Protection of the contents of FLASH,
Protection of the contents of EEPROM,
Operation in single-chip mode,
Operation from external memory with internal FLASH and EEPROM disabled.
The user must be reminded that part of the security must lie with the user’s code. An extreme example
would be user’s code that dumps the contents of the internal program. This code would defeat the purpose
of security. At the same time the user may also wish to put a back door in the user’s program. An example
of this is the user downloads a key through the SCI which allows access to a programming routine that
updates parameters stored in EEPROM.
1.5.2.1 Securing the Microcontroller
Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by
programming the security bits located in the FLASH module. These non-volatile bits will keep the part
secured through resetting the part and through powering down the part.
The security byte resides in a portion of the Flash array.
Check the Flash Block Guide for more details on the security configuration.
1.5.2.2 Operation of the Secured Microcontroller
1.5.2.2.1 Normal Single Chip Mode
This will be the most common usage of the secured part. Everything will appear the same as if the part was
not secured with the exception of BDM operation. The BDM operation will be blocked.
1.5.2.2.2 Executing from External Memory
The user may wish to execute from external space with a secured microcontroller. This is accomplished
by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM
operations will be blocked.
1.5.2.3 Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be
done through an external program in expanded mode.
Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode.
This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program
completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally
done through the BDM, but the user could also change to expanded mode (by writing the mode bits
through the BDM) and jumping to an external program (again through BDM commands). Note that if the
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
68 Freescale Semiconductor
part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be
secured again.
1.5.3 Low Power Modes
The microcontroller features three main low power modes. Consult the respective Block Guide for
information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of
information about the clock system is the Clock and Reset Generator Guide (CRG).
1.5.3.1 Stop
Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static
mode. Wake up from this mode can be done via reset or external interrupts.
1.5.3.2 Pseudo Stop
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running
and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are
turned off. This mode consumes more current than the full STOP mode, but the wake up time from this
mode is significantly shorter.
1.5.3.3 Wait
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU signals (address and data bus) will be fully static. All peripherals stay
active. For further power consumption the peripherals can individually turn off their local clocks.
1.5.3.4 Run
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save
power.
1.6 Resets and Interrupts
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and
interrupts. Both local masking and CCR masking are included as listed in Table 1-12. System resets can
be generated through external control of the RESET pin, through the clock and reset generator module
CRG or through the low voltage reset (LVR) generator of the voltage regulator module. Refer to the CRG
and VREG block description chapters for detailed information on reset generation.
1.6.1 Vectors
1.6.1.1 Vector Table
Table 1-12 lists interrupt sources and vectors in default order of priority.
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 69
Table 1-12. Interrupt Vector Locations
Vector
Address Interrupt
Source CCR
Mask Local
Enable HPRIO Value
to Elevate
0xFFFE, 0xFFFF External Reset, Power On Reset or Low
Voltage Reset (see CRG Flags Register
to determine reset source)
None None
0xFFFC, 0xFFFD Clock Monitor fail reset None PLLCTL (CME, FCME)
0xFFFA, 0xFFFB COP failure reset None COP rate select
0xFFF8, 0xFFF9 Unimplemented instruction trap None None
0xFFF6, 0xFFF7 SWI None None
0xFFF4, 0xFFF5 XIRQ X Bit None
0xFFF2, 0xFFF3 IRQ I Bit IRQCR (IRQEN) 0xF2
0xFFF0, 0xFFF1 Real Time Interrupt I Bit CRGINT (RTIE) 0xF0
0xFFEE, 0xFFEF Standard Timer channel 0 I Bit TIE (C0I) 0xEE
0xFFEC, 0xFFED Standard Timer channel 1 I Bit TIE (C1I) 0xEC
0xFFEA, 0xFFEB Standard Timer channel 2 I Bit TIE (C2I) 0xEA
0xFFE8, 0xFFE9 Standard Timer channel 3 I Bit TIE (C3I) 0xE8
0xFFE6, 0xFFE7 Standard Timer channel 4 I Bit TIE (C4I) 0xE6
0xFFE4, 0xFFE5 Standard Timer channel 5 I Bit TIE (C5I) 0xE4
0xFFE2, 0xFFE3 Standard Timer channel 6 I Bit TIE (C6I) 0xE2
0xFFE0, 0xFFE1 Standard Timer channel 7 I Bit TIE (C7I) 0xE0
0xFFDE, 0xFFDF Standard Timer overflow I Bit TSCR2 (TOI) 0xDE
0xFFDC, 0xFFDD Pulse accumulator overflow I Bit PACTL (PAOVI) 0xDC
0xFFDA, 0xFFDB Pulse accumulator input edge I Bit PACTL (PAI) 0xDA
0xFFD8, 0xFFD9 SPI0 I Bit SPICR1 (SPIE, SPTIE) 0xD8
0xFFD6, 0xFFD7 SCI0 I Bit SCICR2
(TIE, TCIE, RIE, ILIE) 0xD6
0xFFD4, 0xFFD5 SCI1 I Bit SCICR2
(TIE, TCIE, RIE, ILIE) 0xD4
0xFFD2, 0xFFD3 ATD0 I Bit ATDCTL2 (ASCIE) 0xD2
0xFFD0, 0xFFD1 ATD1 I Bit ATDCTL2 (ASCIE) 0xD0
0xFFCE, 0xFFCF Port J I Bit PIEJ
(PIEJ7, PIEJ6, PIEJ1, PIEJ0) 0xCE
0xFFCC, 0xFFCD Port H I Bit PIEH (PIEH7–0) 0xCC
0xFFCA, 0xFFCB Reserved I Bit Reserved 0xCA
0xFFC8, 0xFFC9 I Bit 0xC8
0xFFC6, 0xFFC7 CRG PLL lock I Bit CRGINT (LOCKIE) 0xC6
0xFFC4, 0xFFC5 CRG Self Clock Mode I Bit CRGINT (SCMIE) 0xC4
0xFFC2, 0xFFC3 FLASH Double Fault Detect I Bit FCNFG (DFDIE) 0xC2
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
70 Freescale Semiconductor
0xFFC0, 0xFFC1 IIC Bus I Bit IBCR (IBIE) 0xC0
0xFFBE, 0xFFBF SPI1 I Bit SPICR1 (SPIE, SPTIE) 0xBE
0xFFBC, 0xFFBD SPI2 I Bit SPICR1 (SPIE, SPTIE) 0xBC
0xFFBA, 0xFFBB EEPROM command I Bit ECNFG (CCIE, CBEIE) 0xBA
0xFFB8, 0xFFB9 FLASH command I Bit FCNFG (CCIE, CBEIE) 0xB8
0xFFB6, 0xFFB7 CAN0 wake-up I Bit CAN0RIER (WUPIE) 0xB6
0xFFB4, 0xFFB5 CAN0 errors I Bit CAN0RIER (CSCIE, OVRIE) 0xB4
0xFFB2, 0xFFB3 CAN0 receive I Bit CAN0RIER (RXFIE) 0xB2
0xFFB0, 0xFFB1 CAN0 transmit I Bit CAN0TIER (TXEIE2–TXEIE0) 0xB0
0xFFAE, 0xFFAF CAN1 wake-up I Bit CAN1RIER (WUPIE) 0xAE
0xFFAC, 0xFFAD CAN1 errors I Bit CAN1RIER (CSCIE, OVRIE) 0xAC
0xFFAA, 0xFFAB CAN1 receive I Bit CAN1RIER (RXFIE) 0xAA
0xFFA8, 0xFFA9 CAN1 transmit I Bit CAN1TIER (TXEIE2–TXEIE0) 0xA8
0xFFA6, 0xFFA7
Reserved
I Bit
Reserved
0xA6
0xFFA4, 0xFFA5 I Bit 0xA4
0xFFA2, 0xFFA3 I Bit 0xA2
0xFFA0, 0xFFA1 I Bit 0xA0
0xFF9E, 0xFF9F I Bit 0x9E
0xFF9C, 0xFF9D I Bit 0x9C
0xFF9A, 0xFF9B I Bit 0x9A
0xFF98, 0xFF99 I Bit 0x98
0xFF96, 0xFF97 CAN4 wake-up I Bit CAN4RIER (WUPIE) 0x96
0xFF94, 0xFF95 CAN4 errors I Bit CAN4RIER (CSCIE, OVRIE) 0x94
0xFF92, 0xFF93 CAN4 receive I Bit CAN4RIER (RXFIE) 0x92
0xFF90, 0xFF91 CAN4 transmit I Bit CAN4TIER (TXEIE2–TXEIE0) 0x90
0xFF8E, 0xFF8F Port P I Bit PIEP (PIEP7–0) 0x8E
0xFF8C, 0xFF8D PWM Emergency Shutdown I Bit PWMSDN (PWMIE) 0x8C
0xFF8A, 0xFF8B VREG Low Voltage Interrupt I Bit CTRL0 (LVIE) 0x8A
0xFF80 to
0xFF89 Reserved
Table 1-12. Interrupt Vector Locations (continued)
Vector
Address Interrupt
Source CCR
Mask Local
Enable HPRIO Value
to Elevate
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 71
1.6.2 Resets
Resets are a subset of the interrupts featured inTable 1-12. The different sources capable of generating a
system reset are summarized in Table 1-13.
1.6.2.1 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module block description chapters for register reset states.
Refer to the PIM block description chapter for reset configurations of all peripheral module ports.
Refer to Table 1-5 for locations of the memories depending on the operating mode after reset.
The RAM array is not automatically initialized out of reset.
Table 1-13. Reset Summary
Reset Priority Source Vector
Power-on Reset 1 CRG Module 0xFFFE, 0xFFFF
External Reset 1 RESET pin 0xFFFE, 0xFFFF
Low Voltage Reset 1 VREG Module 0xFFFE, 0xFFFF
Clock Monitor Reset 2 CRG Module 0xFFFC, 0xFFFD
COP Watchdog Reset 3 CRG Module 0xFFFA, 0xFFFB
Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
72 Freescale Semiconductor
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 73
Chapter 2
256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
2.1 Introduction
This document describes the FTS256K2ECC module that includes a 256 Kbyte Flash (nonvolatile)
memory with built-in Error Code Correction (ECC). The Flash memory may be read as either bytes,
aligned words, or misaligned words. Read access time is one bus cycle for bytes and aligned words, and
two bus cycles for misaligned words.
The Flash memory is ideal for program and data storage for single-supply applications allowing for field
reprogramming without requiring external voltage sources for program or erase. Program and erase
functions are controlled by a command driven interface. The Flash module supports both block erase and
sector erase. An erased bit reads 1 and a programmed bit reads 0. The high voltage required to program
and erase the Flash memory is generated internally. It is not possible to read from a Flash block while it is
being erased or programmed.
The ECC logic is included in the Flash module with the program and erase operations automatically
generating the ECC parity bits. The ECC logic implements a modified Hamming code capable of
correcting single bit faults and detecting double bit faults in each word of the Flash memory.
CAUTION
A Flash word must be in the erased state before being programmed.
Cumulative programming of bits within a Flash word is not allowed and will
result in invalid data stored.
Table 2-1. FTS256K2ECC Revision History
Version
Number Revision
Date Author Description of Changes
V01.03 04APR05 1. Reformat document.
V01.04 15SEP06 1. Add address range restriction to data compress command.
2. Describe algorithm for data compress command.
3. Add note about margin read during data compress command.
V01.05 05DEC06 1. Clarify in Section 2.3.2.7,Section 2.4.1.2,Section 2.4.1.4 that
ACCERR, PVIOL, FAIL flags must be clear in all banked FSTAT
registers before starting a command write sequence.
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
74 Freescale Semiconductor
2.1.1 Glossary
Banked Register — A memory-mapped register operating on one Flash block which shares the same
register address as the equivalent registers for the other Flash blocks. The active register bank is selected
by the BKSEL bit in the FCNFG register.
Command Write Sequence — A three-step MCU instruction sequence to execute built-in algorithms
(including program and erase) on the Flash memory.
Common Register — A memory-mapped register which operates on all Flash blocks.
2.1.2 Features
256 Kbytes of Flash memory comprised of two 128 Kbyte blocks with each block divided into 128
sectors of 1024 bytes with every word (two bytes) accompanied by 6 ECC parity bits
Single bit fault correction per word during read operations
Automated program and erase algorithm with generation of ECC parity bits
Interrupts on Flash command completion, command buffer empty and double bit fault detection
Fast sector erase and word program operation
2-stage command pipeline for faster multi-word program times
Sector erase abort feature for critical interrupt response
Flexible protection scheme to prevent accidental program or erase
Single power supply for all Flash operations including program and erase
Security feature to prevent unauthorized access to the Flash memory
Code integrity check using built-in data compression
2.1.3 Modes of Operation
Program, erase, erase verify, and data compress operations (please refer to Section 2.4.1 for details).
2.1.4 Block Diagram
A block diagram of the Flash module is shown in Figure 2-1.
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 75
Figure 2-1. FTS256K2ECC Block Diagram
2.2 External Signal Description
The Flash module contains no signals that connect off-chip.
FTS256K2ECC
Clock
Divider
Command Pipeline
comm2
FCLK
addr2
data2
comm1
addr1
data1
Flash Block 1
64K * 22 Bits
Protection
Security
Error Detection
and Correction
Flash Block 0
64K * 22 Bits
Command
Interface
Common
Registers
Banked
Registers
sector 0
sector 1
sector 127
sector 0
sector 1
sector 127
Flash Block 0-1
Oscillator
Clock
Command
Interrupt
Request
Double Fault
Detect Interrupt
Request
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
76 Freescale Semiconductor
2.3 Memory Map and Register Definition
This subsection describes the memory map and registers for the Flash module.
2.3.1 Module Memory Map
The Flash memory map is shown in Figure 2-2. The HCS12 architecture places the Flash memory
addresses between 0x4000 and 0xFFFF which corresponds to three 16-Kbyte pages. The content of the
HCS12 core PPAGE register is used to map the logical middle page ranging from address 0x8000 to
0xBFFF to any physical 16 Kbyte page in the Flash memory. By placing 0x3E or 0x3F in the HCS12 Core
PPAGE register, the associated 16 Kbyte pages appear twice in the MCU memory map.
The FPROT register, described in Section 2.3.2.5, “Flash Protection Register (FPROT)”, can be set to
globally protect a Flash block. However, three separate memory regions, one growing upward from the
first address in the next-to-last page in the Flash block (called the lower region), one growing downward
from the last address in the last page in the Flash block (called the higher region), and the remaining
addresses in the Flash block, can be activated for protection. The Flash locations of these protectable
regions are shown in Table 2-3. The higher address region of Flash block 0 is mainly targeted to hold the
boot loader code because it covers the vector space. The lower address region of any Flash block can be
used for EEPROM emulation in an MCU without an EEPROM module because it can remain unprotected
while the remaining addresses are protected from program or erase.
Security information that allows the MCU to restrict access to the Flash module is stored in the Flash
configuration field found in Flash block 0, described in Table 2-2.
Table 2-2. Flash Configuration Field
Unpaged
Flash Address
Paged Flash
Address
(PPAGE 0x3F)
Size
(Bytes) Description
0xFF00 – 0xFF07 0xBF00 – 0xBF07 8 Backdoor Comparison Key
Refer to Section 2.6.1, “Unsecuring the MCU using Backdoor Key
Access”
0xFF08 – 0xFF0B 0xBF08 – 0xBF0B 4 Reserved
0xFF0C 0xBF0C 1 Block 1 Flash Protection Byte
Refer to Section 2.3.2.7, “Flash Status Register (FSTAT)”
0xFF0D 0xBF0D 1 Block 0 Flash Protection Byte
Refer toSection 2.3.2.7, “Flash Status Register (FSTAT)”
0xFF0E 0xBF0E 1 Flash Nonvolatile Byte
Refer to Section 2.3.2.9, “Flash Control Register (FCTL)”
0xFF0F 0xBF0F 1 Flash Security Byte
Refer to Section 2.3.2.2, “Flash Security Register (FSEC)”
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 77
Figure 2-2. Flash Memory Map
0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37
Block 1
Flash Registers
MODULE BASE + 0x0000
0xFF00 – 0xFF0F, Flash Configuration Field
MODULE BASE + 0x000F
0x8000
(16 bytes)
Flash Protected Low Sectors
1, 2, 4, 8 Kbytes
FLASH_START = 0x4000
0x5000
0x4400
0x6000
16K PAGED
MEMORY
0x38 0x39 0x3A 0x3B
0x3E
0x3C 0x3D 0x3E 0x3F
Note: 0x30–0x3F correspond to the PPAGE register content
FLASH_END = 0xFFFF
0xF800
0xF000
0xC000
0xE000 Flash Protected High Sectors
2, 4, 8, 16 Kbytes
0x3F
Block 0
0x4800
Flash Blocks
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
78 Freescale Semiconductor
Table 2-3. Detailed Flash Memory Map
MCU Address
Range PPAGE Protectable Lower
Range Protectable Higher
Range Flash
Block Block Relative
Address1
1Block relative address for each 128 Kbyte Flash block consists of 17 address bits.
0x4000–0x7FFF Unpaged
(0x3E) 0x4000–0x43FF N.A. 0 0x018000–0x01BFFF
0x4000–0x47FF
0x4000–0x4FFF
0x4000–0x5FFF
0x8000–0xBFFF 0x30 N.A. N.A. 1 0x000000–0x003FFF
0x31 N.A. N.A. 0x004000–0x007FFF
0x32 N.A. N.A. 0x008000–0x00BFFF
0x33 N.A. N.A. 0x00C000–0x00FFFF
0x34 N.A. N.A. 0x010000–0x013FFF
0x35 N.A. N.A. 0x014000–0x017FFF
0x36 0x8000–0x83FF N.A. 0x018000–0x01BFFF
0x8000–0x87FF
0x8000–0x8FFF
0x8000–0x9FFF
0x37 N.A. 0xB800–0xBFFF 0x01C000–0x01FFFF
0xB000–0xBFFF
0xA000–0xBFFF
0x8000–0xBFFF
0x8000–0xBFFF 0x38 N.A. N.A. 0 0x000000–0x003FFF
0x39 N.A. N.A. 0x004000–0x007FFF
0x3A N.A. N.A. 0x008000–0x00BFFF
0x3B N.A. N.A. 0x00C000–0x00FFFF
0x3C N.A. N.A. 0x010000–0x013FFF
0x3D N.A. N.A. 0x014000–0x017FFF
0x3E 0x8000–0x83FF N.A. 0x018000–0x01BFFF
0x8000–0x87FF
0x8000–0x8FFF
0x8000–0x9FFF
0x3F N.A. 0xB800–0xBFFF 0x01C000–0x01FFFF
0xB000–0xBFFF
0xA000–0xBFFF
0x8000–0xBFFF
0xC000–0xFFFF Unpaged
(0x3F) N.A. 0xF800–0xFFFF 0 0x01C000–0x01FFFF
0xF000–0xFFFF
0xE000–0xFFFF
0xC000–0xFFFF
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 79
The Flash module also contains a set of 16 control and status registers located in address space module
base + 0x0000 to module base + 0x000F. In order to accommodate more than one Flash block with a
minimum register address space, a set of registers located from module base + 0x0004 to module
base + 0x000B are repeated in all banks. The active register bank is selected by the BKSEL bits in the
unbanked Flash configuration register (FCNFG). A summary of these registers is given in Table 2-4 while
their accessibility in normal and special modes is detailed in Section 2.3.2, “Register Descriptions”.
Table 2-4. Flash Register Map
Address
Offset Use Normal Mode
Access
0x0000 Flash Clock Divider Register (FCLKDIV) R/W
0x0001 Flash Security Register (FSEC) R
0x0002 Flash Test Mode Register (FTSTMOD) R/W
0x0003 Flash Configuration Register (FCNFG) R/W
0x0004 Flash Protection Register (FPROT) R/W
0x0005 Flash Status Register (FSTAT) R/W
0x0006 Flash Command Register (FCMD) R/W
0x0007 Flash Control Register (FCTL) R
0x0008 Flash High Address Register (FADDRHI) R
0x0009 Flash Low Address Register (FADDRLO) R
0x000A Flash High Data Register (FDATAHI) R
0x000B Flash Low Data Register (FDATALO) R
0x000C RESERVED11R
0x000D RESERVED21R
0x000E RESERVED31R
0x000F RESERVED41
1Intended for factory test purposes only.
R
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
80 Freescale Semiconductor
2.3.2 Register Descriptions
Register
Name Bit 7 654321Bit 0
0x0000
FCLKDIV RFDIVLD PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0
W
0x0001
FSEC R KEYEN RNV5 RNV4 RNV3 RNV2 SEC
W
0x0002
FTSTMOD R000
WRALL 0000
W
0x0003
FCNFG RCBEIE CCIE KEYACC 0000
BKSEL
W
0x0004
FPROT RFPOPEN RNV6 FPHDIS FPHS FPLDIS FPLS
W
0x0005
FSTAT RCBEIF CCIF PVIOL ACCERR 0 BLANK 0 0
W
0x0006
FCMD R0 CMDB
W
0x0007
FCTL R NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0
W
0x0008
FADDRHI R FADDRHI
W
0x0009
FADDRLO R FADDRLO
W
0x000A
FDATAHI R FDATAHI
W
0x000B
FDATALO R FDATALO
W
0x000C
RESERVED1 R00000000
W
= Unimplemented or Reserved
Figure 2-3. FTS256K2ECC Register Summary
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 81
2.3.2.1 Flash Clock Divider Register (FCLKDIV)
The unbanked FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable.
0x000D
RESERVED2 R00000000
W
0x000E
RESERVED3 R00000000
W
0x000F
RESERVED4 R00000000
W
Module Base + 0x0000
76543210
R FDIVLD PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-4. Flash Clock Divider Register (FCLKDIV)
Table 2-5. FCLKDIV Field Descriptions
Field Description
7
FDIVLD Clock Divider Loaded.
0 Register has not been written.
1 Register has been written to since the last reset.
6
PRDIV8 Enable Prescalar by 8.
0 The oscillator clock is directly fed into the clock divider.
1 The oscillator clock is divided by 8 before feeding into the clock divider.
5-0
FDIV[5:0] Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a
frequency of 150 kHz–200 kHz. The maximum divide ratio is 512. Please refer to Section 2.4.1.1, “Writing the
FCLKDIV Register” for more information.
Register
Name Bit 7 654321Bit 0
= Unimplemented or Reserved
Figure 2-3. FTS256K2ECC Register Summary (continued)
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
82 Freescale Semiconductor
2.3.2.2 Flash Security Register (FSEC)
The unbanked FSEC register holds all bits associated with the security of the MCU and Flash module.
All bits in the FSEC register are readable but are not writable.
The FSEC register is loaded from the Flash Configuration Field at address $FF0F during the reset
sequence, indicated by F in Figure 2-5. If the DFDIF flag in the FSTAT register is set while reading the
security field location during the reset sequence, all bits in the FSEC register will be set to leave the module
in a secured state with backdoor key access disabled.
Module Base + 0x0001
76543210
R KEYEN RNV5 RNV4 RNV3 RNV2 SEC
W
Reset F F FFFFFF
= Unimplemented or Reserved
Figure 2-5. Flash Security Register (FSEC)
Table 2-6. FSEC Field Descriptions
Field Description
1-0
KEYEN[1:0] Backdoor Key Security Enable Bits —The KEYEN[1:0] bits define the enabling of backdoor key access to the
Flash module as shown in Table 2-7.
5-2
RNV[5:2] Reserved Nonvolatile Bits — The RNV[5:2] bits must remain in the erased 1 state for future enhancements.
1-0
SEC[1:0] Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 2-8. If the Flash
module is unsecured using backdoor key access, the SEC bits are forced to 10.
Table 2-7. Flash KEYEN States
KEYEN[1:0] Status of Backdoor Key Access
00 DISABLED
011
1Preferred KEYEN state to disable Backdoor Key Access.
DISABLED
10 ENABLED
11 DISABLED
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 83
The security function in the Flash module is described in Section 2.6, “Flash Module Security”.
2.3.2.3 Flash Test Mode Register (FTSTMOD)
The unbanked FTSTMOD register is used to control Flash test features.
FDFD is readable and writable while all remaining bits read 0 and are not writable in normal mode. The
WRALL bit is writable only in special mode to simplify mass erase and erase verify operations. When
writing to the FTSTMOD register in special mode, all unimplemented/reserved bits must be written to 0.
2.3.2.4 Flash Configuration Register (FCNFG)
The unbanked FCNFG register enables the Flash interrupts and gates the security backdoor writes.
Table 2-8. Flash Security States
SEC[1:0] Status of Security
00 SECURED
011
1Preferred SEC state to set MCU to secured state.
SECURED
10 UNSECURED
11 SECURED
Module Base + 0x0002
76543210
R000
WRALL FDFD 000
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-6. Flash Test Mode Register (FTSTMOD)
Table 2-9. FTSTMOD Field Descriptions
Field Description
4
WRALL Write to All Register Banks — If the WRALL bit is set, all banked registers sharing the same register address
will be written simultaneously during a register write.
0 Write only to the bank selected via BKSEL.
1 Write to all register banks.
3
FDFD Force Double Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array
read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD.
0 Flash array read operations will set the DFDIF flag in the FSTAT register only if a double bit fault is detected.
1 Any Flash array read operation will force the DFDIF flag in the FSTAT register to be set and an interrupt will
be generated as long as the DFDIE interrupt enable in the FCNFG register is set.
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
84 Freescale Semiconductor
CBEIE, CCIE, KEYACC, DFDIE and BKSEL bits are readable and writable while all remaining bits read
0 and are not writable. KEYACC is only writable if KEYEN (see Section 2.3.2.2) is set to the enabled
state.
2.3.2.5 Flash Protection Register (FPROT)
The banked FPROT register defines which Flash sectors are protected against program or erase operations.
All bits in the FPROT register are readable and writable with restrictions except for RNV[6] which is only
readable (see Section 2.3.2.6, “Flash Protection Restrictions”).
During reset, the banked FPROT registers are loaded from the Flash Configuration Field at the address
shown in Table 2-11. To change the Flash protection that will be loaded during the reset sequence, the
upper sector of the Flash memory must be unprotected, then the Flash Protect/Security byte located as
described in Table 2-2 must be reprogrammed. If the DFDIF flag in the FSTAT register is set while reading
Module Base + 0x0003
76543210
RCBEIE CCIE KEYACC 0000
BKSEL
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-7. Flash Configuration Register (FCNFG)
Table 2-10. FCNFG Field Descriptions
Field Description
7
CBEIE Command Buffer Empty Interrupt Enable — The CBEIE bit enables an interrupt in case of an empty command
buffer in the Flash module.
0 Command buffer empty interrupt disabled.
1 An interrupt will be requested whenever the CBEIF flag (see Section 2.3.2.7, “Flash Status Register (FSTAT)”)
is set.
6
CCIE Command Complete Interrupt Enable — The CCIE bit enables an interrupt in case all commands have been
completed in the Flash module.
0 Command complete interrupt disabled.
1 An interrupt will be requested whenever the CCIF flag (see Section 2.3.2.7, “Flash Status Register (FSTAT)”)
is set.
5
KEYACC Enable Security Key Writing
0 Flash writes are interpreted as the start of a command write sequence.
1 Writes to Flash array are interpreted as keys to open the backdoor. Reads of the Flash array return invalid
data.
3
DFDIE Double Fault Detect Interrupt Enable — The DFDIE bit enables an interrupt in case a double bit fault is
detected during a Flash block operation.
0 Double bit fault detect interrupt disabled.
1 An interrupt will be requested whenever the DFDIF flag is set (see Section 2.3.2.7, “Flash Status Register
(FSTAT)”).
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 85
the protection field location during the reset sequence, the FPOPEN bit will be cleared and remaining bits
in the FPROT register will be set to leave the Flash block fully protected.
Trying to alter data in any of the protected areas in the Flash block will result in a protection violation error
and the PVIOL flag will be set in the FSTAT register. A mass erase of the Flash block is not possible if
any of the contained Flash sectors are protected.
Table 2-11. Reset Loading of FPROT
Flash Address Protection Byte for
0xFF0D Flash Block 0
0xFF0C Flash Block 1
Table 2-12. FPROT Field Descriptions
Field Description
7
FPOPEN Protection Function Bit — The FPOPEN bit determines the protection function for program or erase as shown
in Table 2-13.
0 FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS[1:0]
and FPLS[1:0] bits. For an MCU without an EEPROM module, the FPOPEN clear state allows the main part
of the Flash block to be protected while a small address range can remain unprotected for EEPROM
emulation.
1 FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS[1:0]
and FPLS[1:0] bits.
6
RNV[6] Reserved Nonvolatile Bit — The RNV[6] bit must remain in the erased state 1 for future enhancements.
5
FPHDIS Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a
protected/unprotected area in the higher address space of the Flash block.
0 Protection/Unprotection enabled
1 Protection/Unprotection disabled
4:3
FPHS[1:0] Flash Protection Higher Address Size — The FPHS[1:0] bits determine the size of the protected/unprotected
area as shown in Table 2-14. The FPHS[1:0] bits can only be written to while the FPHDIS bit is set.
2
FPLDIS Flash Protection Lower address range Disable — The FPLDIS bit determines whether there is a
protected/unprotected area in the lower address space of the Flash block.
0 Protection/Unprotection enabled
1 Protection/Unprotection disabled
1:0
FPLS[1:0] Flash Protection Lower Address Size — The FPLS[1:0] bits determine the size of the protected/unprotected
area as shown in Table 2-15. The FPLS[1:0] bits can only be written to while the FPLDIS bit is set.
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
86 Freescale Semiconductor
All possible Flash protection scenarios are illustrated in Figure 2-8. Although the protection scheme is
loaded from the Flash array after reset, it can be changed by the user. This protection scheme can be used
by applications requiring re-programming in single-chip mode while providing as much protection as
possible if re-programming is not required.
Table 2-13. Flash Protection Function
FPOPEN FPHDIS FPLDIS Function1
1For range sizes, refer to Table 2-14 and Table 2-15.
1 1 1 No Protection
1 1 0 Protected Low Range
1 0 1 Protected High Range
1 0 0 Protected High and Low Ranges
0 1 1 Full Block Protected
0 1 0 Unprotected Low Range
0 0 1 Unprotected High Range
0 0 0 Unprotected High and Low Ranges
Table 2-14. Flash Protection Higher Address Range
FPHS[1:0] Unpaged
Address Range Paged
Address Range Protected Size
00 0xF800–0xFFFF 0x0037/0x003F: 0xC800–0xCFFF 2 Kbytes
01 0xF000–0xFFFF 0x0037/0x003F: 0xC000–0xCFFF 4 Kbytes
10 0xE000–0xFFFF 0x0037/0x003F: 0xB000–0xCFFF 8 Kbytes
11 0xC000–0xFFFF 0x0037/0x003F: 0x8000–0xCFFF 16 Kbytes
Table 2-15. Flash Protection Lower Address Range
FPLS[1:0] Unpaged
Address Range Paged
Address Range Protected Size
00 0x4000–0x43FF 0x0036/0x003E: 0x8000–0x83FF 1 Kbyte
01 0x4000–0x47FF 0x0036/0x003E: 0x8000–0x87FF 2 Kbytes
10 0x4000–0x4FFF 0x0036/0x003E: 0x8000–0x8FFF 4 Kbytes
11 0x4000–0x5FFF 0x0036/0x003E: 0x8000–0x9FFF 8 Kbytes
|:l|:l ’//// N ’///// N 23$
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 87
Figure 2-8. Flash Protection Scenarios
2.3.2.6 Flash Protection Restrictions
The general guideline is that Flash protection can only be added and not removed. Table 2-16 specifies all
valid transitions between Flash protection scenarios. Any attempt to write an invalid scenario to the
FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the
7 6 5 4
FPHS[1:0] FPLS[1:0]
3 2 1 0
FPHS[1:0] FPLS[1:0]
FPHDIS = 1
FPLDIS = 1
FPHDIS = 1
FPLDIS = 0
FPHDIS = 0
FPLDIS = 1
FPHDIS = 0
FPLDIS = 0
Scenario
Scenario
Unprotected region Protected region with size
Protected region Protected region with size
defined by FPLS
defined by FPHSnot defined by FPLS, FPHS
FPOPEN = 1FPOPEN = 0
PPAGE 0x0036–0x0037
0x003E–0x003F
PPAGE 0x0030–0x0035
0x0038–0x003D
PPAGE 0x0036–0x0037
0x003E–0x003F
PPAGE 0x0030–0x0035
0x0038–0x003D
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
88 Freescale Semiconductor
FPROT register reflect the active protection scenario. See the FPHS and FPLS descriptions for additional
restrictions.
2.3.2.7 Flash Status Register (FSTAT)
The banked FSTAT register defines the operational status of the module.
Table 2-16. Flash Protection Scenario Transitions
From
Protection
Scenario
To Protection Scenario1
1Allowed transitions marked with X.
01234567
0 XXXX
1XX
2XX
3X
4XX
5 XXXX
6XXXX
7 XXXXXXXX
Module Base + 0x0005
76543210
RCBEIF CCIF PVIOL ACCERR DFDIF BLANK 0 0
W
Reset 11000000
= Unimplemented or Reserved
Figure 2-9. Flash Status Register (FSTAT - Normal Mode)
Module Base + 0x0005
76543210
RCBEIF CCIF PVIOL ACCERR DFDIF BLANK FAIL 0
W
Reset 11000000
= Unimplemented or Reserved
Figure 2-10. Flash Status Register (FSTAT - Special Mode)
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 89
CBEIF, PVIOL, ACCERR and DFDIF are readable and writable, CCIF and BLANK are readable and not
writable, remaining bits read 0 and are not writable in normal mode. FAIL is readable and writable in
special mode. FAIL must be clear when starting a command write sequence.
Table 2-17. FSTAT Field Descriptions
Field Description
7
CBEIF Command Buffer Empty Interrupt Flag — The CBEIF flag indicates that the address, data and command
buffers are empty so that a new command write sequence can be started. The CBEIF flag is cleared by writing
a 1 to CBEIF. Writing a 0 to the CBEIF flag has no effect on CBEIF. Writing a 0 to CBEIF after writing an aligned
word to the Flash address space but before CBEIF is cleared will abort a command write sequence and cause
the ACCERR flag to be set. Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR
flag. The CBEIF flag is used together with the CBEIE bit in the FCNFG register to generate an interrupt request
(see Figure 2-31).
0 Buffers are full.
1 Buffers are ready to accept a new command.
6
CCIF Command Complete Interrupt Flag — The CCIF flag indicates that there are no more commands pending. The
CCIF flag is cleared when CBEIF is clear and sets automatically upon completion of all active and pending
commands. The CCIF flag does not set when an active commands completes and a pending command is
fetched from the command buffer. Writing to the CCIF flag has no effect on CCIF. The CCIF flag is used together
with the CCIE bit in the FCNFG register to generate an interrupt request (see Figure 2-31).
0 Command in progress.
1 All commands are completed.
5
PVIOL Protection Violation Flag — The PVIOL flag indicates an attempt was made to program or erase an address
in a protected area of the Flash block during a command write sequence. The PVIOL flag is cleared by writing a
1 to PVIOL. Writing a 0 to the PVIOL flag has no effect on PVIOL. While PVIOL is set, it is not possible to launch
a command or start a command write sequence.
0 No failure.
1 A protection violation has occurred.
4
ACCERR Access Error Flag — The ACCERR flag indicates an illegal access to the Flash array caused by either a
violation of the command write sequence, issuing an illegal command (illegal combination of the CMDBx bits in
the FCMD register), launching the sector erase abort command terminating a sector erase operation early,
detection of a double fault or the execution of a CPU STOP instruction while a command is executing (CCIF =
0). The ACCERR flag is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR flag has no effect on
ACCERR. While ACCERR is set, it is not possible to launch a command or start a command write sequence. If
ACCERR is set by the detection of a double fault, an erase verify operation or a data compress operation, any
buffered command will not launch.
0 No access error detected.
1 Access error has occurred.
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
90 Freescale Semiconductor
2.3.2.8 Flash Command Register (FCMD)
The banked FCMD register is the Flash command register.
All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not
writable.
3
DFDIF Double Fault Detect Interrupt Flag — The DFDIF flag indicates that one of the following Flash block operations
has detected a double bit fault in the stored parity and data bits.
Array Read.
Erase Verify.
Data Compress.
Reset Sequence (reads of the protection and security fields stored in the Flash memory).
When the DFDIF flag is set during a Flash array read operation, the data read from the Flash module are the
data bits read out of the Flash array without correction and should be considered invalid. When the DFDIF flag
is set during a Flash array read, erase verify, data compress or reset sequence operation, the Flash block
address containing the parity and data bits that caused the DFDIF flag to set will be stored in the FADDR register
and the parity bits will be stored in the FDATA register. The DFDIF flag is cleared by writing a 1 to the ACCERR
bit which is set when the DFDIF flag is set. Writing a 0 to the DFDIF flag has no effect on DFDIF. The DFDIF flag
is used together with the DFDIE enable bit to generate an interrupt request (see Figure 2-31). While DFDIF is
set, Flash array read operations are allowed. If DFDIF is not cleared and another double bit fault is detected, the
FADDR and FDATA registers will maintain the contents from the fault that caused the DFDIF bit to set.
0 No double bit fault detected.
1 Double bit fault detected.
2
BLANK Erase Verify Operation Status Flag — When the CCIF flag is set after completion of an erase verify command,
the BLANK flag indicates the result of the erase verify operation. The BLANK flag is cleared by the Flash module
when CBEIF is cleared as part of a new valid command write sequence. Writing to the BLANK flag has no effect
on BLANK.
0 Flash block verified as not erased.
1 Flash block verified as erased.
1
FAIL Flag Indicating a Failed Flash Operation — The FAIL flag will set if the erase verify operation fails (selected
Flash block verified as not erased). The FAIL flag will also set if a double bit fault is detected during an array read,
erase verify, or data compress operation. The FAIL flag is cleared by writing a 1 to FAIL. Writing a 0 to the FAIL
flag has no effect on FAIL. While FAIL is set, it is not possible to launch a command.
0 Flash operation completed without error.
1 Flash operation failed.
Module Base + 0x0006
76543210
R0 CMDB
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-11. Flash Command Register (FCMD - NVM User Mode)
Table 2-17. FSTAT Field Descriptions
Field Description
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 91
2.3.2.9 Flash Control Register (FCTL)
The banked FCTL register is the Flash control register.
All bits in the FCTL register are readable but are not writable.
The FCTL register is loaded from the Flash Configuration Field byte at $FF0E during the reset sequence,
indicated by F in Figure 2-12.
2.3.2.10 Flash Address Registers (FADDR)
The banked FADDRHI and FADDRLO registers are the Flash address registers.
Table 2-18. FCMD Field Descriptions
Field Description
6-0
CMDB[6:0] Flash Command — Valid Flash commands are shown in Table 2-19. Writing any command other than those
listed in Table 2-19 sets the ACCERR flag in the FSTAT register.
Table 2-19. Valid Flash Command List
CMDB[6:0] NVM Command
0x05 Erase Verify
0x06 Data Compress
0x20 Word Program
0x40 Sector Erase
0x41 Mass Erase
0x47 Sector Erase Abort
Module Base + 0x0007
76543210
R NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0
W
Reset F F FFFFFF
= Unimplemented or Reserved
Figure 2-12. Flash Control Register (FCTL)
Table 2-20. FCTL Field Descriptions
Field Description
7-0
NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the Device User Guide for proper
use of the NV bits.
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
92 Freescale Semiconductor
All FADDRHI and FADDRLO bits are readable but are not writable. After an array write as part of a
command write sequence, the FADDR registers will contain the mapped MCU address written. If a double
bit fault is detected, as indicated by the setting of the DFDIF bit in the FSTAT register, the faulty Flash
block address is stored in the FADDR registers as a word address. The faulty Flash block address remains
readable until the start of the next command write sequence. The mapping of the FADDR registers to the
MCU address is shown in Figure 2-15 and Figure 2-16.
Figure 2-15. FADDR to MCU Address Mapping (Paged)
Module Base + 0x0008
76543210
R FADDRHI
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-13. Flash Address High Register (FADDRHI)
Module Base + 0x0009
76543210
R FADDRLO
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-14. Flash Address Low Register (FADDRLO)
AB1AB2AB3AB4AB5AB6AB7AB8AB9AB10AB11AB12AB13
Byte Select
FADDRLO[7:0]
MCU Address
FADDR Register
PPAGE Register PIX2 PIX1 PIX0
PIX3 is Flash block select
FADDRHI[7:0]
PIX311
01 AB0
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 93
Figure 2-16. FADDR to MCU Address Mapping (Unpaged)
2.3.2.11 Flash Data Registers (FDATA)
The banked FDATAHI and FDATALO registers are the Flash data registers.
All FDATAHI and FDATALO bits are readable but are not writable. After an array write as part of a
command write sequence, the FDATA registers will contain the data written. At the completion of a data
compress operation, the resulting 16-bit signature is stored in the FDATA registers. The data compression
signature is readable in the FDATA registers until a new command write sequence is started or a double bit
fault is detected in a Flash array read operation.If a double bit fault is detected during a Flash array read,
erase verify or data compress operation, the parity bits stored in the Flash array at the failed location will
Module Base + 0x000A
76543210
R FDATAHI
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-17. Flash Data High Register (FDATAHI)
Module Base + 0x000B
76543210
R FDATALO
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-18. Flash Data Low Register (FDATALO)
AB1AB2AB3AB4AB5AB6AB7AB8AB9AB10AB11AB12AB13
Byte Select
FADDRLO[7:0]
FADDRHI[4:0]
MCU Address (0x4000-0x7FFF)
FADDR Register
10 AB0
AB1AB2AB3AB4AB5AB6AB7AB8AB9AB10AB11AB12AB13
Byte Select
MCU Address (0xC000-0xFFFF) 11 AB0
1
0
11
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
94 Freescale Semiconductor
be stored in the lower six bits of FDATALO. The faulty parity bits remain readable until the start of the
next command write sequence.
2.3.2.12 RESERVED1
This register is reserved for factory testing and is not accessible.
All bits read 0 and are not writable.
2.3.2.13 RESERVED2
This register is reserved for factory testing and is not accessible.
All bits read 0 and are not writable.
2.3.2.14 RESERVED3
This register is reserved for factory testing and is not accessible.
Module Base + 0x000C
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-19. RESERVED1
Module Base + 0x000D
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-20. RESERVED2
Module Base + 0x000E
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-21. RESERVED3
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 95
All bits read 0 and are not writable.
2.3.2.15 RESERVED4
This register is reserved for factory testing and is not accessible.
All bits read 0 and are not writable.
2.4 Functional Description
2.4.1 Flash Command Operations
Write and read operations are both used for the program, erase, erase verify, and data compress algorithms
described in this subsection. The program and erase algorithms are time controlled by a state machine
whose timebase, FCLK, is derived from the oscillator clock via a programmable divider. The command
register as well as the associated address and data registers operate as a buffer and a register (2-stage FIFO)
so that a second command along with the necessary data and address can be stored to the buffer while the
first command remains in progress. This pipelined operation allows a time optimization when
programming more than one word on a specific row in the Flash block as the high voltage generation can
be kept active in between two programming commands. The pipelined operation also allows a
simplification of command launching. Buffer empty as well as command completion are signalled by flags
in the Flash status register with interrupts generated, if enabled.
The next paragraphs describe:
1. How to write the FCLKDIV register.
2. Command write sequences used to program, erase, and verify the Flash memory.
3. Valid Flash commands.
4. Effects resulting from illegal Flash command write sequences or aborting Flash operations.
2.4.1.1 Writing the FCLKDIV Register
Prior to issuing any program, erase, erase verify, or data compress command, it is first necessary to write
the FCLKDIV register to divide the oscillator clock down to within the 150 kHz to 200 kHz range.
Because the program and erase timings are also a function of the bus clock, the FCLKDIV determination
must take this information into account.
Module Base + 0x000F
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-22. RESERVED4
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
96 Freescale Semiconductor
If we define:
FCLK as the clock of the Flash timing control block,
Tbus as the period of the bus clock, and
INT(x) as taking the integer part of x (e.g. INT(4.323)=4).
Then, FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 2-23.
For example, if the oscillator clock frequency is 950 kHz and the bus clock frequency is 10 MHz,
FCLKDIV bits FDIV[5:0] must be set to 4 (000100) and bit PRDIV8 set to 0. The resulting FCLK
frequency is then 190 kHz. As a result, the Flash program and erase algorithm timings are increased over
the optimum target by:
CAUTION
Program and erase command execution time will increase proportionally
with the period of FCLK. Because of the impact of clock synchronization
on the accuracy of the functional timings, programming or erasing the Flash
memory cannot be performed if the bus clock runs at less than 1 MHz.
Programming or erasing the Flash memory with FCLK < 150 kHz must be
avoided. Setting FCLKDIV to a value such that FCLK < 150 kHz can
destroy the Flash memory due to overstress. Setting FCLKDIV to a value
such that (1/FCLK + Tbus) < 5µs can result in incomplete programming or
erasure of the Flash memory cells.
If the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the
FCLKDIV register has not been written since the last reset. Flash commands will not be executed if the
FCLKDIV register has not been written to.
200 190()200100×5%=
Chapter 2 256 Kbyte ECC Flash Module (S12FTS256K2ECCV1)
MC9S12KT256 Data Sheet, Rev. 1.16
Freescale Semiconductor 97
Figure 2-23. Determination Procedure for PRDIV8 and FDIV Bits
PRDIV8=1
YES
NO
PRDIV8=0 (reset)
FCLK=(PRDCLK)/(1+FDIV[5:0])
PRDCLK=oscillator_clock
PRDCLK=oscillator_clock/8
PRDCLK[MHz]*(5+Tbus[µs]) NO
FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1
YES
START
Tbus < 1µs?
an integer?
FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs]))
1/FCLK[MHz] + Tbus[µs] > 5
AND
FCLK > 0.15 MHz
?
END
YES
NO
FDIV[5:0] > 4?
ALL COMMANDS IMPOSSIBLE
YES
NO