MC9S08DN60,48,32,16 Datasheet by NXP USA Inc.

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‘/RoHS freescale’“ semiconductor
HCS08
Microcontrollers
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MC9S08DN60
MC9S08DN48
MC9S08DN32
MC9S08DN16
Data Sheet
MC9S08DN60
Rev 3
6/2008
8-Bit HCS08 Central Processor Unit (CPU)
40-MHz HCS08 CPU (20-MHz bus)
HC08 instruction set with added BGND instruction
Support for up to 32 interrupt/reset sources
On-Chip Memory
Flash read/program/erase over full operating voltage
and temperature
MC9S08DN60 = 60K
MC9S08DN48 = 48K
MC9S08DN32 = 32K
MC9S08DN16 = 16K
Up to 2K EEPROM in-circuit programmable memory;
8-byte single-page or 4-byte dual-page erase sector;
Program and Erase while executing Flash; Erase abort
Up to 2K random-access memory (RAM)
Power-Saving Modes
Two very low power stop modes
Reduced power wait mode
Very low power real time interrupt for use in run, wait,
and stop
Clock Source Options
Oscillator (XOSC) — Loop-control Pierce oscillator;
Crystal or ceramic resonator range of 31.25 kHz to
38.4 kHz or 1 MHz to 16 MHz
Multi-purpose Clock Generator (MCG) — PLL and
FLL modes (FLL capable of 1.5% deviation using
internal temperature compensation); Internal reference
clock with trim adjustment (trimmed at factory, with
trim value stored in flash); External reference with
oscillator/resonator options
System Protection
Watchdog computer operating properly (COP) reset
with option to run from backup dedicated 1-kHz
internal clock source or bus clock
Low-voltage detection with reset or interrupt; selectable
trip points
Illegal opcode detection with reset
Illegal address detection with reset
Flash block protect
Loss-of-lock protection
Development Support
Single-wire background debug interface
On-chip, in-circuit emulation (ICE) with real-time bus
capture
Peripherals
ADC — 16-channel, 12-bit resolution, 2.5 μs
conversion time, automatic compare function,
temperature sensor, internal bandgap reference channel
ACMPx — Two analog comparators with selectable
interrupt on rising, falling, or either edge of comparator
output; compare option to fixed internal bandgap
reference voltage
SCI1 — One SCI supporting LIN 2.0 Protocol and SAE
J2602 protocols; Full duplex non-return to zero (NRZ);
Master extended break generation; Slave extended
break detection; Wakeup on active edge
SPI — Full-duplex or single-wire bidirectional;
Double-buffered transmit and receive; Master or Slave
mode; MSB-first or LSB-first shifting
IIC — Up to 100 kbps with maximum bus loading;
Multi-master operation; Programmable slave address;
General Call Address; Interrupt driven byte-by-byte
data transfer
TPMx — One 6-channel (TPM1) and one 2-channel
(TPM2); Selectable input capture, output compare, or
buffered edge-aligned PWM on each channel
RTC — (Real-time counter) 8-bit modulus counter with
binary or decimal based prescaler; Real-time clock
capabilities using external crystal and RTC for precise
time base, time-of-day, calendar or task scheduling
functions; Free running on-chip low power oscillator
(1 kHz) for cyclic wake-up without external
components
Input/Output
53 general-purpose input/output (I/O) pins and 1
input-only pin
24 interrupt pins with selectable polarity on each pin
Hysteresis and configurable pull device on all input
pins.
Configurable slew rate and drive strength on all output
pins.
Package Options
64-pin low-profile quad flat-pack (LQFP) — 10x10 mm
48-pin low-profile quad flat-pack (LQFP) — 7x7 mm
32-pin low-profile quad flat-pack (LQFP) — 7x7 mm
MC9S08DN60 Series Features
0" :3' freescale’” semiconductor
MC9S08DN60 Data Sheet
Covers MC9S08DN60
MC9S08DN48
MC9S08DN32
MC9S08DN16
MC9S08DN60
Rev 3
6/2008
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2007-2008. All rights reserved.
MC9S08DN60 Series Data Sheet, Rev 3
6 Freescale Semiconductor
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision
Number Revision
Date Description of Changes
1 6/2006 Advance Information version for alpha samples customers
2 9/2007 Product Launch. Removed the 64-pin QFN package. Changed from standard to extended
mode for MSCAN registers in register summary. Corrected Block diagrams for SCI.
Updated the latest Temp Sensor information. Made FTSTMOD reserved. Updated device
to use the ADC 12-bit module. Revised the MCG module. Updated the TPM block module
to version 3. Added the TPM block module version 2 as an appendix for devices using
3M05C (or earlier) mask sets. Heavily revised the Electricals appendix.
3 6/2008 Sustaining Update. Incorporated PS Issues # 2765, 3177, 3236, 3292, 3311, 3312, 3326,
3335, 3345, 3382, 2795, 3382 and 3386 PLL Jitter Spec update. Also, added internal
reference clock trim adjustment statement to Features page. Updated the TPM module to
the latest version. Adjusted values in Table A-13 Control Timing row 2 and in Table A-6 DC
Characteristics row 24 so that it references 5.0 V instead of 3.0 V.
© Freescale Semiconductor, Inc., 2007-2008. All rights reserved.
This product incorporates SuperFlash® Technology licensed from SST.
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 7
List of Chapters
Chapter Title Page
Chapter 1 Device Overview..............................................................................19
Chapter 2 Pins and Connections.....................................................................23
Chapter 3 Modes of Operation.........................................................................31
Chapter 4 Memory.............................................................................................37
Chapter 5 Resets, Interrupts, and General System Control..........................63
Chapter 6 Parallel Input/Output Control..........................................................79
Chapter 7 Central Processor Unit (S08CPUV3)............................................109
Chapter 8 Multi-Purpose Clock Generator (S08MCGV1).............................129
Chapter 9 Analog Comparator (S08ACMPV3) ..............................................161
Chapter 10 Analog-to-Digital Converter (S08ADC12V1)................................167
Chapter 11 Inter-Integrated Circuit (S08IICV2)...............................................193
Chapter 12 Serial Peripheral Interface (S08SPIV3) ........................................213
Chapter 13 Serial Communications Interface (S08SCIV4).............................229
Chapter 14 Real-Time Counter (S08RTCV1)...................................................249
Chapter 15 Timer Pulse-Width Modulator (S08TPMV3).................................259
Chapter 16 Development Support ...................................................................287
Appendix A Electrical Characteristics..............................................................309
Appendix B Timer Pulse-Width Modulator (TPMV2) .......................................331
Appendix C Ordering Information and Mechanical Drawings........................345
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 9
Contents
Section Number Title Page
Chapter 1
Device Overview
1.1 Devices in the MC9S08DN60 Series...............................................................................................19
1.2 MCU Block Diagram .......................................................................................................................20
1.3 System Clock Distribution ...............................................................................................................21
Chapter 2
Pins and Connections
2.1 Device Pin Assignment ....................................................................................................................23
2.2 Recommended System Connections................................................................................................26
2.2.1 Power ................................................................................................................................27
2.2.2 Oscillator ...........................................................................................................................27
2.2.3 RESET ..............................................................................................................................27
2.2.4 Background / Mode Select (BKGD/MS) ..........................................................................28
2.2.5 ADC Reference Pins (VREFH, VREFL) ..............................................................................28
2.2.6 General-Purpose I/O and Peripheral Ports ........................................................................28
Chapter 3
Modes of Operation
3.1 Introduction......................................................................................................................................31
3.2 Features ............................................................................................................................................31
3.3 Run Mode.........................................................................................................................................31
3.4 Active Background Mode.................................................................................................................31
3.5 Wait Mode........................................................................................................................................32
3.6 Stop Modes.......................................................................................................................................33
3.6.1 Stop3 Mode .......................................................................................................................33
3.6.2 Stop2 Mode .......................................................................................................................34
3.6.3 On-Chip Peripheral Modules in Stop Modes ....................................................................35
Chapter 4
Memory
4.1 MC9S08DN60 Series Memory Map................................................................................................37
4.2 Reset and Interrupt Vector Assignments..........................................................................................38
4.3 Register Addresses and Bit Assignments.........................................................................................40
4.4 RAM.................................................................................................................................................47
4.5 Flash and EEPROM .........................................................................................................................47
4.5.1 Features .............................................................................................................................47
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10 Freescale Semiconductor
Section Number Title Page
4.5.2 Program and Erase Times .................................................................................................48
4.5.3 Program and Erase Command Execution .........................................................................48
4.5.4 Burst Program Execution ..................................................................................................50
4.5.5 Sector Erase Abort ............................................................................................................52
4.5.6 Access Errors ....................................................................................................................53
4.5.7 Block Protection ................................................................................................................54
4.5.8 Vector Redirection ............................................................................................................54
4.5.9 Security .............................................................................................................................54
4.5.10 EEPROM Mapping ...........................................................................................................56
4.5.11 Flash and EEPROM Registers and Control Bits ...............................................................56
Chapter 5
Resets, Interrupts, and General System Control
5.1 Introduction......................................................................................................................................63
5.2 Features ............................................................................................................................................63
5.3 MCU Reset.......................................................................................................................................63
5.4 Computer Operating Properly (COP) Watchdog..............................................................................64
5.5 Interrupts ..........................................................................................................................................65
5.5.1 Interrupt Stack Frame .......................................................................................................66
5.5.2 External Interrupt Request (IRQ) Pin ...............................................................................66
5.5.3 Interrupt Vectors, Sources, and Local Masks ....................................................................67
5.6 Low-Voltage Detect (LVD) System .................................................................................................68
5.6.1 Power-On Reset Operation ...............................................................................................69
5.6.2 Low-Voltage Detection (LVD) Reset Operation ...............................................................69
5.6.3 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................69
5.7 MCLK Output ..................................................................................................................................69
5.8 Reset, Interrupt, and System Control Registers and Control Bits....................................................70
5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................71
5.8.2 System Reset Status Register (SRS) .................................................................................72
5.8.3 System Background Debug Force Reset Register (SBDFR) ............................................73
5.8.4 System Options Register 1 (SOPT1) ................................................................................74
5.8.5 System Options Register 2 (SOPT2) ................................................................................75
5.8.6 System Device Identification Register (SDIDH, SDIDL) ................................................76
5.8.7 System Power Management Status and Control 1 Register (SPMSC1) ...........................77
5.8.8 System Power Management Status and Control 2 Register (SPMSC2) ...........................78
Chapter 6
Parallel Input/Output Control
6.1 Port Data and Data Direction ...........................................................................................................79
6.2 Pull-up, Slew Rate, and Drive Strength............................................................................................80
6.3 Pin Interrupts....................................................................................................................................81
6.3.1 Edge Only Sensitivity .......................................................................................................81
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Freescale Semiconductor 11
Section Number Title Page
6.3.2 Edge and Level Sensitivity ................................................................................................82
6.3.3 Pull-up/Pull-down Resistors .............................................................................................82
6.3.4 Pin Interrupt Initialization .................................................................................................82
6.4 Pin Behavior in Stop Modes.............................................................................................................82
6.5 Parallel I/O and Pin Control Registers .............................................................................................83
6.5.1 Port A Registers ................................................................................................................84
6.5.2 Port B Registers ................................................................................................................88
6.5.3 Port C Registers ................................................................................................................92
6.5.4 Port D Registers ................................................................................................................95
6.5.5 Port E Registers .................................................................................................................99
6.5.6 Port F Registers ...............................................................................................................102
6.5.7 Port G Registers ..............................................................................................................105
Chapter 7
Central Processor Unit (S08CPUV3)
7.1 Introduction....................................................................................................................................109
7.1.1 Features ...........................................................................................................................109
7.2 Programmer’s Model and CPU Registers ......................................................................................110
7.2.1 Accumulator (A) .............................................................................................................110
7.2.2 Index Register (H:X) .......................................................................................................110
7.2.3 Stack Pointer (SP) ...........................................................................................................111
7.2.4 Program Counter (PC) ....................................................................................................111
7.2.5 Condition Code Register (CCR) .....................................................................................111
7.3 Addressing Modes..........................................................................................................................113
7.3.1 Inherent Addressing Mode (INH) ...................................................................................113
7.3.2 Relative Addressing Mode (REL) ...................................................................................113
7.3.3 Immediate Addressing Mode (IMM) ..............................................................................113
7.3.4 Direct Addressing Mode (DIR) ......................................................................................113
7.3.5 Extended Addressing Mode (EXT) ................................................................................114
7.3.6 Indexed Addressing Mode ..............................................................................................114
7.4 Special Operations..........................................................................................................................115
7.4.1 Reset Sequence ...............................................................................................................115
7.4.2 Interrupt Sequence ..........................................................................................................115
7.4.3 Wait Mode Operation ......................................................................................................116
7.4.4 Stop Mode Operation ......................................................................................................116
7.4.5 BGND Instruction ...........................................................................................................117
7.5 HCS08 Instruction Set Summary...................................................................................................118
Chapter 8
Multi-Purpose Clock Generator (S08MCGV1)
8.1 Introduction....................................................................................................................................129
8.1.1 Features ...........................................................................................................................131
MC9S08DN60 Series Data Sheet, Rev 3
12 Freescale Semiconductor
Section Number Title Page
8.1.2 Modes of Operation ........................................................................................................133
8.2 External Signal Description ...........................................................................................................133
8.3 Register Definition .........................................................................................................................134
8.3.1 MCG Control Register 1 (MCGC1) ...............................................................................134
8.3.2 MCG Control Register 2 (MCGC2) ...............................................................................135
8.3.3 MCG Trim Register (MCGTRM) ...................................................................................136
8.3.4 MCG Status and Control Register (MCGSC) .................................................................137
8.3.5 MCG Control Register 3 (MCGC3) ...............................................................................138
8.4 Functional Description...................................................................................................................140
8.4.1 Operational Modes ..........................................................................................................140
8.4.2 Mode Switching ..............................................................................................................144
8.4.3 Bus Frequency Divider ...................................................................................................145
8.4.4 Low Power Bit Usage .....................................................................................................145
8.4.5 Internal Reference Clock ................................................................................................145
8.4.6 External Reference Clock ...............................................................................................145
8.4.7 Fixed Frequency Clock ...................................................................................................146
8.5 Initialization / Application Information .........................................................................................146
8.5.1 MCG Module Initialization Sequence ............................................................................146
8.5.2 MCG Mode Switching ....................................................................................................147
8.5.3 Calibrating the Internal Reference Clock (IRC) .............................................................158
Chapter 9
Analog Comparator (S08ACMPV3)
9.1 Introduction....................................................................................................................................161
9.1.1 ACMP Configuration Information ..................................................................................161
9.1.2 Features ...........................................................................................................................163
9.1.3 Modes of Operation ........................................................................................................163
9.1.4 Block Diagram ................................................................................................................164
9.2 External Signal Description ...........................................................................................................164
9.3 Memory Map/Register Definition..................................................................................................165
9.3.1 ACMPx Status and Control Register (ACMPxSC) .........................................................165
9.4 Functional Description...................................................................................................................166
Chapter 10
Analog-to-Digital Converter (S08ADC12V1)
10.1 Introduction....................................................................................................................................167
10.1.1 Analog Power and Ground Signal Names ......................................................................167
10.1.2 Channel Assignments ......................................................................................................167
10.1.3 Alternate Clock ...............................................................................................................168
10.1.4 Hardware Trigger ............................................................................................................168
10.1.5 Temperature Sensor ........................................................................................................169
10.1.6 Features ...........................................................................................................................171
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 13
Section Number Title Page
10.1.7 ADC Module Block Diagram .........................................................................................171
10.2 External Signal Description ...........................................................................................................172
10.2.1 Analog Power (VDDAD) ..................................................................................................173
10.2.2 Analog Ground (VSSAD) .................................................................................................173
10.2.3 Voltage Reference High (VREFH) ...................................................................................173
10.2.4 Voltage Reference Low (VREFL) .....................................................................................173
10.2.5 Analog Channel Inputs (ADx) ........................................................................................173
10.3 Register Definition .........................................................................................................................173
10.3.1 Status and Control Register 1 (ADCSC1) ......................................................................173
10.3.2 Status and Control Register 2 (ADCSC2) ......................................................................175
10.3.3 Data Result High Register (ADCRH) .............................................................................175
10.3.4 Data Result Low Register (ADCRL) ..............................................................................176
10.3.5 Compare Value High Register (ADCCVH) ....................................................................176
10.3.6 Compare Value Low Register (ADCCVL) .....................................................................177
10.3.7 Configuration Register (ADCCFG) ................................................................................177
10.3.8 Pin Control 1 Register (APCTL1) ..................................................................................178
10.3.9 Pin Control 2 Register (APCTL2) ..................................................................................179
10.3.10Pin Control 3 Register (APCTL3) ..................................................................................180
10.4 Functional Description...................................................................................................................181
10.4.1 Clock Select and Divide Control ....................................................................................182
10.4.2 Input Select and Pin Control ...........................................................................................182
10.4.3 Hardware Trigger ............................................................................................................182
10.4.4 Conversion Control .........................................................................................................182
10.4.5 Automatic Compare Function .........................................................................................185
10.4.6 MCU Wait Mode Operation ............................................................................................185
10.4.7 MCU Stop3 Mode Operation ..........................................................................................186
10.4.8 MCU Stop2 Mode Operation ..........................................................................................186
10.5 Initialization Information ...............................................................................................................187
10.5.1 ADC Module Initialization Example .............................................................................187
10.6 Application Information.................................................................................................................189
10.6.1 External Pins and Routing ..............................................................................................189
10.6.2 Sources of Error ..............................................................................................................190
Chapter 11
Inter-Integrated Circuit (S08IICV2)
11.1 Introduction....................................................................................................................................193
11.1.1 Features ...........................................................................................................................195
11.1.2 Modes of Operation ........................................................................................................195
11.1.3 Block Diagram ................................................................................................................196
11.2 External Signal Description ...........................................................................................................196
11.2.1 SCL — Serial Clock Line ...............................................................................................196
11.2.2 SDA — Serial Data Line ................................................................................................196
MC9S08DN60 Series Data Sheet, Rev 3
14 Freescale Semiconductor
Section Number Title Page
11.3 Register Definition .........................................................................................................................196
11.3.1 IIC Address Register (IICA) ...........................................................................................197
11.3.2 IIC Frequency Divider Register (IICF) ...........................................................................197
11.3.3 IIC Control Register (IICC1) ..........................................................................................200
11.3.4 IIC Status Register (IICS) ...............................................................................................201
11.3.5 IIC Data I/O Register (IICD) ..........................................................................................202
11.3.6 IIC Control Register 2 (IICC2) .......................................................................................202
11.4 Functional Description...................................................................................................................203
11.4.1 IIC Protocol .....................................................................................................................203
11.4.2 10-bit Address .................................................................................................................207
11.4.3 General Call Address ......................................................................................................208
11.5 Resets .............................................................................................................................................208
11.6 Interrupts ........................................................................................................................................208
11.6.1 Byte Transfer Interrupt ....................................................................................................208
11.6.2 Address Detect Interrupt .................................................................................................208
11.6.3 Arbitration Lost Interrupt ................................................................................................208
11.7 Initialization/Application Information ...........................................................................................210
Chapter 12
Serial Peripheral Interface (S08SPIV3)
12.1 Introduction....................................................................................................................................213
12.1.1 Features ...........................................................................................................................215
12.1.2 Block Diagrams ..............................................................................................................215
12.1.3 SPI Baud Rate Generation ..............................................................................................217
12.2 External Signal Description ...........................................................................................................218
12.2.1 SPSCK — SPI Serial Clock ............................................................................................218
12.2.2 MOSI — Master Data Out, Slave Data In ......................................................................218
12.2.3 MISO — Master Data In, Slave Data Out ......................................................................218
12.2.4 SS — Slave Select ...........................................................................................................218
12.3 Modes of Operation........................................................................................................................219
12.3.1 SPI in Stop Modes ..........................................................................................................219
12.4 Register Definition .........................................................................................................................219
12.4.1 SPI Control Register 1 (SPIC1) ......................................................................................219
12.4.2 SPI Control Register 2 (SPIC2) ......................................................................................220
12.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................221
12.4.4 SPI Status Register (SPIS) ..............................................................................................222
12.4.5 SPI Data Register (SPID) ................................................................................................223
12.5 Functional Description...................................................................................................................224
12.5.1 SPI Clock Formats ..........................................................................................................224
12.5.2 SPI Interrupts ..................................................................................................................227
12.5.3 Mode Fault Detection .....................................................................................................227
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 15
Section Number Title Page
Chapter 13
Serial Communications Interface (S08SCIV4)
13.1 Introduction....................................................................................................................................229
13.1.1 Features ...........................................................................................................................231
13.1.2 Modes of Operation ........................................................................................................231
13.1.3 Block Diagram ................................................................................................................232
13.2 Register Definition .........................................................................................................................234
13.2.1 SCI Baud Rate Registers (SCI1BDH, SCI1BDL) ..........................................................234
13.2.2 SCI Control Register 1 (SCI1C1) ...................................................................................235
13.2.3 SCI Control Register 2 (SCI1C2) ...................................................................................236
13.2.4 SCI Status Register 1 (SCI1S1) ......................................................................................237
13.2.5 SCI Status Register 2 (SCI1S2) ......................................................................................239
13.2.6 SCI Control Register 3 (SCI1C3) ...................................................................................240
13.2.7 SCI Data Register (SCI1D) .............................................................................................241
13.3 Functional Description...................................................................................................................241
13.3.1 Baud Rate Generation .....................................................................................................241
13.3.2 Transmitter Functional Description ................................................................................242
13.3.3 Receiver Functional Description .....................................................................................243
13.3.4 Interrupts and Status Flags ..............................................................................................245
13.3.5 Additional SCI Functions ...............................................................................................246
Chapter 14
Real-Time Counter (S08RTCV1)
14.1 Introduction....................................................................................................................................249
14.1.1 RTC Clock Signal Names ...............................................................................................249
14.1.2 Features ...........................................................................................................................251
14.1.3 Modes of Operation ........................................................................................................251
14.1.4 Block Diagram ................................................................................................................252
14.2 External Signal Description ...........................................................................................................252
14.3 Register Definition .........................................................................................................................252
14.3.1 RTC Status and Control Register (RTCSC) ....................................................................253
14.3.2 RTC Counter Register (RTCCNT) ..................................................................................254
14.3.3 RTC Modulo Register (RTCMOD) ................................................................................254
14.4 Functional Description...................................................................................................................254
14.4.1 RTC Operation Example .................................................................................................255
14.5 Initialization/Application Information ...........................................................................................256
Chapter 15
Timer Pulse-Width Modulator (S08TPMV3)
15.1 Introduction....................................................................................................................................259
15.1.1 Features ...........................................................................................................................261
15.1.2 Modes of Operation ........................................................................................................261
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Section Number Title Page
15.1.3 Block Diagram ................................................................................................................262
15.2 Signal Description..........................................................................................................................264
15.2.1 Detailed Signal Descriptions ...........................................................................................264
15.3 Register Definition .........................................................................................................................268
15.3.1 TPM Status and Control Register (TPMxSC) ................................................................268
15.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................269
15.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................270
15.3.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................271
15.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................272
15.4 Functional Description...................................................................................................................274
15.4.1 Counter ............................................................................................................................274
15.4.2 Channel Mode Selection .................................................................................................276
15.5 Reset Overview ..............................................................................................................................279
15.5.1 General ............................................................................................................................279
15.5.2 Description of Reset Operation .......................................................................................279
15.6 Interrupts ........................................................................................................................................279
15.6.1 General ............................................................................................................................279
15.6.2 Description of Interrupt Operation ..................................................................................280
15.7 The Differences from TPM v2 to TPM v3.....................................................................................281
Chapter 16
Development Support
16.1 Introduction....................................................................................................................................287
16.1.1 Forcing Active Background ............................................................................................287
16.1.2 Features ...........................................................................................................................288
16.2 Background Debug Controller (BDC) ...........................................................................................288
16.2.1 BKGD Pin Description ...................................................................................................289
16.2.2 Communication Details ..................................................................................................290
16.2.3 BDC Commands .............................................................................................................294
16.2.4 BDC Hardware Breakpoint .............................................................................................296
16.3 On-Chip Debug System (DBG) .....................................................................................................297
16.3.1 Comparators A and B ......................................................................................................297
16.3.2 Bus Capture Information and FIFO Operation ...............................................................297
16.3.3 Change-of-Flow Information ..........................................................................................298
16.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................298
16.3.5 Trigger Modes .................................................................................................................299
16.3.6 Hardware Breakpoints ....................................................................................................301
16.4 Register Definition .........................................................................................................................301
16.4.1 BDC Registers and Control Bits .....................................................................................301
16.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................303
16.4.3 DBG Registers and Control Bits .....................................................................................304
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 17
Section Number Title Page
Appendix A
Electrical Characteristics
A.1 Introduction ...................................................................................................................................309
A.2 Parameter Classification ................................................................................................................309
A.3 Absolute Maximum Ratings ..........................................................................................................309
A.4 Thermal Characteristics .................................................................................................................310
A.5 ESD Protection and Latch-Up Immunity ......................................................................................312
A.6 DC Characteristics .........................................................................................................................313
A.7 Supply Current Characteristics ......................................................................................................315
A.8 Analog Comparator (ACMP) Electricals ......................................................................................316
A.9 ADC Characteristics ......................................................................................................................316
A.10 External Oscillator (XOSC) Characteristics .................................................................................320
A.11 MCG Specifications ......................................................................................................................321
A.12 AC Characteristics .........................................................................................................................323
A.12.1 Control Timing ...............................................................................................................323
A.12.2 Timer/PWM ....................................................................................................................324
A.12.3 SPI ...................................................................................................................................326
A.13 Flash and EEPROM ......................................................................................................................329
A.14 EMC Performance .........................................................................................................................330
A.14.1 Radiated Emissions .........................................................................................................330
Appendix B
Timer Pulse-Width Modulator (TPMV2)
B.0.1 Features ...........................................................................................................................331
B.0.2 Block Diagram ................................................................................................................331
B.1 External Signal Description ...........................................................................................................333
B.1.1 External TPM Clock Sources ..........................................................................................333
B.1.2 TPMxCHn — TPMx Channel n I/O Pins .......................................................................333
B.2 Register Definition .........................................................................................................................333
B.2.1 Timer Status and Control Register (TPMxSC) ...............................................................334
B.2.2 Timer Counter Registers (TPMxCNTH:TPMxCNTL) ...................................................335
B.2.3 Timer Counter Modulo Registers (TPMxMODH:TPMxMODL) ..................................336
B.2.4 Timer Channel n Status and Control Register (TPMxCnSC) .........................................337
B.2.5 Timer Channel Value Registers (TPMxCnVH:TPMxCnVL) .........................................338
B.3 Functional Description...................................................................................................................339
B.3.1 Counter ............................................................................................................................339
B.3.2 Channel Mode Selection .................................................................................................340
B.3.3 Center-Aligned PWM Mode ...........................................................................................342
B.4 TPM Interrupts...............................................................................................................................343
B.4.1 Clearing Timer Interrupt Flags .......................................................................................343
B.4.2 Timer Overflow Interrupt Description ............................................................................343
B.4.3 Channel Event Interrupt Description ..............................................................................344
MC9S08DN60 Series Data Sheet, Rev 3
18 Freescale Semiconductor
Section Number Title Page
B.4.4 PWM End-of-Duty-Cycle Events ...................................................................................344
Appendix C
Ordering Information and Mechanical Drawings
C.1 Ordering Information ....................................................................................................................345
C.1.1 MC9S08DN60 Series Devices ........................................................................................345
C.2 Mechanical Drawings ....................................................................................................................345
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 19
Chapter 1
Device Overview
Controller Area Network MC9S08DN60 Series devices provide peripheral flexibility and offer a pin and
code compatibility with MC9S08DV60 and MC9S08DZ60 Series devices when the CAN module is
required.
1.1 Devices in the MC9S08DN60 Series
This data sheet covers members of the MC9S08DN60 Series of MCUs:
• MC9S08DN60
• MC9S08DN48
• MC9S08DN32
• MC9S08DN16
Table 1-1 summarizes the feature set available in the MC9S08DN60 Series.
Table 1-1. MC9S08DN60 Series Features by MCU and Pin Count
Feature MC9S08DN60 MC9S08DN48 MC9S08DN32 MC9S08DN16
Flash size
(bytes) 62080 49152 33792 16896
RAM size (bytes) 2048 2048 1536 1024
EEPROM size
(bytes) 2048 1536 1024 512
Pin quantity 64 48 32 64 48 32 64 48 32 48 32
ACMP1 yes
ACMP2 yes yes1
1ACMP2O is not available.
no yes yes1no yes yes1no yes1no
ADC channels 16 16 10 16 16 10 16 16 10 16 10
DBG yes
IIC yes
IRQ yes
MCG yes
RTC yes
SCI1 yes
SPI yes
TPM1 channels 66466466464
TPM2 channels 2
XOSC yes
COP Watchdog yes
I H .. HE HE 0 ADP‘EVADFB $€¢-¢-¢-¢-i-I-¢-I- H4444 Mosw E Rwa Txm W W SDA SCL { XTAL
Chapter 1 Device Overview
MC9S08DN60 Series Data Sheet, Rev 3
20 Freescale Semiconductor
1.2 MCU Block Diagram
Figure 1-1 is the MC9S08DN60 Series system-level block diagram.
Figure 1-1. MC9S08DN60 Block Diagram
ANALOG COMPARATOR
(ACMP1)
ACMP1O
ACMP1-
ACMP1+
VSS
VDD
IIC MODULE (IIC)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI)
USER FLASH
USER RAM
MC9S08DN60 = 60K
HCS08 CORE
CPU
BDC
6-CHANNEL TIMER/PWM
MODULE (TPM1)
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
VOLTAGE
REGULATOR
COP
IRQ
LVD
OSCILLATOR (XOSC)
MULTI-PURPOSE
CLOCK GENERATOR
RESET
VREFL
VREFH
ANALOG-TO-DIGITAL
CONVERTER (ADC)
MC9S08DN60 = 2K
16-CHANNEL, 12-BIT
BKGD/MS
INTERFACE (SCI1)
SERIAL COMMUNICATIONS
SDA
SCL
MISO
SS
SPSCK
TxD1
RxD1
XTAL
EXTAL
8
(MCG)
2-CHANNEL TIMER/PWM
MODULE (TPM2)
REAL TIME COUNTER (RTC)
DEBUG MODULE (DBG)
IRQ
PTA3/PIA3/ADP3/ACMP1O
PTA4/PIA4/ADP4
PTA5/PIA5/ADP5
PTA2/PIA2/ADP2/ACMP1-
PTA1/PIA1/ADP1/ACMP1+
PTA0/PIA0/ADP0/MCLK
PORT A
PTA6/PIA6/ADP6
PTA7/PIA7/ADP7/IRQ
MOSI
PTB3/PIB3/ADP11
PTB4/PIB4/ADP12
PTB5/PIB5/ADP13
PTB2/PIB2/ADP10
PTB1/PIB1/ADP9
PTB0/PIB0/ADP8
PORT B
PTB6/PIB6/ADP14
PTB7/PIB7/ADP15
PTC3
PTC4
PTC5
PTC2
PTC1
PTC0
PORT C
PTC6
PTC7
PTD3/PID3/TPM1CH1
PTD4/PID4/TPM1CH2
PTD5/PID5/TPM1CH3
PTD2/PID2/TPM1CH0
PTD1/PID1/TPM2CH1
PTD0/PID0/TPM2CH0
PORT D
PTD6/PID6/TPM1CH4
PTD7/PID7/TPM1CH5
PTE3/SPSCK
PTE4/SCL/MOSI
PTE5/SDA/MISO
PTE2/SS
PTE1/RxD1
PTE0/TxD1
PORT E
PTE6
PTE7
PTF3/TPM2CLK/SDA
PTF4/ACMP2+
PTF5/ACMP2-
PTF2/TPM1CLK/SCL
PTF1
PTF0
PORT F
PTF6/ACMP2O
PTF7
PTG1/XTAL
PTG2
PTG3
PORT G
PTG4
PTG5
PTG0/EXTAL
VSS
VDD
VSSA
VDDA
BKP
INT
ANALOG COMPARATOR
(ACMP2)
ACMP2O
ACMP2-
ACMP2+
USER EEPROM
MC9S08DN60 = 2K
ADP7-ADP0
ADP15-ADP8
6
TPM1CH5 -
TPM2CH1,
TPM2CH0
TPM2CLK
TPM1CLK
TPM1CH0
- Pin not connected in 48-pin and 32-pin packages
- Pin not connected in 32-pin package
- VREFH/VREFL internally connected to VDDA/VSSA in 48-pin and 32-pin packages
- VDD and VSS pins are each internally connected to two pads in 32-pin package
MC9S08DN48 = 48K
MC9S08DN32 = 32K
MC9S08DN16 =16K
Chapter 1 Device Overview
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 21
Table 1-2 provides the functional version of the on-chip modules.
1.3 System Clock Distribution
Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock
inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module
function.
The following are the clocks used in this MCU:
BUSCLK — The frequency of the bus is always half of MCGOUT.
LPO — Independent 1-kHz clock that can be selected as the source for the COP and RTC modules.
MCGOUT — Primary output of the MCG and is twice the bus frequency.
MCGLCLK — Development tools can select this clock source to speed up BDC communications
in systems where BUSCLK is configured to run at a very slow frequency.
MCGERCLK — External reference clock can be selected as the RTC clock source. It can also be
used as the alternate clock for the ADC.
MCGIRCLK — Internal reference clock can be selected as the RTC clock source.
MCGFFCLK — Fixed frequency clock can be selected as clock source for the TPM1 and TPM2.
TPM1CLK — External input clock source for TPM1.
TPM2CLK — External input clock source for TPM2.
Table 1-2. Module Versions
Module Version
Central Processor Unit (CPU) 3
Multi-Purpose Clock Generator (MCG) 1
Analog Comparator (ACMP) 3
Analog-to-Digital Converter (ADC) 1
Inter-Integrated Circuit (IIC) 2
Serial Peripheral Interface (SPI) 3
Serial Communications Interface (SCI) 4
Real-Time Counter (RTC) 1
Timer Pulse Width Modulator (TPM) 31
13M05C and older masks have TPM version 2.
Debug Module (DBG) 2
+ +
Chapter 1 Device Overview
MC9S08DN60 Series Data Sheet, Rev 3
22 Freescale Semiconductor
Figure 1-2. MC9S08DN60 System Clock Distribution Diagram
TPM1 TPM2 IIC SCI1
BDC
CPU ADC FLASH
MCG
MCGOUT ÷2BUSCLK
MCGLCLK
MCGERCLK
COP
* The fixed frequency clock (FFCLK) is internally
synchronized to the bus clock and must not exceed one half
of the bus clock frequency.
Flash and EEPROM have
frequency requirements
for program and erase
operation. See
the electricals appendix
for details.
ADC has min and max
frequency requirements.
See the ADC chapter
and electricals appendix
for details.
XOSC
EXTAL XTAL
EEPROM
SPI
FFCLK*
MCGFFCLK
RTC
1 kHZ
LPO
TPM1CLK TPM2CLK
MCGIRCLK
÷2
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MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 23
Chapter 2
Pins and Connections
This section describes signals that connect to package pins. It includes pinout diagrams, recommended
system connections, and detailed discussions of signals.
2.1 Device Pin Assignment
This section shows the pin assignments for MC9S08DN60 Series MCUs in the available packages.
Figure 2-1. 64-Pin LQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64-Pin
LQFP
PTB1/PIB1/ADP9
PTB6/PIB6/ADP14
PTA6/PIA6/ADP6
PTE2/SS
PTC2
PTC5
PTA0/PIA0/ADP0/MCLK
PTA7/PIA7/ADP7/IRQ
PTC1
PTC6
PTB0/PIB0/ADP8
PTB7/PIB7/ADP15
PTC0
PTC7
BKGD/MS
VDD
PTD7/PID7/TPM1CH5
VSS
PTD6/PID6/TPM1CH4
PTG0/EXTAL
VDD
PTG1/XTAL
VSS
RESET
PTF7
PTF4/ACMP2+
PTD5/PID5/TPM1CH3
PTF5/ACMP2-
PTD4/PID4/TPM1CH2
PTF6/ACMP2O
PTD3/PID3/TPM1CH1
PTE0/TxD1
PTD2/PID2/TPM1CH0
PTE1/RxD1
PTB5/PIB5/ADP13
PTE3/SPSCK
PTA5/PIA5/ADP5
PTE4/SCL/MOSI
PTC4
PTE5/SDA/MISO
PTB4/PIB4/ADP12
PTG2
PTA4/PIA4/ADP4
PTG3
VDDA
PTF0
VREFH
PTF1
VREFL
PTF2/TPM1CLK/SCL
VSSA
PTF3/TPM2CLK/SDA
PTA3/PIA3/ADP3/ACMP1O
PTG4
PTB3/PIB3/ADP11
PTG5
PTC3
PTE6/
PTA2/PIA2/ADP2/ACMP1-
PTE7
PTB2/PIB2/ADP10
PTD0/PID0/TPM2CH0
PTA1/PIA1/ADP1/ACMP1+
PTD1/PID1/TPM2CH1
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Chapter 2 Pins and Connections
MC9S08DN60 Series Data Sheet, Rev 3
24 Freescale Semiconductor
Figure 2-2. 48-Pin LQFP
PTB1/PIB1/ADP9
PTB6/PIB6/ADP14
PTA6/PIA6/ADP6
PTE2/SS
PTA0/PIA0/ADP0/MCLKPTA7/PIA7/ADP7/IRQ
PTB0/PIB0/ADP8
PTB7/PIB7/ADP15
BKGD/MS
VDD
PTD7/PID7/TPM1CH5
VSS PTD6/PID6/TPM1CH4
PTG0/EXTAL
VDD
PTG1/XTAL
VSS
RESET
PTF4/ACMP2+ PTD5/PID5/TPM1CH3
PTF5/ACMP2- PTD4/PID4/TPM1CH2
PTD3/PID3/TPM1CH1
PTE0/TxD1
PTD2/PID2/TPM1CH0
PTE1/RxD1
PTB5/PIB5/ADP13
PTE3/SPSCK
PTA5/PIA5/ADP5
PTE4/SCL/MOSI
PTE5/SDA/MISO PTB4/PIB4/ADP12
PTA4/PIA4/ADP4
VDDA/VREFH
PTF0
PTF1
PTF2/TPM1CLK/SCL VSSA/VREFL
PTF3/TPM2CLK/SDA PTA3/PIA3/ADP3/ACMP1O
PTB3/PIB3/ADP11
PTE6
PTA2/PIA2/ADP2/ACMP1-
PTE7
PTB2/PIB2/ADP10
PTD0/PID0/TPM2CH0
PTA1/PIA1/ADP1/ACMP1+
PTD1/PID1/TPM2CH1
1
2
3
4
5
6
7
8
9
10
11
12
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
48-Pin LQFP
VREFH and VREFL are internally connected to VDDA and VSSA, respectively.
I—H—H—H—H—H—H—H—V flflfll—H—‘flflfl LILILILILILILILI \‘JUUUUUUU
Chapter 2 Pins and Connections
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 25
Figure 2-3. 32-Pin LQFP
RESET
1
2
3
4
5
6
7
8
VSS
PTG0/EXTAL
PTD1/PID1/TPM2CH1
PTD0/PID0/TPM2CH0
PTE7
PTE6
PTE5/SDA/MISO
PTE4/SCL/MOSI
PTD3/PID3/TPM1CH1
PTD4/PID4/TPM1CH2
PTD5/PID5/TPM1CH3
BKGD/MS
PTA6/PIA6/ADP6
PTA1/ADP1/ACMP+
PTB1/PIB1/ADP9
22
21
20
19
18
17
10 11 12 13 14 15
25
9
24
32
PTE0/TxD1
PTE1/RxD1
16
PTD2/PID2/TPM1CH0
PTA2/ADP2/ACMP-
VSSA/VREFL
26
VDDA/VREFH
27
PTG1/XTAL
PTB0/PIB0/ADP8
23 PTA0/PIA0/ADP0/MCLK
PTA5/PIA5/ADP5
31 30 29
PTA4/PIA4/ADP4
28
PTA7/PIA7/ADP7/IRQ
VDD
PTE2/SS
PTE3/SPSCK
32-Pin LQFP
PTA3/ADP3/ACMPO
VREFH and VREFL are internally connected to VDDA and VSSA, respectively.
Chapter 2 Pins and Connections
MC9S08DN60 Series Data Sheet, Rev 3
26 Freescale Semiconductor
2.2 Recommended System Connections
Figure 2-4 shows pin connections that are common to MC9S08DN60 Series application systems.
Figure 2-4. Basic System Connections (Shown in 64-Pin Package)
NOTES:
1. External crystal circuit not
required if using the
internal clock option.
2. RESET pin can only be
used to reset into user
mode, you can not enter
BDM using RESET pin.
BDM can be entered by
holding MS low during
POR or writing a 1 to
BDFR in SBDFR with MS
low after issuing BDM
command.
3. RC filter on RESET pin
recommended for noisy
environments.
4. For 32-pin and 48-pin
packages: VDDA and VSSA
are double bonded to
VREFH and VREFL
respectively.
PORT
A
C2
C1 X1
RFRS
PTA0/PIA0/ADP0/MCLK
PTA1/PIA1/ADP1/ACMP1+
PTA2/PIA2/ADP2/ACMP1-
PTA3/PIA3/ADP3/ACMP1O
PTA4/PIA4/ADP4
PTA5/PIA5/ADP5
PTA6/PIA6/ADP6
PTA7/PIA7/ADP7/IRQ
PORT
B
PTB0/PIB0/ADP8
PTB1/PIB1/ADP9
PORT
C
PORT
D
PTD2/PID2/TPM1CH0
PTD3/PID3/TPM1CH1
PTD4/PID4/TPM1CH2
PTD5/PID5/TPM1CH3
PORT
E
PORT
G
PTG2
PTG3
PTG4
PTG5
PORT
F
IRQ
MC9S08DN60
PTG0/EXTAL
PTG1/XTAL
PTF0
PTF1
PTF2/TPM1CLK/SCL
PTF3/TPM2CLK/SDA
PTF4/ACMP2+
PTF5/ACMP2–
PTF6/ACMP2O
PTF7
PTE0/TxD1
PTE1/RxD1
PTE2/SS
PTE3/SPSCK
PTE4/SCL/MOSI
PTE5/SDA/MISO
PTE6
PTE7
PTD0/PID0/TPM2CH0
PTD1/PID1/TPM2CH1
PTB2/PIB2/ADP10
PTB3/PIB3/ADP11
PTB4/PIB4/ADP12
PTB5/PIB5/ADP13
PTB6/PIB6/ADP14
PTB7/PIB7/ADP15
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
PTC7
PTD6/PID6/TPM1CH4
PTD7/PID7/TPM1CH5
CBY
0.1 μF
VREFH
VREFL
VSSA
VDDA
VDD
VSS
CBY
0.1 μF
CBLK
10 μF
+
5 V
+
SYSTEM
POWER
BKGD/MS
RESET
OPTIONAL
MANUAL
RESET
VDD
BACKGROUND HEADER
0.1 μF
VDD
4.7 kΩ–10 kΩ
Chapter 2 Pins and Connections
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 27
2.2.1 Power
VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all
I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated
lower-voltage source to the CPU and other internal circuitry of the MCU.
Typically, application systems have two separate capacitors across the power pins. In this case, there
should be a bulk electrolytic capacitor, such as a 10-μF tantalum capacitor, to provide bulk charge storage
for the overall system and a 0.1-μF ceramic bypass capacitor located as near to the MCU power pins as
practical to suppress high-frequency noise. The MC9S08DN60 Series has two VDD pins except on the
32-pin package. Each pin must have a bypass capacitor for best noise suppression.
VDDA and VSSA are the analog power supply pins for the MCU. This voltage source supplies power to the
ADC module. A 0.1-μF ceramic bypass capacitor should be located as near to the MCU power pins as
practical to suppress high-frequency noise.
2.2.2 Oscillator
Immediately after reset, the MCU uses an internally generated clock provided by the multi-purpose clock
generator (MCG) module. For more information on the MCG, see Chapter 8, “Multi-Purpose Clock
Generator (S08MCGV1).”
The oscillator (XOSC) in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic
resonator. Rather than a crystal or ceramic resonator, an external oscillator can be connected to the EXTAL
input pin.
Refer to Figure 2-4 for the following discussion. RS (when used) and RF should be low-inductance
resistors such as carbon composition resistors. Wire-wound resistors and some metal film resistors have
too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specifically
designed for high-frequency applications.
RFis used to provide a bias path to keep the EXTAL input in its linear range during crystal startup; its value
is not generally critical. Typical systems use 1 MΩto 10 MΩ. Higher values are sensitive to humidity, and
lower values reduce gain and (in extreme cases) could prevent startup.
C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific
crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin
capacitance when selecting C1 and C2. The crystal manufacturer typically specifies a load capacitance
which is the series combination of C1 and C2 (which are usually the same size). As a first-order
approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin
(EXTAL and XTAL).
2.2.3 RESET
RESET is a dedicated pin with a pull-up device built in. It has input hysteresis, a high current output driver,
and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make
external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background
debug connector so a development system can directly reset the MCU system. If desired, a manual external
reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset).
Chapter 2 Pins and Connections
MC9S08DN60 Series Data Sheet, Rev 3
28 Freescale Semiconductor
Whenever any reset is initiated (whether from an external signal or from an internal system), the RESET
pin is driven low for about 34 bus cycles. The reset circuitry decodes the cause of reset and records it by
setting a corresponding bit in the system reset status register (SRS).
2.2.4 Background / Mode Select (BKGD/MS)
While in reset, the BKGD/MS pin functions as a mode select pin. Immediately after reset rises, the pin
functions as the background pin and can be used for background debug communication. While functioning
as a background or mode select pin, the pin includes an internal pull-up device, input hysteresis, a standard
output driver, and no output slew rate control.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.
If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD low
during the rising edge of reset which forces the MCU to active background mode.
The BKGD/MS pin is used primarily for background debug controller (BDC) communications using a
custom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s
BDC clock could be as fast as the bus clock rate, so there should never be any significant capacitance
connected to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD/MS pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pull-up device play almost no role in determining rise and fall
times on the BKGD/MS pin.
2.2.5 ADC Reference Pins (VREFH, VREFL)
The VREFH and VREFL pins are the voltage reference high and voltage reference low inputs, respectively,
for the ADC module.
2.2.6 General-Purpose I/O and Peripheral Ports
The MC9S08DN60 Series series of MCUs support up to 53 general-purpose I/O pins and 1 input-only pin,
which are shared with on-chip peripheral functions (timers, serial I/O, ADC, etc.).
When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output,
software can select one of two drive strengths and enable or disable slew rate control. When a port pin is
configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a
pull-up device. Immediately after reset, all of these pins are configured as high-impedance general-purpose
inputs with internal pull-up devices disabled.
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pin’s output buffer. For information about controlling these pins as general-purpose I/O
pins, see Chapter 6, “Parallel Input/Output Control.”
Chapter 2 Pins and Connections
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 29
NOTE
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program should either enable on-chip pull-up
devices or change the direction of unused or non-bonded pins to outputs so
they do not float.
Chapter 2 Pins and Connections
MC9S08DN60 Series Data Sheet, Rev 3
30 Freescale Semiconductor
3
Pin
Number <-- Lowest Priority --> Highest
64 48 32 Port
Pin/Interrupt Alt 1 Alt 2
1 1 — PTB6 PIB6 ADP14
2 — PTC5
3 2 1 PTA7 PIA7 ADP7 IRQ
4 — PTC6
5 3 — PTB7 PIB7 ADP15
6 — PTC7
742 V
DD
853 V
SS
9 6 4 PTG0 EXTAL
10 7 5 PTG1 XTAL
11 8 6 RESET
12 9 — PTF4 ACMP2+
13 10 — PTF5 ACMP2-
14 — PTF6 ACMP2O
15 11 7 PTE0 TxD1
16 12 8 PTE12RxD12
17 13 9 PTE2 SS
18 14 10 PTE3 SPSCK
19 15 11 PTE4 SCL3MOSI
20 16 12 PTE5 SDA3MISO
21 — PTG2
22 — PTG3
23 17 — PTF0
24 18 — PTF1
25 19 — PTF2 TPM1CLK SCL3
26 20 — PTF3 TPM2CLK SDA3
27 — PTG4
28 — PTG5
29 21 13 PTE6
30 22 14 PTE7
31 23 15 PTD0 PID0 TPM2CH0
32 24 16 PTD1 PID1 TPM2CH1
33 25 17 PTD2 PID2 TPM1CH0
34 26 18 PTD3 PID3 TPM1CH1
35 27 19 PTD4 PID4 TPM1CH2
36 28 20 PTD5 PID5 TPM1CH3
37 — PTF7
38 29 VSS
39 30 VDD
40 31 — PTD6 PID6 TPM1CH4
41 32 — PTD7 PID7 TPM1CH5
42 33 21 BKGD MS
43 — PTC0
44 34 22 PTB0 PIB0 ADP8
45 — PTC1
46 35 23 PTA0 PIA0 ADP0 MCLK
47 — PTC2
48 36 24 PTB1 PIB1 ADP9
49 37 25 PTA1 PIA1 ADP11ACMP1+1
50 38 — PTB2 PIB2 ADP10
51 39 26 PTA2 PIA2 ADP21ACMP1-1
52 — PTC3
53 40 — PTB3 PIB3 ADP11
54 41 27 PTA3 PIA3 ADP3 ACMP1O
55 42 28 VSSA
56 VREFL
57 43 29 VREFH
58 VDDA
59 44 30 PTA4 PIA4 ADP4
60 45 — PTB4 PIB4 ADP12
61 — PTC4
62 46 31 PTA5 PIA5 ADP5
63 47 — PTB5 PIB5 ADP13
64 48 32 PTA6 PIA6 ADP6
Pin
Number <-- Lowest Priority --> Highest
64 48 32 Port
Pin/Interrupt Alt 1 Alt 2
Table 2-1. Pin Availability by Package Pin-Count
1. If both of these analog modules are enabled, they both will have access to the pin.
2. Pin does not contain a clamp diode to VDD and should not be driven above VDD. The voltage measured on this pin when internal
pull-up is enabled may be as low as VDD – 0.7 V. The internal gates connected to this pin are pulled to VDD.
3. The IIC module pins can be repositioned using IICPS bit in the SOPT1 register. The default reset locations are on PTF2 and PTF3.
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 31
Chapter 3
Modes of Operation
3.1 Introduction
The operating modes of the MC9S08DN60 Series are described in this chapter. Entry into each mode, exit
from each mode, and functionality while in each of the modes are described.
3.2 Features
Active background mode for code development
Wait mode — CPU shuts down to conserve power; system clocks are running and full regulation
is maintained
Stop modes — System clocks are stopped and voltage regulator is in standby
Stop3 — All internal circuits are powered for fast recovery
Stop2 — Partial power down of internal circuits; RAM content is retained
3.3 Run Mode
This is the normal operating mode for the MC9S08DN60 Series. This mode is selected when the
BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal
memory with execution beginning at the address fetched from memory at 0xFFFE–0xFFFF after reset.
3.4 Active Background Mode
The active background mode functions are managed through the background debug controller (BDC) in
the HCS08 core. The BDC, together with the on-chip debug module (DBG), provide the means for
analyzing MCU operation during software development.
Active background mode is entered in any of five ways:
When the BKGD/MS pin is low at the rising edge of reset
When a BACKGROUND command is received through the BKGD/MS pin
When a BGND instruction is executed
When encountering a BDC breakpoint
When encountering a DBG breakpoint
After entering active background mode, the CPU is held in a suspended state waiting for serial background
commands rather than executing instructions from the user application program.
Chapter 3 Modes of Operation
MC9S08DN60 Series Data Sheet, Rev 3
32 Freescale Semiconductor
Background commands are of two types:
Non-intrusive commands, defined as commands that can be issued while the user program is
running. Non-intrusive commands can be issued through the BKGD/MS pin while the MCU is in
run mode; non-intrusive commands can also be executed when the MCU is in the active
background mode. Non-intrusive commands include:
Memory access commands
Memory-access-with-status commands
BDC register access commands
The BACKGROUND command
Active background commands, which can only be executed while the MCU is in active background
mode. Active background commands include commands to:
Read or write CPU registers
Trace one user program instruction at a time
Leave active background mode to return to the user application program (GO)
The active background mode is used to program a bootloader or user application program into the Flash
program memory before the MCU is operated in run mode for the first time. When the MC9S08DN60
Series is shipped from the Freescale Semiconductor factory, the Flash program memory is erased by
default unless specifically noted so there is no program that could be executed in run mode until the Flash
memory is initially programmed. The active background mode can also be used to erase and reprogram
the Flash memory after it has been previously programmed.
For additional information about the active background mode, refer to the Development Support chapter.
3.5 Wait Mode
Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU
enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the
wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and
resumes processing, beginning with the stacking operations leading to the interrupt service routine.
While the MCU is in wait mode, there are some restrictions on which background debug commands can
be used. Only the BACKGROUND command and memory-access-with-status commands are available
when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access,
but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND
command can be used to wake the MCU from wait mode and enter active background mode.
Chapter 3 Modes of Operation
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 33
3.6 Stop Modes
One of two stop modes is entered upon execution of a STOP instruction when the STOPE bit in SOPT1
register is set. In both stop modes, all internal clocks are halted. The MCG module can be configured to
leave the reference clocks running. See Chapter 8, “Multi-Purpose Clock Generator (S08MCGV1),” for
more information.
Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various
conditions. The selected mode is entered following the execution of a STOP instruction.
3.6.1 Stop3 Mode
Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.
Exit from stop3 is done by asserting RESET or an asynchronous interrupt pin. The asynchronous interrupt
pins are IRQ, PIA0–PIA7, PIB0–PIB7, and PID0–PID7. Exit from stop3 can also be done by the
low-voltage detect (LVD) reset, low-voltage warning (LVW) interrupt, ADC conversion complete
interrupt, real-time clock (RTC) interrupt or SCI receiver interrupt.
If stop3 is exited by means of the RESET pin, the MCU will be reset and operation will resume after
fetching the reset vector. Exit by means of an interrupt will result in the MCU fetching the appropriate
interrupt vector.
3.6.1.1 LVD Enabled in Stop3 Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time
the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode.
For the ADC to operate the LVD must be left enabled when entering stop3.
Table 3-1. Stop Mode Selection
STOPE ENBDM 1
1ENBDM is located in the BDCSCR, which is only accessible through BDC commands, see Section 16.4.1.1, “BDC Status and
Control Register (BDCSCR)”.
LVDE LVDSE PPDC Stop Mode
0 x x x Stop modes disabled; illegal opcode reset if STOP instruction executed
1 1 x x Stop3 with BDM enabled 2
2When in Stop3 mode with BDM enabled, The SIDD will be near RIDD levels because internal clocks are enabled.
1 0 Both bits must be 1 x Stop3 with voltage regulator active
1 0 Either bit a 0 0 Stop3
1 0 Either bit a 0 1 Stop2
Chapter 3 Modes of Operation
MC9S08DN60 Series Data Sheet, Rev 3
34 Freescale Semiconductor
3.6.1.2 Active BDM Enabled in Stop3 Mode
Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This
register is described in Chapter 16, “Development Support.” If ENBDM is set when the CPU executes a
STOP instruction, the system clocks to the background debug logic remain active when the MCU enters
stop mode. Because of this, background debug communication remains possible. In addition, the voltage
regulator does not enter its low-power standby state but maintains full internal regulation.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After entering background debug mode, all background
commands are available.
3.6.2 Stop2 Mode
Stop2 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. Most
of the internal circuitry of the MCU is powered off in stop2 with the exception of the RAM. Upon entering
stop2, all I/O pin control signals are latched so that the pins retain their states during stop2.
Exit from stop2 is performed by asserting RESET. On 3M05C or older masksets only, exit from stop2 can
also be performed by asserting PTA7/ADP7/IRQ.
NOTE
On 3M05C or older masksets only, PTA7/ADP7/IRQ is an active low
wake-up and must be configured as an input prior to executing a STOP
instruction to avoid an immediate exit from stop2. PTA7/ADP7/IRQ can be
disabled as a wake-up if it is configured as a high driven output. For lowest
power consumption in stop2, this pin should not be left open when
configured as input (enable the internal pullup; or tie an external
pullup/down device; or set pin as output).
In addition, the real-time counter (RTC) can wake the MCU from stop2, if enabled.
Upon wake-up from stop2 mode, the MCU starts up as from a power-on reset (POR):
All module control and status registers are reset
The LVD reset function is enabled and the MCU remains in the reset state if VDD is below the LVD
trip point (low trip point selected due to POR)
The CPU takes the reset vector
In addition to the above, upon waking up from stop2, the PPDF bit in SPMSC2 is set. This flag is used to
direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched
until a 1 is written to PPDACK in SPMSC2.
Chapter 3 Modes of Operation
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 35
To maintain I/O states for pins that were configured as general-purpose I/O before entering stop2, the user
must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers
before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to
PPDACK, then the pins will switch to their reset states when PPDACK is written.
For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that
interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.
3.6.3 On-Chip Peripheral Modules in Stop Modes
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.2, “Stop2
Mode” and Section 3.6.1, “Stop3 Mode” for specific information on system behavior in stop modes.
Table 3-2. Stop Mode Behavior
Peripheral Mode
Stop2 Stop3
CPU Off Standby
RAM Standby Standby
Flash/EEPROM Off Standby
Parallel Port Registers Off Standby
ACMP Off Off
ADC Off Optionally On1
1Requires the asynchronous ADC clock and LVD to be enabled, else in standby.
IIC Off Standby
MCG Off Optionally On2
2IRCLKEN and IREFSTEN set in MCGC1, else in standby.
RTC Optionally On3
3Requires the RTC to be enabled, else in standby.
Optionally On3
SCI Off Standby
SPI Off Standby
TPM Off Standby
Voltage Regulator Off Optionally On4
4Requires the LVD or BDC to be enabled.
XOSC Off Optionally On5
I/O Pins States Held States Held
BDM Off6Optionally On
LVD/LVW Off7Optionally On
Chapter 3 Modes of Operation
MC9S08DN60 Series Data Sheet, Rev 3
36 Freescale Semiconductor
5ERCLKEN and EREFSTEN set in MCGC2 for, else in standby. For high frequency
range (RANGE in MCGC2 set) requires the LVD to also be enabled in stop3.
6If ENBDM is set when entering stop2, the MCU will actually enter stop3.
7If LVDSE is set when entering stop2, the MCU will actually enter stop3.
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 37
Chapter 4
Memory
4.1 MC9S08DN60 Series Memory Map
On-chip memory in the MC9S08DN60 Series consists of RAM, EEPROM, and Flash program memory
for nonvolatile data storage, and I/O and control/status registers. The registers are divided into three
groups:
Direct-page registers (0x0000 through 0x007F)
High-page registers (0x1800 through 0x18FF)
Nonvolatile registers (0xFFB0 through 0xFFBF)
x17FF Ox|7FF xwuu Ox|8FF
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
38 Freescale Semiconductor
Figure 4-1. MC9S08DN60 Series Memory Map
4.2 Reset and Interrupt Vector Assignments
Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table
are the labels used in the MC9S08DN60 Series equate file provided by Freescale Semiconductor.
Table 4-1. Reset and Interrupt Vectors
Address
(High/Low) Vector Vector Name
0xFFC0:0xFFC1 ACMP2 Vacmp2
0xFFC2:0xFFC3 ACMP1 Vacmp1
0xFFC4:0xFFCB Reserved
0xFFCC:0xFFCD RTC Vrtc
0xFFCE:0xFFCF IIC Viic
0xFFD0:0xFFD1 ADC Conversion Vadc
DIRECT PAGE REGISTERS
RAM
2048 BYTES
0x0000
0x007F
0x0080
0x1800
0x17FF
0x18FF
0x1400
0xFFFF
9S08DN60
128 BYTES
EEPROM
2 x 1024 BYTES
HIGH PAGE REGISTERS
256 BYTES
FLASH
59136 BYTES
DIRECT PAGE REGISTERS
RAM
2048 BYTES
0x0000
0x007F
0x0080
0x087F
0x1800
0x17FF
0x18FF
0x1900
0xFFFF
0x1500
9S08DN48
0x3FFF
0x4000
128 BYTES
HIGH PAGE REGISTERS
256 BYTES
FLASH
49152 BYTES
UNIMPLEMENTED
0x0880
0x14FF
3200 BYTES
UNIMPLEMENTED
9984 BYTES
DIRECT PAGE REGISTERS
RAM
1536 BYTES
0x0000
0x007F
0x0080
0x067F
0x1800
0x17FF
0x18FF
0x1900
0xFFFF
0x1600
9S08DN32
0x7BFF
0x7C00
128 BYTES
HIGH PAGE REGISTERS
256 BYTES
FLASH
33792 BYTES
UNIMPLEMENTED
0x0680
0x15FF
3968 BYTES
UNIMPLEMENTED
25344 BYTES
DIRECT PAGE REGISTERS
RAM
1024 BYTES
0x0000
0x007F
0x0080
0x047F
0x1800
0x17FF
0x18FF
0x1900
0xFFFF
0x1700
9S08DN16
0xBDFF
0xBE00
128 BYTES
HIGH PAGE REGISTERS
256 BYTES
FLASH
16896 BYTES
UNIMPLEMENTED
0x0480
0x16FF
4736 BYTES
UNIMPLEMENTED
42240 BYTES
EEPROM
2 x 512 BYTES EEPROM
2 x 256 BYTES
0x1900
FLASH
2944 BYTES
0x13FF
EEPROM
2 x 768 BYTES
0x087F
0x0880
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 39
0xFFD2:0xFFD3 Port A, Port B, Port D Vport
0xFFD4:0xFFD9 Reserved
0xFFDA:0xFFDB SCI1 Transmit Vsci1tx
0xFFDC:0xFFDD SCI1 Receive Vsci1rx
0xFFDE:0xFFDF SCI1 Error Vsci1err
0xFFE0:0xFFE1 SPI Vspi
0xFFE2:0xFFE3 TPM2 Overflow Vtpm2ovf
0xFFE4:0xFFE5 TPM2 Channel 1 Vtpm2ch1
0xFFE6:0xFFE7 TPM2 Channel 0 Vtpm2ch0
0xFFE8:0xFFE9 TPM1 Overflow Vtpm1ovf
0xFFEA:0xFFEB TPM1 Channel 5 Vtpm1ch5
0xFFEC:0xFFED TPM1 Channel 4 Vtpm1ch4
0xFFEE:0xFFEF TPM1 Channel 3 Vtpm1ch3
0xFFF0:0xFFF1 TPM1 Channel 2 Vtpm1ch2
0xFFF2:0xFFF3 TPM1 Channel 1 Vtpm1ch1
0xFFF4:0xFFF5 TPM1 Channel 0 Vtpm1ch0
0xFFF6:0xFFF7 MCG Loss of lock Vlol
0xFFF8:0xFFF9 Low-Voltage Detect Vlvd
0xFFFA:0xFFFB IRQ Virq
0xFFFC:0xFFFD SWI Vswi
0xFFFE:0xFFFF Reset Vreset
Table 4-1. Reset and Interrupt Vectors
Address
(High/Low) Vector Vector Name
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
40 Freescale Semiconductor
4.3 Register Addresses and Bit Assignments
The registers in the MC9S08DN60 Series are divided into these groups:
Direct-page registers are located in the first 128 locations in the memory map; these are accessible
with efficient direct addressing mode instructions.
High-page registers are used much less often, so they are located above 0x1800 in the memory
map. This leaves more room in the direct page for more frequently used registers and RAM.
The nonvolatile register area consists of a block of 16 locations in Flash memory at
0xFFB0–0xFFBF. Nonvolatile register locations include:
NVPROT and NVOPT are loaded into working registers at reset
An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to
secure memory
Because the nonvolatile register locations are Flash memory, they must be erased and programmed
like other Flash memory locations.
Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation
instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all
user-accessible direct-page registers and control bits.
The direct page registers in Table 4-2 can use the more efficient direct addressing mode, which requires
only the lower byte of the address. Because of this, the lower byte of the address in column one is shown
in bold text. In Table 4-3 and Table 4-4, the whole address in column one is shown in bold. In Table 4-2,
Table 4-3, and Table 4-4, the register names in column two are shown in bold to set them apart from the
bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0
indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit
locations that could read as 1s or 0s.
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 41
Table 4-2. Direct-Page Register Summary (Sheet 1 of 3)
Address Register
Name Bit 7 654321Bit 0
0x0000 PTAD PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
0x0001 PTADD PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0
0x0002 PTBD PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0
0x0003 PTBDD PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0
0x0004 PTCD PTCD7 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0
0x0005 PTCDD PTCDD7 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0
0x0006 PTDD PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0
0x0007 PTDDD PTDDD7 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0
0x0008 PTED PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0
0x0009 PTEDD PTEDD7 PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1 PTEDD0
0x000A PTFD PTFD7 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0
0x000B PTFDD PTFDD7 PTFDD6 PTFDD5 PTFDD4 PTFDD3 PTFDD2 PTFDD1 PTFDD0
0x000C PTGD 0 0 PTGD5 PTGD4 PTGD3 PTGD2 PTGD1 PTGD0
0x000D PTGDD 0 0 PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0
0x000E ACMP1SC ACME ACBGS ACF ACIE ACO ACOPE ACMOD1 ACMOD0
0x000F ACMP2SC ACME ACBGS ACF ACIE ACO ACOPE ACMOD1 ACMOD0
0x0010 ADCSC1 COCO AIEN ADCO ADCH
0x0011 ADCSC2 ADACT ADTRG ACFE ACFGT 0 0
0x0012 ADCRH 0 0 0 0 ADR11 ADR10 ADR9 ADR8
0x0013 ADCRL ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
0x0014 ADCCVH 0 0 0 0 ADCV11 ADCV10 ADCV9 ADCV8
0x0015 ADCCVL ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0
0x0016 ADCCFG ADLPC ADIV ADLSMP MODE ADICLK
0x0017 APCTL1 ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0
0x0018 APCTL2 ADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8
0x0019 APCTL3 ADPC23 ADPC22 ADPC21 ADPC20 ADPC19 ADPC18 ADPC17 ADPC16
0x001A
0x001B Reserved
0x001C IRQSC 0 IRQPDD IRQEDG IRQPE IRQF IRQACK IRQIE IRQMOD
0x001D
0x001F Reserved
0x0020 TPM1SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
0x0021 TPM1CNTH Bit 15 14 13 12 11 10 9 Bit 8
0x0022 TPM1CNTL Bit 7 654321Bit 0
0x0023 TPM1MODH Bit 15 14 13 12 11 10 9 Bit 8
0x0024 TPM1MODL Bit 7 654321Bit 0
0x0025 TPM1C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0
0x0026 TPM1C0VH Bit 15 14 13 12 11 10 9 Bit 8
0x0027 TPM1C0VL Bit 7 654321Bit 0
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
42 Freescale Semiconductor
0x0028 TPM1C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0
0x0029 TPM1C1VH Bit 15 14 13 12 11 10 9 Bit 8
0x002A TPM1C1VL Bit 7 654321Bit 0
0x002B TPM1C2SC CH2F CH2IE MS2B MS2A ELS2B ELS2A 0 0
0x002C TPM1C2VH Bit 15 14 13 12 11 10 9 Bit 8
0x002D TPM1C2VL Bit 7 654321Bit 0
0x002E TPM1C3SC CH3F CH3IE MS3B MS3A ELS3B ELS3A 0 0
0x002F TPM1C3VH Bit 15 14 13 12 11 10 9 Bit 8
0x0030 TPM1C3VL Bit 7 654321Bit 0
0x0031 TPM1C4SC CH4F CH4IE MS4B MS4A ELS4B ELS4A 0 0
0x0032 TPM1C4VH Bit 15 14 13 12 11 10 9 Bit 8
0x0033 TPM1C4VL Bit 7 654321Bit 0
0x0034 TPM1C5SC CH5F CH5IE MS5B MS5A ELS5B ELS5A 0 0
0x0035 TPM1C5VH Bit 15 14 13 12 11 10 9 Bit 8
0x0036 TPM1C5VL Bit 7 654321Bit 0
0x0037 Reserved ————————
0x0038 SCI1BDH LBKDIE RXEDGIE 0 SBR12 SBR11 SBR10 SBR9 SBR8
0x0039 SCI1BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
0x003A SCI1C1 LOOPS SCISWAI RSRC M WAKE ILT PE PT
0x003B SCI1C2 TIE TCIE RIE ILIE TE RE RWU SBK
0x003C SCI1S1 TDRE TC RDRF IDLE OR NF FE PF
0x003D SCI1S2 LBKDIF RXEDGIF 0 RXINV RWUID BRK13 LBKDE RAF
0x003E SCI1C3 R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE
0x003F SCI1D Bit 7 654321Bit 0
0x0040
0x0047 Reserved
0x0048 MCGC1 CLKS RDIV IREFS IRCLKEN IREFSTEN
0x0049 MCGC2 BDIV RANGE HGO LP EREFS ERCLKEN EREFSTEN
0x004A MCGTRM TRIM
0x004B MCGSC LOLS LOCK PLLST IREFST CLKST OSCINIT FTRIM
0x004C MCGC3 LOLIE PLLS CME 0 VDIV
0x004D
0x004F Reserved
0x0050 SPIC1 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
0x0051 SPIC2 0 0 0 MODFEN BIDIROE 0 SPISWAI SPC0
0x0052 SPIBR 0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0
0x0053 SPIS SPRF 0 SPTEF MODF 0 0 0 0
0x0054 Reserved 00000000
0x0055 SPID Bit 7 654321Bit 0
Table 4-2. Direct-Page Register Summary (Sheet 2 of 3)
Address Register
Name Bit 7 654321Bit 0
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 43
High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers
so they have been located outside the direct addressable memory space, starting at 0x1800.
0x0056
0x0057 Reserved
0x0058 IICA AD7 AD6 AD5 AD4 AD3 AD2 AD1 0
0x0059 IICF MULT ICR
0x005A IICC1 IICEN IICIE MST TX TXAK RSTA 0 0
0x005B IICS TCF IAAS BUSY ARBL 0 SRW IICIF RXAK
0x005C IICD DATA
0x005D IICC2 GCAEN ADEXT 0 0 0 AD10 AD9 AD8
0x005E
0x005F Reserved
0x0060 TPM2SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
0x0061 TPM2CNTH Bit 15 14 13 12 11 10 9 Bit 8
0x0062 TPM2CNTL Bit 7 654321Bit 0
0x0063 TPM2MODH Bit 15 14 13 12 11 10 9 Bit 8
0x0064 TPM2MODL Bit 7 654321Bit 0
0x0065 TPM2C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0
0x0066 TPM2C0VH Bit 15 14 13 12 11 10 9 Bit 8
0x0067 TPM2C0VL Bit 7 654321Bit 0
0x0068 TPM2C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0
0x0069 TPM2C1VH Bit 15 14 13 12 11 10 9 Bit 8
0x006A TPM2C1VL Bit 7 654321Bit 0
0x006B Reserved ————————
0x006C RTCSC RTIF RTCLKS RTIE RTCPS
0x006D RTCCNT RTCCNT
0x006E RTCMOD RTCMOD
0x006F Reserved ————————
0x0070
0x007F Reserved
Table 4-3. High-Page Register Summary (Sheet 1 of 3)
Address Register Name Bit 7 654321Bit 0
0x1800 SRS POR PIN COP ILOP ILAD LOCS LVD 0
0x1801 SBDFR 0000000BDFR
0x1802 SOPT1 COPT STOPE SCI2PS IICPS 0 0 0
0x1803 SOPT2 COPCLKS COPW 0 ADHTS 0 MCSEL
0x1804
0x1805 Reserved
Table 4-2. Direct-Page Register Summary (Sheet 3 of 3)
Address Register
Name Bit 7 654321Bit 0
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
44 Freescale Semiconductor
0x1806 SDIDH — — — — ID11 ID10 ID9 ID8
0x1807 SDIDL ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
0x1808 Reserved ————————
0x1809 SPMSC1 LVWF LVWACK LVWIE LVDRE LVDSE LVDE 0 BGBE
0x180A SPMSC2 0 0 LVDV LVWV PPDF PPDACK 0 PPDC
0x180B–
0x180F Reserved
0x1810 DBGCAH Bit 15 14 13 12 11 10 9 Bit 8
0x1811 DBGCAL Bit 7 654321Bit 0
0x1812 DBGCBH Bit 15 14 13 12 11 10 9 Bit 8
0x1813 DBGCBL Bit 7 654321Bit 0
0x1814 DBGFH Bit 15 14 13 12 11 10 9 Bit 8
0x1815 DBGFL Bit 7 654321Bit 0
0x1816 DBGC DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN
0x1817 DBGT TRGSEL BEGIN 0 0 TRG3 TRG2 TRG1 TRG0
0x1818 DBGS AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0
0x1819
0x181F Reserved
0x1820 FCDIV DIVLD PRDIV8 DIV
0x1821 FOPT KEYEN FNORED EPGMOD 0 0 0 SEC
0x1822 Reserved ————————
0x1823 FCNFG 0 EPGSEL KEYACC Reserved10001
0x1824 FPROT EPS FPS
0x1825 FSTAT FCBEF FCCF FPVIOL FACCERR 0 FBLANK 0 0
0x1826 FCMD FCMD
0x1827
0x183F Reserved
0x1840 PTAPE PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0
0x1841 PTASE PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0
0x1842 PTADS PTADS7 PTADS6 PTADS5 PTADS4 PTADS3 PTADS2 PTADS1 PTADS0
0x1843 Reserved ————————
0x1844 PTASC 0 0 0 0 PTAIF PTAACK PTAIE PTAMOD
0x1845 PTAPS PTAPS7 PTAPS6 PTAPS5 PTAPS4 PTAPS3 PTAPS2 PTAPS1 PTAPS0
0x1846 PTAES PTAES7 PTAES6 PTAES5 PTAES4 PTAES3 PTAES2 PTAES1 PTAES0
0x1847 Reserved ————————
0x1848 PTBPE PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0
0x1849 PTBSE PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0
0x184A PTBDS PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0
0x184B Reserved ————————
0x184C PTBSC 0 0 0 0 PTBIF PTBACK PTBIE PTBMOD
Table 4-3. High-Page Register Summary (Sheet 2 of 3)
Address Register Name Bit 7 654321Bit 0
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 45
Nonvolatile Flash registers, shown in Table 4-4, are located in the Flash memory. These registers include
an 8-byte backdoor key, NVBACKKEY, which can be used to gain access to secure memory resources.
During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the Flash
memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers
to control security and block protection options.
0x184D PTBPS PTBPS7 PTBPS6 PTBPS5 PTBPS4 PTBPS3 PTBPS2 PTBPS1 PTBPS0
0x184E PTBES PTBES7 PTBES6 PTBES5 PTBES4 PTBES3 PTBES2 PTBES1 PTBES0
0x184F Reserved ————————
0x1850 PTCPE PTCPE7 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0
0x1851 PTCSE PTCSE7 PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0
0x1852 PTCDS PTCDS7 PTCDS6 PTCDS5 PTCDS4 PTCDS3 PTCDS2 PTCDS1 PTCDS0
0x1853
0x1857 Reserved
0x1858 PTDPE PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0
0x1859 PTDSE PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0
0x185A PTDDS PTDDS7 PTDDS6 PTDDS5 PTDDS4 PTDDS3 PTDDS2 PTDDS1 PTDDS0
0x185B Reserved ————————
0x185C PTDSC 0 0 0 0 PTDIF PTDACK PTDIE PTDMOD
0x185D PTDPS PTDPS7 PTDPS6 PTDPS5 PTDPS4 PTDPS3 PTDPS2 PTDPS1 PTDPS0
0x185E PTDES PTDES7 PTDES6 PTDES5 PTDES4 PTDES3 PTDES2 PTDES1 PTDES0
0x185F Reserved ————————
0x1860 PTEPE PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0
0x1861 PTESE PTESE7 PTESE6 PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0
0x1862 PTEDS PTEDS7 PTEDS6 PTEDS5 PTEDS4 PTEDS3 PTEDS2 PTEDS1 PTEDS0
0x1863
0x1867 Reserved
0x1868 PTFPE PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0
0x1869 PTFSE PTFSE7 PTFSE6 PTFSE5 PTFSE4 PTFSE3 PTFSE2 PTFSE1 PTFSE0
0x186A PTFDS PTFDS7 PTFDS6 PTFDS5 PTFDS4 PTFDS3 PTFDS2 PTFDS1 PTFDS0
0x186B
0x186F Reserved
0x1870 PTGPE 0 0 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0
0x1871 PTGSE 0 0 PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSE0
0x1872 PTGDS 0 0 PTGDS5 PTGDS4 PTGDS3 PTGDS2 PTGDS1 PTGDS0
0x1873–
0x18FF Reserved
1This bit is reserved. User must write a 1 to this bit. Failing to do so may result in unexpected behavior.
Table 4-3. High-Page Register Summary (Sheet 3 of 3)
Address Register Name Bit 7 654321Bit 0
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
46 Freescale Semiconductor
Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily
disengage memory security. This key mechanism can be accessed only through user code running in secure
memory. (A security key cannot be entered directly through background debug commands.) This security
key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the
only way to disengage security is by mass erasing the Flash if needed (normally through the background
debug interface) and verifying that Flash is blank. To avoid returning to secure mode after the next reset,
program the security bits (SEC) to the unsecured state (1:0).
Table 4-4. Nonvolatile Register Summary
Address Register Name Bit 7 654321Bit 0
0xFFAE Reserved for
storage of FTRIM 0 0 0 0 0 0 0 FTRIM
0xFFAF Res.forstorageof
MCGTRM TRIM
0xFFB0–
0xFFB7
NVBACKKEY 8-Byte Comparison Key
0xFFB8–
0xFFBC
Reserved
0xFFBD NVPROT EPS FPS
0xFFBE Reserved ————————
0xFFBF NVOPT KEYEN FNORED EPGMOD 0 0 0 SEC
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 47
4.4 RAM
The MC9S08DN60 Series includes static RAM. The locations in RAM below 0x0100 can be accessed
using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit
manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed
program variables in this area of RAM is preferred.
The RAM retains data while the MCU is in low-power wait, stop2, or stop3 mode. At power-on the
contents of RAM are uninitialized. RAM data is unaffected by any reset if the supply voltage does not drop
below the minimum value for RAM retention (VRAM).
For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the
MC9S08DN60 Series, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct
page RAM can be used for frequently accessed RAM variables and bit-addressable program variables.
Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated
to the highest address of the RAM in the Freescale Semiconductor equate file).
LDHX #RamLast+1 ;point one past RAM
TXS ;SP<-(H:X-1)
When security is enabled, the RAM is considered a secure memory resource and is not accessible through
BDM or code executing from non-secure memory. See Section 4.5.9, “Security”, for a detailed description
of the security feature.
4.5 Flash and EEPROM
MC9S08DN60 Series devices include Flash and EEPROM memory intended primarily for program and
data storage. In-circuit programming allows the operating program and data to be loaded into Flash and
EEPROM, respectively, after final assembly of the application product. It is possible to program the arrays
through the single-wire background debug interface. Because no special voltages are needed for erase and
programming operations, in-application programming is also possible through other software-controlled
communication paths. For a more detailed discussion of in-circuit and in-application programming, refer
to the HCS08 Family Reference Manual, Volume I, Freescale Semiconductor document order number
HCS08RMv1.
4.5.1 Features
Features of the Flash and EEPROM memory include:
Array size (see Table 1-1 for exact array sizes)
Flash sector size: 768 bytes
EEPROM sector size: selectable 4-byte or 8-byte sector mapping operation
Single power supply program and erase
Command interface for fast program and erase operation
Up to 100,000 program/erase cycles at typical voltage and temperature
Flexible block protection and vector redirection
Security feature for Flash, EEPROM, and RAM
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
48 Freescale Semiconductor
Burst programming capability
Sector erase abort
4.5.2 Program and Erase Times
Before any program or erase command can be accepted, the Flash and EEPROM clock divider register
(FCDIV) must be written to set the internal clock for the Flash and EEPROM module to a frequency
(fFCLK) between 150 kHz and 200 kHz (see Section 4.5.11.1, “Flash and EEPROM Clock Divider
Register (FCDIV)”). This register can be written only once, so normally this write is performed during
reset initialization. The user must ensure that FACCERR is not set before writing to the FCDIV register.
One period of the resulting clock (1/fFCLK) is used by the command processor to time program and erase
pulses. An integer number of these timing pulses is used by the command processor to complete a program
or erase command.
Table 4-5 shows program and erase times. The bus clock frequency and FCDIV determine the frequency
of FCLK (fFCLK). The time for one cycle of FCLK is tFCLK = 1/fFCLK. The times are shown as a number
of cycles of FCLK and as an absolute time for the case where tFCLK =5μs. Program and erase times
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
4.5.3 Program and Erase Command Execution
The FCDIV register must be initialized after any reset and any error flag is cleared before beginning
command execution. The command execution steps are:
1. Write a data value to an address in the Flash or EEPROM array. The address and data information
from this write is latched into the Flash and EEPROM interface. This write is a required first step
in any command sequence. For erase and blank check commands, the value of the data is not
important. For sector erase commands, the address can be any address in the sector of Flash or
EEPROM to be erased. For mass erase and blank check commands, the address can be any address
in the Flash or EEPROM memory. Flash and EEPROM erase independently of each other.
Table 4-5. Program and Erase Times
Parameter Cycles of FCLK Time if FCLK = 200 kHz
Byte program 9 45 μs
Burst program 4 20 μs1
1Excluding start/end overhead
Sector erase 4000 20 ms
Mass erase 20,000 100 ms
Sector erase abort 4 20 μs1
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 49
NOTE
Before programming a particular byte in the Flash or EEPROM, the sector
in which that particular byte resides must be erased by a mass or sector erase
operation. Reprogramming bits in an already programmed byte without first
performing an erase operation may disturb data stored in the Flash or
EEPROM memory.
2. Write the command code for the desired command to FCMD. The six valid commands are blank
check (0x05), byte program (0x20), burst program (0x25), sector erase (0x40), mass erase1(0x41),
and sector erase abort (0x47). The command code is latched into the command buffer.
3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its
address and data information).
A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the
write to the memory array and before writing the 1 that clears FCBEF and launches the complete
command. Aborting a command in this way sets the FACCERR access error flag which must be
cleared before starting a new command.
A strictly monitored procedure must be obeyed or the command will not be accepted. This
minimizes the possibility of any unintended changes to the memory contents. The command
complete flag (FCCF) indicates when a command is complete. The command sequence must be
completed by clearing FCBEF to launch the command. Figure 4-2 is a flowchart for executing all
of the commands except for burst programming and sector erase abort.
4. Wait until the FCCF bit in FSTAT is set. As soon as FCCF= 1, the operation has completed
successfully.
1. A mass erase is possible only when the Flash block is fully unprotected.
iiiiiiiiiiiiiiiiiiiiiiiiii Liiiii7,7,77,77,7777777774
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
50 Freescale Semiconductor
Figure 4-2. Program and Erase Flowchart
4.5.4 Burst Program Execution
The burst program command is used to program sequential bytes of data in less time than would be
required using the standard program command. This is possible because the high voltage to the Flash array
does not need to be disabled between program operations. Ordinarily, when a program or erase command
is issued, an internal charge pump associated with the Flash memory must be enabled to supply high
voltage to the array. Upon completion of the command, the charge pump is turned off. When a burst
program command is issued, the charge pump is enabled and remains enabled after completion of the burst
program operation if these two conditions are met:
The next burst program command sequence has begun before the FCCF bit is set.
The next sequential address selects a byte on the same burst block as the current byte being
programmed. A burst block in this Flash memory consists of 32 bytes. A new burst block begins
at each 32-byte address boundary.
The first byte of a series of sequential bytes being programmed in burst mode will take the same amount
of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst
START
WRITE COMMAND TO FCMD
NO
YES
FPVIOL OR
WRITE 1 TO FCBEF
TO LAUNCH COMMAND
AND CLEAR FCBEF (2)
1
0
FCCF?
ERROR EXIT
DONE
(2) Wait at least four bus cycles
before checking FCBEF or FCCF.
0
FACCERR?
CLEAR ERROR
FACCERR?
WRITE TO FCDIV(1) (1) Required only once
after reset.
PROGRAM AND
ERASE FLOW
WRITE TO FLASH OR EEPROM TO
BUFFER ADDRESS AND DATA
iiiiiiiiiiiiiiiiiiiiiiiii L777777777777777777777774
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 51
program time provided that the conditions above are met. If the next sequential address is the beginning of
a new row, the program time for that byte will be the standard time instead of the burst time. This is because
the high voltage to the array must be disabled and then enabled again. If a new burst command has not been
queued before the current command completes, then the charge pump will be disabled and high voltage
removed from the array.
A flowchart to execute the burst program operation is shown in Figure 4-3.
Figure 4-3. Burst Program Flowchart
1
0
FCBEF?
START
WRITE TO Flash
TO BUFFER ADDRESS AND DATA
WRITE COMMAND TO FCMD
NO
YES
FPVIOL OR
WRITE 1 TO FCBEF
TO LAUNCH COMMAND
AND CLEAR FCBEF (2)
NO
YES
NEW BURST COMMAND?
1
0
FCCF?
ERROR EXIT
DONE
(2) Wait at least four bus cycles
before checking FCBEF or FCCF.
1
0
FACCERR?
CLEAR ERROR
FACCERR?
WRITE TO FCDIV(1) (1) Required only once
after reset.
BURST PROGRAM
FLOW
1\\\\\\\\\\\\\ \\\\\\\\ r\\\\\\\\\\\\\ \\\\\\\\
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
52 Freescale Semiconductor
4.5.5 Sector Erase Abort
The sector erase abort operation will terminate the active sector erase operation so that other sectors are
available for read and program operations without waiting for the sector erase operation to complete.
The sector erase abort command write sequence is as follows:
1. Write to any Flash or EEPROM address to start the command write sequence for the sector erase
abort command. The address and data written are ignored.
2. Write the sector erase abort command, 0x47, to the FCMD register.
3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the sector erase
abort command.
If the sector erase abort command is launched resulting in the early termination of an active sector erase
operation, the FACCERR flag will set once the operation completes as indicated by the FCCF flag being
set. The FACCERR flag sets to inform the user that the Flash sector may not be fully erased and a new
sector erase command must be launched before programming any location in that specific sector.
If the sector erase abort command is launched but the active sector erase operation completes normally,
the FACCERR flag will not set upon completion of the operation as indicated by the FCCF flag being set.
Therefore, if the FACCERR flag is not set after the sector erase abort command has completed, a sector
being erased when the abort command was launched will be fully erased.
A flowchart to execute the sector erase abort operation is shown in Figure 4-4.
Figure 4-4. Sector Erase Abort Flowchart
START
WRITE 0x47 TO FCMD
WRITE 1 TO FCBEF
TO LAUNCH COMMAND
AND CLEAR FCBEF (2)
1
0
FCCF?
SECTOR ERASE ABORTED
(2) Wait at least four bus cycles
0
1
FCCF?
WRITE TO Flash
TO BUFFER ADDRESS AND DATA
FACCERR?
0
1
SECTOR ERASE COMPLETED
before checking FCBEF or FCCF.
SECTOR ERASE
ABORT FLOW
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 53
NOTE
The FCBEF flag will not set after launching the sector erase abort command.
If an attempt is made to start a new command write sequence with a sector
erase abort operation active, the FACCERR flag in the FSTAT register will
be set. A new command write sequence may be started after clearing the
ACCERR flag, if set.
NOTE
The sector erase abort command should be used sparingly since a sector
erase operation that is aborted counts as a complete program/erase cycle.
4.5.6 Access Errors
An access error occurs whenever the command execution protocol is violated.
Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set.
FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed.
Writing to a Flash address before the internal Flash and EEPROM clock frequency has been set by
writing to the FCDIV register.
Writing to a Flash address while FCBEF is not set. (A new command cannot be started until the
command buffer is empty.)
Writing a second time to a Flash address before launching the previous command. (There is only
one write to Flash for every command.)
Writing a second time to FCMD before launching the previous command. (There is only one write
to FCMD for every command.)
Writing to any Flash control register other than FCMD after writing to a Flash address.
Writing any command code other than the six allowed codes (0x05, 0x20, 0x25, 0x40, 0x41, or
0x47) to FCMD.
Writing any Flash control register other than to write to FSTAT (to clear FCBEF and launch the
command) after writing the command to FCMD.
The MCU enters stop mode while a program or erase command is in progress. (The command is
aborted.)
Writing the byte program, burst program, sector erase or sector erase abort command code (0x20,
0x25, 0x40, or 0x47) with a background debug command while the MCU is secured. (The
background debug controller can do blank check and mass erase commands only when the MCU
is secure.)
Writing 0 to FCBEF to cancel a partial command.
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
54 Freescale Semiconductor
4.5.7 Block Protection
The block protection feature prevents the protected region of Flash or EEPROM from program or erase
changes. Block protection is controlled through the Flash and EEPROM protection register (FPROT). The
EPS bits determine the protected region of EEPROM and the FPS bits determine the protected region of
Flash. See Section 4.5.11.4, “Flash and EEPROM Protection Register (FPROT and NVPROT).”
After exit from reset, FPROT is loaded with the contents of the NVPROT location, which is in the
nonvolatile register block of the Flash memory. Any FPROT write that attempts to decrease the size of the
protected region will be ignored. Because NVPROT is within the last sector of Flash, if any amount of
memory is protected, NVPROT is itself protected and cannot be unprotected (intentionally or
unintentionally) by the application software. FPROT can be written through background debug
commands, which provides a way to erase and reprogram protected Flash memory.
One use for block protection is to block protect an area of Flash memory for a bootloader program. this
bootloader program can call a routine outside of Flash that can be used to sector erase the rest of the Flash
memory and reprogram it. The bootloader is protected even if MCU power is lost during an erase and
reprogram operation.
4.5.8 Vector Redirection
While any Flash is block protected, the reset and interrupt vectors will be protected. Vector redirection
allows users to modify interrupt vector information without unprotecting bootloader and reset vector
space. Vector redirection is enabled by programming the FNORED bit in the NVOPT register located at
address 0xFFBF to 0. For redirection to occur, at least some portion of the Flash memory must be block
protected by programming the NVPROT register located at address 0xFFBD. All interrupt vectors
(memory locations 0xFFC0–0xFFFD) are redirected, though the reset vector (0xFFFE:0xFFFF) is not.
For example, if 1536 bytes of Flash are protected, the protected address region is from 0xFA00 through
0xFFFF. The interrupt vectors (0xFFC0–0xFFFD) are redirected to the locations 0xF9C0–0xF9FD. If
vector redirection is enabled and an interrupt occurs, the values in the locations 0xF9E0:0xF9E1 are used
for the vector instead of the values in the locations 0xFFE0:0xFFE1. This allows the user to reprogram the
unprotected portion of the Flash with new program code including new interrupt vector values while
leaving the protected area, which includes the default vector locations, unchanged.
4.5.9 Security
The MC9S08DN60 Series includes circuitry to prevent unauthorized access to the contents of Flash,
EEPROM, and RAM memory. When security is engaged, Flash, EEPROM, and RAM are considered
secure resources. Direct-page registers, high-page registers, and the background debug controller are
considered unsecured resources. Programs executing within secure memory have normal access to any
MCU memory locations and resources. Attempts to access a secure memory location with a program
executing from an unsecured memory space or through the background debug interface are blocked (writes
are ignored and reads return all 0s).
Security is engaged or disengaged based on the state of two register bits (SEC[1:0]) in the FOPT register.
During reset, the contents of the nonvolatile location NVOPT are copied from Flash into the working
FOPT register in high-page register space. A user engages security by programming the NVOPT location,
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 55
which can be performed at the same time the Flash memory is programmed. The 1:0 state disengages
security; the other three combinations engage security. Notice the erased state (1:1) makes the MCU
secure. During development, whenever the Flash is erased, it is good practice to immediately program the
SEC0 bit to 0 in NVOPT so SEC = 1:0. This would allow the MCU to remain unsecured after a subsequent
reset.
The on-chip debug module cannot be enabled while the MCU is secure. The separate background debug
controller can be used for background memory access commands, but the MCU cannot enter active
background mode except by holding BKGD low at the rising edge of reset.
A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor
security key. If the nonvolatile KEYEN bit in NVOPT/FOPT is 0, the backdoor key is disabled and there
is no way to disengage security without completely erasing all Flash locations. If KEYEN is 1, a secure
user program can temporarily disengage security by:
1. Writing 1 to KEYACC in the FCNFG register. This makes the Flash module interpret writes to the
backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to be
compared against the key rather than as the first step in a Flash program or erase command.
2. Writing the user-entered key values to the NVBACKKEY through NVBACKKEY+7 locations.
These writes must be performed in order starting with the value for NVBACKKEY and ending
with NVBACKKEY+7. STHX must not be used for these writes because these writes cannot be
performed on adjacent bus cycles. User software normally would get the key codes from outside
the MCU system through a communication interface such as a serial I/O.
3. Writing 0 to KEYACC in the FCNFG register. If the 8-byte key that was written matches the key
stored in the Flash locations, SEC bits are automatically changed to 1:0 and security will be
disengaged until the next reset.
The security key can be written only from secure memory (either RAM, EEPROM, or Flash), so it cannot
be entered through background commands without the cooperation of a secure user program.
The backdoor comparison key (NVBACKKEY through NVBACKKEY+7) is located in Flash memory
locations in the nonvolatile register space so users can program these locations exactly as they would
program any other Flash memory location. The nonvolatile registers are in the same 768-byte block of
Flash as the reset and interrupt vectors, so block protecting that space also block protects the backdoor
comparison key. Block protects cannot be changed from user application programs, so if the vector space
is block protected, the backdoor security key mechanism cannot permanently change the block protect,
security settings, or the backdoor key.
Security can always be disengaged through the background debug interface by taking these steps:
1. Disable any block protections by writing FPROT. FPROT can be written only with background
debug commands, not from application software.
2. Mass erase Flash if necessary.
3. Blank check Flash. Provided Flash is completely erased, security is disengaged until the next reset.
To avoid returning to secure mode after the next reset, program NVOPT so SEC = 1:0.
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
56 Freescale Semiconductor
4.5.10 EEPROM Mapping
Only half of the EEPROM is in the memory map. The EPGSEL bit in FCNFG register selects which half
of the array can be accessed in foreground while the other half can not be accessed in background. There
are two mapping mode options that can be selected to configure the 8-byte EEPROM sectors: 4-byte mode
and 8-byte mode. Each mode is selected by the EPGMOD bit in the FOPT register.
In 4-byte sector mode (EPGMOD = 0), each 8-byte sector splits four bytes on foreground and four bytes
on background but on the same addresses. The EPGSEL bit selects which four bytes can be accessed.
During a sector erase, the entire 8-byte sector (four bytes in foreground and four bytes in background) is
erased.
In 8-byte sector mode (EPGMOD = 1), each entire 8-byte sector is in a single page. The EPGSEL bit
selects which sectors are on background. During a sector erase, the entire 8-byte sector in foreground is
erased.
4.5.11 Flash and EEPROM Registers and Control Bits
The Flash and EEPROM modules have seven 8-bit registers in the high-page register space and three
locations in the nonvolatile register space in Flash memory. Two of those locations are copied into two
corresponding high-page control registers at reset. There is also an 8-byte comparison key in Flash
memory. Refer to Table 4-3 and Table 4-4 for the absolute address assignments for all Flash and EEPROM
registers. This section refers to registers and control bits only by their names. A Freescale
Semiconductor-provided equate or header file normally is used to translate these names into the
appropriate absolute addresses.
4.5.11.1 Flash and EEPROM Clock Divider Register (FCDIV)
Bit 7 of this register is a read-only flag. Bits 6:0 may be read at any time but can be written only one time.
Before any erase or programming operations are possible, write to this register to set the frequency of the
clock for the nonvolatile memory system within acceptable limits.
76543210
R DIVLD PRDIV8 DIV
W
Reset 00000000
= Unimplemented or Reserved
Figure 4-5. Flash and EEPROM Clock Divider Register (FCDIV)
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 57
if PRDIV8 = 0 — fFCLK = fBus ÷ (DIV + 1) Eqn. 4-1
if PRDIV8 = 1 — fFCLK = fBus ÷ (8 × (DIV + 1)) Eqn. 4-2
Table 4-7 shows the appropriate values for PRDIV8 and DIV for selected bus frequencies.
4.5.11.2 Flash and EEPROM Options Register (FOPT and NVOPT)
During reset, the contents of the nonvolatile location NVOPT are copied from Flash into FOPT. To change
the value in this register, erase and reprogram the NVOPT location in Flash memory as usual and then issue
a new MCU reset.
Table 4-6. FCDIV Register Field Descriptions
Field Description
7
DIVLD Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for Flash and EEPROM.
1 FCDIV has been written since reset; erase and program operations enabled for Flash and EEPROM.
6
PRDIV8 Prescale (Divide) Flash and EEPROM Clock by 8 (This bit is write once.)
0 Clock input to the Flash and EEPROM clock divider is the bus rate clock.
1 Clock input to the Flash and EEPROM clock divider is the bus rate clock divided by 8.
5:0
DIV Divisor for Flash and EEPROM Clock Divider — These bits are write once. The Flash and EEPROM clock
divider divides the bus rate clock (or the bus rate clock divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV
field plus one. The resulting frequency of the internal Flash and EEPROM clock must fall within the range of
200 kHz to 150 kHz for proper Flash and EEPROM operations. Program/Erase timing pulses are one cycle of
this internal Flash and EEPROM clock which corresponds to a range of 5 μs to 6.7 μs. The automated
programming logic uses an integer number of these pulses to complete an erase or program operation. See
Equation 4-1 and Equation 4-2.
Table 4-7. Flash and EEPROM Clock Divider Settings
fBus PRDIV8
(Binary) DIV
(Decimal) fFCLK Program/Erase Timing Pulse
(5 μs Min, 6.7 μs Max)
20 MHz 1 12 192.3 kHz 5.2 μs
10 MHz 0 49 200 kHz 5 μs
8 MHz 0 39 200 kHz 5 μs
4 MHz 0 19 200 kHz 5 μs
2 MHz 0 9 200 kHz 5 μs
1 MHz 0 4 200 kHz 5 μs
200 kHz 0 0 200 kHz 5 μs
150 kHz 0 0 150 kHz 6.7 μs
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
58 Freescale Semiconductor
76543210
R KEYEN FNORED EPGMOD 0 0 0 SEC
W
Reset F F F 0 0 0 F F
= Unimplemented or Reserved F = loaded from nonvolatile location NVOPT during reset
Figure 4-6. Flash and EEPROM Options Register (FOPT)
Table 4-8. FOPT Register Field Descriptions
Field Description
7
KEYEN Backdoor Key Mechanism Enable — When this bit is 0, the backdoor key mechanism cannot be used to
disengage security. The backdoor key mechanism is accessible only from user (secured) firmware. BDM
commands cannot be used to write key comparison values that would unlock the backdoor key. For more detailed
information about the backdoor key mechanism, refer to Section 4.5.9, “Security.”
0 No backdoor key access allowed.
1 If user firmware writes an 8-byte value that matches the nonvolatile backdoor key (NVBACKKEY through
NVBACKKEY+7 in that order), security is temporarily disengaged until the next MCU reset.
6
FNORED Vector Redirection Disable — When this bit is 1, then vector redirection is disabled.
0 Vector redirection enabled.
1 Vector redirection disabled.
5
EPGMOD EEPROM Sector Mode — When this bit is 0, each sector is split into two pages (4-byte mode). When this bit is
1, each sector is in a single page (8-byte mode).
0 Half of each EEPROM sector is in Page 0 and the other half is in Page 1.
1 Each sector is in a single page.
1:0
SEC Security State Code — This 2-bit field determines the security state of the MCU as shown in Table 4-9. When
the MCU is secure, the contents of RAM, EEPROM and Flash memory cannot be accessed by instructions from
any unsecured source including the background debug interface. SEC changes to 1:0 after successful backdoor
key entry or a successful blank check of Flash. For more detailed information about security, refer to Section
4.5.9, “Security.”
Table 4-9. Security States1
1SEC changes to 1:0 after successful backdoor key entry
or a successful blank check of Flash.
SEC[1:0] Description
0:0 secure
0:1 secure
1:0 unsecured
1:1 secure
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 59
4.5.11.3 Flash and EEPROM Configuration Register (FCNFG)
4.5.11.4 Flash and EEPROM Protection Register (FPROT and NVPROT)
The FPROT register defines which Flash and EEPROM sectors are protected against program and erase
operations.
During the reset sequence, the FPROT register is loaded from the nonvolatile location NVPROT. To
change the protection that will be loaded during the reset sequence, the sector containing NVPROT must
be unprotected and erased, then NVPROT can be reprogrammed.
FPROT bits are readable at any time and writable as long as the size of the protected region is being
increased. Any write to FPROT that attempts to decrease the size of the protected memory will be ignored.
Trying to alter data in any protected area will result in a protection violation error and the FPVIOL flag
will be set in the FSTAT register. Mass erase is not possible if any one of the sectors is protected.
Figure 4-8. Flash and EEPROM Protection Register (FPROT)
76543210
R0 EPGSEL KEYACC Reserved1
1User must write a 1 to this bit. Failing to do so may result in unexpected behavior.
0001
W
Reset 00010001
= Unimplemented or Reserved
Figure 4-7. Flash Configuration Register (FCNFG)
Table 4-10. FCNFG Register Field Descriptions
Field Description
6
EPGSEL EEPROM Page Select — This bit selects which EEPROM page is accessed in the memory map.
0 Page 0 is in foreground of memory map. Page 1 is in background and can not be accessed.
1 Page 1 is in foreground of memory map. Page 0 is in background and can not be accessed.
5
KEYACC Enable Writing of Access Key — This bit enables writing of the backdoor comparison key. For more detailed
information about the backdoor key mechanism, refer to Section 4.5.9, “Security.”
0 Writes to 0xFFB0–0xFFB7 are interpreted as the start of a Flash programming or erase command.
1 Writes to NVBACKKEY (0xFFB0–0xFFB7) are interpreted as comparison key writes.
76543210
REPS1
1Background commands can be used to change the contents of these bits in FPROT.
FPS1
W
Reset This register is loaded from nonvolatile location NVPROT during reset.
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
60 Freescale Semiconductor
Table 4-11. FPROT Register Field Descriptions
Field Description
7:6
EPS EEPROM Protect Select Bits — This 2-bit field determines the protected EEPROM locations that cannot be
erased or programmed. See Table 4-12.
5:0
FPS Flash Protect Select Bits — This 6-bit field determines the protected Flash locations that cannot be erased or
programmed. SeeTable 4-13.
Table 4-12. EEPROM Block Protection
EPS Address Area Protected Memory Size Protected (bytes) Number of Sectors Protected
0x3 N/A 0 0
0x2 0x17F0 - 0x17FF 32 4
0x1 0x17E0 - 0x17FF 64 8
0x0 0x17C0–0x17FF 128 16
Table 4-13. Flash Block Protection
FPS Address Area Protected Memory Size Protected (bytes) Number of Sectors Protected
0x3F N/A 0 0
0x3E 0xFA00–0xFFFF 1.5K 2
0x3D 0xF400–0xFFFF 3K 4
0x3C 0xEE00–0xFFFF 4.5K 6
0x3B 0xE800–0xFFFF 6K 8
... ... ... ...
0x37 0xD000–0xFFFF 12K 16
0x36 0xCA00–0xFFFF 13.5K 18
0x35 0xC400–0xFFFF 15K 20
0x34 0xBE00–0xFFFF 16.5K 22
... ... ... ...
0x2C 0x8E00–0xFFFF 28.5K 38
0x2B 0x8800–0xFFFF 30K 40
0x2A 0x8200–0xFFFF 31.5K 42
0x29 0x7C00–0xFFFF 33K 44
... ... ... ...
0x22 0x5200–0xFFFF 43.5K 58
0x21 0x4C00–0xFFFF 45K 60
0x20 0x4600–0xFFFF 46.5K 62
0x1F 0x4000–0xFFFF 48K 64
... ... ... ...
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 61
4.5.11.5 Flash and EEPROM Status Register (FSTAT)
0x1B 0x2800–0xFFFF 54K 72
0x1A 0x2200–0xFFFF 55.5K 74
0x19 0x1C00–0xFFFF 57K 76
0x18–0x00 0x0000–0xFFFF 64K 86
76543210
RFCBEF FCCF FPVIOL FACCERR 0 FBLANK 0 0
W
Reset 11000000
= Unimplemented or Reserved
Figure 4-9. Flash and EEPROM Status Register (FSTAT)
Table 4-14. FSTAT Register Field Descriptions
Field Description
7
FCBEF Command Buffer Empty Flag — The FCBEF bit is used to launch commands. It also indicates that the
command buffer is empty so that a new command sequence can be executed when performing burst
programming. The FCBEF bit is cleared by writing a 1 to it or when a burst program command is transferred to
the array for programming. Only burst program commands can be buffered.
0 Command buffer is full (not ready for additional commands).
1 A new burst program command can be written to the command buffer.
6
FCCF Command Complete Flag — FCCF is set automatically when the command buffer is empty and no command
is being processed. FCCF is cleared automatically when a new command is started (by writing 1 to FCBEF to
register a command). Writing to FCCF has no meaning or effect.
0 Command in progress
1 All commands complete
5
FPVIOL Protection Violation Flag — FPVIOL is set automatically when a command that attempts to erase or program
a location in a protected block is launched (the erroneous command is ignored). FPVIOL is cleared by writing a
1 to FPVIOL.
0 No protection violation.
1 An attempt was made to erase or program a protected location.
Table 4-13. Flash Block Protection (continued)
FPS Address Area Protected Memory Size Protected (bytes) Number of Sectors Protected
Chapter 4 Memory
MC9S08DN60 Series Data Sheet, Rev 3
62 Freescale Semiconductor
4.5.11.6 Flash and EEPROM Command Register (FCMD)
Only six command codes are recognized in normal user modes, as shown in Table 4-15. All other
command codes are illegal and generate an access error. Refer to Section 4.5.3, “Program and Erase
Command Execution,” for a detailed discussion of Flash and EEPROM programming and erase
operations.
It is not necessary to perform a blank check command after a mass erase operation. Only blank check is
required as part of the security unlocking mechanism.
4
FACCERR Access Error Flag — FACCERR is set automatically when the proper command sequence is not obeyed exactly
(the erroneous command is ignored), if a program or erase operation is attempted before the FCDIV register has
been initialized, or if the MCU enters stop while a command was in progress. For a more detailed discussion of
the exact actions that are considered access errors, see Section 4.5.6, “Access Errors.” FACCERR is cleared by
writing a 1 to FACCERR. Writing a 0 to FACCERR has no meaning or effect.
0 No access error.
1 An access error has occurred.
2
FBLANK Verified as All Blank (erased) Flag — FBLANK is set automatically at the conclusionof a blank check command
if the entire Flash or EEPROM array was verified to be erased. FBLANK is cleared by clearing FCBEF to write a
new valid command. Writing to FBLANK has no meaning or effect.
0 After a blank check command is completed and FCCF = 1, FBLANK = 0 indicates the Flash or EEPROM array
is not completely erased.
1 After a blank check command is completed and FCCF = 1, FBLANK = 1 indicates the Flash or EEPROM array
is completely erased (all 0xFFFF).
76543210
R00000000
W FCMD
Reset 00000000
Figure 4-10. Flash and EEPROM Command Register (FCMD)
Table 4-15. Flash and EEPROM Commands
Command FCMD Equate File Label
Blank check 0x05 mBlank
Byte program 0x20 mByteProg
Burst program 0x25 mBurstProg
Sector erase 0x40 mSectorErase
Mass erase 0x41 mMassErase
Sector erase abort 0x47 mEraseAbort
Table 4-14. FSTAT Register Field Descriptions (continued)
Field Description
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 63
Chapter 5
Resets, Interrupts, and General System Control
5.1 Introduction
This section discusses basic reset and interrupt mechanisms and their various sources in the MC9S08DN60
Series. Some interrupt sources from peripheral modules are discussed in greater detail within other
sections of this data sheet. This section gathers basic information about all reset and interrupt sources in
one place for easy reference. A few reset and interrupt sources, including the computer operating properly
(COP) watchdog, are not part of on-chip peripheral systems with their own chapters.
5.2 Features
Reset and interrupt features include:
Multiple sources of reset for flexible system configuration and reliable operation
Reset status register (SRS) to indicate source of most recent reset
Separate interrupt vector for each module (reduces polling overhead); see Table 5-1
5.3 MCU Reset
Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset,
most control and status registers are forced to initial values and the program counter is loaded from the
reset vector (0xFFFE:0xFFFF). On-chip peripheral modules are disabled and I/O pins are initially
configured as general-purpose high-impedance inputs with pull-up devices disabled. The I bit in the
condition code register (CCR) is set to block maskable interrupts so the user program has a chance to
initialize the stack pointer (SP) and system control settings. (See the CPU chapter for information on the
Interrupt (I) bit.) SP is forced to 0x00FF at reset.
The MC9S08DN60 Series has eight sources for reset:
Power-on reset (POR)
External pin reset (PIN)
Computer operating properly (COP) timer
Illegal opcode detect (ILOP)
Illegal address detect (ILAD)
Low-voltage detect (LVD)
Loss of clock (LOC)
Background debug forced reset (BDFR)
Each of these sources, with the exception of the background debug forced reset, has an associated bit in
the system reset status register (SRS).
Chapter 5 Resets, Interrupts, and General System Control
MC9S08DN60 Series Data Sheet, Rev 3
64 Freescale Semiconductor
5.4 Computer Operating Properly (COP) Watchdog
The COP watchdog is intended to force a system reset when the application software fails to execute as
expected. To prevent a system reset from the COP timer (when it is enabled), application software must
reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter
before it times out, a system reset is generated to force the system back to a known starting point.
After any reset, the COP watchdog is enabled (see Section 5.8.4, “System Options Register 1 (SOPT1),”
for additional information). If the COP watchdog is not used in an application, it can be disabled by
clearing COPT bits in SOPT1.
The COP counter is reset by writing 0x55 and 0xAA (in this order) to the address of SRS during the
selected timeout period. Writes do not affect the data in the read-only SRS. As soon as the write sequence
is done, the COP timeout period is restarted. If the program fails to do this during the time-out period, the
MCU will reset. Also, if any value other than 0x55 or 0xAA is written to SRS, the MCU is immediately
reset.
The COPCLKS bit in SOPT2 (see Section 5.8.5, “System Options Register 2 (SOPT2),” for additional
information) selects the clock source used for the COP timer. The clock source options are either the bus
clock or an internal 1-kHz clock source. With each clock source, there are three associated time-outs
controlled by the COPT bits in SOPT1. Table 5-6 summaries the control functions of the COPCLKS and
COPT bits. The COP watchdog defaults to operation from the 1-kHz clock source and the longest time-out
(210 cycles).
When the bus clock source is selected, windowed COP operation is available by setting COPW in the
SOPT2 register. In this mode, writes to the SRS register to clear the COP timer must occur in the last 25%
of the selected timeout period. A premature write immediately resets the MCU. When the 1-kHz clock
source is selected, windowed COP operation is not available.
The COP counter is initialized by the first writes to the SOPT1 and SOPT2 registers and after any system
reset. Subsequent writes to SOPT1 and SOPT2 have no effect on COP operation. Even if the application
will use the reset default settings of COPT, COPCLKS, and COPW bits, the user should write to the
write-once SOPT1 and SOPT2 registers during reset initialization to lock in the settings. This will prevent
accidental changes if the application program gets lost.
The write to SRS that services (clears) the COP counter should not be placed in an interrupt service routine
(ISR) because the ISR could continue to be executed periodically even if the main application program
fails.
If the bus clock source is selected, the COP counter does not increment while the MCU is in background
debug mode or while the system is in stop mode. The COP counter resumes when the MCU exits
background debug mode or stop mode.
If the 1-kHz clock source is selected, the COP counter is re-initialized to zero upon entry to either
background debug mode or stop mode and begins from zero upon exit from background debug mode or
stop mode.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 65
5.5 Interrupts
Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine
(ISR), and then restore the CPU status so processing resumes where it left off before the interrupt. Other
than the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events
such as an edge on the IRQ pin or a timer-overflow event. The debug module can also generate an SWI
under certain circumstances.
If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. The
CPU will not respond unless the local interrupt enable is a 1 to enable the interrupt and the I bit in the CCR
is 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset which
prevents all maskable interrupt sources. The user program initializes the stack pointer and performs other
system setup before clearing the I bit to allow the CPU to respond to interrupts.
When the CPU receives a qualified interrupt request, it completes the current instruction before responding
to the interrupt. The interrupt sequence obeys the same cycle-by-cycle sequence as the SWI instruction and
consists of:
Saving the CPU registers on the stack
Setting the I bit in the CCR to mask further interrupts
Fetching the interrupt vector for the highest-priority interrupt that is currently pending
Filling the instruction queue with the first three bytes of program information starting from the
address fetched from the interrupt vector locations
While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of another
interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is restored to 0
when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit can be cleared
inside an ISR (after clearing the status flag that generated the interrupt) so that other interrupts can be
serviced without waiting for the first service routine to finish. This practice is not recommended for anyone
other than the most experienced programmers because it can lead to subtle program errors that are difficult
to debug.
The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR,
A, X, and PC registers to their pre-interrupt values by reading the previously saved information from the
stack.
NOTE
For compatibility with M68HC08 devices, the H register is not
automatically saved and restored. It is good programming practice to push
H onto the stack at the start of the interrupt service routine (ISR) and restore
it immediately before the RTI that is used to return from the ISR.
If more than one interrupt is pending when the I bit is cleared, the highest priority source is serviced first
(see Table 5-1).
Chapter 5 Resets, Interrupts, and General System Control
MC9S08DN60 Series Data Sheet, Rev 3
66 Freescale Semiconductor
5.5.1 Interrupt Stack Frame
Figure 5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer
(SP) points at the next available byte location on the stack. The current values of CPU registers are stored
on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR. After
stacking, the SP points at the next available location on the stack which is the address that is one less than
the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the
main program that would have executed next if the interrupt had not occurred.
Figure 5-1. Interrupt Stack Frame
When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part of
the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information,
starting from the PC address recovered from the stack.
The status flag corresponding to the interrupt source must be acknowledged (cleared) before returning
from the ISR. Typically, the flag is cleared at the beginning of the ISR so that if another interrupt is
generated by this same source, it will be registered so it can be serviced after completion of the current ISR.
5.5.2 External Interrupt Request (IRQ) Pin
External interrupts are managed by the IRQ status and control register, IRQSC. When the IRQ function is
enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in
stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ (if enabled)
can wake the MCU.
5.5.2.1 Pin Configuration Options
The IRQ pin enable (IRQPE) control bit in IRQSC must be 1 in order for the IRQ pin to act as the interrupt
request (IRQ) input. As an IRQ input, the user can choose the polarity of edges or levels detected
(IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD), and whether an event
causes an interrupt or only sets the IRQF flag which can be polled by software.
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER (LOW BYTE X)
PROGRAM COUNTER HIGH
* High byte (H) of index register is not automatically stacked.
*
PROGRAM COUNTER LOW
70
UNSTACKING
ORDER
STACKING
ORDER
5
4
3
2
1
1
2
3
4
5
TOWARD LOWER ADDRESSES
TOWARD HIGHER ADDRESSES
SP BEFORE
SP AFTER
INTERRUPT STACKING
THE INTERRUPT
Chapter 5 Resets, Interrupts, and General System Control
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 67
The IRQ pin, when enabled, defaults to use an internal pull device (IRQPDD = 0), the device is a pull-up
or pull-down depending on the polarity chosen. If the user desires to use an external pull-up or pull-down,
the IRQPDD can be written to a 1 to turn off the internal device.
BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is configured to act
as the IRQ input.
5.5.2.2 Edge and Level Sensitivity
The IRQMOD control bit reconfigures the detection logic so it detects edge events and pin levels. In the
edge and level detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ
pin changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be
cleared) as long as the IRQ pin remains at the asserted level.
5.5.3 Interrupt Vectors, Sources, and Local Masks
Table 5-1 provides a summary of all interrupt sources. Higher-priority sources are located toward the
bottom of the table. The high-order byte of the address for the interrupt service routine is located at the
first address in the vector address column, and the low-order byte of the address for the interrupt service
routine is located at the next higher address.
When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt
enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in
the CCR) is 0, the CPU will finish the current instruction; stack the PCL, PCH, X, A, and CCR CPU
registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt.
Processing then continues in the interrupt service routine.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08DN60 Series Data Sheet, Rev 3
68 Freescale Semiconductor
5.6 Low-Voltage Detect (LVD) System
The MC9S08DN60 Series includes a system to protect against low-voltage conditions in order to protect
memory contents and control MCU system states during supply voltage variations. The system is
Table 5-1. Vector Summary1
1Vector priority is shown from lowest (first row) to highest (last row). For example, Vreset is the highest priority vector.
Vector
No. Address
(High/Low) Vector
Name Module Source Enable Description
31 0xFFC0/0xFFC1 Vacmp2 ACMP2 ACF ACIE Analog comparator 2
30 0xFFC2/0xFFC3 Vacmp1 ACMP1 ACF ACIE Analog comparator 1
29–26 0xFFC4/0xFFC5–
0xFFCA/0xFFCB (Reserved)
25 0xFFCC/0xFFCD Vrtc RTC RTIF RTIE Real-time interrupt
24 0xFFCE/0xFFCF Viic IIC IICIS IICIE IIC control
23 0xFFD0/0xFFD1 Vadc ADC COCO AIEN ADC
22 0xFFD2/0xFFD3 Vport Port A,B,D PTAIF, PTBIF,
PTDIF PTAIE, PTBIE, PTDIE Port Pins
21–19 0xFFD4/0xFFD5–
0xFFD8/0xFFD9 (Reserved)
18 0xFFDA/0xFFDB Vsci1tx SCI1 TDRE, TC TIE, TCIE SCI1 transmit
17 0xFFDC/0xFFDD Vsci1rx SCI1 IDLE, LBKDIF,
RDRF, RXEDGIF ILIE, LBKDIE, RIE,
RXEDGIE SCI1 receive
16 0xFFDE/0xFFDF Vsci1err SCI1 OR, NF,
FE, PF ORIE, NFIE,
FEIE, PFIE SCI1 error
15 0xFFE0/0xFFE1 Vspi SPI SPIF, MODF,
SPTEF SPIE, SPIE, SPTIE SPI
14 0xFFE2/0xFFE3 Vtpm2ovf TPM2 TOF TOIE TPM2 overflow
13 0xFFE4/0xFFE5 Vtpm2ch1 TPM2 CH1F CH1IE TPM2 channel 1
12 0xFFE6/0xFFE7 Vtpm2ch0 TPM2 CH0F CH0IE TPM2 channel 0
11 0xFFE8/0xFFE9 Vtpm1ovf TPM1 TOF TOIE TPM1 overflow
10 0xFFEA/0xFFEB Vtpm1ch5 TPM1 CH5F CH5IE TPM1 channel 5
9 0xFFEC/0xFFED Vtpm1ch4 TPM1 CH4F CH4IE TPM1 channel 4
8 0xFFEE/0xFFEF Vtpm1ch3 TPM1 CH3F CH3IE TPM1 channel 3
7 0xFFF0/0xFFF1 Vtpm1ch2 TPM1 CH2F CH2IE TPM1 channel 2
6 0xFFF2/0xFFF3 Vtpm1ch1 TPM1 CH1F CH1IE TPM1 channel 1
5 0xFFF4/0xFFF5 Vtpm1ch0 TPM1 CH0F CH0IE TPM1 channel 0
4 0xFFF6/0xFFF7 Vlol MCG LOLS LOLIE MCG loss of lock
3 0xFFF8/0xFFF9 Vlvd System
control LVWF LVWIE Low-voltage warning
2 0xFFFA/0xFFFB Virq IRQ IRQF IRQIE IRQ pin
1 0xFFFC/0xFFFD Vswi Core SWI Instruction Software interrupt
0 0xFFFE/0xFFFF Vreset System
control COP,
LOC,
LVD,
RESET,
ILOP,
ILAD,
POR,
BDFR
COPE
CME
LVDRE
Watchdog timer
Loss-of-clock
Low-voltage detect
External pin
Illegal opcode
Illegal address
Power-on-reset
BDM-forced reset
Chapter 5 Resets, Interrupts, and General System Control
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 69
comprised of a power-on reset (POR) circuit and a LVD circuit with trip voltages for warning and
detection. The LVD circuit is enabled when LVDE in SPMSC1 is set to 1. The LVD is disabled upon
entering any of the stop modes unless LVDSE is set in SPMSC1. If LVDSE and LVDE are both set, then
the MCU cannot enter stop2 (it will enter stop3 instead), and the current consumption in stop3 with the
LVD enabled will be higher.
5.6.1 Power-On Reset Operation
When power is initially applied to the MCU, or when the supply voltage drops below the power-on reset
rearm voltage level, VPOR, the POR circuit will cause a reset condition. As the supply voltage rises, the
LVD circuit will hold the MCU in reset until the supply has risen above the low-voltage detection low
threshold, VLVDL. Both the POR bit and the LVD bit in SRS are set following a POR.
5.6.2 Low-Voltage Detection (LVD) Reset Operation
The LVD can be configured to generate a reset upon detection of a low-voltage condition by setting
LVDRE to 1. The low-voltage detection threshold is determined by the LVDV bit. After an LVD reset has
occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the
low-voltage detection threshold. The LVD bit in the SRS register is set following either an LVD reset or
POR.
5.6.3 Low-Voltage Warning (LVW) Interrupt Operation
The LVD system has a low-voltage warning flag to indicate to the user that the supply voltage is
approaching the low-voltage condition. When a low-voltage warning condition is detected and is
configured for interrupt operation (LVWIE set to 1), LVWF in SPMSC1 will be set and an LVW interrupt
request will occur.
5.7 MCLK Output
The PTA0 pin is shared with the MCLK clock output. If the MCSEL bits are all zeroes, the MCLK clock
is disabled. Setting any of the MCSEL bits causes the PTA0 pin to output a divided version of the internal
MCU bus clock regardless of the state of the port data direction control bit for the pin. The divide ratio is
determined by the MCSEL bits. The slew rate and drive strength for the pin are controlled by PTASE0 and
PTADS0, respectively. The maximum clock output frequency is limited if slew rate control is enabled, see
the electrical specifications for the maximum frequency under different conditions.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08DN60 Series Data Sheet, Rev 3
70 Freescale Semiconductor
5.8 Reset, Interrupt, and System Control Registers and Control Bits
One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space
are related to reset and interrupt systems.
Refer to Table 4-2 and Table 4-3 in Chapter 4, “Memory,” of this data sheet for the absolute address
assignments for all registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief
descriptions of these bits are provided here, the related functions are discussed in greater detail in
Chapter 3, “Modes of Operation.”
Chapter 5 Resets, Interrupts, and General System Control
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 71
5.8.1 Interrupt Pin Request Status and Control Register (IRQSC)
This direct page register includes status and control bits which are used to configure the IRQ function,
report status, and acknowledge IRQ events.
76543210
R0 IRQPDD IRQEDG IRQPE IRQF 0 IRQIE IRQMOD
W IRQACK
Reset 00000000
= Unimplemented or Reserved
Figure 5-2. Interrupt Request Status and Control Register (IRQSC)
Table 5-2. IRQSC Register Field Descriptions
Field Description
6
IRQPDD Interrupt Request (IRQ) Pull Device Disable— This read/write control bit is used to disable the internal
pull-up/pull-down device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used.
0 IRQ pull device enabled if IRQPE = 1.
1 IRQ pull device disabled if IRQPE = 1.
5
IRQEDG Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or
levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is
sensitive to both edges and levels or only edges. When the IRQ pin is enabled as the IRQ input and is configured
to detect rising edges, it has a pull-down. When the IRQ pin is enabled as the IRQ input and is configured to
detect falling edges, it has a pull-up.
0 IRQ is falling edge or falling edge/low-level sensitive.
1 IRQ is rising edge or rising edge/high-level sensitive.
4
IRQPE IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set the IRQ pin can
be used as an interrupt request.
0 IRQ pin function is disabled.
1 IRQ pin function is enabled.
3
IRQF IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred.
0 No IRQ request.
1 IRQ event detected.
2
IRQACK IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).
Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1),
IRQF cannot be cleared while the IRQ pin remains at its asserted level.
1
IRQIE IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate an interrupt
request.
0 Interrupt request when IRQF set is disabled (use polling).
1 Interrupt requested whenever IRQF = 1.
0
IRQMOD IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level
detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt
request events. See Section 5.5.2.2, “Edge and Level Sensitivity” for more details.
0 IRQ event on falling edges or rising edges only.
1 IRQ event on falling edges and low levels or on rising edges and high levels.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08DN60 Series Data Sheet, Rev 3
72 Freescale Semiconductor
5.8.2 System Reset Status Register (SRS)
This high page register includes read-only status flags to indicate the source of the most recent reset. When
a debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will
be set. Writing any value to this register address causes a COP reset when the COP is enabled except the
values 0x55 and 0xAA. Writing a 0x55-0xAA sequence to this address clears the COP watchdog timer
without affecting the contents of this register. The reset state of these bits depends on what caused the
MCU to reset.
Figure 5-3. System Reset Status (SRS)
76543210
R POR PIN COP ILOP ILAD LOC LVD 0
W Writing 0x55, 0xAA to SRS address clears COP watchdog timer.
POR: 10000010
LVD: u0000010
Any other
reset: 0 Note(1)
1Any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set; bits
corresponding to sources that are not active at the time of reset entry will be cleared.
Note(1) Note(1) Note(1) 000
Table 5-3. SRS Register Field Descriptions
Field Description
7
POR Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVD threshold.
0 Reset not caused by POR.
1 POR caused reset.
6
PIN External Reset Pin — Reset was caused by an active-low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
5
COP Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source can be blocked by COPE = 0.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
4
ILOP Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
3
ILAD Illegal Address — Reset was caused by an attempt to access either data or an instruction at an unimplemented
memory address.
0 Reset not caused by an illegal address.
1 Reset caused by an illegal address.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 73
5.8.3 System Background Debug Force Reset Register (SBDFR)
This high page register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
2
LOC Loss of Clock — Reset was caused by a loss of external clock.
0 Reset not caused by loss of external clock
1 Reset caused by loss of external clock
1
LVD Low-Voltage Detect — If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset will
occur. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
76543210
R00000000
W BDFR1
1BDFR is writable only through serial background debug commands, not from user programs.
Reset: 00000000
= Unimplemented or Reserved
Table 5-4. SBDFR Register Field Descriptions
Field Description
0
BDFR Background Debug Force Reset — A serial background command such as WRITE_BYTE can be used to allow
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program.
Table 5-3. SRS Register Field Descriptions
Field Description
Chapter 5 Resets, Interrupts, and General System Control
MC9S08DN60 Series Data Sheet, Rev 3
74 Freescale Semiconductor
5.8.4 System Options Register 1 (SOPT1)
This high page register is a write-once register so only the first write after reset is honored. It can be read
at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to
avoid accidental changes to these sensitive settings. This register should be written during the user’s reset
initialization program to set the desired controls even if the desired settings are the same as the reset
settings.
76543210
RCOPT STOPE Reserved IICPS 000
W
Reset: 11000000
= Unimplemented or Reserved
Figure 5-5. System Options Register 1 (SOPT1)
Table 5-5. SOPT1 Register Field Descriptions
Field Description
7:6
COPT[1:0] COP Watchdog Timeout — These write-once bits select the timeout period of the COP. COPT along with
COPCLKS in SOPT2 defines the COP timeout period. See Table 5-6.
5
STOPE Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user
program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
3
IICPS IIC Pin Select— This write-once bit selects the location of the SCL and SDA pins of the IIC module.
0 SCL on PTF2, SDA on PTF3.
1 SCL on PTE4, SDA on PTE5.
Table 5-6. COP Configuration Options
Control Bits Clock Source COP Window1 Opens
(COPW = 1)
1Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This column
displays the minimum number of clock counts required before the COP timer can be reset when in windowed COP mode
(COPW = 1).
COP Overflow Count
COPCLKS COPT[1:0]
N/A 0:0 N/A N/A COP is disabled
0 0:1 1 kHz N/A 25cycles (32 ms2)
2Values shown in milliseconds based on tLPO = 1 ms. See tLPO in the appendix Section A.12.1, “Control Timing,” for the
tolerance of this value.
0 1:0 1 kHz N/A 28 cycles (256 ms1)
0 1:1 1 kHz N/A 210 cycles (1.024 s1)
1 0:1 Bus 6144 cycles 213 cycles
1 1:0 Bus 49,152 cycles 216 cycles
1 1:1 Bus 196,608 cycles 218 cycles
Chapter 5 Resets, Interrupts, and General System Control
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 75
5.8.5 System Options Register 2 (SOPT2)
This high page register contains bits to configure MCU specific features on the MC9S08DN60 Series
devices.
76543210
RCOPCLKS1
1This bit can be written only one time after reset. Additional writes are ignored.
COPW10ADHTS 0MCSEL
W
Reset: 00000000
= Unimplemented or Reserved
Figure 5-6. System Options Register 2 (SOPT2)
Table 5-7. SOPT2 Register Field Descriptions
Field Description
7
COPCLKS COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog. See
Table 5-6 for details.
0 Internal 1-kHz clock is source to COP.
1 Bus clock is source to COP.
6
COPW COP Window — This write-once bit selects the COP operation mode. When set, the 0x55-0xAA write sequence
to the SRS register must occur in the last 25% of the selected period. Any write to the SRS register during the
first 75% of the selected period will reset the MCU.
0 Normal COP operation.
1 Window COP operation.
4
ADHTS ADC Hardware Trigger Select — This bit selects which hardware trigger initiates conversion for the analog to
digital converter when the ADC hardware trigger is enabled (ADCTRG is set in ADCSC2 register).
0 Real Time Counter (RTC) overflow.
1 External Interrupt Request (IRQ) pin.
2:0
MCSEL MCLK Divide Select— These bits enable the MCLK output on PTA0 pin and select the divide ratio for the MCLK
output according to the formula below when the MCSEL bits are not equal to all zeroes. In case that the MCSEL
bits are all zeroes, the MCLK output is disabled.
MCLK frequency = Bus Clock frequency ÷ (2 * MCSEL)
Chapter 5 Resets, Interrupts, and General System Control
MC9S08DN60 Series Data Sheet, Rev 3
76 Freescale Semiconductor
5.8.6 System Device Identification Register (SDIDH, SDIDL)
These high page read-only registers are included so host development systems can identify the HCS08
derivative and revision number. This allows the development software to recognize where specific memory
blocks, registers, and control bits are located in a target MCU.
Figure 5-7. System Device Identification Register — High (SDIDH)
76543210
R Reserved ID11 ID10 ID9 ID8
W
Reset: 01
1The revision number that is hard coded into these bits reflects the current silicon revision level.
0101010000
= Unimplemented or Reserved
Table 5-8. SDIDH Register Field Descriptions
Field Description
3:0
ID[11:8] Part Identification Number — MC9S08DN60 Series MCUs are hard-coded to the value 0x00E. See also ID bits
in Table 5-9.
76543210
R ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
W
Reset: 00001110
= Unimplemented or Reserved
Figure 5-8. System Device Identification Register — Low (SDIDL)
Table 5-9. SDIDL Register Field Descriptions
Field Description
7:0
ID[7:0] Part Identification Number — MC9S08DN60 Series MCUs are hard-coded to the value 0x00E. See also ID bits
in Table 5-8.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 77
5.8.7 System Power Management Status and Control 1 Register
(SPMSC1)
This high page register contains status and control bits to support the low-voltage detect function, and to
enable the bandgap voltage reference for use by the ADC and ACMP modules. This register should be
written during the user’s reset initialization program to set the desired controls even if the desired settings
are the same as the reset settings.
Figure 5-9. System Power Management Status and Control 1 Register (SPMSC1)
76543210
R LVWF1
1LVWF will be set in the case when VSupply transitions below the trip point or after reset and VSupply is already below VLVW.
0LVWIE LVDRE2
2This bit can be written only one time after reset. Additional writes are ignored.
LVDSE LVDE20BGBE
WLVWACK
Reset: 00011100
= Unimplemented or Reserved
Table 5-10. SPMSC1 Register Field Descriptions
Field Description
7
LVWF Low-Voltage Warning Flag — The LVWF bit indicates the low-voltage warning status.
0 low-voltage warning is not present.
1 low-voltage warning is present or was present.
6
LVWACK Low-Voltage Warning Acknowledge — If LVWF = 1, a low-voltage condition has occurred. To acknowledge this
low-voltage warning, write 1 to LVWACK, which will automatically clear LVWF to 0 if the low-voltage warning is
no longer present.
5
LVWIE Low-Voltage Warning Interrupt Enable — This bit enables hardware interrupt requests for LVWF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVWF = 1.
4
LVDRE Low-Voltage Detect Reset Enable — This write-once bit enables LVD events to generate a hardware reset
(provided LVDE = 1).
0 LVD events do not generate hardware resets.
1 Force an MCU reset when an enabled low-voltage detect event occurs.
3
LVDSE Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage
detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.
2
LVDE Low-Voltage Detect Enable — This write-once bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
0
BGBE Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the
ADC and ACMP modules on one of its internal channels.
0 Bandgap buffer disabled.
1 Bandgap buffer enabled.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08DN60 Series Data Sheet, Rev 3
78 Freescale Semiconductor
5.8.8 System Power Management Status and Control 2 Register
(SPMSC2)
This register is used to report the status of the low-voltage warning function, and to configure the stop
mode behavior of the MCU. This register should be written during the user’s reset initialization program
to set the desired controls even if the desired settings are the same as the reset settings.
Figure 5-10. System Power Management Status and Control 2 Register (SPMSC2)
76543210
R0 0 LVDV1
1This bit can be written only one time after power-on reset. Additional writes are ignored.
LVWV PPDF 0 0 PPDC2
2This bit can be written only one time after reset. Additional writes are ignored.
WPPDACK
Power-on Reset: 0 0 0 0 0 0 0 0
LVD Reset: 0 0 u u 0 0 0 0
Any other Reset: 0 0 u u 0 0 0 0
= Unimplemented or Reserved u = Unaffected by reset
Table 5-11. SPMSC2 Register Field Descriptions
Field Description
5
LVDV Low-Voltage Detect Voltage Select — This write-once bit selects the low-voltage detect (LVD) trip point setting.
It also selects the warning voltage range. See Table 5-12.
4
LVWV Low-Voltage Warning Voltage Select — This bit selects the low-voltage warning (LVW) trip point voltage. See
Table 5-12.
3
PPDF Partial Power Down Flag — This read-only status bit indicates that the MCU has recovered from stop2 mode.
0 MCU has not recovered from stop2 mode.
1 MCU recovered from stop2 mode.
2
PPDACK Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit.
0
PPDC Partial Power Down Control — This write-once bit controls whether stop2 or stop3 mode is selected.
0 Stop3 mode enabled.
1 Stop2, partial power down, mode enabled.
Table 5-12. LVD and LVW Trip Point Typical Values1
1See Electrical Characteristics appendix for minimum and maximum values.
LVDV:LVWV LVW Trip Point LVD Trip Point
0:0 VLVW0 = 2.74 V VLVD0 = 2.56 V
0:1 VLVW1 = 2.92 V
1:0 VLVW2 = 4.3 V VLVD1 = 4.0 V
1:1 VLVW3 = 4.6 V
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 79
Chapter 6
Parallel Input/Output Control
This section explains software controls related to parallel input/output (I/O) and pin control. The
MC9S08DN60 Series has seven parallel I/O ports which include a total of up to 53 I/O pins and one
input-only pin. See Chapter 2, “Pins and Connections,” for more information about pin assignments and
external hardware considerations of these pins.
Many of these pins are shared with on-chip peripherals such as timer systems, communication systems, or
pin interrupts as shown in Table 2-1. The peripheral modules have priority over the general-purpose I/O
functions so that when a peripheral is enabled, the I/O functions associated with the shared pins are
disabled.
After reset, the shared peripheral functions are disabled and the pins are configured as inputs
(PTxDDn = 0). The pin control functions for each pin are configured as follows: slew rate control enabled
(PTxSEn = 1), low drive strength selected (PTxDSn = 0), and internal pull-ups disabled (PTxPEn = 0).
NOTE
Not all general-purpose I/O pins are available on all packages. To avoid
extra current drain from floating input pins, the user’s reset initialization
routine in the application program must either enable on-chip pull-up
devices or change the direction of unconnected pins to outputs so the
pins do not float.
The PTE1 pin does not contain a clamp diode to VDD and should not be
driven above VDD. The voltage measured on the internally pulled up
PTE1 pin may be as low as VDD – 0.7 V. The internal gates connected
to this pin are pulled all the way to VDD.
6.1 Port Data and Data Direction
Reading and writing of parallel I/Os are performed through the port data registers. The direction, either
input or output, is controlled through the port data direction registers. The parallel I/O port function for an
individual pin is illustrated in the block diagram shown in Figure 6-1.
The data direction control bit (PTxDDn) determines whether the output buffer for the associated pin is
enabled, and also controls the source for port data register reads. The input buffer for the associated pin is
always enabled unless the pin is enabled as an analog function or is an output-only pin.
When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function.
However, the data direction register bit will continue to control the source for reads of the port data register.
When a shared analog function is enabled for a pin, both the input and output buffers are disabled. A value
of 0 is read for any port data bit where the bit is an input (PTxDDn = 0) and the input buffer is disabled.
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
80 Freescale Semiconductor
In general, whenever a pin is shared with both an alternate digital function and an analog function, the
analog function has priority such that if both the digital and analog functions are enabled, the analog
function controls the pin.
It is a good programming practice to write to the port data register before changing the direction of a port
pin to become an output. This ensures that the pin will not be driven momentarily with an old data value
that happened to be in the port data register.
Figure 6-1. Parallel I/O Block Diagram
6.2 Pull-up, Slew Rate, and Drive Strength
Associated with the parallel I/O ports is a set of registers located in the high page register space that operate
independently of the parallel I/O registers. These registers are used to control pull-ups, slew rate, and drive
strength for the pins.
An internal pull-up device can be enabled for each port pin by setting the corresponding bit in the pull-up
enable register (PTxPEn). The pull-up device is disabled if the pin is configured as an output by the parallel
I/O control logic or any shared peripheral function regardless of the state of the corresponding pull-up
enable register bit. The pull-up device is also disabled if the pin is controlled by an analog function.
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PTxSEn). When enabled, slew control limits the rate at which an output can transition in order to
reduce EMC emissions. Slew rate control has no effect on pins that are configured as inputs.
NOTE
Slew rate reset default values may differ between engineering samples and
final production parts. Always initialize slew rate control to the desired
value to ensure correct operation.
QD
QD
1
0
Port Read
PTxDDn
PTxDn
Output Enable
Output Data
Input Dat
a
Synchronizer
Data
BUSCLK
QFQF W E
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 81
An output pin can be selected to have high output drive strength by setting the corresponding bit in the
drive strength select register (PTxDSn). When high drive is selected, a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that
the total current source and sink limits for the MCU are not exceeded. Drive strength selection is intended
to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin
to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.
Because of this, the EMC emissions may be affected by enabling pins as high drive.
6.3 Pin Interrupts
Port A, port B, and port D pins can be configured as external interrupt inputs and as an external means of
waking the MCU from stop or wait low-power modes.
The block diagram for each port interrupt logic is shown Figure 6-2.
Figure 6-2. Port Interrupt Block Diagram
Writing to the PTxPSn bits in the port interrupt pin select register (PTxPS) independently enables or
disables each port pin. Each port can be configured as edge sensitive or edge and level sensitive based on
the PTxMOD bit in the port interrupt status and control register (PTxSC). Edge sensitivity can be software
programmed to be either falling or rising; the level can be either low or high. The polarity of the edge or
edge and level sensitivity is selected using the PTxESn bits in the port interrupt edge select register
(PTxES).
Synchronous logic is used to detect edges. Prior to detecting an edge, enabled port inputs must be at the
deasserted logic level. A falling edge is detected when an enabled port input signal is seen as a logic 1 (the
deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising
edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during
the next cycle.
6.3.1 Edge Only Sensitivity
A valid edge on an enabled port pin will set PTxIF in PTxSC. If PTxIE in PTxSC is set, an interrupt request
will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to PTxACK in PTxSC.
PTxESn
DQ
CK
CLR
VDD
PTxMOD
PTxIE
PORT
INTERRUPT FF
PTxACK
RESET
SYNCHRONIZER
PTxIF
STOP BYPASS
STOP
BUSCLK
PTxPSn
0
1
S
PTxPS0
0
1
S
PTxES0
PTxn
PTxn
PTx
INTERRUPT
REQUEST
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
82 Freescale Semiconductor
6.3.2 Edge and Level Sensitivity
A valid edge or level on an enabled port pin will set PTxIF in PTxSC. If PTxIE in PTxSC is set, an interrupt
request will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to PTxACK in
PTxSC provided all enabled port inputs are at their deasserted levels. PTxIF will remain set if any enabled
port pin is asserted while attempting to clear by writing a 1 to PTxACK.
6.3.3 Pull-up/Pull-down Resistors
The port interrupt pins can be configured to use an internal pull-up/pull-down resistor using the associated
I/O port pull-up enable register. If an internal resistor is enabled, the PTxES register is used to select
whether the resistor is a pull-up (PTxESn = 0) or a pull-down (PTxESn = 1).
6.3.4 Pin Interrupt Initialization
When an interrupt pin is first enabled, it is possible to get a false interrupt flag. To prevent a false interrupt
request during pin interrupt initialization, the user should do the following:
1. Mask interrupts by clearing PTxIE in PTxSC.
2. Select the pin polarity by setting the appropriate PTxESn bits in PTxES.
3. If using internal pull-up/pull-down device, configure the associated pull enable bits in PTxPE.
4. Enable the interrupt pins by setting the appropriate PTxPSn bits in PTxPS.
5. Write to PTxACK in PTxSC to clear any false interrupts.
6. Set PTxIE in PTxSC to enable interrupts.
6.4 Pin Behavior in Stop Modes
Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An
explanation of pin behavior for the various stop modes follows:
Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their state as
before the STOP instruction was executed. CPU register status and the state of I/O registers should
be saved in RAM before the STOP instruction is executed to place the MCU in stop2 mode. Upon
recovery from stop2 mode, before accessing anyI/O, the user should examine the state of the PPDF
bit in the SPMSC2 register. If the PPDF bit is 0, I/O must be initialized as if a power on reset had
occurred. If the PPDF bit is 1, peripherals may require initialization to be restored to their pre-stop
condition. This can be done using data previously stored in RAM if it was saved before the STOP
instruction was executed. The user must then write a 1 to the PPDACK bit in the SPMSC2 register.
Access to I/O is now permitted again in the user application program.
In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon
recovery, normal I/O function is available to the user.
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 83
6.5 Parallel I/O and Pin Control Registers
This section provides information about the registers associated with the parallel I/O ports. The data and
data direction registers are located in page zero of the memory map. The pull up, slew rate, drive strength,
and interrupt control registers are located in the high page section of the memory map.
Refer to tables in Chapter 4, “Memory,” for the absolute address assignments for all parallel I/O and their
pin control registers. This section refers to registers and control bits only by their names. A Freescale
Semiconductor-provided equate or header file normally is used to translate these names into the
appropriate absolute addresses.
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
84 Freescale Semiconductor
6.5.1 Port A Registers
Port A is controlled by the registers listed below.
6.5.1.1 Port A Data Register (PTAD)
6.5.1.2 Port A Data Direction Register (PTADD)
76543210
RPTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
W
Reset: 00000000
Figure 6-3. Port A Data Register (PTAD)
Table 6-1. PTAD Register Field Descriptions
Field Description
7:0
PTAD[7:0] Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups/pull-downs disabled.
76543210
RPTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0
W
Reset: 00000000
Figure 6-4. Port A Data Direction Register (PTADD)
Table 6-2. PTADD Register Field Descriptions
Field Description
7:0
PTADD[7:0] Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 85
6.5.1.3 Port A Pull Enable Register (PTAPE)
NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.
6.5.1.4 Port A Slew Rate Enable Register (PTASE)
Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
rate control to the desired value to ensure correct operation.
76543210
RPTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0
W
Reset: 00000000
Figure 6-5. Internal Pull Enable for Port A Register (PTAPE)
Table 6-3. PTAPE Register Field Descriptions
Field Description
7:0
PTAPE[7:0] Internal Pull Enable for Port A Bits — Each of these control bits determines if the internal pull-up or pull-down
device is enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port A bit n.
1 Internal pull-up/pull-down device enabled for port A bit n.
76543210
RPTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0
W
Reset: 00000000
Figure 6-6. Slew Rate Enable for Port A Register (PTASE)
Table 6-4. PTASE Register Field Descriptions
Field Description
7:0
PTASE[7:0] Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
86 Freescale Semiconductor
6.5.1.5 Port A Drive Strength Selection Register (PTADS)
6.5.1.6 Port A Interrupt Status and Control Register (PTASC)
76543210
RPTADS7 PTADS6 PTADS5 PTADS4 PTADS3 PTADS2 PTADS1 PTADS0
W
Reset: 00000000
Figure 6-7. Drive Strength Selection for Port A Register (PTADS)
Table 6-5. PTADS Register Field Descriptions
Field Description
7:0
PTADS[7:0] Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high
output drive for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port A bit n.
1 High output drive strength selected for port A bit n.
76543210
R0000PTAIF0
PTAIE PTAMOD
W PTAACK
Reset: 00000000
= Unimplemented or Reserved
Figure 6-8. Port A Interrupt Status and Control Register (PTASC)
Table 6-6. PTASC Register Field Descriptions
Field Description
3
PTAIF Port A Interrupt Flag — PTAIF indicates when a port A interrupt is detected. Writes have no effect on PTAIF.
0 No port A interrupt detected.
1 Port A interrupt detected.
2
PTAACK Port A Interrupt Acknowledge — Writing a 1 to PTAACK is part of the flag clearing mechanism. PTAACK
always reads as 0.
1
PTAIE Port A Interrupt Enable — PTAIE determines whether a port A interrupt is requested.
0 Port A interrupt request not enabled.
1 Port A interrupt request enabled.
0
PTAMOD Port A Detection Mode — PTAMOD (along with the PTAES bits) controls the detection mode of the port A
interrupt pins.
0 Port A pins detect edges only.
1 Port A pins detect both edges and levels.
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 87
6.5.1.7 Port A Interrupt Pin Select Register (PTAPS)
6.5.1.8 Port A Interrupt Edge Select Register (PTAES)
76543210
RPTAPS7 PTAPS6 PTAPS5 PTAPS4 PTAPS3 PTAPS2 PTAPS1 PTAPS0
W
Reset: 00000000
Figure 6-9. Port A Interrupt Pin Select Register (PTAPS)
Table 6-7. PTAPS Register Field Descriptions
Field Description
7:0
PTAPS[7:0] Port A Interrupt Pin Selects — Each of the PTAPSn bits enable the corresponding port A interrupt pin.
0 Pin not enabled as interrupt.
1 Pin enabled as interrupt.
76543210
RPTAES7 PTAES6 PTAES5 PTAES4 PTAES3 PTAES2 PTAES1 PTAES0
W
Reset: 00000000
Figure 6-10. Port A Edge Select Register (PTAES)
Table 6-8. PTAES Register Field Descriptions
Field Description
7:0
PTAES[7:0] Port A Edge Selects — Each of the PTAESn bits serves a dual purpose by selecting the polarity of the active
interrupt edge as well as selecting a pull-up or pull-down device if enabled.
0 A pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation.
1 A pull-down device is connected to the associated pin and detects rising edge/high level for interrupt
generation.
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
88 Freescale Semiconductor
6.5.2 Port B Registers
Port B is controlled by the registers listed below.
6.5.2.1 Port B Data Register (PTBD)
6.5.2.2 Port B Data Direction Register (PTBDD)
76543210
RPTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0
W
Reset: 00000000
Figure 6-11. Port B Data Register (PTBD)
Table 6-9. PTBD Register Field Descriptions
Field Description
7:0
PTBD[7:0] Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups/pull-downs disabled.
76543210
RPTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0
W
Reset: 00000000
Figure 6-12. Port B Data Direction Register (PTBDD)
Table 6-10. PTBDD Register Field Descriptions
Field Description
7:0
PTBDD[7:0] Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for
PTBD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn.
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 89
6.5.2.3 Port B Pull Enable Register (PTBPE)
NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.
6.5.2.4 Port B Slew Rate Enable Register (PTBSE)
Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
rate control to the desired value to ensure correct operation.
76543210
RPTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0
W
Reset: 00000000
Figure 6-13. Internal Pull Enable for Port B Register (PTBPE)
Table 6-11. PTBPE Register Field Descriptions
Field Description
7:0
PTBPE[7:0] Internal Pull Enable for Port B Bits — Each of these control bits determines if the internal pull-up or pull-down
device is enabled for the associated PTB pin. For port B pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port B bit n.
1 Internal pull-up/pull-down device enabled for port B bit n.
76543210
RPTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0
W
Reset: 00000000
Figure 6-14. Slew Rate Enable for Port B Register (PTBSE)
Table 6-12. PTBSE Register Field Descriptions
Field Description
7:0
PTBSE[7:0] Output Slew Rate Enable for Port B Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port B bit n.
1 Output slew rate control enabled for port B bit n.
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
90 Freescale Semiconductor
6.5.2.5 Port B Drive Strength Selection Register (PTBDS)
6.5.2.6 Port B Interrupt Status and Control Register (PTBSC)
76543210
RPTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0
W
Reset: 00000000
Figure 6-15. Drive Strength Selection for Port B Register (PTBDS)
Table 6-13. PTBDS Register Field Descriptions
Field Description
7:0
PTBDS[7:0] Output Drive Strength Selection for Port B Bits — Each of these control bits selects between low and high
output drive for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port B bit n.
1 High output drive strength selected for port B bit n.
76543210
R0000PTBIF 0 PTBIE PTBMOD
W PTBACK
Reset: 00000000
= Unimplemented or Reserved
Figure 6-16. Port B Interrupt Status and Control Register (PTBSC)
Table 6-14. PTBSC Register Field Descriptions
Field Description
3
PTBIF Port B Interrupt Flag — PTBIF indicates when a Port B interrupt is detected. Writes have no effect on PTBIF.
0 No Port B interrupt detected.
1 Port B interrupt detected.
2
PTBACK Port B Interrupt Acknowledge — Writing a 1 to PTBACK is part of the flag clearing mechanism. PTBACK
always reads as 0.
1
PTBIE Port B Interrupt Enable — PTBIE determines whether a port B interrupt is requested.
0 Port B interrupt request not enabled.
1 Port B interrupt request enabled.
0
PTBMOD Port B Detection Mode — PTBMOD (along with the PTBES bits) controls the detection mode of the port B
interrupt pins.
0 Port B pins detect edges only.
1 Port B pins detect both edges and levels.
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 91
6.5.2.7 Port B Interrupt Pin Select Register (PTBPS)
6.5.2.8 Port B Interrupt Edge Select Register (PTBES)
76543210
RPTBPS7 PTBPS6 PTBPS5 PTBPS4 PTBPS3 PTBPS2 PTBPS1 PTBPS0
W
Reset: 00000000
Figure 6-17. Port B Interrupt Pin Select Register (PTBPS)
Table 6-15. PTBPS Register Field Descriptions
Field Description
7:0
PTBPS[7:0] Port B Interrupt Pin Selects — Each of the PTBPSn bits enable the corresponding port B interrupt pin.
0 Pin not enabled as interrupt.
1 Pin enabled as interrupt.
76543210
RPTBES7 PTBES6 PTBES5 PTBES4 PTBES3 PTBES2 PTBES1 PTBES0
W
Reset: 00000000
Figure 6-18. Port B Edge Select Register (PTBES)
Table 6-16. PTBES Register Field Descriptions
Field Description
7:0
PTBES[7:0] Port B Edge Selects — Each of the PTBESn bits serves a dual purpose by selecting the polarity of the active
interrupt edge as well as selecting a pull-up or pull-down device if enabled.
0 A pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation.
1 A pull-down device is connected to the associated pin and detects rising edge/high level for interrupt
generation.
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
92 Freescale Semiconductor
6.5.3 Port C Registers
Port C is controlled by the registers listed below.
6.5.3.1 Port C Data Register (PTCD)
6.5.3.2 Port C Data Direction Register (PTCDD)
76543210
RPTCD7 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0
W
Reset: 00000000
Figure 6-19. Port C Data Register (PTCD)
Table 6-17. PTCD Register Field Descriptions
Field Description
7:0
PTCD[7:0] Port C Data Register Bits — For port C pins that are inputs, reads return the logic level on the pin. For port C
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pull-ups disabled.
76543210
RPTCDD7 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0
W
Reset: 00000000
Figure 6-20. Port C Data Direction Register (PTCDD)
Table 6-18. PTCDD Register Field Descriptions
Field Description
7:0
PTCDD[7:0] Data Direction for Port C Bits — These read/write bits control the direction of port C pins and what is read for
PTCD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn.
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 93
6.5.3.3 Port C Pull Enable Register (PTCPE)
NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.
6.5.3.4 Port C Slew Rate Enable Register (PTCSE)
Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
rate control to the desired value to ensure correct operation.
76543210
RPTCPE7 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0
W
Reset: 00000000
Figure 6-21. Internal Pull Enable for Port C Register (PTCPE)
Table 6-19. PTCPE Register Field Descriptions
Field Description
7:0
PTCPE[7:0] Internal Pull Enable for Port C Bits — Each of these control bits determines if the internal pull-up device is
enabled for the associated PTC pin. For port C pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port C bit n.
1 Internal pull-up device enabled for port C bit n.
76543210
RPTCSE7 PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0
W
Reset: 00000000
Figure 6-22. Slew Rate Enable for Port C Register (PTCSE)
Table 6-20. PTCSE Register Field Descriptions
Field Description
7:0
PTCSE[7:0] Output Slew Rate Enable for Port C Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTC pin. For port C pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port C bit n.
1 Output slew rate control enabled for port C bit n.
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
94 Freescale Semiconductor
6.5.3.5 Port C Drive Strength Selection Register (PTCDS)
76543210
RPTCDS7 PTCDS6 PTCDS5 PTCDS4 PTCDS3 PTCDS2 PTCDS1 PTCDS0
W
Reset: 00000000
Figure 6-23. Drive Strength Selection for Port C Register (PTCDS)
Table 6-21. PTCDS Register Field Descriptions
Field Description
7:0
PTCDS[7:0] Output Drive Strength Selection for Port C Bits — Each of these control bits selects between low and high
output drive for the associated PTC pin. For port C pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port C bit n.
1 High output drive strength selected for port C bit n.
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 95
6.5.4 Port D Registers
Port D is controlled by the registers listed below.
6.5.4.1 Port D Data Register (PTDD)
6.5.4.2 Port D Data Direction Register (PTDDD)
76543210
RPTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0
W
Reset: 00000000
Figure 6-24. Port D Data Register (PTDD)
Table 6-22. PTDD Register Field Descriptions
Field Description
7:0
PTDD[7:0] Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin. For port D
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pull-ups/pull-downs disabled.
76543210
RPTDDD7 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0
W
Reset: 00000000
Figure 6-25. Port D Data Direction Register (PTDDD)
Table 6-23. PTDDD Register Field Descriptions
Field Description
7:0
PTDDD[7:0] Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for
PTDD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
96 Freescale Semiconductor
6.5.4.3 Port D Pull Enable Register (PTDPE)
NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.
6.5.4.4 Port D Slew Rate Enable Register (PTDSE)
Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
rate control to the desired value to ensure correct operation.
76543210
RPTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0
W
Reset: 00000000
Figure 6-26. Internal Pull Enable for Port D Register (PTDPE)
Table 6-24. PTDPE Register Field Descriptions
Field Description
7:0
PTDPE[7:0] Internal Pull Enable for Port D Bits — Each of these control bits determines if the internal pull-up or pull-down
device is enabled for the associated PTD pin. For port D pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port D bit n.
1 Internal pull-up/pull-down device enabled for port D bit n.
76543210
RPTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0
W
Reset: 00000000
Figure 6-27. Slew Rate Enable for Port D Register (PTDSE)
Table 6-25. PTDSE Register Field Descriptions
Field Description
7:0
PTDSE[7:0] Output Slew Rate Enable for Port D Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTD pin. For port D pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port D bit n.
1 Output slew rate control enabled for port D bit n.
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 97
6.5.4.5 Port D Drive Strength Selection Register (PTDDS)
6.5.4.6 Port D Interrupt Status and Control Register (PTDSC)
76543210
RPTDDS7 PTDDS6 PTDDS5 PTDDS4 PTDDS3 PTDDS2 PTDDS1 PTDDS0
W
Reset: 00000000
Figure 6-28. Drive Strength Selection for Port D Register (PTDDS)
Table 6-26. PTDDS Register Field Descriptions
Field Description
7:0
PTDDS[7:0] Output Drive Strength Selection for Port D Bits — Each of these control bits selects between low and high
output drive for the associated PTD pin. For port D pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port D bit n.
1 High output drive strength selected for port D bit n.
76543210
R0000PTDIF 0 PTDIE PTDMOD
W PTDACK
Reset: 00000000
= Unimplemented or Reserved
Figure 6-29. Port D Interrupt Status and Control Register (PTDSC)
Table 6-27. PTDSC Register Field Descriptions
Field Description
3
PTDIF Port D Interrupt Flag — PTDIF indicates when a port D interrupt is detected. Writes have no effect on PTDIF.
0 No port D interrupt detected.
1 Port D interrupt detected.
2
PTDACK Port D Interrupt Acknowledge — Writing a 1 to PTDACK is part of the flag clearing mechanism. PTDACK
always reads as 0.
1
PTDIE Port D Interrupt Enable — PTDIE determines whether a port D interrupt is requested.
0 Port D interrupt request not enabled.
1 Port D interrupt request enabled.
0
PTDMOD Port A Detection Mode — PTDMOD (along with the PTDES bits) controls the detection mode of the port D
interrupt pins.
0 Port D pins detect edges only.
1 Port D pins detect both edges and levels.
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
98 Freescale Semiconductor
6.5.4.7 Port D Interrupt Pin Select Register (PTDPS)
6.5.4.8 Port D Interrupt Edge Select Register (PTDES)
76543210
RPTDPS7 PTDPS6 PTDPS5 PTDPS4 PTDPS3 PTDPS2 PTDPS1 PTDPS0
W
Reset: 00000000
Figure 6-30. Port D Interrupt Pin Select Register (PTDPS)
Table 6-28. PTDPS Register Field Descriptions
Field Description
7:0
PTDPS[7:0] Port D Interrupt Pin Selects — Each of the PTDPSn bits enable the corresponding port D interrupt pin.
0 Pin not enabled as interrupt.
1 Pin enabled as interrupt.
76543210
RPTDES7 PTDES6 PTDES5 PTDES4 PTDES3 PTDES2 PTDES1 PTDES0
W
Reset: 00000000
Figure 6-31. Port D Edge Select Register (PTDES)
Table 6-29. PTDES Register Field Descriptions
Field Description
7:0
PTDES[7:0] Port D Edge Selects — Each of the PTDESn bits serves a dual purpose by selecting the polarity of the active
interrupt edge as well as selecting a pull-up or pull-down device if enabled.
0 A pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation.
1 A pull-down device is connected to the associated pin and detects rising edge/high level for interrupt
generation.
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor 99
6.5.5 Port E Registers
Port E is controlled by the registers listed below.
6.5.5.1 Port E Data Register (PTED)
6.5.5.2 Port E Data Direction Register (PTEDD)
76543210
RPTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED11
1Reads of this bit always return the pin value of the associated pin, regardless of the value stored in the port data direction bit.
PTED0
W
Reset: 00000000
Figure 6-32. Port E Data Register (PTED)
Table 6-30. PTED Register Field Descriptions
Field Description
7:0
PTED[7:0] Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port E pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.
76543210
RPTEDD7 PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD11
1PTEDD1 has no effect on the input-only PTE1 pin.
PTEDD0
W
Reset: 00000000
Figure 6-33. Port E Data Direction Register (PTEDD)
Table 6-31. PTEDD Register Field Descriptions
Field Description
7:0
PTEDD[7:0] Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for
PTED reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn.
Chapter 6 Parallel Input/Output Control
MC9S08DN60 Series Data Sheet, Rev 3
100 Freescale Semiconductor
6.5.5.3 Port E Pull Enable Register (PTEPE)
NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.
6.5.5.4 Port E Slew Rate Enable Register (PTESE)
Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
rate control to the desired value to ensure correct operation.
76543210
RPTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0
W
Reset: 00000000
Figure 6-34. Internal Pull Enable for Port E Register (PTEPE)
Table 6-32. PTEPE Register Field Descriptions
Field Description
7:0
PTEPE[7:0] Internal Pull Enable for Port E Bits — Each of these control bits determines if the internal pull-up device is
enabled for the associated PTE pin. For port E pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port E bit n.
1 Internal pull-up dev