MC68HC908JL3E Family Datasheet by Freescale Semiconductor - NXP

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Microcontrollers
M68HC08
MC68HC908JK1
MC68HRC908JK1
MC68HC908JK3
JC68HRC908JK3
MC68HC908JL3
MC68HRC908JL3
Technical Data
Rev. 1.1
MC68HC908JL3/H
August 1, 2005
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor List of Sections 3
Technical Data — MC68H(R)C908JL3
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . .21
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Section 3. Random-Access Memory (RAM) . . . . . . . . . .37
Section 4. FLASH Memory (FLASH) . . . . . . . . . . . . . . . .39
Section 5. Configuration Register (CONFIG) . . . . . . . . .47
Section 6. Central Processor Unit (CPU) . . . . . . . . . . . .51
Section 7. System Integration Module (SIM) . . . . . . . . .71
Section 8. Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . . .95
Section 9. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . .101
Section 10. Timer Interface Module (TIM) . . . . . . . . . . .115
Section 11. Analog-to-Digital Converter (ADC) . . . . . .137
Section 12. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Section 13. External Interrupt (IRQ) . . . . . . . . . . . . . . .159
Section 14. Keyboard Interrupt Module (KBI). . . . . . . .165
Section 15. Computer Operating Properly (COP) . . . .173
Section 16. Low Voltage Inhibit (LVI) . . . . . . . . . . . . . .179
Section 17. Break Module (BREAK) . . . . . . . . . . . . . . .183
Section 18. Electrical Specifications. . . . . . . . . . . . . . .191
Section 19. Mechanical Specifications . . . . . . . . . . . . .203
Section 20. Ordering Information . . . . . . . . . . . . . . . . .207
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Table of Contents
Section 1. General Description
1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Section 2. Memory
2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.4 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Section 3. Random-Access Memory (RAM)
3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Section 4. FLASH Memory (FLASH)
4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
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4.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.5 FLASH Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .41
4.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .42
4.7 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.8 FLASH Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.9 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . .46
Section 5. Configuration Register (CONFIG)
5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Section 6. Central Processor Unit (CPU)
6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .55
6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .58
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.9 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
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Section 7. System Integration Module (SIM)
7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
7.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . .75
7.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
7.3.2 Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . .75
7.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . .75
7.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . .76
7.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
7.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . .77
7.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
7.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . .79
7.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
7.4.2.4 Illegal Address Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .79
7.4.2.5 LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
7.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
7.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . .80
7.5.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . .80
7.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . .81
7.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
7.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
7.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
7.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
7.6.2 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .85
7.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . .86
7.6.2.2 Interrupt Status Register 2. . . . . . . . . . . . . . . . . . . . . . . .86
7.6.2.3 Interrupt Status Register 3. . . . . . . . . . . . . . . . . . . . . . . .87
7.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
7.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
7.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . .87
7.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
7.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
7.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
7.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
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7.8.1 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . .91
7.8.2 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . .92
7.8.3 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . .94
Section 8. Oscillator (OSC)
8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
8.3 X-tal Oscillator (MC68HC908xxx). . . . . . . . . . . . . . . . . . . . . . .96
8.4 RC Oscillator (MC68HRC908xxx) . . . . . . . . . . . . . . . . . . . . . .97
8.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
8.5.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . .98
8.5.2 Crystal Amplifier Output Pin (OSC2/PTA6/RCCLK). . . . . . .98
8.5.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . .98
8.5.4 X-tal Oscillator Clock (XTALCLK). . . . . . . . . . . . . . . . . . . . .98
8.5.5 RC Oscillator Clock (RCCLK). . . . . . . . . . . . . . . . . . . . . . . .99
8.5.6 Oscillator Out 2 (2OSCOUT) . . . . . . . . . . . . . . . . . . . . . . . .99
8.5.7 Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . .99
8.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8.7 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . .100
Section 9. Monitor ROM (MON)
9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
9.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
9.4.1 Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .104
9.4.2 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
9.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
9.4.4 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
9.4.5 Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
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9.4.6 Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
9.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Section 10. Timer Interface Module (TIM)
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
10.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
10.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
10.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
10.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
10.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .120
10.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .120
10.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .121
10.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .122
10.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .123
10.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
10.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
10.7 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
10.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .126
10.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
10.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
10.10.1 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . .127
10.10.2 TIM Counter Registers (TCNTH:TCNTL). . . . . . . . . . . . . .129
10.10.3 TIM Counter Modulo Registers (TMODH:TMODL) . . . . . .130
10.10.4 TIM Channel Status and Control Registers (TSC0:TSC1).131
10.10.5 TIM Channel Registers (TCH0H/L:TCH1H/L) . . . . . . . . . .135
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Section 11. Analog-to-Digital Converter (ADC)
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
11.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
11.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
11.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
11.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .140
11.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . .141
11.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
11.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
11.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
11.7.1 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . .142
11.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
11.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . .142
11.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
11.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . .145
Section 12. I/O Ports
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
12.4 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .149
12.4.1 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . .150
12.4.2 Port A Input Pull-up Enable Register (PTAPUE) . . . . . . . .151
12.5 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
12.5.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . .153
12.5.2 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . .153
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12.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
12.6.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . .155
12.6.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . .156
12.6.3 Port D Control Register (PDCR). . . . . . . . . . . . . . . . . . . . .157
Section 13. External Interrupt (IRQ)
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
13.4.1 IRQ1 Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
13.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .163
13.6 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . .163
Section 14. Keyboard Interrupt Module (KBI)
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
14.4.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
14.4.2 Keyboard Status and Control Register. . . . . . . . . . . . . . . .169
14.4.3 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . .170
14.5 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
14.6 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
14.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .171
Section 15. Computer Operating Properly (COP)
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
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15.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
15.4.1 2OSCOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
15.4.2 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
15.4.3 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
15.4.4 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
15.4.5 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
15.4.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
15.4.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . .176
15.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
15.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
15.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
15.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
15.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
15.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
15.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .178
Section 16. Low Voltage Inhibit (LVI)
16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
16.5 LVI Control Register (CONFIG2/CONFIG1). . . . . . . . . . . . . .180
16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
16.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
16.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
Section 17. Break Module (BREAK)
17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
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17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
17.4.1 Flag Protection During Break Interrupts. . . . . . . . . . . . . . .186
17.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .186
17.4.3 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . .186
17.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .186
17.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
17.5.1 Break Status and Control Register (BRKSCR) . . . . . . . . .187
17.5.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .188
17.5.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
17.5.4 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . .190
17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
17.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
Section 18. Electrical Specifications
18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
18.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .192
18.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .193
18.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
18.6 5V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . .194
18.7 5V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
18.8 5V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .196
18.9 3V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . .197
18.10 3V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
18.11 3V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .199
18.12 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
18.13 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
18.14 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
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Section 19. Mechanical Specifications
19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
19.3 20-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
19.4 20-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
19.5 28-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
19.6 28-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
Section 20. Ordering Information
20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
20.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
MC68H(R)C908JL3Rev. 1.1 Technical Data
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List of Figures
Figure Title Page
1-1 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1-2 MCU Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2-1 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2-2 Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .30
4-1 FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . . .40
4-2 FLASH Programming Flowchart. . . . . . . . . . . . . . . . . . . . . . . .45
4-3 FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . . .46
5-1 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . .48
5-2 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . .49
6-1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6-2 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6-3 Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
6-4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
6-5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
6-6 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .56
7-1 SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
7-2 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . .74
7-3 SIM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
7-4 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
7-5 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
7-6 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
7-7 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
7-8 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
7-9 Interrupt Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
7-10 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
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Figure Title Page
7-11 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . .84
7-12 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . .86
7-13 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . .86
7-14 Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . . .87
7-15 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
7-16 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . .89
7-17 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . .89
7-18 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
7-19 Stop Mode Recovery from Interrupt or Break. . . . . . . . . . . . . .91
7-20 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . .91
7-21 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . .93
7-22 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . .94
8-1 X-tal Oscillator External Connections . . . . . . . . . . . . . . . . . . . .96
8-2 RC Oscillator External Connections . . . . . . . . . . . . . . . . . . . . .97
9-1 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
9-2 Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . .106
9-3 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
9-4 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .108
9-5 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
9-6 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
9-7 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .113
10-1 TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
10-2 TIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .118
10-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .122
10-4 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . .127
10-5 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . . .130
10-6 TIM Counter Modulo Registers (TMODH:TMODL). . . . . . . . .131
10-7 TIM Channel Status and Control Registers (TSC0:TSC1) . . .132
10-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
10-9 TIM Channel Registers (TCH0H/L:TCH1H/L). . . . . . . . . . . . .136
11-1 ADC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .138
11-2 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
11-3 ADC Status and Control Register (ADSCR). . . . . . . . . . . . . .142
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Figure Title Page
11-4 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . .145
11-5 ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . . .145
12-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .148
12-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .149
12-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .150
12-4 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
12-5 Port A Input Pull-up Enable Register (PTAPUE) . . . . . . . . . .152
12-6 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .153
12-7 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .153
12-8 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
12-9 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .155
12-10 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . .156
12-11 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
12-12 Port D Control Register (PDCR). . . . . . . . . . . . . . . . . . . . . . .157
13-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .161
13-2 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .161
13-3 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . .163
13-4 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . .164
14-1 KBI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .166
14-2 Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . .166
14-3 Keyboard Status and Control Register (KBSCR) . . . . . . . . . .169
14-4 Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . .170
15-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
15-2 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . .176
15-3 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .177
16-1 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .180
16-2 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . .180
16-3 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . .181
17-1 Break Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .185
17-2 Break I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .185
17-3 Break Status and Control Register (BRKSCR). . . . . . . . . . . .187
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Figure Title Page
17-4 Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . .188
17-5 Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . .188
17-6 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . .188
17-7 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . .190
18-1 RC vs. Frequency (5V @25°C) . . . . . . . . . . . . . . . . . . . . . . .196
18-2 RC vs. Frequency (3V @25°C) . . . . . . . . . . . . . . . . . . . . . . .199
18-3 Typical Operating IDD, with All Modules Turned On (25 °C) .200
18-4 Typical Wait Mode IDD, with ADC Turned On (25 °C) . . . . . .200
18-5 Typical Stop Mode IDD, with all Modules Disabled (25 °C) . .200
19-1 20-Pin PDIP (Case #738) . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
19-2 20-Pin SOIC (Case #751D) . . . . . . . . . . . . . . . . . . . . . . . . . .204
19-3 28-Pin PDIP (Case #710) . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
19-4 28-Pin SOIC (Case #751F). . . . . . . . . . . . . . . . . . . . . . . . . . .205
MC68H(R)C908JL3Rev. 1.1 Technical Data
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List of Tables
Table Title Page
1-1 Summary of Device Variations . . . . . . . . . . . . . . . . . . . . . . . . .21
1-2 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2-1 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
6-1 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
6-2 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
7-1 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
7-2 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
7-3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
7-4 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
9-1 Monitor Mode Entry Requirements and Options. . . . . . . . . . .104
9-2 Monitor Mode Vector Differences. . . . . . . . . . . . . . . . . . . . . .107
9-3 Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . .107
9-4 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . .110
9-5 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . .110
9-6 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . .111
9-7 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . .111
9-8 READSP (Read Stack Pointer) Command. . . . . . . . . . . . . . .112
9-9 RUN (Run User Program) Command. . . . . . . . . . . . . . . . . . .112
10-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
10-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
10-3 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .134
11-1 MUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
11-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
List of Tables
Technical Data MC68H(R)C908JL3Rev. 1.1
20 List of Tables Freescale Semiconductor
Table Title Page
12-1 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
12-2 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
12-3 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
18-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .192
18-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
18-3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
18-4 DC Electrical Characteristics (5V) . . . . . . . . . . . . . . . . . . . . .194
18-5 Control Timing (5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
18-6 Oscillator Component Specifications (5V) . . . . . . . . . . . . . . .196
18-7 DC Electrical Characteristics (3V) . . . . . . . . . . . . . . . . . . . . .197
18-8 Control Timing (3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
18-9 Oscillator Component Specifications (3V) . . . . . . . . . . . . . . .199
18-10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
18-11 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
20-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor General Description 21
Technical Data — MC68H(R)C908JL3
Section 1. General Description
1.1 Contents
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.2 Introduction
The MC68H(R)C908JL3 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08
Family is based on the customer-specified integrated circuit (CSIC)
design strategy. All MCUs in the family use the enhanced M68HC08
central processor unit (CPU08) and are available with a variety of
modules, memory sizes and types, and package types.
All references to the MC68H(R)C908JL3 in this data book apply equally
to the MC68H(R)C908JK3 and MC68H(R)C908JK1, unless otherwise
stated.
Table 1-1. Summary of Device Variations
Device FLASH Memory Size Pin Count
MC68H(R)C908JL3 4096 bytes 28 pins
MC68H(R)C908JK3 4096 bytes 20 pins
MC68H(R)C908JK1 1536 bytes 20 pins
General Description
Technical Data MC68H(R)C908JL3Rev. 1.1
22 General Description Freescale Semiconductor
1.3 Features
Features of the MC68H(R)C908JL3 include the following:
High-performance M68HC08 architecture
Fully upward-compatible object code with M6805, M146805, and
M68HC05 Families
Low-power design; fully static with stop and wait modes
5V and 3V operating voltages
8MHz internal bus operation
RC-oscillator circuit or crystal-oscillator options
In-system FLASH programming
FLASH security1
User FLASH memory
4096 bytes for MC68H(R)C908JL3/JK3
1536 bytes for MC68H(R)C908JK1
128 bytes of on-chip random-access memory (RAM)
2-channel, 16-bit timer interface module (TIM)
12-channel, 8-bit analog-to-digital converter (ADC)
23 general purpose I/O ports for MC68H(R)C908JL3:
7 keyboard interrupt with internal pull-up
10 LED drivers
–2 × 25mA open-drain I/O with pull-up
2 ICAP/OCAP/PWM
15 general purpose I/O ports for MC68H(R)C908JK3/JK1:
1 keyboard interrupt with internal pull-up
(with RC oscillator option selected)
4 LED drivers
–2 × 25mA open-drain I/O with pull-up
2 ICAP/OCAP/PWM
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
General Description
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor General Description 23
System protection features:
Optional computer operating properly (COP) reset
Optional low-voltage detection with reset and selectable trip
points for 3V and 5V operation.
Illegal opcode detection with reset
Illegal address detection with reset
Master reset pin with internal pull-up and power-on reset
•IRQ1 with programmable pull-up and schmitt-trigger input
28-pin PDIP and 28-pin SOIC packages for MC68H(R)C908JL3
20-pin PDIP and 20-pin SOIC packages for
MC68H(R)C908JK3/JK1
Features of the CPU08 include the following:
Enhanced HC05 programming model
Extensive loop control functions
16 addressing modes (eight more than the HC05)
16-bit index register and stack pointer
Memory-to-memory data transfers
Fast 8 × 8 multiply instruction
Fast 16/8 divide instruction
Binary-coded decimal (BCD) instructions
Optimization for controller applications
Efficient C language support
1.4 MCU Block Diagram
Figure 1-1 shows the structure of the MC68H(R)C908JL3.
H a a H MWMWMW MW MWMW it it
General Description
Technical Data MC68H(R)C908JL3Rev. 1.1
24 General Description Freescale Semiconductor
Figure 1-1. MCU Block Diagram
RST, IRQ1: PIN HAS INTERNAL 30K PULL-UP
PTD[6:7]: PINS HAVE 25mA OPEN-DRAIN OUTPUT & PROGRAMMABLE 5K PULL-UP
PTA[0:5], PTD[2:3], PTD[6:7]: PIN HAS LED DRIVE
PTA[0:6]: PINS HAVE PROGRAMMABLE KEYBOARD INTERRUPT AND PULL-UP
PTA[0:5] and PTD[0:1]: NOT AVAILABLE ON 20-PIN DEVICES – MC68H(R)C908JK3/JK1
MC68H(R)C908JL3/JK3: 4096 BYTES
MC68H(R)C908JK1: 1536 BYTES
USER FLASH
COND CODE REG V 1 1 I N Z CH
INDEX REG
CPU CONTROL
STK PNTR
ALU
68HC08 CPU
ACCUM
PROGRAM COUNTER
CPU REGISTERS
128 BYTES RAM
OSC1
RST
IRQ1
VDD
VSS
16-BIT
TIMER MODULE
COP
MODULE
POWER-ON RESET
MODULE
BREAK
MODULE
MODE SELECT
MODULE
SYSTEM INTEGRATION
MODULE
X-TAL OSCILLATOR
OR
RC-OSCILLATOR
POWER SUPPLY
AND
VOLTAGE REGULATOR
PTB[0:7]
PTB
DDRB
MONITOR ROM
960 BYTES
PTD[0:7]
PTA/KBI[0:6]
8-BIT ADC
ADC[0:7]/
PTB[0:7]
TCH0/PTD4
TCH1/PTD5
OSC2/RCCLK/PTA6
PTD
DDRD
PTA
DDRA
ADC[11:8]/
PTD[0:3]
T S R jjjjjjjjjj EEEEEEEEEE Q R T S R jjjjjjjjjjjjjj EEEEEEEEEEEEEE Q R
General Description
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor General Description 25
1.5 Pin Assignments
The MC68H(R)C908JL3 is available in 28-pin packages and the
MC68H(R)C908JK3/JK1 in 20-pin packages. Figure 1-2 shows the pin
assignment for the two packages.
Figure 1-2. MCU Pin Assignments
1
2
3
4
5
6
7
28
27
26
25
24
23
22
21
20
19
18
12
13
14
17
16
15
8
9
10
11
1
2
3
4
5
6
7
20
19
18
17
16
15
14
13
12
11
8
9
10
RST
PTA5
PTD4
PTD5
PTD2
PTA4
PTD3
PTB0
PTB1
PTD1
PTB2
PTB3
PTD0
PTB4
IRQ1
PTA0
VSS
OSC1
OSC2/PTA6
PTA1
VDD
PTA2
PTA3
PTB7
PTB6
PTB5
PTD7
PTD6
RST
PTD4
PTD5
PTD2
PTD3
PTB0
PTB1
PTB2
PTB3
PTB4
IRQ1
VSS
OSC1
OSC2/PTA6
VDD
PTB7
PTB6
PTB5
PTD7
PTD6
28-PIN ASSIGNMENT
MC68H(R)C908JL3
20-PIN ASSIGNMENT
MC68H(R)C908JK3/JK1
Pins not bonded out on 20-pin package:
PTA0, PTA1, PTA2, PTA3, PTA4, PTA5,
PTD0, PTD1.
General Description
Technical Data MC68H(R)C908JL3Rev. 1.1
26 General Description Freescale Semiconductor
1.6 Pin Functions
Description of the pin functions are provided in Table 1-2.
NOTE: On the 20-pin package, the following pins are not available:
PTA0, PTA1, PTA2, PTA3, PTA4, PTA5, PTD0, and PTD1.
Table 1-2. Pin Functions
PIN NAME PIN DESCRIPTION IN/OUT VOLTAGE LEVEL
VDD Power supply. In 5V or 3V
VSS Power supply ground Out 0V
RST RESET input, active low.
With Internal pull-up and schmitt trigger input. Input VDD
IRQ1
External IRQ pin.
With software programmable internal pull-up and
schmitt trigger input.
This pin is also used for mode entry selection.
Input VDD to VDD+VHI
OSC1 X-tal or RC oscillator input. In Analog
OSC2
For X-tal oscillator option:
X-tal oscillator output, this is the inverting OSC1
signal. Out Analog
For RC oscillator option:
Default is RCCLK output.
Shared with PTA6/KBI6, with programmable pull-up. In/Out VDD
PTA[0:6]
7-bit general purpose I/O port. In/Out VDD
Shared with 7 keyboard interrupts KBI[0:6]. In VDD
Each pin has programmable internal pull-up device. In VDD
PTB[0:7] 8-bit general purpose I/O port. In/Out VDD
Shared with 8 ADC inputs, ADC[0:7]. In Analog
PTD[0:7]
8-bit general purpose I/O port. In/Out VDD
PTD[3:0] shared with 4 ADC inputs, ADC[8:11]. Input Analog
PTD[4:5] shared with TIM channels, TCH0 and TCH1. In/Out VDD
PTD[6:7] can be configured as 25mA open-drain
output with pull-up. In/Out VDD
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor Memory 27
Technical Data — MC68H(R)C908JL3
Section 2. Memory
2.1 Contents
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.4 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.2 Introduction
The CPU08 can address 64 Kbytes of memory space. The memory
map, shown in Figure 2-1, includes:
4096 bytes of user FLASH for MC68H(R)C908JL3/JK3
1536 bytes of user FLASH for MC68H(R)C908JK1
128 bytes of RAM
48 bytes of user-defined vectors
960 bytes of Monitor ROM
Memory
Technical Data MC68H(R)C908JL3Rev. 1.1
28 Memory Freescale Semiconductor
$0000
$003F
I/O REGISTERS
64 BYTES
$0040
$007F
RESERVED
64 BYTES
$0080
$00FF
RAM
128 BYTES
$0100
$EBFF
UNIMPLEMENTED
60160 BYTES UNIMPLEMENTED
62720 BYTES
$0100
$F5FF
$EC00
$FBFF
FLASH MEMORY
MC68H(R)C908JL3/JK3
4096 BYTES FLASH MEMORY
MC68H(R)C908JK1
1536 BYTES
$F600
$FBFF
$FC00
$FDFF
MONITOR ROM
512 BYTES
$FE00 BREAK STATUS REGISTER (BSR)
$FE01 RESET STATUS REGISTER (RSR)
$FE02 RESERVED (UBAR)
$FE03 BREAK FLAG CONTROL REGISTER (BFCR)
$FE04 INTERRUPT STATUS REGISTER 1 (INT1)
$FE05 INTERRUPT STATUS REGISTER 2 (INT2)
$FE06 INTERRUPT STATUS REGISTER 3 (INT3)
$FE07 RESERVED
$FE08 FLASH CONTROL REGISTER (FLCR)
$FE09 FLASH BLOCK PROTECT REGISTER (FLBPR)
$FE0A RESERVED
$FE0B RESERVED
$FE0C BREAK ADDRESS HIGH REGISTER (BRKH)
$FE0D BREAK ADDRESS LOW REGISTER (BRKL)
$FE0E BREAK STATUS AND CONTROL REGISTER (BRKSCR)
$FE0F RESERVED
$FE10
$FFCF
MONITOR ROM
448 BYTES
$FFD0
$FFFF
USER VECTORS
48 BYTES
Figure 2-1. Memory Map
Memory
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor Memory 29
2.3 I/O Section
Addresses $0000–$003F, shown in Figure 2-2, contain most of the
control, status, and data registers. Additional I/O registers have the
following addresses:
$FE00 (Break Status Register, BSR)
$FE01 (Reset Status Register, RSR)
$FE02 (Reserved, SUBAR)
$FE03 (Break Flag Control Register, BFCR)
$FE04 (Interrupt Status Register 1, INT1)
$FE05 (Interrupt Status Register 2, INT2)
$FE06 (Interrupt Status Register 3, INT3)
$FE07 (Reserved)
$FE08 (FLASH Control Register, FLCR)
$FE09 (FLASH Block Protect Register, FLBPR)
$FE0A (Reserved)
$FE0B (Reserved)
$FE0C (Break Address Register High, BRKH)
$FE0D (Break Address Register Low, BRKL)
$FE0E (Break Status and Control Register, BRKSCR)
$FE0F (Reserved)
$FFFF (COP Control Register, COPCTL)
2.4 Monitor ROM
The 960 bytes at addresses $FC00–$FDFF and $FE10–$FFCF are
reserved ROM addresses that contain the instructions for the monitor
functions. (See Section 9. Monitor ROM (MON).)
Memory
Technical Data MC68H(R)C908JL3Rev. 1.1
30 Memory Freescale Semiconductor
Addr.Register Name Bit 7654321Bit 0
$0000 Port A Data Register
(PTA)
Read: 0 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
Write:
Reset: Unaffected by reset
$0001 Port B Data Register
(PTB)
Read: PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
Write:
Reset: Unaffected by reset
$0002 Unimplemented
Read:
Write:
$0003 Port D Data Register
(PTD)
Read: PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
Write:
Reset: Unaffected by reset
$0004 Data Direction Register A
(DDRA)
Read: 0 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset:00000000
$0005 Data Direction Register B
(DDRB)
Read: DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset:00000000
$0006 Unimplemented
Read:
Write:
$0007 Data Direction Register D
(DDRD)
Read: DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
Write:
Reset:00000000
$0008
$0009
Unimplemented
Read:
Write:
$000A Port D Control Register
(PDCR)
Read: 0000
SLOWD7 SLOWD6 PTDPU7 PTDPU6
Write:
Reset:00000000
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 5)
_____4 _ _
Memory
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor Memory 31
$000B
$000C
Unimplemented
Read:
Write:
$000D
Port A Input Pull-up
Enable Register
(PTAPUE)
Read: PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Write:
Reset:00000000
$000E
$0019 Unimplemented
Read:
Write:
$001A
Keyboard Status and
Control Register
(KBSCR)
Read: 0000KEYF 0 IMASKK MODEK
Write: ACKK
Reset:00000000
$001B
Keyboard Interrupt
Enable Register
(KBIER)
Read: 0 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
Write:
Reset:00000000
$001C Unimplemented
Read:
Write:
$001D
IRQ Status and Control
Register
(INTSCR)
Read: 0000IRQF10
IMASK1 MODE1
Write: ACK1
Reset:00000000
$001E Configuration Register 2
(CONFIG2)
Read: IRQPUD R R LVIT1 LVIT0 R R R
Write:
Reset:0000*0*000
$001F Configuration Register 1
(CONFIG1)
Read: COPRS R R LVID R SSREC STOP COPD
Write:
Reset:00000000
† One-time writable register after each reset. * LVIT1 and LVIT0 reset to logic 0 by a power-on reset (POR) only.
$0020
TIM Status and Control
Register
(TSC)
Read: TOF TOIE TSTOP 00
PS2 PS1 PS0
Write: 0 TRST
Reset:00100000
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 5)
Memory
Technical Data MC68H(R)C908JL3Rev. 1.1
32 Memory Freescale Semiconductor
$0021
TIM Counter Register
High
(TCNTH)
Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset:00000000
$0022
TIM Counter Register
Low
(TCNTL)
Read: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Write:
Reset:00000000
$0023
TIM Counter Modulo
Register High
(TMODH)
Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset:11111111
$0024
TIM Counter Modulo
Register Low
(TMODL)
Read: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Write:
Reset:11111111
$0025
TIM Channel 0 Status and
Control Register
(TSC0)
Read: CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:00000000
$0026
TIM Channel 0
Register High
(TCH0H)
Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset: Indeterminate after reset
$0027
TIM Channel 0
Register Low
(TCH0L)
Read: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Write:
Reset: Indeterminate after reset
$0028
TIM Channel 1 Status and
Control Register
(TSC1)
Read: CH1F CH1IE 0MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset:00000000
$0029
TIM Channel 1
Register High
(TCH1H)
Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset: Indeterminate after reset
$002A
TIM Channel 1
Register Low
(TCH1L)
Read: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Write:
Reset: Indeterminate after reset
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 5)
______
Memory
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor Memory 33
$002B
$003B Unimplemented
Read:
Write:
$003C
ADC Status and Control
Register
(ADSCR)
Read: COCO AIEN ADCO CH4 CH3 CH2 CH1 CH0
Write:
Reset:00011111
$003D ADC Data Register
(ADR)
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write:
Reset: Indeterminate after reset
$003E ADC Input Clock Register
(ADICLK)
Read: ADIV2 ADIV1 ADIV0 00000
Write:
Reset:00000000
$003F Unimplemented
Read:
Write:
$FE00 Break Status Register
(BSR)
Read: RRRRRR
SBSW R
Write: See note
Reset: 0
Note: Writing a logic 0 clears SBSW.
$FE01 Reset Status Register
(RSR)
Read: POR PIN COP ILOP ILAD MODRST LVI 0
Write:
POR:10000000
$FE02 Reserved
Read: RRRRRRRR
Write:
$FE03
Break Flag Control
Register
(BFCR)
Read: BCFERRRRRRR
Write:
Reset: 0
$FE04 Interrupt Status Register 1
(INT1)
Read: 0 IF5 IF4 IF3 0 IF1 0 0
Write:RRRRRRRR
Reset:00000000
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 5)
Memory
Technical Data MC68H(R)C908JL3Rev. 1.1
34 Memory Freescale Semiconductor
$FE05 Interrupt Status Register 2
(INT2)
Read: IF14 0000000
Write:RRRRRRRR
Reset:00000000
$FE06 Interrupt Status Register 3
(INT3)
Read: 0000000IF15
Write:RRRRRRRR
Reset:00000000
$FE07 Reserved
Read: RRRRRRRR
Write:
$FE08 FLASH Control Register
(FLCR)
Read: 0000
HVEN MASS ERASE PGM
Write:
Reset:00000000
$FE09 FLASH Block Protect
Register (FLBPR)
Read: BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 0
Write:
Reset:00000000
$FE0A
$FE0B
Reserved
Read: RRRRRRRR
Write:
$FE0C
Break Address High
Register
(BRKH)
Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset:00000000
$FE0D
Break Address low
Register
(BRKL)
Read: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Write:
Reset:00000000
$FE0E
Break Status and Control
Register
(BRKSCR)
Read: BRKE BRKA 000000
Write:
Reset:00000000
$FFFF COP Control Register
(COPCTL)
Read: Low byte of reset vector
Write: Writing clears COP counter (any value)
Reset: Unaffected by reset
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 5)
Memory
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor Memory 35
.
Table 2-1. Vector Addresses
Vector Priority Vector Address Vector
Lowest IF15 $FFDE ADC Conversion Complete Vector (High)
$FFDF ADC Conversion Complete Vector (Low)
IF14 $FFE0 Keyboard Vector (High)
$FFE1 Keyboard Vector (Low)
IF13
to
IF6 —Not Used
IF5 $FFF2 TIM Overflow Vector (High)
$FFF3 TIM Overflow Vector (Low)
IF4 $FFF4 TIM Channel 1 Vector (High)
$FFF5 TIM Channel 1 Vector (Low)
IF3 $FFF6 TIM Channel 0 Vector (High)
$FFF7 TIM Channel 0 Vector (Low)
IF2 Not Used
IF1 $FFFA IRQ Vector (High)
$FFFB IRQ Vector (Low)
$FFFC SWI Vector (High)
$FFFD SWI Vector (Low)
$FFFE Reset Vector (High)
Highest $FFFF Reset Vector (Low)
Memory
Technical Data MC68H(R)C908JL3Rev. 1.1
36 Memory Freescale Semiconductor
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor Random-Access Memory (RAM) 37
Technical Data — MC68H(R)C908JL3
Section 3. Random-Access Memory (RAM)
3.1 Contents
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.2 Introduction
This section describes the 128 bytes of RAM.
3.3 Functional Description
Addresses $0080 through $00FF are RAM locations. The location of the
stack RAM is programmable. The 16-bit stack pointer allows the stack to
be anywhere in the 64-Kbyte memory space.
NOTE: For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 128 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF, direct addressing mode instructions can
access efficiently all page zero RAM locations. Page zero RAM,
therefore, provides ideal locations for frequently accessed global
variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
NOTE: For M6805 compatibility, the H register is not stacked.
Random-Access Memory (RAM)
Technical Data MC68H(R)C908JL3Rev. 1.1
38 Random-Access Memory (RAM) Freescale Semiconductor
During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
NOTE: Be careful when using nested subroutines. The CPU may overwrite data
in the RAM during a subroutine or during the interrupt stacking
operation.
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor FLASH Memory (FLASH) 39
Technical Data — MC68H(R)C908JL3
Section 4. FLASH Memory (FLASH)
4.1 Contents
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.5 FLASH Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .41
4.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .42
4.7 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.8 FLASH Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.9 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . .46
4.2 Introduction
This section describes the operation of the embedded FLASH memory.
The FLASH memory can be read, programmed, and erased from a
single external supply. The program and erase operations are enabled
through the use of an internal charge pump.
MC68H(R)C908JL3/JK3: 4096 bytes user FLASH from $EC00 – $FBFF.
MC68H(R)C908JK1: 1536 bytes user FLASH from $F600 – $FBFF.
FLASH Memory (FLASH)
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4.3 Functional Description
The FLASH memory consists of an array of 4096 or 1536 bytes with an
additional 48 bytes for user vectors. The minimum size of FLASH
memory that can be erased is 64 bytes; and the maximum size of FLASH
memory that can be programmed in a program cycle is 32 bytes (a row).
Program and erase operations are facilitated through control bits in the
Flash Control Register (FLCR). Details for these operations appear later
in this section. The address ranges for the user memory and vectors are:
$EC00 – $FBFF; user memory, 4096 bytes:
MC68H(R)C908JL3/JK3
$F600 – $FBFF; user memory, 1536 bytes: MC68H(R)C908JK1
$FFD0 – $FFFF; user interrupt vectors, 48 bytes.
NOTE: An erased bit reads as logic 1 and a programmed bit reads as logic 0.
A security feature prevents viewing of the FLASH contents.1
4.4 FLASH Control Register
The FLASH Control Register controls FLASH program and erase
operations.
HVEN — High Voltage Enable Bit
This read/write bit enables high voltage from the charge pump to the
memory for either program or erase operation. It can only be set if
either PGM=1 or ERASE=1 and the proper sequence for program or
erase is followed.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Address: $FE08
Bit 7654321Bit 0
Read: 0000
HVEN MASS ERASE PGM
Write:
Reset:00000000
Figure 4-1. FLASH Control Register (FLCR)
FLASH Memory (FLASH)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor FLASH Memory (FLASH) 41
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation or
block erase operation when the ERASE bit is set.
1 = Mass Erase operation selected
0 = Block Erase operation selected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. This bit
and the PGM bit should not be set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation not selected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. This
bit and the ERASE bit should not be set to 1 at the same time.
1 = Program operation selected
0 = Program operation not selected
4.5 FLASH Block Erase Operation
Use the following procedure to erase a block of FLASH memory. A block
consists of 64 consecutive bytes starting from addresses $XX00,
$XX40, $XX80 or $XXC0. The 48-byte User Interrupt Vectors area also
forms a block. Any block within the 4K bytes User Memory area
($EC00–$FBFF) can be erased alone. The 48-byte User Interrupt Vector
blocks can not be erased alone due to security concern. Mass erase is
required to erase this block.
1. Set the ERASE bit and clear the MASS bit in the FLASH Control
Register.
2. Write any data to any FLASH location within the address range of
the block to be erased.
3. Wait for a time, tnvs (10µs).
4. Set the HVEN bit.
FLASH Memory (FLASH)
Technical Data MC68H(R)C908JL3Rev. 1.1
42 FLASH Memory (FLASH) Freescale Semiconductor
5. Wait for a time tERASE (1ms).
6. Clear the ERASE bit.
7. Wait for a time, tnvh (5µs).
8. Clear the HVEN bit.
9. After time, trcv (1µs), the memory can be accessed in read mode
again.
NOTE: Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
4.6 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory:
1. Set both the ERASE bit and the MASS bit in the FLASH Control
Register.
2. Write any data to any FLASH location within the FLASH memory
address range.
3. Wait for a time, tnvs (10µs).
4. Set the HVEN bit.
5. Wait for a time tERASE (4ms).
6. Clear the ERASE bit.
7. Wait for a time, tnvh1 (100µs).
8. Clear the HVEN bit.
9. After time, trcv (1µs), the memory can be accessed in read mode
again.
NOTE: Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
FLASH Memory (FLASH)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor FLASH Memory (FLASH) 43
4.7 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row
consists of 32 consecutive bytes starting from addresses $XX00,
$XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0 or $XXE0. Use this
step-by-step procedure to program a row of FLASH memory:
(Figure 4-2 shows a flowchart of the programming algorithm.)
NOTE: In order to avoid program disturbs, the row must be erased before any
byte on that row is programmed.
1.
Set the PGM bit. This configures the memory for program
operation and enables the latching of address and data for
programming.
2. Write any data to any FLASH location within the address range of
the row to be programmed.
3. Wait for a time, tnvs (10µs).
4. Set the HVEN bit.
5. Wait for a time, tpgs (5µs).
6. Write data to the byte being programmed.
7. Wait for time, tPROG (30µs).
8. Repeat step 6 and 7 until all the bytes within the row are
programmed.
9. Clear the PGM bit.
10. Wait for time, tnvh (5µs).
11. Clear the HVEN bit.
12. After time, trcv (1µs), the memory can be accessed in read mode
again.
This program sequence is repeated throughout the memory until all data
is programmed.
FLASH Memory (FLASH)
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44 FLASH Memory (FLASH) Freescale Semiconductor
NOTE: The time between each FLASH address change (step 6 to step 6), or the
time between the last FLASH addressed programmed to clearing the
PGM bit (step 6 to step 10), must not exceed the maximum programming
time, tPROG max.
NOTE: Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps.
4.8 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made to protect
blocks of memory from unintentional erase or program operations due to
system malfunction. This protection is done by use of a FLASH Block
Protect Register (FLBPR). The FLBPR determines the range of the
FLASH memory which is to be protected. The range of the protected
area starts from a location defined by FLBPR and ends to the bottom of
the FLASH memory ($FFFF). When the memory is protected, the HVEN
bit cannot be set in either ERASE or PROGRAM operations.
Camp‘s-led programmmg thxs vow?
FLASH Memory (FLASH)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor FLASH Memory (FLASH) 45
Figure 4-2. FLASH Programming Flowchart
Set HVEN bit
Write any data to any FLASH address
within the row address range desired
Wait for a time, tnvs
Set PGM bit
Wait for a time, tpgs
Write data to the FLASH address
to be programmed
Wait for a time, tPROG
Clear PGM bit
Wait for a time, tnvh
Clear HVEN bit
Wait for a time, trcv
Completed
programming
this row?
Y
N
End of Programming
The time between each FLASH address change (step 6 to step 6), or
must not exceed the maximum programming
time, tPROG max.
the time between the last FLASH address programmed
to clearing PGM bit (step 6 to step 9)
NOTE:
1
2
3
4
5
6
7
9
10
11
12
Algorithm for programming
a row (32 bytes) of FLASH memory
This row program algorithm assumes the row/s
to be programmed are initially erased.
FLASH Memory (FLASH)
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4.9 FLASH Block Protect Register
The FLASH Block Protect Register is implemented as an 8-bit I/O
register. The value in this register determines the starting address of the
protected range within the FLASH memory.
BPR[7:1], bit-0 — FLASH Protection Register Bits [7:1]
These eight bits in FLBPR (bit-0 is always 0) represent bits [12:5] of
a 16-bit memory address. Bits [15:13] are logic 1s and bits [4:0] are
logic 0s.
The resultant 16-bit address is used for specifying the start address
of the FLASH memory for block protection. The FLASH is protected
from this start address to the end of FLASH memory, at $FFFF. With
this mechanism, the protect start address can be XX00, XX40, XX80,
or XXC0 within the FLASH memory.
Examples of protect start address:
Address: $FE09
Bit 7654321Bit 0
Read:
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1
0
Write:
Reset:00000000
Figure 4-3. FLASH Block Protect Register (FLBPR)
BPR[7:0] Start of Address of Protect Range
$00–$60 The entire FLASH memory is protected.
$62 (0110 0010) $EC40 (1110 1100 0100 0000)
$64 (0110 0100) $EC80 (1110 1100 1000 0000)
$68 (0110 1000) $ED00 (1110 1101 0000 0000)
and so on...
$DE (1101 1110)$FBC0 (1111 1011 1100 0000)
$FE (1111 1110) $FFC0 (1111 1111 1100 0000)
$FF The entire FLASH memory is not protected.
FLASH Memory (FLASH)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor FLASH Memory (FLASH) 47
FLASH Memory (FLASH)
Technical Data MC68H(R)C908JL3Rev. 1.1
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MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor Configuration Register (CONFIG) 47
Technical Data — MC68H(R)C908JL3
Section 5. Configuration Register (CONFIG)
5.1 Contents
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
5.2 Introduction
This section describes the configuration registers (CONFIG1 and
CONFIG2). The configuration registers enables or disables the following
options:
Stop mode recovery time (32 × 2OSCOUT cycles or
4096 × 2OSCOUT cycles)
STOP instruction
Computer operating properly module (COP)
COP reset period (COPRS), (213–24) × 2OSCOUT or
(218–24) × 2OSCOUT
Enable LVI circuit
Select LVI trip voltage
Configuration Register (CONFIG)
Technical Data MC68H(R)C908JL3Rev. 1.1
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5.3 Functional Description
The configuration register is used in the initialization of various options.
The configuration register can be written once after each reset. All of the
configuration register bits are cleared during reset. Since the various
options affect the operation of the MCU it is recommended that this
register be written immediately after reset. The configuration register is
located at $001E and $001F, and may be read at anytim
e.
NOTE: The CONFIG registers are one-time writable by the user after each
reset. Upon a reset, the CONFIG registers default to predetermined
settings as shown in Figure 5-1 and Figure 5-2.
IRQPUD — IRQ1 Pin Pull-up control bit
1 = Internal Pull-up is disconnected
0 = Internal Pull-up is connected between IRQ1 pin and VDD
LVIT1, LVIT0 — Low Voltage Inhibit trip voltage selection bits
Detail description of the LVI control signals is given in Section 16.
Address: $001E
Bit 7654321Bit 0
Read:
IRQPUD R R LVIT1 LVIT0 R R R
Write:
Reset:000
Not affected Not affected 000
POR:00000000
R=Reserved
Figure 5-1. Configuration Register 2 (CONFIG2)
Configuration Register (CONFIG)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor Configuration Register (CONFIG) 49
COPRS —þCOP reset period selection bit
1 = COP reset cycle = (2
13
– 2
4
)
×
2OSCOUT
0 = COP reset cycle = (2
18
– 2
4
)
×
2OSCOUT
LVID —þLow Voltage Inhibit Disable Bit
1 = Low Voltage Inhibit disabled
0 = Low Voltage Inhibit enabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of
32 × OSCXCLK cycles instead of a 4096 × 2OSCOUT cycle delay.
1 = Stop mode recovery after 32 × 2OSCOUT cycles
0 = Stop mode recovery after 4096 × 2OSCOUT cycles
NOTE: Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal, do not set the SSREC bit.
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Section 15. Computer
Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
Address: $001F
Bit 7654321Bit 0
Read:
COPRS R R LVID R SSREC STOP COPD
Write:
Reset:00000000
R=Reserved
Figure 5-2. Configuration Register 1 (CONFIG1)
Configuration Register (CONFIG)
Technical Data MC68H(R)C908JL3Rev. 1.1
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MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor Central Processor Unit (CPU) 51
Technical Data — MC68H(R)C908JL3
Section 6. Central Processor Unit (CPU)
6.1 Contents
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .55
6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .58
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.9 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.2 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully
object-code-compatible version of the M68HC05 CPU. The CPU08
Reference Manual (Freescale document order number CPU08RM/AD)
contains a description of the CPU instruction set, addressing modes,
and architecture.
Central Processor Unit (CPU)
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6.3 Features
Object code fully upward-compatible with M68HC05 Family
16-bit stack pointer with stack manipulation instructions
16-bit index register with x-register manipulation instructions
8-MHz CPU internal bus frequency
64-Kbyte program/data memory space
16 addressing modes
Memory-to-memory data moves without using accumulator
Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
Enhanced binary-coded decimal (BCD) data handling
Modular architecture with expandable internal bus definition for
extension of addressing range beyond 64 Kbytes
Low-power stop and wait modes
6.4 CPU Registers
Figure 6-1 shows the five CPU registers. CPU registers are not part of
the memory map.
géééa
Central Processor Unit (CPU)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor Central Processor Unit (CPU) 53
Figure 6-1. CPU Registers
6.4.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
ACCUMULATOR (A)
INDEX REGISTER (H:X)
STACK POINTER (SP)
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
V11HINZC
H X
0
0
0
0
7
15
15
15
70
Bit 7654321Bit 0
Read:
Write:
Reset: Unaffected by reset
Figure 6-2. Accumulator (A)
Central Processor Unit (CPU)
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6.4.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte
memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
The index register can serve also as a temporary data storage location.
6.4.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
Bit
15 1413121110987654321
Bit
0
Read:
Write:
Reset:00000000XXXXXXXX
X = Indeterminate
Figure 6-3. Index Register (H:X)
Central Processor Unit (CPU)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor Central Processor Unit (CPU) 55
NOTE: The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct
address (page 0) space. For correct operation, the stack pointer must
point only to RAM locations.
6.4.4 Program Counter
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
6.4.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
Bit
15 1413121110987654321
Bit
0
Read:
Write:
Reset:0000000011111111
Figure 6-4. Stack Pointer (SP)
Bit
15 1413121110987654321
Bit
0
Read:
Write:
Reset: Loaded with Vector from $FFFE and $FFFF
Figure 6-5. Program Counter (PC)
Central Processor Unit (CPU)
Technical Data MC68H(R)C908JL3Rev. 1.1
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5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add-without-carry (ADD) or add-
with-carry (ADC) operation. The half-carry flag is required for binary-
coded decimal (BCD) arithmetic operations. The DAA instruction uses
the states of the H and C flags to determine the appropriate correction
factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
Bit 7654321Bit 0
Read:
V11HINZC
Write:
Reset:X11X1XXX
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)
Central Processor Unit (CPU)
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Freescale Semiconductor Central Processor Unit (CPU) 57
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE: To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can be cleared only by the clear
interrupt mask software instruction (CLI).
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting bit
7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
Central Processor Unit (CPU)
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C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
6.5 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the
instruction set.
Refer to the CPU08 Reference Manual (Freescale document order
number CPU08RM/AD) for a description of the instructions and
addressing modes and more detail about the architecture of the CPU.
6.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption
standby modes.
6.6.1 Wait Mode
The WAIT instruction:
Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
Central Processor Unit (CPU)
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Freescale Semiconductor Central Processor Unit (CPU) 59
6.6.2 Stop Mode
The STOP instruction:
Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
6.7 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break
interrupt by:
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD or with
$FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
6.8 Instruction Set Summary
6.9 Opcode Map
See Table 6-2.
Central Processor Unit (CPU)
Technical Data MC68H(R)C908JL3Rev. 1.1
60 Central Processor Unit (CPU) Freescale Semiconductor
Table 6-1. Instruction Set Summary
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
Add with Carry A (A) + (M) + (C) ↕↕↕↕↕
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A9
B9
C9
D9
E9
F9
9EE9
9ED9
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
Add without Carry A (A) + (M) ↕↕↕↕↕
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
AB
BB
CB
DB
EB
FB
9EEB
9EDB
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
AIS #opr Add Immediate Value (Signed) to SP SP (SP) + (16 « M) ––––––IMM A7 ii 2
AIX #opr Add Immediate Value (Signed) to H:X H:X (H:X) + (16 « M) ––––––IMM AF ii 2
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
Logical AND A (A) & (M) 0 ↕↕
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A4
B4
C4
D4
E4
F4
9EE4
9ED4
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
Arithmetic Shift Left
(Same as LSL) ––↕↕↕
DIR
INH
INH
IX1
IX
SP1
38
48
58
68
78
9E68
dd
ff
ff
4
1
1
4
3
5
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
Arithmetic Shift Right ––↕↕↕
DIR
INH
INH
IX1
IX
SP1
37
47
57
67
77
9E67
dd
ff
ff
4
1
1
4
3
5
BCC rel Branch if Carry Bit Clear PC (PC) + 2 + rel ? (C) = 0 REL 24 rr 3
BCLR n, opr Clear Bit n in M Mn 0 ––––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
C
b0
b7
0
b0
b7
C
Central Processor Unit (CPU)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor Central Processor Unit (CPU) 61
BCS rel Branch if Carry Bit Set (Same as BLO) PC (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3
BEQ rel Branch if Equal PC (PC) + 2 + rel ? (Z) = 1 ––––––REL 27 rr 3
BGE opr Branch if Greater Than or Equal To
(Signed Operands) PC (PC) + 2 + rel ? (N V) = 0 ––––––REL 90 rr 3
BGT opr Branch if Greater Than (Signed
Operands) PC (PC) + 2 + rel ? (Z) | (N V) =
0––––––REL 92 rr 3
BHCC rel Branch if Half Carry Bit Clear PC (PC) + 2 + rel ? (H) = 0 ––––––REL 28 rr 3
BHCS rel Branch if Half Carry Bit Set PC (PC) + 2 + rel ? (H) = 1 ––––––REL 29 rr 3
BHI rel Branch if Higher PC (PC) + 2 + rel ? (C) | (Z) = 0 REL 22 rr 3
BHS rel Branch if Higher or Same
(Same as BCC) PC (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3
BIH rel Branch if IRQ Pin High PC (PC) + 2 + rel ? IRQ = 1 ––––––REL 2F rr 3
BIL rel Branch if IRQ Pin Low PC (PC) + 2 + rel ? IRQ = 0 ––––––REL 2E rr 3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
Bit Test (A) & (M) 0 ↕↕
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A5
B5
C5
D5
E5
F5
9EE5
9ED5
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
BLE opr Branch if Less Than or Equal To
(Signed Operands) PC (PC) + 2 + rel ? (Z) | (N V) =
1––––––REL 93 rr 3
BLO rel Branch if Lower (Same as BCS) PC (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3
BLS rel Branch if Lower or Same PC (PC) + 2 + rel ? (C) | (Z) = 1 REL 23 rr 3
BLT opr Branch if Less Than (Signed Operands) PC (PC) + 2 + rel ? (N V) =1 ––––––REL 91 rr 3
BMC rel Branch if Interrupt Mask Clear PC (PC) + 2 + rel ? (I) = 0 ––––––REL 2C rr 3
BMI rel Branch if Minus PC (PC) + 2 + rel ? (N) = 1 ––––––REL 2B rr 3
BMS rel Branch if Interrupt Mask Set PC (PC) + 2 + rel ? (I) = 1 ––––––REL 2D rr 3
BNE rel Branch if Not Equal PC (PC) + 2 + rel ? (Z) = 0 ––––––REL 26 rr 3
BPL rel Branch if Plus PC (PC) + 2 + rel ? (N) = 0 ––––––REL 2A rr 3
BRA rel Branch Always PC (PC) + 2 + rel ––––––REL 20 rr 3
Table 6-1. Instruction Set Summary
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
Central Processor Unit (CPU)
Technical Data MC68H(R)C908JL3Rev. 1.1
62 Central Processor Unit (CPU) Freescale Semiconductor
BRCLR n,opr,rel Branch if Bit n in M Clear PC (PC) + 3 + rel ? (Mn) = 0 –––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BRN rel Branch Never PC (PC) + 2 ––––––REL 21 rr 3
BRSET n,opr,rel Branch if Bit n in M Set PC (PC) + 3 + rel ? (Mn) = 1 –––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BSET n,opr Set Bit n in M Mn 1 ––––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BSR rel Branch to Subroutine
PC (PC) + 2; push (PCL)
SP (SP) – 1; push (PCH)
SP (SP) – 1
PC (PC) + rel
––––––REL AD rr 4
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
Compare and Branch if Equal
PC (PC) + 3 + rel ? (A) – (M) = $00
PC (PC) + 3 + rel ? (A) – (M) = $00
PC (PC) + 3 + rel ? (X) – (M) = $00
PC (PC) + 3 + rel ? (A) – (M) = $00
PC (PC) + 2 + rel ? (A) – (M) = $00
PC (PC) + 4 + rel ? (A) – (M) = $00
––––––
DIR
IMM
IMM
IX1+
IX+
SP1
31
41
51
61
71
9E61
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
4
6
CLC Clear Carry Bit C 0 –––––0INH 98 1
CLI Clear Interrupt Mask I 0 ––0–––INH 9A 2
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
Clear
M $00
A $00
X $00
H $00
M $00
M $00
M $00
0––01–
DIR
INH
INH
INH
IX1
IX
SP1
3F
4F
5F
8C
6F
7F
9E6F
dd
ff
ff
3
1
1
1
3
2
4
Table 6-1. Instruction Set Summary
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
Central Processor Unit (CPU)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor Central Processor Unit (CPU) 63
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
Compare A with M (A) – (M) ––↕↕↕
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A1
B1
C1
D1
E1
F1
9EE1
9ED1
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
Complement (One’s Complement)
M (M) = $FF – (M)
A (A) = $FF – (M)
X (X) = $FF – (M)
M (M) = $FF – (M)
M (M) = $FF – (M)
M (M) = $FF – (M)
0––↕↕1
DIR
INH
INH
IX1
IX
SP1
33
43
53
63
73
9E63
dd
ff
ff
4
1
1
4
3
5
CPHX #opr
CPHX opr Compare H:X with M (H:X) – (M:M + 1) ––↕↕↕IMM
DIR 65
75 ii ii+1
dd 3
4
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
Compare X with M (X) – (M) ––↕↕↕
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A3
B3
C3
D3
E3
F3
9EE3
9ED3
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
DAA Decimal Adjust A (A)10 U–↕↕↕INH 72 2
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
Decrement and Branch if Not Zero
A (A) – 1 or M (M) – 1 or X (X) –
1
PC (PC) + 3 + rel ? (result) 0
PC (PC) + 2 + rel ? (result) 0
PC (PC) + 2 + rel ? (result) 0
PC (PC) + 3 + rel ? (result) 0
PC (PC) + 2 + rel ? (result) 0
PC (PC) + 4 + rel ? (result) 0
––––––
DIR
INH
INH
IX1
IX
SP1
3B
4B
5B
6B
7B
9E6B
dd rr
rr
rr
ff rr
rr
ff rr
5
3
3
5
4
6
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
Decrement
M (M) – 1
A (A) – 1
X (X) – 1
M (M) – 1
M (M) – 1
M (M) – 1
––↕↕
DIR
INH
INH
IX1
IX
SP1
3A
4A
5A
6A
7A
9E6A
dd
ff
ff
4
1
1
4
3
5
DIV Divide A (H:A)/(X)
H Remainder ––––↕↕INH 52 7
Table 6-1. Instruction Set Summary
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
Central Processor Unit (CPU)
Technical Data MC68H(R)C908JL3Rev. 1.1
64 Central Processor Unit (CPU) Freescale Semiconductor
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
Exclusive OR M with A A (A M) 0––↕↕
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A8
B8
C8
D8
E8
F8
9EE8
9ED8
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
Increment
M (M) + 1
A (A) + 1
X (X) + 1
M (M) + 1
M (M) + 1
M (M) + 1
––↕↕
DIR
INH
INH
IX1
IX
SP1
3C
4C
5C
6C
7C
9E6C
dd
ff
ff
4
1
1
4
3
5
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Jump PC Jump Address ––––––
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
dd
hh ll
ee ff
ff
2
3
4
3
2
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3)
Push (PCL); SP (SP) – 1
Push (PCH); SP (SP) – 1
PC Unconditional Address
––––––
DIR
EXT
IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
4
5
6
5
4
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
Load A from M A (M) 0––↕↕
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A6
B6
C6
D6
E6
F6
9EE6
9ED6
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
LDHX #opr
LDHX opr Load H:X from M H:X ← (M:M + 1)0––↕↕IMM
DIR 45
55 ii jj
dd 3
4
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
Load X from M X (M) 0––↕↕
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
AE
BE
CE
DE
EE
FE
9EEE
9EDE
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
Logical Shift Left
(Same as ASL) ––↕↕↕
DIR
INH
INH
IX1
IX
SP1
38
48
58
68
78
9E68
dd
ff
ff
4
1
1
4
3
5
Table 6-1. Instruction Set Summary
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
C
b0
b7
0
Central Processor Unit (CPU)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor Central Processor Unit (CPU) 65
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
Logical Shift Right ––0↕↕
DIR
INH
INH
IX1
IX
SP1
34
44
54
64
74
9E64
dd
ff
ff
4
1
1
4
3
5
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
Move (M)Destination (M)Source
H:X (H:X) + 1 (IX+D, DIX+) 0––↕↕
DD
DIX+
IMD
IX+D
4E
5E
6E
7E
dd dd
dd
ii dd
dd
5
4
4
4
MUL Unsigned multiply X:A (X) × (A) –0–––0INH 42 5
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
Negate (Two’s Complement)
M –(M) = $00 – (M)
A –(A) = $00 – (A)
X –(X) = $00 – (X)
M –(M) = $00 – (M)
M –(M) = $00 – (M)
––↕↕↕
DIR
INH
INH
IX1
IX
SP1
30
40
50
60
70
9E60
dd
ff
ff
4
1
1
4
3
5
NOP No Operation None INH 9D 1
NSA Nibble Swap A A (A[3:0]:A[7:4]) INH 62 3
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
Inclusive OR A and M A (A) | (M) 0 ↕↕
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
AA
BA
CA
DA
EA
FA
9EEA
9EDA
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
PSHA Push A onto Stack Push (A); SP (SP) 1 ––––––INH 87 2
PSHH Push H onto Stack Push (H); SP (SP) 1 ––––––INH 8B 2
PSHX Push X onto Stack Push (X); SP (SP) 1 ––––––INH 89 2
PULA Pull A from Stack SP (SP + 1); Pull (A)––––––INH 86 2
PULH Pull H from Stack SP (SP + 1); Pull (H)––––––INH 8A 2
PULX Pull X from Stack SP (SP + 1); Pull (X)––––––INH 88 2
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
Rotate Left through Carry ––↕↕↕
DIR
INH
INH
IX1
IX
SP1
39
49
59
69
79
9E69
dd
ff
ff
4
1
1
4
3
5
Table 6-1. Instruction Set Summary
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
b0
b7
C0
C
b0
b7
Central Processor Unit (CPU)
Technical Data MC68H(R)C908JL3Rev. 1.1
66 Central Processor Unit (CPU) Freescale Semiconductor
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
Rotate Right through Carry ––↕↕↕
DIR
INH
INH
IX1
IX
SP1
36
46
56
66
76
9E66
dd
ff
ff
4
1
1
4
3
5
RSP Reset Stack Pointer SP $FF ––––––INH 9C 1
RTI Return from Interrupt
SP (SP) + 1; Pull (CCR)
SP (SP) + 1; Pull (A)
SP (SP) + 1; Pull (X)
SP (SP) + 1; Pull (PCH)
SP (SP) + 1; Pull (PCL)
↕↕↕↕↕↕INH 80 7
RTS Return from Subroutine SP SP + 1; Pull (PCH)
SP SP + 1; Pull (PCL) ––––––INH 81 4
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
Subtract with Carry A (A) – (M) – (C) ––↕↕↕
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A2
B2
C2
D2
E2
F2
9EE2
9ED2
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
SEC Set Carry Bit C 1 –––––1INH 99 1
SEI Set Interrupt Mask I 1 ––1–––INH 9B 2
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M M (A) 0––↕↕
DIR
EXT
IX2
IX1
IX
SP1
SP2
B7
C7
D7
E7
F7
9EE7
9ED7
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
STHX opr Store H:X in M (M:M + 1) (H:X) 0 ↕↕– DIR 35 dd 4
STOP Enable IRQ Pin; Stop Oscillator I 0; Stop Oscillator 0 INH 8E 1
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
Store X in M M (X) 0––↕↕
DIR
EXT
IX2
IX1
IX
SP1
SP2
BF
CF
DF
EF
FF
9EEF
9EDF
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
Table 6-1. Instruction Set Summary
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
b0
b7
C
Central Processor Unit (CPU)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor Central Processor Unit (CPU) 67
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
Subtract A (A) – (M) ––↕↕↕
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A0
B0
C0
D0
E0
F0
9EE0
9ED0
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
SWI Software Interrupt
PC (PC) + 1; Push (PCL)
SP (SP) – 1; Push (PCH)
SP (SP) – 1; Push (X)
SP (SP) – 1; Push (A)
SP (SP) – 1; Push (CCR)
SP (SP) – 1; I 1
PCH Interrupt Vector High Byte
PCL Interrupt Vector Low Byte
––1–––INH 83 9
TAP Transfer A to CCR CCR (A) ↕↕↕↕↕↕INH 84 2
TAX Transfer A to X X (A) ––––––INH 97 1
TPA Transfer CCR to A A (CCR) INH 85 1
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 0 ↕↕
DIR
INH
INH
IX1
IX
SP1
3D
4D
5D
6D
7D
9E6D
dd
ff
ff
3
1
1
3
2
4
TSX Transfer SP to H:X H:X (SP) + 1 ––––––INH 95 2
TXA Transfer X to A A (X) ––––––INH 9F 1
TXS Transfer H:X to SP (SP) (H:X) 1 ––––––INH 94 2
Table 6-1. Instruction Set Summary
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
Central Processor Unit (CPU)
Technical Data MC68H(R)C908JL3Rev. 1.1
68 Central Processor Unit (CPU) Freescale Semiconductor
A Accumulator nAny bit
C Carry/borrow bit opr Operand (one or two bytes)
CCR Condition code register PC Program counter
dd Direct address of operand PCH Program counter high byte
dd rr Direct address of operand and relative offset of branch instruction PCL Program counter low byte
DD Direct to direct addressing mode REL Relative addressing mode
DIR Direct addressing mode rel Relative program counter offset byte
DIX+ Direct to indexed with post increment addressing mode rr Relative program counter offset byte
ee ff High and low bytes of offset in indexed, 16-bit offset addressing SP1 Stack pointer, 8-bit offset addressing mode
EXT Extended addressing mode SP2 Stack pointer 16-bit offset addressing mode
ff Offset byte in indexed, 8-bit offset addressing SP Stack pointer
H Half-carry bit U Undefined
H Index register high byte V Overflow bit
hh ll High and low bytes of operand address in extended addressing X Index register low byte
I Interrupt mask Z Zero bit
ii Immediate operand byte & Logical AND
IMD Immediate source to direct destination addressing mode | Logical OR
IMM Immediate addressing mode Logical EXCLUSIVE OR
INH Inherent addressing mode ( ) Contents of
IX Indexed, no offset addressing mode –( ) Negation (two’s complement)
IX+ Indexed, no offset, post increment addressing mode # Immediate value
IX+D Indexed with post increment to direct addressing mode «Sign extend
IX1 Indexed, 8-bit offset addressing mode Loaded with
IX1+ Indexed, 8-bit offset, post increment addressing mode ? If
IX2 Indexed, 16-bit offset addressing mode : Concatenated with
M Memory location Set or cleared
N Negative bit Not affected
Table 6-1. Instruction Set Summary
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
MSE LSE MSE LEE
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor Central Processor Unit (CPU) 69
Central Processor Unit (CPU)
Table 6-2. Opcode Map
Bit Manipulation Branch Read-Modify-Write Control Register/Memory
DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR EXT IX2 SP2 IX1 SP1 IX
01234569E6789ABCD9EDE9EEF
05
BRSET0
3DIR
4
BSET0
2DIR
3
BRA
2REL
4
NEG
2DIR
1
NEGA
1INH
1
NEGX
1INH
4
NEG
2IX1
5
NEG
3SP1
3
NEG
1IX
7
RTI
1INH
3
BGE
2REL
2
SUB
2IMM
3
SUB
2DIR
4
SUB
3EXT
4
SUB
3IX2
5
SUB
4SP2
3
SUB
2IX1
4
SUB
3SP1
2
SUB
1IX
15
BRCLR0
3DIR
4
BCLR0
2DIR
3
BRN
2REL
5
CBEQ
3DIR
4
CBEQA
3IMM
4
CBEQX
3IMM
5
CBEQ
3IX1+
6
CBEQ
4SP1
4
CBEQ
2IX+
4
RTS
1INH
3
BLT
2REL
2
CMP
2IMM
3
CMP
2DIR
4
CMP
3EXT
4
CMP
3IX2
5
CMP
4SP2
3
CMP
2IX1
4
CMP
3SP1
2
CMP
1IX
25
BRSET1
3DIR
4
BSET1
2DIR
3
BHI
2REL
5
MUL
1INH
7
DIV
1INH
3
NSA
1INH
2
DAA
1INH
3
BGT
2REL
2
SBC
2IMM
3
SBC
2DIR
4
SBC
3EXT
4
SBC
3IX2
5
SBC
4SP2
3
SBC
2IX1
4
SBC
3SP1
2
SBC
1IX
35
BRCLR1
3DIR
4
BCLR1
2DIR
3
BLS
2REL
4
COM
2DIR
1
COMA
1INH
1
COMX
1INH
4
COM
2IX1
5
COM
3SP1
3
COM
1IX
9
SWI
1INH
3
BLE
2REL
2
CPX
2IMM
3
CPX
2DIR
4
CPX
3EXT
4
CPX
3IX2
5
CPX
4SP2
3
CPX
2IX1
4
CPX
3SP1
2
CPX
1IX
45
BRSET2
3DIR
4
BSET2
2DIR
3
BCC
2REL
4
LSR
2DIR
1
LSRA
1INH
1
LSRX
1INH
4
LSR
2IX1
5
LSR
3SP1
3
LSR
1IX
2
TAP
1INH
2
TXS
1INH
2
AND
2IMM
3
AND
2DIR
4
AND
3EXT
4
AND
3IX2
5
AND
4SP2
3
AND
2IX1
4
AND
3SP1
2
AND
1IX
55
BRCLR2
3DIR
4
BCLR2
2DIR
3
BCS
2REL
4
STHX
2DIR
3
LDHX
3IMM
4
LDHX
2DIR
3
CPHX
3IMM
4
CPHX
2DIR
1
TPA
1INH
2
TSX
1INH
2
BIT
2IMM
3
BIT
2DIR
4
BIT
3EXT
4
BIT
3IX2
5
BIT
4SP2
3
BIT
2IX1
4
BIT
3SP1
2
BIT
1IX
65
BRSET3
3DIR
4
BSET3
2DIR
3
BNE
2REL
4
ROR
2DIR
1
RORA
1INH
1
RORX
1INH
4
ROR
2IX1
5
ROR
3SP1
3
ROR
1IX
2
PULA
1INH
2
LDA
2IMM
3
LDA
2DIR
4
LDA
3EXT
4
LDA
3IX2
5
LDA
4SP2
3
LDA
2IX1
4
LDA
3SP1
2
LDA
1IX
75
BRCLR3
3DIR
4
BCLR3
2DIR
3
BEQ
2REL
4
ASR
2DIR
1
ASRA
1INH
1
ASRX
1INH
4
ASR
2IX1
5
ASR
3SP1
3
ASR
1IX
2
PSHA
1INH
1
TAX
1INH
2
AIS
2IMM
3
STA
2DIR
4
STA
3EXT
4
STA
3IX2
5
STA
4SP2
3
STA
2IX1
4
STA
3SP1
2
STA
1IX
85
BRSET4
3DIR
4
BSET4
2DIR
3
BHCC
2REL
4
LSL
2DIR
1
LSLA
1INH
1
LSLX
1INH
4
LSL
2IX1
5
LSL
3SP1
3
LSL
1IX
2
PULX
1INH
1
CLC
1INH
2
EOR
2IMM
3
EOR
2DIR
4
EOR
3EXT
4
EOR
3IX2
5
EOR
4SP2
3
EOR
2IX1
4
EOR
3SP1
2
EOR
1IX
95
BRCLR4
3DIR
4
BCLR4
2DIR
3
BHCS
2REL
4
ROL
2DIR
1
ROLA
1INH
1
ROLX
1INH
4
ROL
2IX1
5
ROL
3SP1
3
ROL
1IX
2
PSHX
1INH
1
SEC
1INH
2
ADC
2IMM
3
ADC
2DIR
4
ADC
3EXT
4
ADC
3IX2
5
ADC
4SP2
3
ADC
2IX1
4
ADC
3SP1
2
ADC
1IX
A5
BRSET5
3DIR
4
BSET5
2DIR
3
BPL
2REL
4
DEC
2DIR
1
DECA
1INH
1
DECX
1INH
4
DEC
2IX1
5
DEC
3SP1
3
DEC
1IX
2
PULH
1INH
2
CLI
1INH
2
ORA
2IMM
3
ORA
2DIR
4
ORA
3EXT
4
ORA
3IX2
5
ORA
4SP2
3
ORA
2IX1
4
ORA
3SP1
2
ORA
1IX
B5
BRCLR5
3DIR
4
BCLR5
2DIR
3
BMI
2REL
5
DBNZ
3DIR
3
DBNZA
2INH
3
DBNZX
2INH
5
DBNZ
3IX1
6
DBNZ
4SP1
4
DBNZ
2IX
2
PSHH
1INH
2
SEI
1INH
2
ADD
2IMM
3
ADD
2DIR
4
ADD
3EXT
4
ADD
3IX2
5
ADD
4SP2
3
ADD
2IX1
4
ADD
3SP1
2
ADD
1IX
C5
BRSET6
3DIR
4
BSET6
2DIR
3
BMC
2REL
4
INC
2DIR
1
INCA
1INH
1
INCX
1INH
4
INC
2IX1
5
INC
3SP1
3
INC
1IX
1
CLRH
1INH
1
RSP
1INH
2
JMP
2DIR
3
JMP
3EXT
4
JMP
3IX2
3
JMP
2IX1
2
JMP
1IX
D5
BRCLR6
3DIR
4
BCLR6
2DIR
3
BMS
2REL
3
TST
2DIR
1
TSTA
1INH
1
TSTX
1INH
3
TST
2IX1
4
TST
3SP1
2
TST
1IX
1
NOP
1INH
4
BSR
2REL
4
JSR
2DIR
5
JSR
3EXT
6
JSR
3IX2
5
JSR
2IX1
4
JSR
1IX
E5
BRSET7
3DIR
4
BSET7
2DIR
3
BIL
2REL
5
MOV
3DD
4
MOV
2DIX+
4
MOV
3IMD
4
MOV
2IX+D
1
STOP
1INH *2
LDX
2IMM
3
LDX
2DIR
4
LDX
3EXT
4
LDX
3IX2
5
LDX
4SP2
3
LDX
2IX1
4
LDX
3SP1
2
LDX
1IX
F5
BRCLR7
3DIR
4
BCLR7
2DIR
3
BIH
2REL
3
CLR
2DIR
1
CLRA
1INH
1
CLRX
1INH
3
CLR
2IX1
4
CLR
3SP1
2
CLR
1IX
1
WAIT
1INH
1
TXA
1INH
2
AIX
2IMM
3
STX
2DIR
4
STX
3EXT
4
STX
3IX2
5
STX
4SP2
3
STX
2IX1
4
STX
3SP1
2
STX
1IX
INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset
IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset
DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with
EXT Extended IX2 Indexed, 16-Bit Offset Post Increment
DD Direct-Direct IMD Immediate-Direct IX1+ Indexed, 1-Byte Offset with
IX+D Indexed-Direct DIX+ Direct-Indexed Post Increment
*Pre-byte for stack pointer indexed instructions
0 High Byte of Opcode in Hexadecimal
Low Byte of Opcode in Hexadecimal 0 5
BRSET0
3DIR
Cycles
Opcode Mnemonic
Number of Bytes / Addressing Mode
MSB
LSB
MSB
LSB
Central Processor Unit (CPU)
Technical Data MC68H(R)C908JL3Rev. 1.1
70 Central Processor Unit (CPU) Freescale Semiconductor
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor System Integration Module (SIM) 71
Technical Data — MC68H(R)C908JL3
Section 7. System Integration Module (SIM)
7.1 Contents
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
7.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . .75
7.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
7.3.2 Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . .75
7.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . .75
7.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . .76
7.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
7.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . .77
7.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
7.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . .79
7.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
7.4.2.4 Illegal Address Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .79
7.4.2.5 LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
7.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
7.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . .80
7.5.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . .80
7.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . .81
7.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
7.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
7.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
7.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
7.6.2 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .85
7.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . .86
7.6.2.2 Interrupt Status Register 2. . . . . . . . . . . . . . . . . . . . . . . .86
7.6.2.3 Interrupt Status Register 3. . . . . . . . . . . . . . . . . . . . . . . .87
7.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
7.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
7.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . .87
System Integration Module (SIM)
Technical Data MC68H(R)C908JL3Rev. 1.1
72 System Integration Module (SIM) Freescale Semiconductor
7.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
7.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
7.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
7.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
7.8.1 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . .91
7.8.2 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . .92
7.8.3 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . .94
7.2 Introduction
This section describes the system integration module (SIM), which
supports up to 24 external and/or internal interrupts. Together with the
CPU, the SIM controls all MCU activities. A block diagram of the SIM is
shown in Figure 7-1. Figure 7-2 is a summary of the SIM I/O registers.
The SIM is a system state controller that coordinates CPU and exception
timing. The SIM is responsible for:
Bus clock generation and control for CPU and peripherals
– Stop/wait/reset/break entry and recovery
Internal clock control
Master reset control, including power-on reset (POR) and COP
timeout
Interrupt control:
Acknowledge timing
Arbitration control timing
Vector address generation
CPU enable/disable timing
Modular architecture expandable to 128 interrupt sources
HE ET PW LOG‘C SW! COUNTER
System Integration Module (SIM)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor System Integration Module (SIM) 73
Figure 7-1. SIM Block Diagram
Table 7-1. Signal Name Conventions
Signal Name Description
2OSCOUT Buffered clock from the X-tal oscillator circuit or the RC oscillator circuit.
OSCOUT The 2OSCOUT frequency divided by two. This signal is again divided by two in the
SIM to generate the internal bus clocks. (Bus clock = 2OSCOUT ÷ 4)
IAB Internal address bus
IDB Internal data bus
PORRST Signal from the power-on reset module to the SIM
IRST Internal reset signal
R/W Read/write signal
STOP/WAIT
CLOCK
CONTROL CLOCK GENERATORS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
INTERRUPT CONTROL
AND PRIORITY DECODE
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
OSCOUT (FROM OSCILLATOR)
INTERNAL CLOCKS
MASTER
RESET
CONTROL
RESET
PIN LOGIC
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
RESET
CONTROL
SIM
COUNTER COP CLOCK
2OSCOUT (FROM OSCILLATOR)
÷2
USB RESET (FROM USB MODULE)
VDD
INTERNAL
PULL-UP
System Integration Module (SIM)
Technical Data MC68H(R)C908JL3Rev. 1.1
74 System Integration Module (SIM) Freescale Semiconductor
Addr.Register Name Bit 7654321Bit 0
$FE00 Break Status Register
(BSR)
Read:
RRRRRR
SBSW
R
Write: NOTE
Reset:00000000
Note: Writing a logic 0 clears SBSW.
$FE01 Reset Status Register
(RSR)
Read: POR PIN COP ILOP ILAD MODRST LVI 0
Write:
POR:10000000
$FE02 Reserved
Read:
RRRRRRRR
Write:
Reset:
$FE03
Break Flag Control
Register
(BFCR)
Read:
BCFERRRRRRR
Write:
Reset: 0
$FE04 Interrupt Status Register 1
(INT1)
Read: 0 IF5 IF4 IF3 0 IF1 0 0
Write:RRRRRRRR
Reset:00000000
$FE05 Interrupt Status Register 2
(INT2)
Read: IF14 0000000
Write:RRRRRRRR
Reset:00000000
$FE06 Interrupt Status Register 3
(INT3)
Read: 0000000IF15
Write:RRRRRRRR
Reset:00000000
= Unimplemented R = Reserved
Figure 7-2. SIM I/O Register Summary
System Integration Module (SIM)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor System Integration Module (SIM) 75
7.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, OSCOUT, as shown in Figure 7-3.
Figure 7-3. SIM Clock Signals
7.3.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency
(2OSCOUT) divided by four.
7.3.2 Clock Start-Up from POR
When the power-on reset module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after
the 4096 2OSCOUT cycle POR time-out has completed. The RST pin is
driven low by the SIM during this entire period. The IBUS clocks start
upon completion of the time-out.
7.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
2OSCOUT to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay time-out. This time-out is
selectable as 4096 or 32 2OSCOUT cycles. (See 7.7.2 Stop Mode.)
÷ 2BUS CLOCK
GENERATORS
SIM
SIM COUNTER
From
OSCILLATOR
From
OSCILLATOR OSCOUT
2OSCOUT
System Integration Module (SIM)
Technical Data MC68H(R)C908JL3Rev. 1.1
76 System Integration Module (SIM) Freescale Semiconductor
In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
7.4 Reset and System Initialization
The MCU has these reset sources:
Power-on reset module (POR)
External reset pin (RST)
Computer operating properly module (COP)
Low-voltage inhibit module (LVI)
Illegal opcode
Illegal address
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in
Monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
An internal reset clears the SIM counter (see 7.5 SIM Counter), but an
external reset does not. Each of the resets sets a corresponding bit in
the reset status register (RSR). (See 7.8 SIM Registers.)
7.4.1 External Pin Reset
The RST pin circuits include an internal pull-up device. Pulling the
asynchronous RST pin low halts all processing. The PIN bit of the reset
status register (RSR) is set as long as RST is held low for a minimum of
67 2OSCCLK cycles, assuming that the POR was not the source of the
reset. See Table 7-2 for details. Figure 7-4 shows the relative timing.
Table 7-2. PIN Bit Set Timing
Reset Type Number of Cycles Required to Set PIN
POR 4163 (4096 + 64 + 3)
All others 67 (64 + 3)
WW \_I -VIIOIOIOIO'IIOIOIOIO'IIOIOW010101031010101031010103310101033101.1031(01010101010101.1010---- 4MP 32 CYCLES—b‘ H7 WI—ng—‘MWI—W[ "0'(OIOIOIt{(01010It{(01010It{(01010It{(01010It{(01010It{(01010It{(01010It{(01010IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO— m
System Integration Module (SIM)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor System Integration Module (SIM) 77
Figure 7-4. External Reset Timing
7.4.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 2OSCOUT
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles (Figure 7-5).
An internal reset can be caused by an illegal address, illegal opcode,
COP time-out, or POR. (See Figure 7-6 . Sources of Internal Reset.)
Note that for POR resets, the SIM cycles through 4096 2OSCOUT
cycles during which the SIM forces the RST pin low. The internal reset
signal then follows the sequence from the falling edge of RST shown in
Figure 7-5.
Figure 7-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
Figure 7-6. Sources of Internal Reset
RST
IAB PC VECT H VECT L
OSCOUT
IRST
RST RST PULLED LOW BY MCU
IAB
32 CYCLES 32 CYCLES
VECTOR HIGH
2OSCOUT
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
LVI
INTERNAL RESET
J ‘ CVCLES ‘ mmm‘mm 4 L4 L4 L; M u u u X X
System Integration Module (SIM)
Technical Data MC68H(R)C908JL3Rev. 1.1
78 System Integration Module (SIM) Freescale Semiconductor
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
7.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 2OSCOUT cycles. Sixty-four 2OSCOUT cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to
occur.
At power-on, the following events occur:
A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables the oscillator to drive 2OSCOUT.
Internal clocks to the CPU and modules are held inactive for 4096
2OSCOUT cycles to allow stabilization of the oscillator.
The RST pin is driven low during the oscillator stabilization time.
The POR bit of the reset status register (RSR) is set and all other
bits in the register are cleared.
Figure 7-7. POR Recovery
PORRST
OSC1
2OSCOUT
OSCOUT
RST
IAB
4096
CYCLES 32
CYCLES 32
CYCLES
$FFFE $FFFF
System Integration Module (SIM)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor System Integration Module (SIM) 79
7.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
reset status register (RSR). The SIM actively pulls down the RST pin for
all internal reset sources.
To prevent a COP module time-out, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and stages 12 through
5 of the SIM counter. The SIM counter output, which occurs at least
every (212 – 24) 2OSCOUT cycles, drives the COP counter. The COP
should be serviced as soon as possible out of reset to guarantee the
maximum amount of time before the first time-out.
The COP module is disabled if the RST pin or the IRQ1 pin is held at
VDD +V
HI while the MCU is in monitor mode. The COP module can be
disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ1 pin. This prevents the COP from
becoming disabled as a result of external noise. During a break state,
VDD +V
HI on the RST pin disables the COP module.
7.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the reset status register (RSR) and
causes a reset.
If the stop enable bit, STOP, in the mask option register is logic zero, the
SIM treats the STOP instruction as an illegal opcode and causes an
illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
7.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the reset status register (RSR) and resetting
the MCU. A data fetch from an unmapped address does not generate a
reset. The SIM actively pulls down the RST pin for all internal reset
sources.
System Integration Module (SIM)
Technical Data MC68H(R)C908JL3Rev. 1.1
80 System Integration Module (SIM) Freescale Semiconductor
7.4.2.5 LVI Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the VDD voltage falls to the LVI trip voltage VTRIP. The LVI bit in the SIM
reset status register (SRSR) is set, and the external reset pin (RSTB) is
held low while the SIM counter counts out 4096 2OSCCLK cycles. Sixty-
four 2OSCOUT cycles later, the CPU and memories are released from
reset to allow the reset vector sequence to occur. The SIM actively pulls
down the (RSTB) pin for all internal reset sources.
7.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM
counter uses 12 stages for counting, followed by a 13th stage that
triggers a reset of SIM counters and supplies the clock for the COP
module. The SIM counter is clocked by the falling edge of 2OSCOUT.
7.5.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the oscillator to drive the bus clock state machine.
7.5.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a logic one, then the stop recovery is
reduced from the normal delay of 4096 2OSCOUT cycles down to 32
2OSCOUT cycles. This is ideal for applications using canned oscillators
that do not require long start-up times from stop mode. External crystal
applications should use the full stop recovery time, that is, with SSREC
cleared in the configuration register (CONFIG).
System Integration Module (SIM)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor System Integration Module (SIM) 81
7.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See 7.7.2 Stop Mode
for details.) The SIM counter is free-running after all reset states. (See
7.4.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.)
7.6 Exception Control
Normal, sequential program execution can be changed in three different
ways:
• Interrupts
Maskable hardware CPU interrupts
Non-maskable software interrupt instruction (SWI)
• Reset
Break interrupts
7.6.1 Interrupts
An interrupt temporarily changes the sequence of program execution to
respond to a particular event. Figure 7-8 flow charts the handling of
system interrupts.
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared).
NO NO NO NO YES NO
System Integration Module (SIM)
Technical Data MC68H(R)C908JL3Rev. 1.1
82 System Integration Module (SIM) Freescale Semiconductor
Figure 7-8. Interrupt Processing
NO
NO
NO
YES
NO
NO
YES
NO
YES
YES
(As many interrupts as exist on chip)
I BIT SET?
FROM RESET
BREAK INTERRUPT?
I BIT SET?
IRQ
INTERRUPT?
TIMER
INTERRUPT?
SWI
INSTRUCTION?
RTI
INSTRUCTION?
FETCH NEXT
INSTRUCTION
UNSTACK CPU REGISTERS.
STACK CPU REGISTERS.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
EXECUTE INSTRUCTION.
YES
YES
System Integration Module (SIM)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor System Integration Module (SIM) 83
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 7-9 shows interrupt entry timing. Figure
7-10 shows interrupt recovery timing.
Figure 7-9. Interrupt Entry
Figure 7-10. Interrupt Recovery
7.6.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of
a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
condition code register), and if the corresponding interrupt enable bit is
MODULE
IDB
R/W
INTERRUPT
DUMMY SP SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR
IAB
DUMMY PC – 1[7:0] PC – 1[15:8] X A CCR V DATA H V DATA L OPCODE
I BIT
MODULE
IDB
R/W
INTERRUPT
SP – 4 SP – 3 SP – 2 SP – 1 SP PC PC + 1
IAB
CCR A X PC – 1[7:0] PC – 1[15:8] OPCODE OPERAND
I BIT
System Integration Module (SIM)
Technical Data MC68H(R)C908JL3Rev. 1.1
84 System Integration Module (SIM) Freescale Semiconductor
set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first. Figure 7-11
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service routine,
the pending interrupt is serviced before the LDA instruction is executed.
Figure 7-11. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
NOTE: To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
CLI
LDA
INT1
PULH
RTI
INT2
BACKGROUND ROUTINE#$FF
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
PSHH
INT2 INTERRUPT SERVICE ROUTINE
System Integration Module (SIM)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor System Integration Module (SIM) 85
7.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
NOTE: A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
7.6.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt
sources. Table 7-3 summarizes the interrupt sources and the interrupt
status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 7-3. Interrupt Sources
Priority Source Flag Mask1INT
Register
Flag Vector Address
Highest Reset $FFFE–$FFFF
SWI Instruction $FFFC–$FFFD
IRQ1 Pin IRQF1 IMASK1 IF1 $FFFA–$FFFB
Timer Channel 0 Interrupt CH0F CH0IE IF3 $FFF6–$FFF7
Timer Channel 1 Interrupt CH1F CH1IE IF4 $FFF4–$FFF5
Timer Overflow Interrupt TOF TOIE IF5 $FFF2–$FFF3
Keyboard Interrupt KEYF IMASKK IF14 $FFE0–$FFE1
Lowest ADC Conversion Complete Interrupt COCO AIEN IF15 $FFDE–$FFDF
Note:
1. The I bit in the condition code register is a global mask for all interrupts sources except the SWI
instruction.
System Integration Module (SIM)
Technical Data MC68H(R)C908JL3Rev. 1.1
86 System Integration Module (SIM) Freescale Semiconductor
7.6.2.1 Interrupt Status Register 1
IF1, IF3 to IF5 — Interrupt Flags
These flags indicate the presence of interrupt requests from the
sources shown in Table 7-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0, 1, 3 and 7 — Always read 0
7.6.2.2 Interrupt Status Register 2
IF14 — Interrupt Flags
This flag indicates the presence of interrupt requests from the sources
shown in Table 7-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0 to 6 — Always read 0
Address: $FE04
Bit 7654321Bit 0
Read: 0 IF5 IF4 IF3 0 IF1 0 0
Write:RRRRRRRR
Reset:00000000
R= Reserved
Figure 7-12. Interrupt Status Register 1 (INT1)
Address: $FE05
Bit 7654321Bit 0
Read: IF14 0000000
Write:RRRRRRRR
Reset:00000000
R= Reserved
Figure 7-13. Interrupt Status Register 2 (INT2)
System Integration Module (SIM)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor System Integration Module (SIM) 87
7.6.2.3 Interrupt Status Register 3
IF15 — Interrupt Flags
These flags indicate the presence of interrupt requests from the
sources shown in Table 7-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 1 to 7 — Always read 0
7.6.3 Reset
All reset sources always have equal and highest priority and cannot be
arbitrated.
7.6.4 Break Interrupts
The break module can stop normal program flow at a software-
programmable break point by asserting its break interrupt output. (See
Section 17. Break Module (BREAK).) The SIM puts the CPU into the
break state by forcing it to the SWI vector location. Refer to the break
interrupt subsection of each module to see how each module is affected
by the break state.
7.6.5 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can
be cleared during break mode. The user can select whether flags are
Address: $FE06
Bit 7654321Bit 0
Read: 0000000IF15
Write:RRRRRRRR
Reset:00000000
R= Reserved
Figure 7-14. Interrupt Status Register 3 (INT3)
System Integration Module (SIM)
Technical Data MC68H(R)C908JL3Rev. 1.1
88 System Integration Module (SIM) Freescale Semiconductor
protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the break flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared
while in break mode. This protection allows registers to be freely read
and written during break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in
break mode, a flag remains cleared even when break mode is exited.
Status flags with a two-step clearing mechanism — for example, a read
of one register followed by the read or write of another — are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the flag
as normal.
7.7 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low-power-
consumption mode for standby situations. The SIM holds the CPU in a
non-clocked state. The operation of each of these modes is described
below. Both STOP and WAIT clear the interrupt mask (I) in the condition
code register, allowing interrupts to occur.
7.7.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks
continue to run. Figure 7-15 shows the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred. In
wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode. Some modules can be programmed to be active in wait
mode.
Wait mode can also be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the break
System Integration Module (SIM)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor System Integration Module (SIM) 89
status register (BSR). If the COP disable bit, COPD, in the mask option
register is logic zero, then the computer operating properly module
(COP) is enabled and remains active in wait mode.
Figure 7-15. Wait Mode Entry Timing
Figure 7-16 and Figure 7-17 show the timing for WAIT recovery.
Figure 7-16. Wait Recovery from Interrupt or Break
Figure 7-17. Wait Recovery from Internal Reset
WAIT ADDR + 1 SAME SAMEIAB
IDB PREVIOUS DATA NEXT OPCODE SAME
WAIT ADDR
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
$6E0C$6E0B $00FF $00FE $00FD $00FC
$A6 $A6 $01 $0B $6E$A6
IAB
IDB
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
IAB
IDB
RST
$A6 $A6
$6E0B RST VCT H RST VCT L
$A6
2OSCOUT
32
Cycles
32
Cycles
System Integration Module (SIM)
Technical Data MC68H(R)C908JL3Rev. 1.1
90 System Integration Module (SIM) Freescale Semiconductor
7.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (OSCOUT and 2OSCOUT) in
stop mode, stopping the CPU and peripherals. Stop recovery time is
selectable using the SSREC bit in the configuration register (CONFIG).
If SSREC is set, stop recovery is reduced from the normal delay of 4096
2OSCOUT cycles down to 32. This is ideal for applications using canned
oscillators that do not require long start-up times from stop mode.
NOTE: External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the break status register (BSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period. Figure 7-18 shows stop mode entry timing.
NOTE: To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
Figure 7-18. Stop Mode Entry Timing
STOP ADDR + 1 SAME SAMEIAB
IDB PREVIOUS DATA NEXT OPCODE SAME
STOP ADDR
SAME
R/W
CPUSTOP
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
System Integration Module (SIM)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor System Integration Module (SIM) 91
Figure 7-19. Stop Mode Recovery from Interrupt or Break
7.8 SIM Registers
The SIM has three memory mapped registers. Table 7-4 shows the
mapping of these registers.
7.8.1 Break Status Register (BSR)
The break status register contains a flag to indicate that a break caused
an exit from stop or wait mode.
2OSCOUT
INT/BREAK
IAB STOP + 2 STOP + 2 SP SP – 1 SP – 2 SP – 3
STOP +1
STOP RECOVERY PERIOD
Table 7-4. SIM Registers
Address Register Access Mode
$FE00 BSR User
$FE01 RSR User
$FE03 BFCR User
Address: $FE00
Bit 7654321Bit 0
Read:
RRRRRR
SBSW
R
Write: Note(1)
Reset: 0
R = Reserved 1. Writing a logic zero clears SBSW.
Figure 7-20. Break Status Register (BSR)
System Integration Module (SIM)
Technical Data MC68H(R)C908JL3Rev. 1.1
92 System Integration Module (SIM) Freescale Semiconductor
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic zero to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example of this. Writing zero to the SBSW bit clears
it.
7.8.2 Reset Status Register (RSR)
This register contains six flags that show the source of the last reset.
Clear the SIM reset status register by reading it. A power-on reset sets
the POR bit and clears all other bits in the register.
;
;
;
This code works if the H register has been pushed onto the stack in the break
service routine software. This code should be executed at the end of the
break service routine software.
HIBYTE EQU 5
LOBYTE EQU 6
; If not SBSW, do RTI
BRCLR SBSW,BSR, RETURN ;
;See if wait mode or stop mode was exited
by break.
TST LOBYTE,SP ; If RETURNLO is not zero,
BNE DOLO ; then just decrement low byte.
DEC HIBYTE,SP ; Else deal with high byte, too.
DOLO DEC LOBYTE,SP ; Point to WAIT/STOP opcode.
RETURN PULH
RTI ; Restore H register.
System Integration Module (SIM)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor System Integration Module (SIM) 93
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
MODRST — Monitor Mode Entry Module Reset bit
1 = Last reset caused by monitor mode entry when vector locations
$FFFE and $FFFF are $00 after POR while IRQB = VDD
0 = POR or read of SRSR
LVI — Low Voltage Inhibit Reset bit
1 = Last reset caused by LVI circuit
0 = POR or read of SRSR
Address: $FE01
Bit 7654321Bit 0
Read: POR PIN COP ILOP ILAD MODRST LVI 0
Write:
POR:10000000
= Unimplemented
Figure 7-21. Reset Status Register (RSR)
System Integration Module (SIM)
Technical Data MC68H(R)C908JL3Rev. 1.1
94 System Integration Module (SIM) Freescale Semiconductor
7.8.3 Break Flag Control Register (BFCR)
The break control register contains a bit that enables software to clear
status bits while the MCU is in a break state.
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
Address: $FE03
Bit 7654321Bit 0
Read:
BCFERRRRRRR
Write:
Reset: 0
R= Reserved
Figure 7-22. Break Flag Control Register (BFCR)
MC68H(R)C908JL3Rev. 1.1 Technical Data
Freescale Semiconductor Oscillator (OSC) 95
Technical Data — MC68H(R)C908JL3
Section 8. Oscillator (OSC)
8.1 Contents
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
8.3 X-tal Oscillator (MC68HC908xxx). . . . . . . . . . . . . . . . . . . . . . .96
8.4 RC Oscillator (MC68HRC908xxx) . . . . . . . . . . . . . . . . . . . . . .97
8.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
8.5.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . .98
8.5.2 Crystal Amplifier Output Pin (OSC2/PTA6/RCCLK). . . . . . .98
8.5.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . .98
8.5.4 X-tal Oscillator Clock (XTALCLK). . . . . . . . . . . . . . . . . . . . .98
8.5.5 RC Oscillator Clock (RCCLK). . . . . . . . . . . . . . . . . . . . . . . .99
8.5.6 Oscillator Out 2 (2OSCOUT) . . . . . . . . . . . . . . . . . . . . . . . .99
8.5.7 Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . .99
8.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8.7 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . .100
8.2 Introduction
The oscillator module provides the reference clock for the MCU system
and bus. Two types of oscillator modules are available:
MC68HC908xxx— built-in oscillator module (X-tal oscillator) that
requires an external crystal or ceramic-resonator. This option also
allows an external clock that can be driven directly into OSC1.
MC68HRC908xxx — built-in oscillator module (RC oscillator) that
requires an external RC connection only.
DJJ %
Oscillator (OSC)
Technical Data MC68H(R)C908JL3Rev. 1.1
96 Oscillator (OSC) Freescale Semiconductor
8.3 X-tal Oscillator (MC68HC908xxx)
The X-tal oscillator