MC100ES6254 Datasheet by Renesas Electronics America Inc

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‘DID'IZ DATASH EET
DATASHEET
2.5/3.3V Differential LVPECL 2x2 Clock
Switch and Fanout Buffer
MC100ES6254
MC100ES6254 REV. 7 JANUARY 7, 2013 1 ©2013 Integrated Device Technology, Inc.
The Freescale MC100ES6254 is a bipolar monolithic differential 2x2 clock
switch and fanout buffer. Designed for most demanding clock distribution
systems, the MC100ES6254 supports various applications that require a large
number of outputs to drive precisely aligned clock signals. The device is capable
of driving and switching differential LVPECL signals. Using SiGe technology and
a fully differential architecture, the device offers superior digital signal
characteristics and very low clock skew error. Target applications for this clock
driver are high performance clock/data switching, clock distribution or data
loopback in computing, networking and telecommunication systems.
Features
Fully differential architecture from input to all outputs
SiGe technology supports near-zero output skew
Supports DC to 3GHz operation(1) of clock or data signals
LVPECL compatible differential clock inputs and outputs
LVCMOS compatible control inputs
Single 3.3 V or 2.5 V supply
50 ps maximum device skew(1)
Synchronous output enable eliminating output runt pulse generation and
metastability
Standard 32 lead LQFP package
Industrial temperature range
32-lead Pb-free package
Functional Description
MC100ES6254 is designed for very skew critical differential clock distribution
systems and supports clock frequencies from DC up to 3.0GHz. Typical
applications for the MC100ES6254 are primary clock distribution, switching and
loopback systems of high-performance computer, networking and
telecommunication systems, as well as on-board clocking of OC-3, OC-12 and
OC-48 speed communication systems. Primary purpose of the MC100ES6254 is
high-speed clock switching applications. In addition, the MC100ES6254 can be
configured as single 1:6 or dual 1:3 LVPECL fanout buffer for clock signals, or as
loopback device in high-speed data applications.
The MC100ES6254 can be operated from a 3.3 V or 2.5 V positive supply
without the requirement of a negative supply line.
1. The device is functional up to 3GHz and characterized up to 2.7GHz.
ORDERING INFORMATION
Device Package
MC100ES6254AC LQFP-32 (Pb-Free)
MC100ES6254ACR2 LQFP-32 (Pb-Free)
2.5/3.3 V DIFFERENTIAL
LVPECL 2x2
CLOCK SWITCH
AND FANOUT BUFFER
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-04
Product Discontinuance Notice – Last Time Buy Expires on (12/7/2013)
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MC100ES6254 REV. 7 JANUARY 7, 2013 2 ©2013 Integrated Device Technology, Inc.
MC100ES6254 Data Sheet 2.5/3.3V DIFFERENTIAL LVPECL 2X2 CLOCK SWITCH AND FANOUT BUFFER
Figure 2. 32-Lead Package Pinout (Top View)
Figure 1. MC100ES6254 Logic Diagram
OEA
SEL0
QA0
QA0
QA1
QA2
QA2
QA1
OEB
QB0
QB0
QB1
QB2
QB2
QB1
CLK0
CLK0
SEL1
VCC
Bank A
Bank B
SYNC
CLK1
CLK1
VCC
0
1
0
1
QA2
VCC
QA1
QA0
QB2
VCC
QB1
VCC
VCC
GND
CLK0
SEL0
GND
VCC
VCC
GND
SEL1
CLK1
GND
VCC
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
12345678
24 23 22 21 20 19 18 17
16
MC100ES6254
VCC
QB0
QA2
QA1
QA0
OEA
CLK0
QB2
QB1
QB0
CLK1
OEB
MC100ES6254 REV. 7 JANUARY 7, 2013 3 ©2013 Integrated Device Technology, Inc.
MC100ES6254 Data Sheet 2.5/3.3V DIFFERENTIAL LVPECL 2X2 CLOCK SWITCH AND FANOUT BUFFER
Table 1. Pin Configuration
Pin I/O Type Function
CLK0, CLK0 Input LVPECL Differential reference clock signal input 0
CLK1, CLK1 Input LVPECL Differential reference clock signal input 1
OEA, OEB Input LVCMOS Output enable
SEL0, SEL1 Input LVCMOS Clock switch select
QA[0-2], QA[0-2]
QB[0-2], QB[0-2]
Output LVPECL Differential clock outputs (banks A and B)
GND Supply GND Negative power supply
VCC Supply VCC Positive power supply. All VCC pins must be connected to the positive
power supply for correct DC and AC operation
Table 2. Function Table
Control Default 0 1
OEA 0 QA[0-2], Qx[0-2] are active. Deassertion of OE
can be asynchronous to the reference clock
without generation of output runt pulses
QA[0-2] = L, QA[0-2] = H (outputs disabled). Assertion
of OE can be asynchronous to the reference clock
without generation of output runt pulses
OEB 0 QA[0-2], Qx[0-2] are active. Deassertion of OE
can be asynchronous to the reference clock
without generation of output runt pulses
QA[0-2] = L, QA[0-2] = H (outputs disabled). Assertion
of OE can be asynchronous to the reference clock
without generation of output runt pulses
SEL0, SEL1 00 Refer to Table 4
Table 3. Clock Select Control
SEL0 SEL1 CLK0 Routed to CLK1 Routed to Application Mode
0 0 QA[0:2] and QB[0:2] 1:6 fanout of CLK0
0 1 QA[0:2] and QB[0:2] 1:6 fanout of CLK1
1 0 QA[0:2] QB[0:2] Dual 1:3 buffer
1 1 QB[0:2] QA[0:2] Dual 1:3 buffer (crossed)
Table 4. Absolute Maximum Ratings(1)
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Symbol Characteristics Min Max Unit Condition
VCC Supply Voltage -0.3 3.6 V
VIN DC Input Voltage -0.3 VCC+0.3 V
VOUT DC Output Voltage -0.3 VCC+0.3 V
IIN DC Input Current 20 mA
IOUT DC Output Current 50 mA
TSStorage Temperature -65 125 C
MC100ES6254 REV. 7 JANUARY 7, 2013 4 ©2013 Integrated Device Technology, Inc.
MC100ES6254 Data Sheet 2.5/3.3V DIFFERENTIAL LVPECL 2X2 CLOCK SWITCH AND FANOUT BUFFER
Table 5. General Specifications
Symbol Characteristics Min Typ Max Unit Condition
VTT Output termination voltage VCC–2(1)
1. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase.
V
MM ESD Protection (Machine model) 200 V
HBM ESD Protection (Human body model) 2000 V
CDM ESD Protection (Charged device model) 1500 V
LU Latch-up immunity 200 mA
CIN 4.0 pF Inputs
JA Thermal resistance junction to ambient
JESD 51-3, single layer test board
JESD 51-6, 2S2P multilayer test board
83.1
73.3
68.9
63.8
57.4
59.0
54.4
52.5
50.4
47.8
86.0
75.4
70.9
65.3
59.6
60.6
55.7
53.8
51.5
48.8
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
JC Thermal resistance junction to case 23.0 26.3 C/W MIL-SPEC 883E Method 1012.1
Operating junction temperature(2)
(continuous operation) MTBF = 9.1 years
2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according
to the application life time requirements (See application note AN1545 and the application section in this data sheet for more information).
The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES6254 to be used in applications
requiring industrial temperature range. It is recommended that users of the MC100ES6254 employ thermal modeling analysis to assist in
applying the junction temperature specifications to their particular application.
110 C
TFunc Functional temperature range TA = –40 TJ = +110 C
MC100ES6254 REV. 7 JANUARY 7, 2013 5 ©2013 Integrated Device Technology, Inc.
MC100ES6254 Data Sheet 2.5/3.3V DIFFERENTIAL LVPECL 2X2 CLOCK SWITCH AND FANOUT BUFFER
Table 6. DC Characteristics (VCC = 3.3 V 5% or 2.5 V 5%, TJ = 0 to +110C)
Symbol Characteristics Min Typ Max Unit Condition
LVCMOS Control Inputs (OEA, OEB, SEL0, SEL1)
VIL Input Voltage Low 0.8 V
VIH Input Voltage High 2.0 V
IIN Input Current(1)
1. Inputs have internal pullup/pulldown resistors that affect the input current.
100 AV
IN = VCC or VIN = GND
-+ Clock Inputs (CLK0, CLK0, CLK1, CLK1)
VPP AC differential input voltage(2)
2. VPP is the minimum differential input voltage swing required to maintain AC characteristic.
0.1 1.3 V Differential operation
VCMR Differential cross point voltage(3)
3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC)
range and the input swing lies within the VPP (DC) specification.
1.0 VCC–0.3 V Differential operation
LVPECL Clock Outputs (QA0–2, QA0–2, QB0–2, QB0–2)
VOH Output High Voltage VCC–1.2 VCC–1.005 VCC–0.7 V IOH = –30 mA(4)
4. Equivalent to a termination 50 to VTT.
VOL Output Low Voltage VCC = 3.3 V5%
VCC = 2.5 V5%
VCC–1.9
VCC–1.9
VCC–1.705
VCC–1.705
VCC–1.5
VCC–1.3
VI
OL = –5 mA(5)
5. ICC calculation: ICC = (number of differential output pairs used) * (IOH + IOL) + IGND
ICC = (number of differential output pairs used) * (VOH-VTT)Rload +(VOL-VTT)Rload) + IGND
Supply Current
IGND Maximum Quiescent Supply Current without
output termination current
52 85 mA GND pin
“_
MC100ES6254 REV. 7 JANUARY 7, 2013 6 ©2013 Integrated Device Technology, Inc.
MC100ES6254 Data Sheet 2.5/3.3V DIFFERENTIAL LVPECL 2X2 CLOCK SWITCH AND FANOUT BUFFER
Table 7. AC Characteristics (VCC = 3.3 V 5% or 2.5 V 5%, TJ = 0 to +110C)(1)
1. AC characteristics apply for parallel output termination of 50 to VTT.
Symbol Characteristics Min Typ Max Unit Condition
VPP Differential Input Voltage(2) (peak-to-peak)
2. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew.
0.3 1.3 V
VCMR Differential Input Crosspoint Voltage(3)
3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC)
range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay,
device and part-to-part skew.
1.2 VCC-0.3 V
VO(P–P) Differential Output Voltage (peak-to-peak)
fO < 1.1GHz
fO < 2.5GHz
fO < 3.0GHz
0.45
0.35
0.20
0.7
0.55
0.35
V
V
V
fCLK Input Frequency 0 3000(4)
4. The MC100ES6254 is fully operational up to 3.0 GHz and is characterized up to 2.7GHz.
MHz
tPD Propagation Delay CLK, 1 to QA[] or QB[] 360 485 610 ps Differential
tsk(O) Output-to-Output Skew 50 ps Differential
tsk(PP) Output-to-Output Skew (part-to-part) 250 ps Differential
tSK(P)
DCO
Output Pulse Skew(5)
Output Duty Cycle tREF < 100MHz
tREF < 800MHz
5. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |.
49.4
45.2
60
50.6
54.8
ps
%
%
DCfref = 50%
DCfref = 50%
tJIT(CC) Output Cycle-to-Cycle Jitter (SEL0 SEL1) TBD
tr, tfOutput Rise/Fall Time 0.05 300 ps 20% to 80%
tPDL(6)
6. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high).
Output Disable Time 2.5T + tPD 3.5T + tPD ns T = CLK period
tPLD(7)
7. Propagation delay OE assertion to output enabled (active).
Output Enable Time 3T + tPD 4T + tPD ns T = CLK period
Figure 3. MC100ES6254 Output Disable/Enable Timing
tPDL (OEX to Qx[])
50%
tPLD (OEX to Qx[])
Outputs Disabled
CLKX
CLKX
OEX
Qx[]
Qx[]
1 x 2 CLOCK SWITCH
MC100ES6254 REV. 7 JANUARY 7, 2013 7 ©2013 Integrated Device Technology, Inc.
MC100ES6254 Data Sheet 2.5/3.3V DIFFERENTIAL LVPECL 2X2 CLOCK SWITCH AND FANOUT BUFFER
APPLICATIONS INFORMATION
Example Configurations Understanding the Junction Temperature Range of the
MC100ES6254
To make the optimum use of high clock frequency and low
skew capabilities of the MC100ES6254, the MC100ES6254
is specified, characterized and tested for the junction
temperature range of TJ = 0C to +110C. Because the exact
thermal performance depends on the PCB type, design,
thermal management and natural or forced air convection,
the junction temperature provides an exact way to correlate
the application specific conditions to the published
performance data of this data sheet. The correlation of the
junction temperature range to the application ambient
temperature range and vice versa can be done by
calculation:
TJ = TA + Rthja Ptot
Assuming a thermal resistance (junction to ambient) of
54.4C/W (2s2p board, 200 ft/min airflow, refer to Table 8)
and a typical power consumption of 467mW (all outputs
terminated 50 to VTT
, VCC = 3.3 V, frequency independent),
the junction temperature of the MC100ES6254 is
approximately TA+ 24.5C, and the minimum ambient
temperature in this example case calculates to –24.5C (the
maximum ambient temperature is 85.5C, refer to Table 8).
Exceeding the minimum junction temperature specification of
the MC100ES6254 does not have a significant impact on the
device functionality. However, the continuous use the
MC100ES6254 at high ambient temperatures requires
thermal management to not exceed the specified maximum
junction temperature. Refer to the Freescale application note
AN1545 for a power consumption calculation guideline.
Figure 4. MC100ES6254 AC Test Reference
Differential
Pulse Generator
Z = 50
RT = 50
ZO = 50
DUT
MC100ES6254
VTT
RT = 50
ZO = 50
VTT
2 x 2 CLOCK SWITCH
CLK0
CLK1
SEL0
SEL1
System A
System B
MC100ES6254
3
3
SEL0 SEL1 Switch Configuration
0 0 CLK0 clocks systems A and system B
0 1 CLK1 clocks system A and system B
1 0 CLK0 clocks system A and CLK1 clocks system B
1 1 CLK1 clocks system B and CLK1 clocks system A
1:6 CLOCK FANOUT BUFFER
CLK0
CLK1
SEL0
SEL1
MC100ES6254
0
0
LOOPBACK DEVICE
SEL0 SEL1 Switch Configuration
0 0 System loopback
0 1 Line loopback
1 0 Transmit/Receive operation
1 1 System and line loopback
CLK0
CLK1
SEL0
SEL1
Transmitter
Receiver
MC100ES6254
QA[]
System-Tx
System-Rx QB[]
Table 8. Ambient Temperature Range (Ptot = 467 mW)
Rthja (2s2p board) TA, min(1)
1. The MC100ES6254 device function is guaranteed from
TA = –40C to TJ = 110C.
TA, max
Natural Convection 59.0C/W –28C82C
100 ft/min 54.4C/W –25C85C
200 ft/min 52.5C/W –24.5C 85.5C
400 ft/min 50.4C/W –23.5C 86.5C
800 ft/min 47.8C/W –22C88C
MC100ES6254 REV. 7 JANUARY 7, 2013 8 ©2013 Integrated Device Technology, Inc.
MC100ES6254 Data Sheet 2.5/3.3V DIFFERENTIAL LVPECL 2X2 CLOCK SWITCH AND FANOUT BUFFER
Maintaining Lowest Device Skew
The MC100ES6254 guarantees low output-to-output bank
skew of 50 ps and a part-to-part skew of maximum 250 ps. To
ensure low skew clock signals in the application, both outputs
of any differential output pair need to be terminated
identically, even if only one output is used. When fewer than
all nine output pairs are used, identical termination of all
output pairs within the output bank is recommended. If an
entire output bank is not used, it is recommended to leave all
of these outputs open and unterminated. This will reduce the
device power consumption while maintaining minimum
output skew.
Power Supply Bypassing
The MC100ES6254 is a mixed analog/digital product. The
differential architecture of the MC100ES6254 supports low
noise signal operation at high frequencies. In order to
maintain its superior signal quality, all VCC pins should be
bypassed by high-frequency ceramic capacitors connected
to GND. If the spectral frequencies of the internally generated
switching noise on the supply pins cross the series resonant
point of an individual bypass capacitor, its overall impedance
begins to look inductive and thus increases with increasing
frequency. The parallel capacitor combination shown ensures
that a low impedance path to ground exists for frequencies
well above the noise bandwidth.
Figure 5. VCC Power Supply Bypass
VCC
MC100ES6254
VCC
33...100 nF 0.1 nF
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MC100ES6254 REV. 7 JANUARY 7, 2013 9 ©2013 Integrated Device Technology, Inc.
MC100ES6254 Data Sheet 2.5/3.3V DIFFERENTIAL LVPECL 2X2 CLOCK SWITCH AND FANOUT BUFFER
PACKAGE DIMENSIONS
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
PAGE 1 OF 3
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MC100ES6254 REV. 7 JANUARY 7, 2013 10 ©2013 Integrated Device Technology, Inc.
MC100ES6254 Data Sheet 2.5/3.3V DIFFERENTIAL LVPECL 2X2 CLOCK SWITCH AND FANOUT BUFFER
PACKAGE DIMENSIONS
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
PAGE 2 OF 3
NOTES. T, )TMEVSTCVS ARE TN MTLLWETERS. 2. TNTERPQET DTMENSTONS AND TOLERANCES PER AS\/TE YT4,5*T994, A)ATU\ITS A, E, AND D TO BE DETERVTTNED AT DATLM PLANE H ADTMEVSTONS TO BE DETERMTNED AT SEATTNG DLANE DATJN/ C, ADTMEVSTON DOES NOT TNCLUDE DAMBAR P?DTRUSTON ALLOWABLE DAMBAR PQOTRUSTON SHALL NOT CAUSE THE LEAD WTDTH TD EXCEED THE NAXTVTLM DTMENSTON BY MORE THAN 0.08 \ITM, DAMBAR CANNOT BE LOCATED ON THi LOWER RAUTUS C? THE FOOT MTNTMEW SPACE BETWEEN PRCTRUSTON AND ADJACENT LEAD OR PRCTRUSTON: 0,07 \ITM, ADTMEVSTONS DO NOT TNCLUDE MOLD PROTflJSTON ALLOWABLE PROTRJSTDV TS (175 NM PER STTJE )MENSTCNS ARE NAXWUM PLASTTI: %()T)Y \‘T/E TJWENSTDNS TNCLJTING MOLD MTSNATCH AEXACT SHAPE OF EACH CO?NE? TS OPTTCNAL, /B\THESE DTMENSTONS APPLY TO THE FLAT SECTTCV OF THE LEAD BETWEEN 0‘ MN AVD 025 \ITTVT F-ezw THE LEAT) TTF. OEREEscALE szcowucvcm mc. ‘ MECHANICAL OUTLIVE ALL n x GHTS RESERVE) DRINT VERSIEIN NEIT TI] SCALE TITLE LOW PROFTLE QLAD FLAT PACK (LQFP) 37 LEA) 08 PTTCH (7 X 7 X TA) DIIICLNENT NET 98A§H7UOE9A CASE \TUMBEK 8/3A704 REV C OT APR 2000 STANDARD JEEEC M37026 EBA CASE 873A-04
MC100ES6254 REV. 7 JANUARY 7, 2013 11 ©2013 Integrated Device Technology, Inc.
MC100ES6254 Data Sheet 2.5/3.3V DIFFERENTIAL LVPECL 2X2 CLOCK SWITCH AND FANOUT BUFFER
PACKAGE DIMENSIONS
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
PAGE 3 OF 3
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including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
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MC100ES6254 Data Sheet 2.5/3.3V DIFFERENTIAL LVPECL 2X2 CLOCK SWITCH AND FANOUT BUFFER

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