PIC18F1xK22,PIC18LF1xK22 Flash Programming Spec Datasheet by Microchip Technology

Q ‘MICROCHIP
© 2009 Microchip Technology Inc. Advance Information DS41357B-page 1
PIC18F1XK22/LF1XK22
1.0 DEVICE OVERVIEW
This document includes the programming
specifications for the following devices:
2.0 PROGRAMMING OVERVIEW
The PIC18F1XK22/LF1XK22 devices can be
programmed using either the high-voltage In-Circuit
Serial Programming™ (ICSP™) method or the low-
voltage ICSP method. Both methods can be done with
the device in the users’ system. The low-voltage ICSP
method is slightly different than the high-voltage
method and these differences are noted where
applicable. The PIC18F1XK22 devices operate from
1.8 to 5.5 volts and the PIC18LF1XK22 devices
operate from 1.8 to 3.6 volts. All other aspects of the
PIC18F1XK22 with regards to the PIC18LF1XK22
devices are identical.
2.1 Hardware Requirements
In High-Voltage ICSP mode, the PIC18F1XK22/
LF1XK22 devices require two programmable power
supplies: one for VDD and one for MCLR/VPP/RA3.
Both supplies should have a minimum resolution of
0.25V. Refer to Section 8.0 “AC/DC Characteristics
Timing Requirements for Program/Verify Test
Mode” for additional hardware parameters.
2.1.1 LOW-VOLTAGE ICSP
PROGRAMMING
In Low-Voltage ICSP mode, the PIC18F1XK22/
LF1XK22 devices can be programmed using a single
VDD source in the operating range. The MCLR/VPP/
RA3 does not have to be brought to a different voltage,
but can instead be left at the normal operating voltage.
Refer to Section 8.0 “AC/DC Characteristics Timing
Requirements for Program/Verify Test Mode” for
additional hardware parameters.
2.1.1.1 Single-Supply ICSP Programming
The LVP bit in Configuration register, CONFIG4L,
enables single-supply (low-voltage) ICSP
programming. The LVP bit defaults to a ‘1’ (enabled)
from the factory.
If Single-Supply Programming mode is not used, the
LVP bit can be programmed to a ‘0’ and RC3/PGM
becomes a digital I/O pin. However, the LVP bit may
only be programmed by entering the High-Voltage
ICSP mode, where MCLR/VPP/RA3 is raised to VIHH.
Once the LVP bit is programmed to a ‘0’, only the
High-Voltage ICSP mode is available and only the
High-Voltage ICSP mode can be used to program the
device.
• PIC18F13K22 • PIC18LF13K22
• PIC18F14K22 • PIC18LF14K22
Note 1: The High-Voltage ICSP mode is always
available, regardless of the state of the
LVP bit, by applying VIHH to the MCLR/
VPP/RA3 pin.
2: While in Low-Voltage ICSP mode, the
RC3 pin can no longer be used as a
general I/O.
Flash Memory Programming Specification
PIC18F1XK22/LF1XK22
DS41357B-page 2 Advance Information © 2009 Microchip Technology Inc.
2.2 Pin Diagrams
The pin diagrams for the PIC18F1XK22/LF1XK22
family are shown in Figure 2-1.
TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18F1XK22/LF1XK22
Pin Name During Programming
Pin Name Pin Type Pin Description
MCLR/VPP/RA3 VPP P Programming Enable
VDD(2) VDD P Power Supply
VSS(2) VSS PGround
RC3 PGM I Low-Voltage ICSP™ input when LVP Configuration bit equals ‘1(1)
RA1 PGC I Serial Clock
RA0 PGD I/O Serial Data
Legend: I = Input, O = Output, P = Power
Note 1: See Figure 6-1 for more information.
2: All power supply (VDD) and ground (VSS) pins must be connected.
::::: :H: egggiiigig :31:
© 2009 Microchip Technology Inc. Advance Information DS41357B-page 3
PIC18F1XK22/LF1XK22
FIGURE 2-1: 20-PIN PDIP, SSOP AND SOIC PIN DIAGRAM FOR PIC18F1XK22/LF1XK22
20-pin PDIP, SSOP, SOIC (300 MIL)
10
2
3
4
5
6
1
8
7
9
11
12
13
14
15
16
19
20
18
17
VDD
RA5/OSC1/CLKIN/T13CKI
RA4/AN3/OSC2/CLKOUT
RA3/MCLR/VPP
RC5/CCP1/P1A
RC4/C2OUT/P1B/SRQ
RC3/AN7/C12IN3-/P1C/PGM
RC6/AN8/SS
RC7/AN9/SDO
RB7/TX/CK
VSS
RA0/AN0/CVREF/VREF-/C1IN+/INT0/PGD
RA1/AN1/C12IN0-/VREF+/INT1/PGC
RA2/AN2/C1OUT/T0CKI/INT2/SRQ
RC0/AN4/C2IN+
RC1/AN5/C12IN1-
RC2/AN6/C12IN2-/P1D
RB4/AN10/SDI/SDA
RB5/AN11/RX/DT
RB6/SCK/SCL
PIC18F1XK22/LF1XK22
-
89
2
3
114
15
16
10
11
6
12
13
17181920
7
5
4
PIC18F1XK22/
LF1XK22
RA3/MCLR/VPP
RC5/CCP1/P1A
RC4/C2OUT/P1B/SRQ
RC3/AN7/C12IN3-/P1C/PGM
RC6/AN8/SS
RC7/AN9/SDO
RB7/TX/CK
RB4/AN10/SDI/SDA
RB5/AN11/RX/DT
RB6/SCK/SCL
RC1/AN5/C12IN1-
RC0/AN4/C2IN+
RA2/AN2/C1OUT/T0CKI/INT2/SRQ
RA1/AN1/C12IN0-/VREF+/INT1/PGC
RA0/AN0/CVREF/VREF-/C1IN+/INT0/PGD
VSS
VDD
RA4/AN3/OSC2/CLKOUT
RA5/OSC1/CLKIN/T13CKI
RC2/AN6/C12IN2-/P1D
20-Pin QFN 4x4
PIC18F1XK22/LF1XK22
DS41357B-page 4 Advance Information © 2009 Microchip Technology Inc.
3.0 MEMORY MAPS
For the PIC18F14K22/LF14K22 device, the program
Flash space extends from 0000h to 03FFFh
(16 Kbytes) in two 8-Kbyte blocks. For the
PIC18F13K22/LF13K22 device, the program Flash
space extends from 0000h to 01FFFh (8 Kbytes) in two
4-Kbyte blocks.
For the PIC18F14K22/LF14K22 addresses 0000h
through 0FFFh, however, define a “Boot Block” region
that is treated separately from Block 0. For the
PIC18F13K22/LF13K22 addresses 0000h through
07FFh, define the “Boot Block” region. All of these
blocks define code protection boundaries within the
program Flash space. The size of the Boot Block in the
PIC18F14K22/LF14K22 devices can be configured as
2K, or 4 Kbyte (see Figure 3-1). The size of the Boot
Block in the PIC18F13K22/LF13K22 devices can be
configured as 1K, or 2 Kbytes (see Figure 3-1). This is
done through the BBSIZ bit in the Configuration regis-
ter, CONFIG4L. It is important to note that increasing
the size of the Boot Block decreases the size of the
Block 0.
TABLE 3-1: IMPLEMENTATION OF
PROGRAM FLASH
FIGURE 3-1: MEMORY MAP AND THE PROGRAM FLASH SPACE FOR PIC18F14K22/LF14K22
DEVICES(1)
Device Program Flash Size (Bytes)
PIC18F13K22/
LF13K22 000000h-001FFFh (8K)
PIC18F14K22/
LF14K22 000000h-003FFFh (16K)
000000h
200000h
3FFFFFh
01FFFFh
Note 1: Sizes of memory areas are not to scale.
2: Boot Block size is determined by the BBSIZ bit in the CONFIG4L register.
Program Flash
Unimplemented
Read as ‘0
Configuration
and ID
Space
MEMORY SIZE/DEVICE Address
Range
16 Kbytes
(PIC18F14K22)
BBSIZ = 1BBSIZ = 0
Boot Block(2) Boot Block(2) 000000h
0007FFh
Block 0
000800h
000FFFh
Block 0
001000h
001FFFh
Block 1 Block 1
002000h
003FFFh
Unimplemented
Read ‘0’s Unimplemented
Read ‘0’s
004000h
01FFFFh
© 2009 Microchip Technology Inc. Advance Information DS41357B-page 5
PIC18F1XK22/LF1XK22
FIGURE 3-2: MEMORY MAP AND THE PROGRAM FLASH SPACE FOR PIC18F13K22/LF13K22
DEVICES(1)
Note 1: Sizes of memory areas are not to scale.
2: Boot Block size is determined by the BBSIZ bit in the CONFIG4L register.
000000h
200000h
3FFFFFh
01FFFFh Program Flash
Unimplemented
Read as ‘0
Configuration
and ID
Space
MEMORY SIZE/DEVICE Address
Range
8 Kbytes
(PIC18F13K22)
BBSIZ = 1BBSIZ = 0
Boot Block(2) Boot Block(2) 000000h
0003FFh
Block 0
000400h
0007FFh
Block 0
000800h
000FFFh
Block 1 Block 1
001000h
001FFFh
Unimplemented
Read ‘0’s Unimplemented
Read ‘0’s
002000h
01FFFFh
PIC18F1XK22/LF1XK22
DS41357B-page 6 Advance Information © 2009 Microchip Technology Inc.
In addition to the program Flash space, there are three
blocks in the Configuration and ID space that are
accessible to the user through table reads and table
writes. Their locations in the memory map are shown in
Figure 3-3.
Users may store identification information (ID) in eight
ID registers. These ID registers are mapped in
addresses 200000h through 200007h. The ID locations
read out normally, even after code protection is applied.
Locations 300001h through 30000Dh are reserved for
the Configuration bits. These bits select various device
options and are described in Section 6.0 “Configura-
tion Word”. These Configuration bits read out
normally, even after code protection.
Locations 3FFFFEh and 3FFFFFh are reserved for the
device ID bits. These bits may be used by the
programmer to identify what device type is being
programmed and are described in Section 6.0
“Configuration Word”. These device ID bits read out
normally, even after code protection.
3.0.1 MEMORY ADDRESS POINTER
Memory in the address space, 0000000h to 3FFFFFh,
is addressed via the Table Pointer register, which is
comprised of three Pointer registers:
TBLPTRU, at RAM address 0FF8h
TBLPTRH, at RAM address 0FF7h
TBLPTRL, at RAM address 0FF6h
The 4-bit command, ‘0000’ (core instruction), is used to
load the Table Pointer prior to using any read or write
operations.
FIGURE 3-3: CONFIGURATION AND ID LOCATIONS FOR PIC18F1XK22/LF1XK22 DEVICES
TBLPTRU TBLPTRH TBLPTRL
Addr[21:16] Addr[15:8] Addr[7:0]
ID Location 1 200000h
ID Location 2 200001h
ID Location 3 200002h
ID Location 4 200003h
ID Location 5 200004h
ID Location 6 200005h
ID Location 7 200006h
ID Location 8 200007h
CONFIG1H 300001h
CONFIG2L 300002h
CONFIG2H 300003h
300004h
CONFIG3H 300005h
CONFIG4L 300006h
300007h
CONFIG5L 300008h
CONFIG5H 300009h
CONFIG6L 30000Ah
CONFIG6H 30000Bh
CONFIG7L 30000Ch
CONFIG7H 30000Dh
Device ID1 3FFFFEh
Device ID2 3FFFFFh
Note: Sizes of memory areas are not to scale.
000000h
1FFFFFh
3FFFFFh
01FFFFh Program Flash
Unimplemented
Read as0
Configuration
and ID
Space
2FFFFFh
© 2009 Microchip Technology Inc. Advance Information DS41357B-page 7
PIC18F1XK22/LF1XK22
3.1 High-Level Overview of the
Programming Process
Figure 3-4 shows the high-level overview of the
programming process. First, a Bulk Erase is performed.
Next, the program Flash, ID locations and data
EEPROM are programmed. These memories are then
verified to ensure that programming was successful. If
no errors are detected, the Configuration bits are then
programmed and verified.
FIGURE 3-4: HIGH-LEVEL
PROGRAMMING FLOW
3.2 Entering and Exiting High-Voltage
ICSP Program/Verify Mode
As shown in Figure 3-6, the High-Voltage ICSP
Program/Verify mode is entered by holding PGC and
PGD low and then raising MCLR/VPP/RA3 to VIHH
(high voltage). Once in this mode, the program Flash,
data EEPROM, ID locations and Configuration bits can
be accessed and programmed in serial fashion.
Figure 3-7 shows the exit sequence.
The sequence that enters the device into the Program/
Verify mode places all unused I/Os in the high-impedance
state.
FIGURE 3-5: VPP-FIRST PROGRAM/
VERIFY MODE ENTRY
FIGURE 3-6: VDD-FIRST PROGRAM/
VERIFY MODE ENTRY
Start
Program Memory
Program IDs
Program Data EE
Verify Program
Verify IDs
Verify Data
Program
Configuration Bits
Verify
Configuration Bits
Done
Perform Bulk
Erase
MCLR/VPP/RA3
P12
PGD
PGD = Input
PGC
VDD
D110
P13
P1
Note: This method of entry is valid, regardless
of Configuration Word selected.
MCLR/VPP/RA3
P12
PGD
PGD = Input
PGC
VDD
D110
P13
P1
PIC18F1XK22/LF1XK22
DS41357B-page 8 Advance Information © 2009 Microchip Technology Inc.
FIGURE 3-7: EXITING HIGH-VOLTAGE
PROGRAM/VERIFY MODE
3.3 Entering and Exiting Low-Voltage
ICSP Program/Verify Mode
When the LVP Configuration bit is ‘1’ (see
Section 2.1.1.1 “Single-Supply ICSP Programming”),
the Low-Voltage ICSP mode is enabled. As shown in
Figure 3-8, Low-Voltage ICSP Program/Verify mode is
entered by holding PGC and PGD low, placing a logic
high on PGM and then raising MCLR/VPP/RA3 to VIH. In
this mode, the RC3/PGM pin is dedicated to the
programming function and ceases to be a general
purpose I/O pin. Figure 3-9 shows the exit sequence.
The sequence that enters the device into the Program/
Verify mode places all unused I/Os in the high-impedance
state.
FIGURE 3-8: ENTERING LOW-VOLTAGE
PROGRAM/VERIFY MODE
FIGURE 3-9: EXITING LOW-VOLTAGE
PROGRAM/VERIFY MODE
MCLR/VPP/RA3
P16
PGD
PGD = Input
PGC
VDD
D110
P17
P1
MCLR/VPP/RA3
P12
PGD
PGD = Input
PGC
PGM
P15
VDD
VIH
VIH
MCLR/VPP/RA3
P16
PGD
PGD = Input
PGC
PGM
P18
VDD
VIH
VIH
© 2009 Microchip Technology Inc. Advance Information DS41357B-page 9
PIC18F1XK22/LF1XK22
3.4 Serial Program/Verify Operation
The PGC pin is used as a clock input pin and the PGD
pin is used for entering command bits and data input/
output during serial operation. Commands and data are
transmitted on the rising edge of PGC, latched on the
falling edge of PGC and are Least Significant bit (LSb)
first.
3.4.1 4-BIT COMMANDS
All instructions are 20 bits, consisting of a leading 4-bit
command followed by a 16-bit operand, which depends
on the type of command being executed. To input a
command, PGC is cycled four times. The commands
needed for programming and verification are shown in
Table 3-2.
Depending on the 4-bit command, the 16-bit operand
represents 16 bits of input data or 8 bits of input data
and 8 bits of output data.
Throughout this specification, commands and data are
presented as illustrated in Table 3-3. The 4-bit
command, Most Significant bit (MSb), is shown first.
The command operand, or “Data Payload”, is shown
<MSB><LSB>. Figure 3-10 demonstrates how to
serially present a 20-bit command/operand to the
device.
3.4.2 CORE INSTRUCTION
The core instruction passes a 16-bit instruction to the
CPU core for execution. This is needed to set up
registers as appropriate for use with other commands.
TABLE 3-2: COMMANDS FOR
PROGRAMMING
Description 4-Bit
Command
Core Instruction
(Shift in16-bit instruction) 0000
Shift out TABLAT register 0010
Table Read 1000
Table Read, post-increment 1001
Table Read, post-decrement 1010
Table Read, pre-increment 1011
Table Write 1100
Table Write, post-increment by 2 1101
Table Write, start programming,
post-increment by 2 1110
Table Write, start programming 1111
PIC18F1XK22/LF1XK22
DS41357B-page 10 Advance Information © 2009 Microchip Technology Inc.
TABLE 3-3: SAMPLE COMMAND
SEQUENCE
FIGURE 3-10: TABLE WRITE, POST-INCREMENT TIMING DIAGRAM (1101)
4-Bit
Command Data
Payload Core Instruction
1101 3C 40 Table Write,
post-increment by 2
1234
PGC
P5
PGD
PGD = Input
5678 1234
P5A
910 11 13 15 161412
Fetch Next 4-bit Command
1011
1234
nnnn
P3
P2 P2A
000000 010001111 0
04C3
P4
4-bit Command 16-bit Data Payload
P2B
© 2009 Microchip Technology Inc. Advance Information DS41357B-page 11
PIC18F1XK22/LF1XK22
4.0 DEVICE PROGRAMMING
Programming includes the ability to erase or write the
various memory regions within the device.
In all cases, except high-voltage ICSP Bulk Erase, the
EECON1 register must be configured in order to
operate on a particular memory region.
When using the EECON1 register to act on program
Flash, the EEPGD bit must be set (EECON1<7> = 1)
and the CFGS bit must be cleared (EECON1<6> = 0).
The WREN bit must be set (EECON1<2> = 1) to
enable writes of any sort (e.g., erases) and this must be
done prior to initiating a write sequence. The FREE bit
must be set (EECON1<4> = 1) in order to erase the
program space being pointed to by the Table Pointer.
The erase or write sequence is initiated by setting the
WR bit (EECON1<1> = 1). It is strongly recommended
that the WREN bit only be set immediately prior to a
program or erase.
4.1 ICSP Erase
4.1.1 HIGH-VOLTAGE ICSP BULK ERASE
Erasing program Flash or data EEPROM is
accomplished by configuring two Bulk Erase Control
registers located at 3C0004h and 3C0005h. Program
Flash may be erased portions at a time, or the user may
erase the entire device in one action. Bulk Erase
operations will also clear any code-protect settings
associated with the memory block erased. Erase
options are detailed in Table 4-1. If data EEPROM is
code-protected (CPD = 0), the user must request an
erase of data EEPROM (e.g., 0084h as shown in
Table 4-1).
TABLE 4-1: BULK ERASE OPTIONS
The actual Bulk Erase function is a self-timed
operation. Once the erase has started (falling edge of
the 4th PGC after the NOP command), serial execution
will cease until the erase completes (parameter P11).
During this time, PGC may continue to toggle but PGD
must be held low.
The code sequence to erase the entire device is shown
in Table 4-2 and the flowchart is shown in Figure 4-1.
TABLE 4-2: BULK ERASE COMMAND
SEQUENCE
FIGURE 4-1: BULK ERASE FLOW
Description Data
(3C0005h:3C0004h)
Chip Erase 0F8Fh
Erase User IDs 0088h
Erase Data EEPROM 0084h
Erase Boot Block 0081h
Erase Config Bits 0082h
Erase Program Flash Block 0 0180h
Erase Program Flash Block 1 0280h
Erase Program Flash Block 2 0480h
Erase Program Flash Block 3 0880h
Note: A Bulk Erase is the only way to reprogram
code-protect bits from an “on” state to an
“off” state.
4-Bit
Command Data
Payload Core Instruction
0000 0E 3C MOVLW 3Ch
0000 6E F8 MOVWF TBLPTRU
0000 0E 00 MOVLW 00h
0000 6E F7 MOVWF TBLPTRH
0000 0E 05 MOVLW 05h
0000 6E F6 MOVWF TBLPTRL
1100 0F 0F Write 0Fh to 3C0005h
0000 0E 3C MOVLW 3Ch
0000 6E F8 MOVWF TBLPTRU
0000 0E 00 MOVLW 00h
0000 6E F7 MOVWF TBLPTRH
0000 0E 04 MOVLW 04h
0000 6E F6 MOVWF TBLPTRL
1100 8F 8F Write 8F8Fh TO 3C0004h
to erase entire device.
0000 00 00 NOP
0000 00 00 Hold PGD low until erase
completes.
Start
Done
Write 8F8Fh to
3C0004h to Erase
Entire Device
Write 0F0Fh
Delay P11 + P10
Time
to 3C0005h
PIC18F1XK22/LF1XK22
DS41357B-page 12 Advance Information © 2009 Microchip Technology Inc.
FIGURE 4-2: BULK ERASE TIMING DIAGRAM
4.1.2 LOW-VOLTAGE ICSP BULK ERASE
When using low-voltage ICSP, the part must be
supplied by the voltage specified in parameter D111 if a
Bulk Erase is to be executed. All other Bulk Erase
details as described above apply.
If it is determined that a program memory erase must
be performed at a supply voltage below the Bulk Erase
limit, refer to the erase methodology described in
Section 4.1.3 “ICSP Row Erase and Section 4.2.1
“Modifying Program Flash”.
If it is determined that a data EEPROM erase must be
performed at a supply voltage below the Bulk Erase
limit, follow the methodology described in Section 4.3
“Data EEPROM Programming” and write ‘1’s to the
array.
4.1.3 ICSP ROW ERASE
Regardless of whether high or low-voltage ICSP is
used, it is possible to erase one row (64 bytes of data),
provided the block is not code or write-protected. Rows
are located at static boundaries beginning at program
memory address 000000h, extending to the internal
program memory limit (see Section 3.0 “Memory
Maps”).
The Row Erase duration is self-timed. After the WR bit
in EECON1 is set, two NOPs are issued. Erase starts
upon the 4th PGC of the second NOP. It ends when the
WR bit is cleared by hardware.
The code sequence to Row Erase a PIC18F1XK22/
LF1XK22 device is shown in Table 4-3. The flowchart
shown in Figure 4-3 depicts the logic necessary to com-
pletely erase the PIC18F1XK22/LF1XK22 devices. The
timing diagram for Row Erase is identical to the data
EEPROM write timing shown in Figure 4-7.
n
1234 121516 123
PGC
P5 P5A
PGD
PGD = Input
0
0011
P11
P10
Erase Time
000000
12
00
4
0
1 2 15 16
P5
123
P5A
4
0000 n
4-bit Command 4-bit Command 4-bit Command
16-bit
Data Payload
16-bit
Data Payload 16-bit
Data Payload
11
Note 1: The TBLPTR register can point at any
byte within the row intended for erase.
2: ICSP row erase of the User ID locations
is also possible using the technique
described in Section 4.1.3 “ICSP Row
Erase”. The address argument used
should be 0x200000. A row erase of the
User ID locations is required when VDD is
below the Bulk Erase threshold.
© 2009 Microchip Technology Inc. Advance Information DS41357B-page 13
PIC18F1XK22/LF1XK22
TABLE 4-3: ERASE PROGRAM FLASH CODE SEQUENCE
4-bit
Command Data Payload Core Instruction
Step 1: Direct access to program Flash and enable writes.
0000
0000
0000
8E A6
9C A6
84 A6
BSF EECON1, EEPGD
BCF EECON1, CFGS
BSF EECON1, WREN
Step 2: Point to first row in program Flash.
0000
0000
0000
6A F8
6A F7
6A F6
CLRF TBLPTRU
CLRF TBLPTRH
CLRF TBLPTRL
Step 3: Enable erase and erase single row.
0000
0000
0000
0000
88 A6
82 A6
00 00
00 00
BSF EECON1, FREE
BSF EECON1, WR
NOP
NOP Erase starts on the 4th clock of this instruction
Step 4: Poll WR bit. Repeat until bit is clear.
0000
0000
0000
0010
50 A6
6E F5
00 00
<MSB><LSB>
MOVF EECON1, W, 0
MOVWF TABLAT
NOP
Shift out data(1)
Step 5: Hold PGC low for time P10.
Step 6: Repeat step 3 with Address Pointer incremented by 64 until all rows are erased.
Step 7: Disable writes.
0000 94 A6 BCF EECON1, WREN
Note 1: See Figure 5-4 for details on shift out data timing.
PIC18F1XK22/LF1XK22
DS41357B-page 14 Advance Information © 2009 Microchip Technology Inc.
FIGURE 4-3: SINGLE ROW ERASE PROGRAM FLASH FLOW
Done
Start
All
Rows
done?
No
Yes
Addr = 0
Configure
Device for
Row Erases
Addr = Addr + 64
Perform Erase
Sequence
WR Bit
Clear? No
Yes
© 2009 Microchip Technology Inc. Advance Information DS41357B-page 15
PIC18F1XK22/LF1XK22
4.2 Program Flash Programming
Programming program Flash is accomplished by first
loading data into the write buffer and then initiating a
programming sequence. The write and erase buffer
sizes shown in Table 4-4 can be mapped to any
location of the same size beginning at 000000h. The
actual memory write sequence takes the contents of
this buffer and programs the proper amount of program
Flash that contains the Table Pointer.
The programming duration is externally timed and is
controlled by PGC. After a Start Programming
command is issued (4-bit command, ‘1111’), a NOP is
issued, where the 4th PGC is held high for the duration
of the programming time, P9.
After PGC is brought low, the programming sequence
is terminated. PGC must be held low for the time
specified by parameter P10 to allow high-voltage
discharge of the memory array.
The code sequence to program a PIC18F1XK22/
LF1XK22 device is shown in Table 4-5. The flowchart
shown in Figure 4-4 depicts the logic necessary to
completely write a PIC18F1XK22/LF1XK22 device.
The timing diagram that details the Start Programming
command and parameters P9 and P10 is shown in
Figure 4-5.
TABLE 4-4: WRITE AND ERASE BUFFER SIZES
TABLE 4-5: WRITE PROGRAM FLASH CODE SEQUENCE
Note: The TBLPTR register must point to the
same region when initiating the program-
ming sequence as it did when the write
buffers were loaded.
Devices Write Buffer Size
(bytes) Erase Size (bytes)
PIC18F14K22 16 64
PIC18F13K22 8 64
4-bit
Command Data Payload Core Instruction
Step 1: Direct access to program Flash.
0000
0000
0000
8E A6
9C A6
84 A6
BSF EECON1, EEPGD
BCF EECON1, CFGS
BSF EECON1, WREN
Step 2: Point to row to write.
0000
0000
0000
0000
0000
0000
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Step 3: Load write buffer. Repeat for all but the last two bytes.
1101 <MSB><LSB> Write 2 bytes and post-increment address by 2.
Step 4: Load write buffer for last two bytes and start programming.
1111
0000 <MSB><LSB>
00 00 Write 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
To continue writing data, repeat steps 2 through 4, where the Address Pointer is incremented by 2 at each iteration of
the loop.
PIC18F1XK22/LF1XK22
DS41357B-page 16 Advance Information © 2009 Microchip Technology Inc.
FIGURE 4-4: PROGRAM FLASH FLOW
FIGURE 4-5: TABLE WRITE AND START PROGRAMMING INSTRUCTION
TIMING DIAGRAM (1111)
Start Write Sequence
All
locations
done?
No
Done
Start
Yes
Hold PGC Low
for Time P10
Load 2 Bytes
to Write
Buffer at <Addr>
All
bytes
written?
No
Yes
and Hold PGC
High until Done
N = 1
LoopCount = 0
Configure
Device for
Writes
N = 1
LoopCount =
LoopCount + 1
N = N + 1
and Wait P9
1234 1 2 15 16 123 4
PGC
P5A
PGD
PGD = Input
n
1111
34 65
P9
(1)
P10
Programming Time
nnn nn n n
00
12
0
00
16-bit
Data Payload
0
3
0
P5
4-bit Command 16-bit Data Payload 4-bit Command
Note 1: Use P9A for Configuration Word programming.
© 2009 Microchip Technology Inc. Advance Information DS41357B-page 17
PIC18F1XK22/LF1XK22
4.2.1 MODIFYING PROGRAM FLASH
The previous programming example assumed that the
device has been Bulk Erased prior to programming
(see Section 4.1.1 “High-Voltage ICSP Bulk Erase”).
It may be the case, however, that the user wishes to
modify only a section of an already programmed
device.
The appropriate number of bytes required for the erase
buffer must be read out of program Flash (as described
in Section 5.2 “Verify Program Flash and ID Loca-
tions”) and buffered. Modifications can be made on
this buffer. Then, the block of program Flash that was
read out must be erased and rewritten with the
modified data.
The WREN bit must be set if the WR bit in EECON1 is
used to initiate a write sequence.
TABLE 4-6: MODIFYING PROGRAM FLASH
4-bit
Command Data Payload Core Instruction
Step 1: Direct access to program Flash.
0000
0000
8E A6
9C A6 BSF EECON1, EEPGD
BCF EECON1, CFGS
Step 2: Read program Flash into buffer (Section 5.1 “Read Program Flash, ID Locations and Configuration Bits”).
Step 3: Set the Table Pointer for the block to be erased.
0000
0000
0000
0000
0000
0000
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[8:15]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Step 4: Enable memory writes and setup an erase.
0000
0000
84 A6
88 A6 BSF EECON1, WREN
BSF EECON1, FREE
Step 5: Initiate erase.
0000
0000
0000
0000
88 A6
82 A6
00 00
00 00
BSF EECON1, FREE
BSF EECON1, WR
NOP
NOP Erase starts on the 4th clock of this instruction
Step 6: Poll WR bit. Repeat until bit is clear.
0000
0000
0000
0000
50 A6
6E F5
00 00
<MSB><LSB>
MOVF EECON1, W, 0
MOVWF TABLAT
NOP
Shift out data(1)
Step 7: Load write buffer. The correct bytes will be selected based on the Table Pointer.
0000
0000
0000
0000
0000
0000
1101
1111
0000
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
<MSB><LSB>
<MSB><LSB>
00 00
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[8:15]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2.
Repeat as many times as necessary to fill the write buffer
Write 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
To continue modifying data, repeat Steps 2 through 6, where the Address Pointer is incremented by the appropriate number of bytes
(see Table 4-4) at each iteration of the loop. The write cycle must be repeated enough times to completely rewrite the contents of the
erase buffer.
Step 8: Disable writes.
0000 94 A6 BCF EECON1, WREN
mmm‘é“ 1; 15 {, J wfiwmwwwm fig fir /—5
PIC18F1XK22/LF1XK22
DS41357B-page 18 Advance Information © 2009 Microchip Technology Inc.
4.3 Data EEPROM Programming
Data EEPROM is accessed one byte at a time via an
Address Pointer (register EEADR) and a data latch
(EEDATA). Data EEPROM is written by loading
EEADR with the desired memory location, EEDATA
with the data to be written and initiating a memory write
by appropriately configuring the EECON1 register. A
byte write automatically erases the location and writes
the new data (erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1<7:6> = 00). The WREN bit must
be set (EECON1<2> = 1) to enable writes of any sort
and this must be done prior to initiating a write
sequence. The write sequence is initiated by setting the
WR bit (EECON1<1> = 1).
The write begins on the falling edge of the 24th PGC
after the WR bit is set. It ends when the WR bit is
cleared by hardware.
After the programming sequence terminates, PGC
must be held low for the time specified by parameter
P10 to allow high-voltage discharge of the memory
array.
FIGURE 4-6: PROGRAM DATA FLOW
FIGURE 4-7: DATA EEPROM WRITE TIMING DIAGRAM
Start
Start Write
Set Data
Done
No
Yes
done?
Enable Write
Sequence
Set Address
WR bit
clear? No
Yes
n
PGC
PGD
PGD = Input
0000
BSF EECON1, WR4-bit Command
1234 121516
P5 P5A
P10
12
n
Poll WR bit, Repeat until Clear 16-bit Data
Payload
1234 121516 123
P5 P5A
41 2 15 16
P5 P5A
0000
MOVF EECON1, W, 0
4-bit Command
0000
4-bit Command Shift Out Data
MOVWF TABLAT
PGC
PGD
(see below)
(see Figure 4-4)
PGD = Input PGD = Output
Poll WR bit
P11A
P5A
2 NOP commands
© 2009 Microchip Technology Inc. Advance Information DS41357B-page 19
PIC18F1XK22/LF1XK22
TABLE 4-7: PROGRAMMING DATA MEMORY
4-bit
Command Data Payload Core Instruction
Step 1: Direct access to data EEPROM.
0000
0000 9E A6
9C A6 BCF EECON1, EEPGD
BCF EECON1, CFGS
Step 2: Set the data EEPROM Address Pointer.
0000
0000 0E <Addr>
6E A9 MOVLW <Addr>
MOVWF EEADR
Step 3: Load the data to be written.
0000
0000 0E <Data>
6E A8 MOVLW <Data>
MOVWF EEDATA
Step 4: Enable memory writes.
0000 84 A6 BSF EECON1, WREN
Step 5: Initiate write.
0000
0000
0000
82 A6
00 00
00 00
BSF EECON1, WR
NOP
NOP ;write starts on 4th clock of this instruction
Step 6: Poll WR bit, repeat until the bit is clear.
0000
0000
0000
0010
50 A6
6E F5
00 00
<MSB><LSB>
MOVF EECON1, W, 0
MOVWF TABLAT
NOP
Shift out data(1)
Step 7: Hold PGC low for time P10.
Step 8: Disable writes.
0000 94 A6 BCF EECON1, WREN
Repeat steps 2 through 8 to write more data.
Note 1: See Figure 5-4 for details on shift out data timing.
PIC18F1XK22/LF1XK22
DS41357B-page 20 Advance Information © 2009 Microchip Technology Inc.
4.4 ID Location Programming
The ID locations are programmed much like the
program Flash. The ID registers are mapped in
addresses 200000h through 200007h. These locations
read out normally even after code protection.
Table 4-8 demonstrates the code sequence required to
write the ID locations.
In order to modify the ID locations, refer to the
methodology described in Section 4.2.1 “Modifying
Program Flash”. As with program Flash, the ID
locations must be erased before being modified.
TABLE 4-8: WRITE ID SEQUENCE
Note: The user only needs to fill the first 8 bytes
of the write buffer in order to write the ID
locations.
4-bit
Command Data Payload Core Instruction
Step 1: Direct access to program Flash.
0000
0000
0000
8E A6
9C A6
84 A6
BSF EECON1, EEPGD
BCF EECON1, CFGS
BSF EECON1, WREN
Step 2: Set Table Pointer to ID. Load write buffer with 8 bytes and write.
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
0E 20
6E F8
0E 00
6E F7
0E 00
6E F6
<MSB><LSB>
<MSB><LSB>
<MSB><LSB>
<MSB><LSB>
00 00
MOVLW 20h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 00h
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2.
Write 2 bytes and post-increment address by 2.
Write 2 bytes and post-increment address by 2.
Write 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
© 2009 Microchip Technology Inc. Advance Information DS41357B-page 21
PIC18F1XK22/LF1XK22
4.5 Boot Block Programming
The code sequence detailed in Table 4-5 should be
used, except that the address used in “Step 2” will be in
the following ranges:
If BBSIZ = 0:
000000h-0003FFh for PIC18F13K22/LF13K22
000000h-0007FFh for PIC18F14K22/LF14K22
If BBSIZ = 1:
000000h-0007FFh for PIC18F13K22/LF13K22
000000h-000FFFh for PIC18F14K22/LF14K22
4.6 Configuration Bits Programming
Unlike program Flash, the Configuration bits are
programmed a byte at a time. The Table Write, Begin
Programming 4-bit command (‘1111’) is used, but only
8 bits of the following 16-bit payload will be written. The
LSB of the payload will be written to even addresses
and the MSB will be written to odd addresses. The
code sequence to program two consecutive
configuration locations is shown in Table 4-9. See
Figure 4-5 for the timing diagram.
TABLE 4-9: SET ADDRESS POINTER TO CONFIGURATION LOCATION
FIGURE 4-8: CONFIGURATION PROGRAMMING FLOW
Note: The address must be explicitly written for
each byte programmed. The addresses
can not be incremented in this mode.
4-bit
Command Data Payload Core Instruction
Step 1: Direct access to configuration memory.
0000
0000
0000
8E A6
8C A6
84 A6
BSF EECON1, EEPGD
BSF EECON1, CFGS
BSF EECON1, WREN
Step 2(1): Set Table Pointer for configuration byte to be written. Write even/odd addresses.
0000
0000
0000
0000
0000
0000
1111
0000
0000
0000
1111
0000
0E 30
6E F8
0E 00
6E F7
0E 00
6E F6
<MSB ignored><LSB>
00 00
0E 01
6E F6
<MSB><LSB ignored>
00 00
MOVLW 30h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPRTH
MOVLW 00h
MOVWF TBLPTRL
Load 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
MOVLW 01h
MOVWF TBLPTRL
Load 2 bytes and start programming.
NOP - hold PGC high for time P9A and low for time P10.
Note 1: Enabling the write protection of Configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of Configura-
tion bits. Always write all the Configuration bits before enabling the write protection for Configuration bits.
Load Even
Configuration
Start
Program Program
MSB
Delay P9 and P10
Time for Write
LSB
Load Odd
Configuration
Address Address
Done
Start
Delay P9 and P10
Time for Write
Done
PIC18F1XK22/LF1XK22
DS41357B-page 22 Advance Information © 2009 Microchip Technology Inc.
5.0 READING THE DEVICE
5.1 Read Program Flash, ID Locations
and Configuration Bits
Program Flash is accessed one byte at a time via the
4-bit command, ‘1001’ (table read, post-increment).
The contents of memory pointed to by the Table Pointer
(TBLPTRU:TBLPTRH:TBLPTRL) are serially output on
PGD.
The 4-bit command is shifted in LSb first. The read is
executed during the next 8 clocks, then shifted out on
PGD during the last 8 clocks, LSb to MSb. A delay of
P6 must be introduced after the falling edge of the 8th
PGC of the operand to allow PGD to transition from an
input to an output. During this time, PGC must be held
low (see Figure 5-1). This operation also increments
the Table Pointer by one, pointing to the next byte in
program Flash for the next read.
This technique will work to read any memory in the
000000h to 3FFFFFh address space, so it also applies
to the reading of the ID and Configuration registers.
TABLE 5-1: READ PROGRAM FLASH SEQUENCE
FIGURE 5-1: TABLE READ POST-INCREMENT INSTRUCTION TIMING DIAGRAM (1001)
4-bit
Command Data Payload Core Instruction
Step 1: Set Table Pointer
0000
0000
0000
0000
0000
0000
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
MOVLW Addr[21:16]
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Step 2: Read memory and then shift out on PGD, LSb to MSb
1001 00 00 TBLRD *+
1234
PGC
P5
PGD
PGD = Input
Shift Data Out
P6
PGD = Output
5678 1234
P5A
910 11 13 15 161412
Fetch Next 4-bit Command
1001
PGD = Input
LSb MSb
123456
1234
nnnn
P14
Note 1: Magnification of the high-impedance delay between PGC and PGD is shown in Figure 5-5.
(Note 1)
EL 1
© 2009 Microchip Technology Inc. Advance Information DS41357B-page 23
PIC18F1XK22/LF1XK22
5.2 Verify Program Flash and ID
Locations
The verify step involves reading back the program
Flash space and comparing it against the copy held in
the programmers buffer. Memory reads occur a single
byte at a time, so two bytes must be read to compare
against the word in the programmer’s buffer. Refer to
Section 5.1 “Read Program Flash, ID Locations and
Configuration Bits” for implementation details of
reading program Flash.
The Table Pointer must be manually set to 200000h
(base address of the ID locations) once the program
Flash has been verified. The post-increment feature of
the table read 4-bit command can not be used to
increment the Table Pointer beyond the program Flash
space. In a 64-Kbyte device, for example, a post-
increment read of address FFFFh will wrap the Table
Pointer back to 000000h, rather than point to
unimplemented address, 010000h.
FIGURE 5-2: VERIFY PROGRAM FLASH FLOW
Read Low Byte
Read High Byte
Does
Word = Expect
data? Failure,
Report
Error
All
program Flash
verified?
No
Yes
No
Set TBLPTR = 0
Start
Set TBLPTR = 200000h
Yes
Read Low Byte
Read High byte
Does
Word = Expect
data? Failure,
Report
Error
All
ID locations
verified?
No
Yes
Done
Yes
No
with Post-increment
with Post-increment Increment
Pointer
with Post-Increment
with Post-Increment
PIC18F1XK22/LF1XK22
DS41357B-page 24 Advance Information © 2009 Microchip Technology Inc.
5.3 Verify Configuration Bits
A Configuration address may be read and output on
PGD via the 4-bit command, ‘1001’. Configuration data
is read and written in a byte-wise fashion, so it is not
necessary to merge two bytes into a word prior to a
compare. The result may then be immediately
compared to the appropriate configuration data in the
programmer’s memory for verification. Refer to
Section 5.1 “Read Program Flash, ID Locations and
Configuration Bits” for implementation details of
reading Configuration data.
5.4 Read Data EEPROM Memory
Data EEPROM is accessed one byte at a time via an
Address Pointer (register EEADR) and a data latch
(EEDATA). Data EEPROM is read by loading EEADR
with the desired memory location and initiating a
memory read by appropriately configuring the
EECON1 register. The data will be loaded into
EEDATA, where it may be serially output on PGD via
the 4-bit command, ‘0010’ (Shift Out Data Holding
register). A delay of P6 must be introduced after the
falling edge of the 8th PGC of the operand to allow
PGD to transition from an input to an output. During this
time, PGC must be held low (see Figure 5-4).
The command sequence to read a single byte of data
is shown in Table 5-2.
FIGURE 5-3: READ DATA EEPROM
FLOW
TABLE 5-2: READ DATA EEPROM MEMORY
Start
Set
Address
Read
Byte
Done
No
Yes
done?
Move to TABLAT
Shift Out Data
4-bit
Command Data Payload Core Instruction
Step 1: Direct access to data EEPROM.
0000
0000
9E A6
9C A6 BCF EECON1, EEPGD
BCF EECON1, CFGS
Step 2: Set the data EEPROM Address Pointer.
0000
0000
0E <Addr>
6E A9 MOVLW <Addr>
MOVWF EEADR
Step 3: Initiate a memory read.
0000 80 A6 BSF EECON1, RD
Step 4: Load data into the Serial Data Holding register.
0000
0000
0000
0010
50 A8
6E F5
00 00
<MSB><LSB>
MOVF EEDATA, W, 0
MOVWF TABLAT
NOP
Shift Out Data(1)
Note 1: The <LSB> is undefined. The <MSB> is the data.
© 2009 Microchip Technology Inc. Advance Information DS41357B-page 25
PIC18F1XK22/LF1XK22
FIGURE 5-4: SHIFT OUT DATA HOLDING REGISTER TIMING DIAGRAM (0010)
FIGURE 5-5: HIGH-IMPEDANCE DELAY
5.5 Verify Data EEPROM
A data EEPROM address may be read via a sequence
of core instructions (4-bit command, ‘0000’) and then
output on PGD via the 4-bit command,0010’ (TABLAT
register). The result may then be immediately
compared to the appropriate data in the programmer’s
memory for verification. Refer to Section 5.4 “Read
Data EEPROM Memory” for implementation details of
reading data EEPROM.
5.6 Blank Check
The term “Blank Check” means to verify that the device
has no programmed memory cells. All memories must
be verified: program Flash, data EEPROM, ID locations
and Configuration bits. The device ID registers
(3FFFFEh:3FFFFFh) should be ignored.
A “blank” or “erased” memory cell will read as a ‘1’.
Therefore, Blank Checking a device merely means to
verify that all bytes read as FFh except the
Configuration bits. Unused (reserved) Configuration
bits will read ‘0 (programmed). Refer to Table 6-1 for
blank configuration expect data for the various
PIC18F1XK22/LF1XK22 devices.
Given that Blank Checking is merely code and data
EEPROM verification with FFh expect data, refer to
Section 5.4 “Read Data EEPROM Memory” and
Section 5.2 “Verify Program Flash and ID Locations”
for implementation details.
FIGURE 5-6: BLANK CHECK FLOW
1234
PGC
P5
PGD
PGD = Input
Shift Data Out
P6
PGD = Output
5678 1234
P5A
91011 13 15161412
Fetch Next 4-bit Command
0100
PGD = Input
LSb MSb
123456
1234
nn n n
P14
(Note 1)
Note 1: Magnification of the high-impedance delay between PGC and PGD is shown in Figure 5-5.
(Note 1)
MSb nn
12
P19
PGD
PGC
P3
Yes
No
Start
Blank Check Device
Is
device
blank? Continue
Abort
PIC18F1XK22/LF1XK22
DS41357B-page 26 Advance Information © 2009 Microchip Technology Inc.
6.0 CONFIGURATION WORD
The PIC18F1XK22/LF1XK22 devices have several
Configuration Words. These bits can be set or cleared
to select various device configurations. All other mem-
ory areas should be programmed and verified prior to
setting Configuration Words. These bits may be read
out normally, even after read or code protection. See
Table 6-1 for a list of Configuration bits and device IDs
and Table 6-3 for the Configuration bit descriptions.
6.1 ID Locations
A user may store identification information (ID) in eight
ID locations mapped in 200000h:200007h. It is recom-
mended that the Most Significant nibble of each ID be
Fh. In doing so, if the user code inadvertently tries to
execute from the ID space, the ID data will execute as
a NOP.
6.2 Device ID Word
The device ID word for the PIC18F1XK22/LF1XK22
devices is located at 3FFFFEh:3FFFFFh. These bits
may be used by the programmer to identify what device
type is being programmed and read out normally, even
after code or read protection. See Table 6-2 for a
complete list of device ID values.
FIGURE 6-1: READ DEVICE ID WORD
FLOW
TABLE 6-1: CONFIGURATION BITS AND DEVICE IDs
Start
Set TBLPTR = 3FFFFE
Done
Read Low Byte
Read High Byte
with Post-Increment
with Post-Increment
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/
Unprogrammed
Value
300001h CONFIG1H IESO FCMEN PRI_CLK_EN PLL_EN FOSC3 FOSC2 FOSC1 FOSC0 0010 0111
300002h CONFIG2L — — BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111
300003h CONFIG2H — — WDPS3 WDPS2 WDPS1 WDPS0 WDTEN ---1 1111
300005h CONFIG3H MCLRE — — HFOFST 1--- 1---
300006h CONFIG4L BKBUG ENHCPU BBSIZ LVP —STVREN10-- 01-1
300008h CONFIG5L — — —CP1CP0---- --11
300009h CONFIG5H CPD CPB 11-- ----
30000Ah CONFIG6L — — WRT1 WRT0 ---- --11
30000Bh CONFIG6H WRTD WRTB WRTC 111- ----
30000Ch CONFIG7L — — EBTR1 EBTR0 ---- --11
30000Dh CONFIG7H —EBTRB -1-- ----
3FFFFEh DEVID1(2) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 See Table 6-2
3FFFFFh DEVID2(2) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 See Table 6-2
Legend: x = unknown, u = unchanged, – = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: These bits are only implemented on specific devices. Refer to Section 3.0 “Memory Maps” to determine which bits apply based on
available memory.
2: DEVID registers are read-only and cannot be programmed by the user.
© 2009 Microchip Technology Inc. Advance Information DS41357B-page 27
PIC18F1XK22/LF1XK22
TABLE 6-2: DEVICE ID VALUE
Device Device ID Value
DEVID2 DEVID1
PIC18LF13K22 4Fh 100x xxxx
PIC18LF14K22 4Fh 011x xxxx
PIC18F13K22 4Fh 010x xxxx
PIC18F14K22 4Fh 001x xxxx
Note: The ‘x’s in DEVID1 contain the device revision code.
PIC18F1XK22/LF1XK22
DS41357B-page 28 Advance Information © 2009 Microchip Technology Inc.
TABLE 6-3: PIC18F1XK22/LF1XK22 BIT DESCRIPTIONS
Bit Name Configuration
Words Description
IESO CONFIG1H Internal External Switchover bit
1 = Internal External Switchover mode enabled
0 = Internal External Switchover mode disabled
FCMEN CONFIG1H Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor enabled
0 = Fail-Safe Clock Monitor disabled
PRI_CLK_EN CONFIG1H Primary Clock Enable bit
1 = Primary Clock enabled
0 = Primary Clock disabled
PLL_EN CONFIG1H 4 X PLL Enable bit
1 = Oscillator multiplied by 4
0 = Oscillator used directly
FOSC<3:0> CONFIG1H Oscillator Selection bits
1111 = External RC oscillator, CLKOUT function on OSC2
1110 = External RC oscillator, CLKOUT function on OSC2
1101 = EC oscillator (low)
1100 = EC oscillator, CLKOUT function on OSC2 (low)
1011 = EC oscillator (medium)
1010 = EC oscillator, CLKOUT function on OSC2 (medium)
1001 = Internal RC oscillator, CLKOUT function on OSC2
1000 = Internal RC oscillator
0111 = External RC oscillator
0110 = External RC oscillator, CLKOUT function on OSC2
0101 = EC oscillator (high)
0100 = EC oscillator, CLKOUT function on OSC2 (high)
0011 = External RC oscillator, CLKOUT function on OSC2
0010 = HS oscillator
0001 = XT oscillator
0000 = LP oscillator
BORV<1:0> CONFIG2L Brown-out Reset Voltage bits
11 =V
BOR set to 1.9V
10 =V
BOR set to 2.2V
01 =V
BOR set to 2.7V
00 =V
BOR set to 3.0V
BOREN<1:0> CONFIG2L Brown-out Reset Enable bits
11 = Brown-out Reset enabled in hardware only (SBOREN is disabled)
10 = Brown-out Reset enabled in hardware only and disabled in Sleep
mode
SBOREN is disabled)
01 = Brown-out Reset enabled and controlled by software (SBOREN is
enabled)
00 = Brown-out Reset disabled in hardware and software
PWRTEN CONFIG2L Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
.
© 2009 Microchip Technology Inc. Advance Information DS41357B-page 29
PIC18F1XK22/LF1XK22
WDPS<3:0> CONFIG2H Watchdog Timer Postscaler Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
WDTEN CONFIG2H Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on SWDTEN bit)
MCLRE CONFIG3H MCLR Pin Enable bit
1 =MCLR pin enabled, RA3 input pin disabled
0 = RA3 input pin enabled, MCLR pin disabled
HFOFST CONFIG3H HFINTOSC Fast Start
1 = HFINTOSC output is not delayed
0 = HFINTOSC output is delayed until oscillator is stable (IOFS = 1)
ENHCPU CONFIG4L Enhanced CPU Enable bit
1 = Enhanced CPU enabled
0 = Enhanced CPU disabled
BBSIZ CONFIG4L Boot Block Size Select bit
1 = 2 kW Boot Block size for PIC18F14K22 (1 kW Boot Block size for
PIC18F13K22)
0 = 1 kW Boot Block size for PIC18F14K22 (512 W Boot Block size for
PIC18F13K22)
LVP CONFIG4L Low-Voltage Programming Enable bit
1 = Low-Voltage Programming enabled, RC3 is the PGM pin
0 = Low-Voltage Programming disabled, RC3 is an I/O pin
STVREN CONFIG4L Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow enabled
0 = Reset on stack overflow/underflow disabled
CP1 CONFIG5L Code Protection bits (Block 1 program Flash area)
1 = Block 1 is not code-protected
0 = Block 1 is code-protected
CP0 CONFIG5L Code Protection bits (Block 0 program Flash area)
1 = Block 0 is not code-protected
0 = Block 0 is code-protected
CPD CONFIG5H Code Protection bits (Data EEPROM)
1 = Data EEPROM is not code-protected
0 = Data EEPROM is code-protected
TABLE 6-3: PIC18F1XK22/LF1XK22 BIT DESCRIPTIONS (CONTINUED)
Bit Name Configuration
Words Description
.
PIC18F1XK22/LF1XK22
DS41357B-page 30 Advance Information © 2009 Microchip Technology Inc.
CPB CONFIG5H Code Protection bits (Boot Block memory area)
1 = Boot Block is not code-protected
0 = Boot Block is code-protected
WRT1 CONFIG6L Write Protection bits (Block 1 program Flash area)
1 = Block 1 is not write-protected
0 = Block 1 is write-protected
WRT0 CONFIG6L Write Protection bits (Block 0 program Flash area)
1 = Block 0 is not write-protected
0 = Block 0 is write-protected
WRTD CONFIG6H Write Protection bit (Data EEPROM)
1 = Data EEPROM is not write-protected
0 = Data EEPROM is write-protected
WRTB CONFIG6H Write Protection bit (Boot Block memory area)
1 = Boot Block is not write-protected
0 = Boot Block is write-protected
WRTC CONFIG6H Write Protection bit (Configuration registers)
1 = Configuration registers are not write-protected
0 = Configuration registers are write-protected
EBTR1 CONFIG7L Table Read Protection bit (Block 1 program Flash area)
1 = Block 1 is not protected from table reads executed in other blocks
0 = Block 1 is protected from table reads executed in other blocks
EBTR0 CONFIG7L Table Read Protection bit (Block 0 program Flash area)
1 = Block 0 is not protected from table reads executed in other blocks
0 = Block 0 is protected from table reads executed in other blocks
EBTRB CONFIG7H Table Read Protection bit (Boot Block memory area)
1 = Boot Block is not protected from table reads executed in other blocks
0 = Boot Block is protected from table reads executed in other blocks
DEV<10:3> DEVID2 Device ID bits
These bits are used with the DEV<2:0> bits in the DEVID1 register to
identify part number.
DEV<2:0> DEVID1 Device ID bits
These bits are used with the DEV<10:3> bits in the DEVID2 register to
identify part number.
REV<4:0> DEVID1 Revision ID bits
These bits are used to indicate the revision of the device.
TABLE 6-3: PIC18F1XK22/LF1XK22 BIT DESCRIPTIONS (CONTINUED)
Bit Name Configuration
Words Description
.
© 2009 Microchip Technology Inc. Advance Information DS41357B-page 31
PIC18F1XK22/LF1XK22
7.0 EMBEDDING CONFIGURATION
WORD INFORMATION IN THE
HEX FILE
To allow portability of code, a PIC18F1XK22/LF1XK22
programmer is required to read the Configuration Word
locations from the hex file. If Configuration Word infor-
mation is not present in the hex file, then a simple warn-
ing message should be issued. Similarly, while saving
a hex file, all Configuration Word information must be
included. An option to not include the Configuration
Word information may be provided. When embedding
Configuration Word information in the hex file, it should
start at address 300000h.
Microchip Technology Inc. feels strongly that this
feature is important for the benefit of the end customer.
7.1 Embedding Data EEPROM
Information In the HEX File
To allow portability of code, a PIC18F1XK22/LF1XK22
programmer is required to read the data EEPROM
information from the hex file. If data EEPROM
information is not present, a simple warning message
should be issued. Similarly, when saving a hex file, all
data EEPROM information must be included. An option
to not include the data EEPROM information may be
provided. When embedding data EEPROM information
in the hex file, it should start at address F00000h.
Microchip Technology Inc. believes that this feature is
important for the benefit of the end customer.
7.2 Checksum Computation
The checksum is calculated by summing the following:
The contents of all program Flash locations
The Configuration Word, appropriately masked
ID locations (Only if any portion of program
memory is code-protected)
The Least Significant 16 bits of this sum are the
checksum.
Code protection limits access to program memory by
both external programmer (code-protect) and code
execution (table read protect). The ID locations, when
included in a code protected checksum, contain the
checksum of an unprotected part. The unprotected
checksum is distributed: one nibble per ID location.
Each nibble is right justified.
Table 7-1 describes how to calculate the checksum for
each device.
Note: The checksum calculation differs
depending on the code-protect setting.
Since the program Flash locations read
out differently depending on the code-
protect setting, the table describes how to
manipulate the actual program Flash
values to simulate the values that would
be read from a protected device. When
calculating a checksum by reading a
device, the entire program Flash can
simply be read and summed. The
Configuration Word and ID locations can
always be read.
Descflpl‘on
PIC18F1XK22/LF1XK22
DS41357B-page 32 Advance Information © 2009 Microchip Technology Inc.
TABLE 7-1: CHECKSUM COMPUTATION
Device Code-Protect
BBSIZ = 0Checksum Blank
Value
0xAA at 0
and Max
Address
PIC18F14K22/
PIC18LF14K22
None SUM[0000:01FFF]+SUM[2000:3FFF]+
(CONFIG1L & 00h)+(CONFIG1H & FFh)+(CONFIG2L & 1Fh)+
(CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 88h)+
(CONFIG4L & CDh)+(CONFIG4H & 00h)+(CONFIG5L & 03h)+
(CONFIG5H & C0h)+(CONFIG6L & 03h)+(CONFIG6H & E0h)+
(CONFIG7L & 03h)+(CONFIG7H & 40h)
C35Bh C2B1h
Boot Block SUM[0800:1FFF]+SUM[2000:3FFF]+
(CONFIG1L & 00h)+(CONFIG1H & FFh)+(CONFIG2L & 1Fh)+
(CONFIG2H & 1F)+(CONFIG3L & 00h)+ (CONFIG3H & 88h)+
(CONFIG4L & CDh)+(CONFIG4H & 00h)+(CONFIG5L & 03h)+
(CONFIG5H & C0h)+(CONFIG6L & 03h)+(CONFIG6H & E0h)+
(CONFIG7L & 03h)+(CONFIG7H & 40h)+SUM_ID
CB3Ah CAE0h
Boot/
Block 0 SUM[2000:3FFF]+
(CONFIG1L & 00h)+(CONFIG1H & FFh)+(CONFIG2L & 1Fh)+
(CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 88h)+
(CONFIG4L & CDh)+(CONFIG4H & 00h)+(CONFIG5L & 03h)+
(CONFIG5H & C0h)+(CONFIG6L & 03h)+(CONFIG6H & E0h)+
(CONFIG7L & 03h)+(CONFIG7H & 40h)+SUM_ID
E537h E2DFh
All (CONFIG1L & 00h)+(CONFIG1H & FFh)+(CONFIG2L & 1Fh)+
(CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 88h)+
(CONFIG4L & CDh)+(CONFIG4H & 00h)+(CONFIG5L & 03h)+
(CONFIG5H & C0h)+(CONFIG6L & 03h)+(CONFIG6H & E0h)+
(CONFIG7L & 03h)+(CONFIG7H & 40h)+SUM_ID
0337h 0332h
PIC18F13K22/
PIC18LF13K22
None SUM[0000:0FFF]+SUM[1000:1FFF]+
(CONFIG1L & 00h)+(CONFIG1H & FFh)+(CONFIG2L & 1Fh)+
(CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 88h)+
(CONFIG4L & CDh)+(CONFIG4H & 00h)+(CONFIG5L & 03h)+
(CONFIG5H & C0h)+(CONFIG6L & 03h)+(CONFIG6H & E0h)+
(CONFIG7L & 03h)+(CONFIG7H & 40h)
E35Bh E2B1h
Boot Block SUM[0400:0FFF]+SUM[1000:1FFF]+
(CONFIG1L & 00h)+(CONFIG1H & FFh)+(CONFIG2L & 1Fh)+
(CONFIG2H & 1F)+(CONFIG3L & 00h)+ (CONFIG3H & 88h)+
(CONFIG4L & CDh)+(CONFIG4H & 00h)+(CONFIG5L & 03h)+
(CONFIG5H & C0h)+(CONFIG6L & 03h)+(CONFIG6H & E0h)+
(CONFIG7L & 03h)+(CONFIG7H & 40h)+SUM_ID
E73Ch E6E2h
Boot/
Block 0 SUM[1000:1FFF]+
(CONFIG1L & 00h)+(CONFIG1H & FFh)+(CONFIG2L & 1Fh)+
(CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 88h)+
(CONFIG4L & CDh)+(CONFIG4H & 00h)+(CONFIG5L & 03h)+
(CONFIG5H & C0h)+(CONFIG6L & 03h)+(CONFIG6H & E0h)+
(CONFIG7L & 03h)+(CONFIG7H & 40h)+SUM_ID
F539h F2E1h
All (CONFIG1L & 00h)+(CONFIG1H & FFh)+(CONFIG2L & 1Fh)+
(CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 88h)+
(CONFIG4L & CDh)+(CONFIG4H & 00h)+(CONFIG5L & 03h)+
(CONFIG5H & C0h)+(CONFIG6L & 03h)+(CONFIG6H & E0h)+
(CONFIG7L & 03h)+(CONFIG7H & 40h)+SUM_ID
0339h 0334h
Legend: Item Description
CONFIGx = Configuration Word
SUM[a:b] = Sum of locations, a to b inclusive
SUM_ID = Byte-wise sum of lower four bits of all customer ID locations
+=Addition
& = Bit-wise AND
© 2009 Microchip Technology Inc. Advance Information DS41357B-page 33
PIC18F1XK22/LF1XK22
8.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/
VERIFY TEST MODE
Standard Operating Conditions
Operating Temperature: 25°C is recommended
Para
m No. Sym. Characteristic Min. Max. Units Conditions
D110 VIHH High-Voltage Programming Voltage on
MCLR/VPP/RA3 89V
D110
AVIHL Low-Voltage Programming Voltage on
MCLR/VPP/RA3 1.80 VDD V
D111 VDD PIC18F1XK22 (includes Bulk Erase) 2.70 5.50 V
PIC18LF1XK22 (includes Bulk Erase) 2.70 3.60 V
D112 IPP Programming Current on MCLR/VPP/RA3 5 mA
D113 IDDP Supply Current During Programming 5 mA
D031 VIL Input Low Voltage VSS 0.2 VDD V
D041 VIH Input High Voltage 0.8 VDD VDD V
D080 VOL Output Low Voltage 0.6 V IOL = 3.0 mA @ 2.7V
D090 VOH Output High Voltage VDD – 0.7 V IOH = -2.0 mA @ 2.7V
D012 CIO Capacitive Loading on I/O pin (PGD) 50 pF To meet AC specifica-
tions
P1 TRMCLR/VPP/RA3 Rise Time to enter
Program/Verify mode —1.0μs(Note 1)
P2 TPGC Serial Clock (PGC) Period 100 ns VDD = 3.6V
1 μs VDD = 1.8V
P2A TPGCL Serial Clock (PGC) Low Time 40 ns VDD = 3.6V
400 ns VDD = 1.8V
P2B TPGCH Serial Clock (PGC) High Time 40 ns VDD = 3.6V
400 ns VDD = 1.8V
P3 TSET1 Input Data Setup Time to Serial Clock 15 — ns
P4 THLD1 Input Data Hold Time from PGC 15 — ns
P5 TDLY1 Delay between 4-bit Command and Command
Operand 40 — ns
P5A TDLY1ADelay between 4-bit Command Operand and next
4-bit Command 40 — ns
P6 TDLY2 Delay between Last PGC of Command Byte to
First PGC of Read of Data Word 20 — ns
P9 TDLY5 PGC High Time (minimum programming time) 1 ms Externally Timed
P9A TDLY5
A
PGC High Time 5 ms Configuration Word
programming time
P10 TDLY6 PGC Low Time after Programming
(high-voltage discharge time) 100 μs
P11 TDLY7 Delay to allow Self-Timed Data Write or
Bulk Erase to occur 5—ms
P11A TDRWT Data Write Polling Time 4 ms
Note 1: Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program
executions to occur. The maximum transition time is:
1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) + 2 ms (for HS/PLL mode
only) + 1.5 μs (for EC mode only) where TCY is the instruction cycle time, TPWRT is the Power-up Timer period
and TOSC is the oscillator period. For specific values, refer to the Electrical Characteristics section of the device
data sheet for the particular device.
PIC18F1XK22/LF1XK22
DS41357B-page 34 Advance Information © 2009 Microchip Technology Inc.
P12 THLD2 Input Data Hold Time from MCLR/VPP/RA3 2—μs
P12A THLD2
A
Input Data Hold Time from MCLR/VPP/RA3 70 μs PIC18F1XK22 Only.
Refer to Figure 2.1.1.
P13 TSET2VDD Setup Time to MCLR/VPP/RA3 100 — ns
P13A TSET2
A
VDD Setup Time to MCLR/VPP/RA3 70 μs PIC18F1XK22 Only.
Refer to Figure 2.1.1.
P14 TVALID Data Out Valid from PGC 10 — ns
P15 TSET3PGM Setup Time to MCLR/VPP/RA3 2—μs
P16 TDLY8 Delay between Last PGC and MCLR/VPP/RA3
0—s
P17 THLD3MCLR/VPP/RA3 to VDD 100 ns
P18 THLD4MCLR/VPP/RA3 to PGM 0—s
P19 THIZ Delay from PGC to PGD High-Z 3 10 nS
P20 TPPDP Hold time after VPP changes 5 μs
8.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/
VERIFY TEST MODE (CONTINUED)
Standard Operating Conditions
Operating Temperature: 25°C is recommended
Para
m No. Sym. Characteristic Min. Max. Units Conditions
Note 1: Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program
executions to occur. The maximum transition time is:
1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) + 2 ms (for HS/PLL mode
only) + 1.5 μs (for EC mode only) where TCY is the instruction cycle time, TPWRT is the Power-up Timer period
and TOSC is the oscillator period. For specific values, refer to the Electrical Characteristics section of the device
data sheet for the particular device.
QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV = ISO/TS 16949:2002 =
© 2009 Microchip Technology Inc. Advance Information DS41357B-page 35
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Hampshire, Linear Active Thermistor, MXDEV,
MXLAB, SEEVAL, SmartSensor and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Total Endurance, TSHARC, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Q ‘MICROCHIP
DS41357B-page 36 Advance Information © 2009 Microchip Technology Inc.
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