TLE7269G Datasheet by Infineon Technologies

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Data Sheet 1 Rev. 1.4
www.infineon.com/automotive-transceivers 2018-06-20
TLE7269G
Twin LIN Transceiver
1 Overview
Features
Two stand-alone LIN transceivers up to 20 kBaud transmission rate
Pin compatible to single LIN Transceivers (e.g TLE7259-3GE)
Compliant to LIN specification 1.3, 2.0, 2.1 and SAE J2602
Very high ESD robustness, ± 8 kV according to IEC61000-4-2
Optimized for low electromagnetic emission (EME)
Optimized for high immunity against electromagnetic interference (EMI)
Very low current consumption in sleep mode with Wake-Up functions
Wake-Up source detection on Wake-Up disable function
Very low leakage current on the BUS output
Control output for voltage regulator
Digital I/O levels compatible for 3.3V and 5V microcontrollers
Bus short to VBAT protection and Bus short to GND handling
Over-temperature and Under-voltage protection
Flash mode and Low-Slope Mode
Green Product (RoHS compliant)
Product validation
Qualified for automotive applications. Product validation according to AEC-Q100.
Description
The TLE7269G is a transceiver for the Local Interconnect Network (LIN) with integrated Wake-Up and
protection features. It is designed for in-vehicle networks using data transmission rates from 2.4 kBaud to
20 kBaud. The TLE7269G functions as a bus driver between the protocol controller and the physical bus inside
the LIN network. Compliant to all LIN standards and with a wide operational supply range the TLE7269G can
be used in all automotive applications.
Two stand-alone LIN transceivers are integrated on one monolithic circuit inside TLE7269G. Both transceivers
offer different operation modes and separate INH outputs to control external circuitry, like voltage regulators.
In Sleep-mode the TLE7269G draws less than 10 mA of quiescent current for both integrated LIN Transceivers,
while both transceivers are still able to wake up off of LIN bus traffic or the local Wake-Up input. The very low
@neon
Data Sheet 2 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Overview
leakage current on the BUS pins makes the TLE7269G especially suitable for partially supplied networks and
supports the low quiescent current requirements of the LIN network.
Based on the Infineon Smart Power Technology SPT®, the TLE7269G provides excellent ESD robustness
together with a very high electromagnetic immunity (EMI). The TLE7269G reaches a very low level of
electromagnetic emission (EME) within a broad frequency range and independent from the battery voltage.
The Infineon Smart Power Technology SPT® allows bipolar and CMOS control circuitry in accordance with
DMOS power devices to exist on the same monolithic circuit. The TLE7269G and the Infineon SPT® technology
are AEC qualified and tailored to withstand the harsh conditions of the Automotive Environment.
Type Package Marking
TLE7269G PG-DSO-14 7269G
@neon
Data Sheet 3 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Normal Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2.1 Normal Slope Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.2 Low Slope Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.3 Flash Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 Stand-By Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 Wake-Up Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.6 Wake-Up Bus2 Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.7 Bus Wake-Up via LIN bus 1 and bus 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.8 Local Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.9 Mode Transition via EN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.10 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.11 TxD Time Out function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.12 Over Temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.13 3.3 V and 5 V Logic Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14 BUS Short to GND Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.15 LIN Specifications 1.2, 1.3, 2.0 and 2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 Functional Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2 Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1 ESD Robustness according to IEC61000-4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2 Pin Compatibility to the Single LIN Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.3 Master Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.4 External Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.5 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table of Contents
@neon
Data Sheet 4 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Block Diagram
2 Block Diagram
Figure 1 Functional Block Diagram
RxD1
12
Bus1
INH1
14
13
VS
3
WK
GND
11
RxD2
Bus2 TxD2
W2O
INH2
VIO
8
Driver
Current
Limit
10
5
RTD
Temp -
Sensor
VS
Receiver
Filter
Wake and Bus
Comparators
Filter
Receiver
Filter
Mode
Control
Output
Stage 1
Driver
Current
Limit
RBUS
VS
RBUS
VS
TxD Input
Timeout
TxD Input
Timeout TxD1
4
RTD
1
6
7
VIO
RW2O
EN
REN
2
9
Output
Stage 2
@neon
Data Sheet 5 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Pin Configuration
3 Pin Configuration
3.1 Pin Assignment
Figure 2 Pin Configuration (top view)
Note: The pin configuration of the TLE7269G is pin compatible to the devices TLE7259-3GE and TLE7258/
TLE7257. In comparison to the TLE7259-3GE and the TLE7258/TLE7257, no pull up resistors on the RxD
pins are required for the TLE7269G. Details can be found inside the “Pin Compatibility to the Single LIN
Transceivers” on Page 28.
3.2 Pin Definitions and Functions
Table 1 Pin Definitions and Functions
Pin No. Symbol Function
1 RxD1 Receive data output 1;
LOW in dominant state, active LOW after a Wake-Up event at BUS1 or WK pin
2ENEnable input;
integrated pull-down, device set to normal operation mode when HIGH
3WKWake input;
active LOW, negative edge triggered, internal pull-up
4TxD1Transmit data input 1;
integrated pull-down, LOW in dominant state; active LOW after Wake-Up via WK pin
5TxD2Transmit data input 2;
integrated pull-down, LOW in dominant state
6V
IO Logic Voltage supply input;
3.3V or 5V supply for the RxD and TxD pins
7 RxD2 Receive data output 2;
LOW in dominant state, active LOW after a Wake-Up event at BUS2
RxD1
1
2
3
4
5
6
78
EN
WK
TxD1
INH1
V
S
BUS1
GND
TxD2
V
IO
RxD2
BUS2
W2O
INH2
9
10
11
12
13
14
@neon
Data Sheet 6 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Pin Configuration
8 INH2 Inhibit output 2;
battery supply related output
HIGH (VS) in Normal and Stand-By operation mode
can be used to control an external voltage regulator
can be used to control external bus termination resistor when the device will be used
as Master node
9W2OWake BUS 2 OFF;
switch off Wake-Up feature on BUS 2; active HIGH,
integrated pull-down
10 BUS 2 Bus 2 input / output;
LIN bus line input/output
LOW in dominant state
Internal termination and pull-up current source
11 GND Ground
12 BUS 1 Bus 1 input / output;
LIN bus line input/output
LOW in dominant state
Internal termination and pull-up current source
13 VSBattery supply input
14 INH1 Inhibit output 1;
battery supply related output
HIGH (VS) in Normal and Stand-By operation mode
can be used to control an external voltage regulator
can be used to control external bus termination resistor when the device will be used
as Master node
Table 1 Pin Definitions and Functions (cont’d)
Pin No. Symbol Function
@neon
Data Sheet 7 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Functional Description
4 Functional Description
The LIN Bus is a single wire, bi-directional bus, used for in-vehicle networks. The LIN Transceiver TLE7269G is
the interface between the microcontroller and the physical LIN Bus (see Figure 17 and Figure 18). The logical
values of the microcontroller are driven to the LIN bus via the TxD inputs of the TLE7269G. The transmit data
stream on the TxD input is converted to a LIN bus signal with optimized slew rate to minimize the EME level of the
LIN network. The RxD outputs read back the information from the LIN bus to the microcontroller. The receiver has
an integrated filter network to suppress noise on the LIN Bus and to increase the EMI (Electro Magnetic Immunity)
level of the transceiver.
Two logical states are possible on the LIN bus according to the LIN Specification 2.1 (see Figure 3):
In dominant state, the voltage on the LIN bus is set to the GND level. In recessive state, the voltage on the LIN
bus is set to the supply voltage VS. By setting the TxD1, TxD2 inputs of the TLE7269G to “Low” the transceiver
generates a dominant level on the BUS1, BUS2 LIN interface pins. The RxD1, RxD2 outputs read back the signal
on the LIN bus and indicate a dominant signal on the LIN bus with a logical “Low” to the microcontroller. Setting
the TXD1, TxD2 pins to “High” the transceiver TLE7269G sets the BUS1, BUS2 LIN interface pins to recessive
level, at the same time the recessive level on the LIN bus is indicated by a logical “High” on the RxD1, RxD2
outputs.
Every LIN network consists of a master node and one or more slave nodes. To configure the TLE7269G for master
node applications, a resistor in the range of 1 kΩ and a reverse diode must be connected between the LIN bus
and the power supply VS or between the LIN bus and INH pin of the TLE7269G (see Figure 17 and Figure 18).
Both integrated transceivers can operate independent from each other and several operation modes and Wake-
Up functions are implemented. The bus Wake-Up function of the transceiver 2 can be turned off via the W2O pin.
Figure 3 LIN bus signals
t
TxD1
TxD2
VIO
RecessiveRecessive
BUS1
BUS2
VSRecessive Dominant Recessive
t
t
VIO
RecessiveRecessive
RxD1
RxD2
Dominant
Dominant
@neon
Data Sheet 8 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Functional Description
4.1 Operating Modes
Figure 4 Operation Mode State Diagram
The TLE7269G has 3 major operation modes:
Status TxD1?
HIGHLOW
Stand-By Mode
Low Slope Mode
(Transceiver 1 &
Transceiver 2)
Sleep Mode
INH1/INH2 = Float
EN = LOW
RxD1/RxD2 = Float
Status W2O ?
INH1, INH2 = HIGH
TxD1 (see Note 1)
RxD1, RxD2 (see Note 2)
Note 1:
TxD1: Strong Pull Down > 1.5 mA
after Wake-Up via pin WK
TxD1: Weak Pull Down 350 kΩ
after Power-Up and
Wake-Up via BUS1 or BUS2
INH1 = HIGH
INH2 = HIGH
EN = HIGH
Flash Mode
(Transceiver 1 &
Transceiver 2)
INH1 = High
INH2 = High
EN = High
Normal Operation Mode
Note 2:
RxD1: logical „High“
after Power-Up
RxD1: logical „Low“
after Wake-Up via BUS1 or BUS2
or after Wake-Up via pin WK
RxD2: logical „Low“
after Wake-Up via BUS2
Start-Up
Power-Up
EN
EN
TxD1
EN High
Normal Slope Mode
(Transceiver 1 &
Transceiver 2)
INH1 = HIGH
INH2 = HIGH
EN = HIGH
TxD1
EN
TxD1
EN
EN EN
EN
HIGHLOW
Bus Wake-Up
feature on BUS2
turned off!
Sleep Mode
INH1/INH2 = Float
EN = LOW
RxD1/RxD2 = Float
EN Low
EN EN
Wake-Up
via on pin Wk
via  on pin BUS1 or BUS2
Wake-Up
via on pin Wk
via  on pin BUS1 only !
TxD1
EN High
EN Low
Go To Normal
Operation Mode
Go To
Sleep Mode
@neon
Data Sheet 9 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Functional Description
Stand-By mode
Normal Operation mode
Sleep mode
The Normal Operation mode contains 3 sub-operation modes, which differentiate by the slew rate control of the
LIN Bus signal (see Figure 4).
Sub-operation modes with different slew rates on the BUS1,BUS2 pins:
Low Slope mode, for data transmission rates up to 10.4 kBaud
Normal Slope mode, for data transmission rates up to 20 kBaud
Flash mode, for programming of the external microcontroller
The TLE7269G contains 2 separate LIN transceivers, which are able to operate in two independent LIN networks
with two different data transmission rates. The operation mode of the TLE7269G is selected by the EN pin and the
TxD1 pin. Selecting the operation mode applies to the whole device. Transceiver1 and transceiver2 are always
set to the same operation mode and sub-operation mode (see Figure 4).
4.2 Normal Operation Mode
The TLE7269G enters the Normal Operation mode after the microcontroller sets EN to “High” (see
Figure 4
). In
Normal Operation mode both LIN bus receivers and both LIN bus transmitters are active. Data from the
microcontroller is transmitted to the LIN bus1 or LIN bus2 via the TxD1 or TxD2 pin, the receiver detects the data
stream on the LIN bus1 or bus2 and forwards it to the RxD1 or RxD2 output pins. In Normal Operation mode, the
INH1 pin and the INH2 are “High” (set to
V
S
) and the bus termination is set to 30 k
Ω
for both integrated transceivers.
Normal Slope mode, Low Slope mode and the Flash mode are Normal Operation modes and in these sub-modes
the behavior of the INH pin and the bus termination is the same. To set the device into one of these 3 sub-modes
the TxD1 pin and the EN pin are used for the sub-operation mode selection. In order to avoid any bus disturbance
during a mode change, the output stages of the TLE7269G are disabled and set to recessive state during the
mode change procedure. To release the TLE7269G for data communication on the LIN bus1 and LIN bus2, the
TxD1 and TxD2 pins need to be set to “High” for the time tto,rec.
Table 2 Operating modes
Mode EN INH1
INH2
TxD1
TXD2
RxD1
RxD2
LIN Bus
Termination
Comments
Sleep Low Floating Low High
resistive
High
Impedance
No Wake-Up request detected
Stand-By Low High Low
High2)
Low
High 1)
1) To indicate the Wake-Up sources via the RxD pins the power supply VIO has to be present
30 kΩ
(typical)
RxD1 “Low” after local or bus Wake-Up (BUS 1,
BUS 2)
RxD2 “Low” after bus Wake-Up on Bus2. RxD2
“High” on all other Wake-Up and Power-Up events.
RxD1 “High” after Power-Up
TxD1 strong pull down after local Wake-Up (WK
pin)
2)
TxD1 weak pull down after bus Wake-Up (BUS1,
BUS2) or Power-Up
2)
2) The TxD1 input needs an external termination to indicate a “High” or a “Low” signal. The external termination could be a
pull-up resistor or an active microcontroller output.
Normal
Operation
High High Low
High
Low
High
30 kΩ
(typical)
RxD1, RxD2 reflects the signal on the BUS1,
BUS2
TxD1,TxD2 driven by the microcontroller
@neon
Data Sheet 10 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Functional Description
4.2.1 Normal Slope Mode
In Normal Slope mode data transmission rates up to 20 kBauds are possible. Setting the EN pin to “High” starts
the transition to Normal Operation mode. Depending on the signal on the TxD1 pin, the TLE7269G changes either
into Normal Slope mode or Low Slope mode (see Figure 5).
The mode change to Normal Slope mode is defined by the time tMODE and the time tTXD,SET. The time tMODE
specifies the delay time between the threshold, where the EN pin detects a “High” input signal, and the actual
mode change of TLE7269G into Normal Slope mode. The time tTXD,SET defines the setup time in which the TxD1
pin has be set to “High”. After the time tTXD,SET expires, the logical “High” signal on the TxD1 pin has to be stable
to put the part into Normal Slope mode.
In the time window tMODE - tTXD,SET the TLE7269G makes the transition to Normal Slope mode but remains in Stand-
By mode until the time tMODE expires.
Finally to release the data communication it is required to set the TxD1 and the TxD2 pin to “High” for the time tto,rec.
Figure 5 Timing to enter Normal Slope Mode
4.2.2 Low Slope Mode
In Low Slope mode data transmission rates up to 10.4 kBauds are possible. Setting the EN pin to “High” starts the
transition to Normal Operation mode. Depending on the signal of the TxD1 pin the TLE7269G changes either into
Normal Slope mode or Low Slope mode (see Figure 6).
The mode change to Low Slope mode is defined by the time tMODE and the time tTXD,SET. The time tMODE specifies
the delay time between the threshold, where the EN pin detects a “High” input signal, and the actual mode change
of TLE7269G to Low Slope mode. The time tTXD,SET defines the setup time in which the TxD1 pin can be set to
“Low”. After the time tTXD,SET expires, the logical “Low” signal on the TxD1 pin has to be stable to put the part into
Low Slope mode.
In the time window tMODE - tTXD,SET the TLE7269G makes the transition into Low Slope mode but remains in Stand-
By mode until the time tMODE expires.
Finally to release the data communication it is required to set the TxD1 and the TxD2 pin to “High” for the time tto,rec.
@neon Normal Slope Mode Low S‘ope EN Mode tm Flash Mode [m
Data Sheet 11 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Functional Description
.
Figure 6 Timing to enter Low Slope Mode
4.2.3 Flash Mode
In Flash mode it is possible to transmit and receive LIN messages on the LIN bus. The slew rate control
mechanism of the LIN bus signal is disabled. This allows higher data transmission rates, disregarding the EMC
limitations of the LIN network. The Flash mode is intended to be used during the ECU production for programming
the microcontroller via the LIN bus interface.
The TLE7269G can be set to Flash mode either from Normal Slope mode or from Low Slope mode (see Figure 4).
Flash mode is entered by setting the EN pin to “Low” for the time tfl1 and generating a falling and a rising edge at
the TxD1 pin with the timing tfl2, tfl3 and tfl4 (see Figure 7). Leaving the Flash mode by the same sequence, sets
the TLE7269G back to its previous state, be that either Normal Slope mode or Low Slope mode. Finally to release
the data transmission it is required to set the TxD1 pin and the TxD2 pin to “High” for the time tto,rec.
The TLE7269G can be set from Flash mode directly to Sleep mode by switching the EN pin to “Low”. Setting the
pin EN to “High” again, the device will return to Flash mode.
Figure 7 Timing to enter and exit Flash Mode
4.3 Stand-By Mode
The Stand-By mode is entered automatically after:
Normal Slope Mode
Low Slope Mode
TxD1
EN
tfl3
Data transmission
tfl1
Flash Mode
tfl2 tfl4
tfl1
Data transm.
Normal Slope Mode
Low Slope Mode
tfl3
tfl2 tfl4
ttorec ttorec
@neon
Data Sheet 12 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Functional Description
A Power-Up event on the supply VS.
A bus Wake-Up event on pin BUS1 or pin BUS2.
A local Wake-Up event on the pin WK.
A power on reset caused by power supply VS or by the power supply VIO
In Stand-By mode the Wake-Up sources are monitored by the TxD1, RxD1 and RxD2 pins.
In Stand-By mode no communication on the LIN Bus is possible. The output stages are disabled and the LIN Bus
termination remains activated on both integrated transceivers. Only the RxD1, RxD2 and the TxD1 pin are used
to indicate the Wake-Up source. The TxD2 pin remains inactive. The RxD1 pin remains “Low” after a local Wake-
Up event on the pin WK and a bus Wake-Up event on either the bus 1 or the bus 2. The RxD2 pin remains “Low”
only after a bus Wake-Up event on the bus 2. A Power-Up event is indicated by a logical “High” on the RxD1 pin.
The signal on the TxD1 pin indicates the Wake-Up source, a weak pull-down signals a bus Wake-Up event on the
bus 1 and bus 2 and a strong pull-down signals a local Wake-Up event caused by the WK pin (see Table 2 and
Table 3). In order to detect a Wake-Up event via the TxD1 pin, the external microcontroller output needs to provide
a logical “High” signal. The Wake-Up flags indicating the Wake-Up source on the pins TxD1, RxD1 and RxD2 are
reset by changing the operation mode to Normal Operation mode.
The signal on the EN pin remains “Low” due to an internal pull-down resistor. Setting the EN pin to “High”, by the
microcontroller returns the TLE7269G to Normal Operation mode. In Stand-By mode the INH1 and INH2 outputs
are switching to VS. The INH outputs can be used to control external device like a voltage regulator.
Table 3 Logic table for wake up monitoring
Inputs Outputs
power up WK BUS1 BUS2 RxD11)
1) To indicate the Wake-Up or Power-Up event on the RxD pin, the supply VIO has to be present
RxD21) TxD12)
2) The TxD1 input needs an external termination to indicate a “High” or a “Low” signal. The external termination could be a
pull-up resistor or an active microcontroller output.
Remarks
Yes 1 1 1 1 1 1 No Wake-Up, Power-Up event
No Wake-
Up3)
3) A local Wake-Up event is considered after a low signal on the pin WK (see Chapter 4.8).
1 1 0 1 0 Wake via wake pin
No 1 Wake-
Up4)
1 0 1 1 Wake via BUS1
No 1 1 Wake-
Up4)
4) A bus Wake-Up event is considered after the low to high transition on the bus (see Chapter 4.7).
Note: In the case of a sequence of Wake-Up events only the first Wake-Up event will be monitored on TxD1, RxD1
and RxD2. Subsequent Wake-Up events are ignored.
0 0 1 Wake via BUS2
@neon
Data Sheet 13 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Functional Description
4.4 Sleep Mode
In order to reduce the current consumption the TLE7269G offers a Sleep mode. In Sleep mode the quiescent
current on VS and the leakage current on the pins BUS1 and BUS2 are cut back to a minimum.
To switch the TLE7269G from Normal Operation mode to Sleep mode, the EN pin has to be set to “Low”.
Conversely a logical “High” on the EN pin sets the device directly back to Normal Operation mode (see Figure 4).
While the TLE7269G is in Sleep mode the following functions are available:
The output stages are disabled and the internal bus terminations are switched off (High Impedance on the pins
BUS1 and BUS2). Internal current sources on the bus pins ensure that the levels on the pins BUS1 and BUS2
remain recessive and protect the LIN network against accidental bus Wake-Up events.
The receiver stages are turned off.
RxD1, RxD2 output pins are inactive and “High resistive”. The TxD1, TxD2 pins are disabled. The logical state
on the TxD1 pin and the TxD2 pin is “Low” due to the internal pull-down resistors.
The INH1 and INH2 outputs are switched off and floating.
The bus Wake-Up comparator is active and turns the TLE7269G to Stand-By mode in case of a bus Wake-Up
event.
The WK pin is active and turns the TLE7269G to Stand-By mode in case of a local Wake-Up.
The EN pin remains active, switching the EN pin to “High” changes the operation mode to Normal Operation
mode.
4.5 Wake-Up Events
A Wake-Up event changes the operation mode of the TLE7269G from Sleep mode to Stand-By mode. Both
integrated transceivers are changing the mode.
There are 4 different ways to Wake-Up the TLE7269G from Sleep mode.
Bus or also called remote Wake-Up via a dominant signal on the pin BUS1.
Bus or also called remote Wake-Up via a dominant signal on the pin BUS2.
Local Wake-Up via a minimum dominant time (tWK) on the WK pin.
Mode change from Sleep mode to Normal Operation mode, by setting EN pin to logical “High”.
4.6 Wake-Up Bus2 Off
A Wake-Up event on the LIN bus1 or on the bus2 wakes up the TLE7269G and sets it to Stand-By mode. In
applications where a Wake-Up via bus1 is required but a Wake-Up via bus2 is not wanted, the bus Wake-Up event
on the BUS2 can be disabled. This is done by setting the W2O pin to “High”. During the mode change from Normal
Operation mode to Sleep mode the TLE7269G checks for the status on the pin W2O. In case the W2O pin is
“High”, the Wake-Up feature for the transceiver 2 will be disabled. The TLE7269G can still be wake off by a bus
Wake-Up event on LIN bus1 or by a local Wake-Up event on the pin WK. A bus Wake-Up event on the bus 2 won’t
be recognized and the device remains in Sleep mode (see Figure 4).
In case the Wake-Up Bus2 Off feature is not used, the W2O pin can be left open, due to the internal pull-down
resistor, a not connected W2O pin is set to logical “Low”. The function of the EN pin remain unchanged.
@neon
Data Sheet 14 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Functional Description
4.7 Bus Wake-Up via LIN bus 1 and bus 2
Figure 8 Bus Wake-Up behavior
The bus Wake-Up event, often called remote Wake-Up, changes the operation mode from Sleep mode to Stand-
By mode. The TLE7269G wakes-up via a bus Wake-Up event on either the pin BUS1 or BUS2. The bus Wake-
Up behavior is identical on both pins. A falling edge on the LIN bus, followed by a dominant bus signal t > tWK,bus
results in a bus Wake-Up event. The mode change to Stand-By mode becomes active with the following rising
edge on the LIN bus. The TLE7269G remains in Sleep mode until it detects a change from dominant to recessive
on the LIN bus (see Figure 8).
In Stand-By mode the TxD1 pin indicates the source of the Wake-Up event, the TxD2 pin remains inactive. A weak
pull-down on the pin TxD1 indicates a bus Wake-Up event (see Figure 4 or Table 2). The RxD1 pin signals if a
Wake-Up event occurred or the power-up event. A “Low” signal on the RxD1 pin reports a local or bus Wake-Up
event, a logical “High“ signal on RxD1 indicates a power-up event. A “Low” signal on the RxD2 pin indicates a
Wake-Up event on the pin BUS2.
VBUS1 &2
VBUS,dom
VBUS,wk
LIN BUS1 or BUS2 Signal
Sleep Mode Stand-By Mode
INH1/
INH2
tWK,bus
@neon Q
Data Sheet 15 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Functional Description
4.8 Local Wake-Up
Figure 9 Local Wake-Up behavior
Beside the remote Wake-Up, a Wake-Up of the TLE7269G via the WK pin is possible. This type of Wake-Up event
is called “Local Wake Up”. A falling edge on the WK pin followed by a “Low” signal for t > tWK results in a local
Wake-Up (see Figure 9) and changes the operation mode to Stand-By mode.
In Stand-By mode the TxD1 pin indicates the source of the Wake-Up event, the TxD2 pin remains inactive. A
strong pull-down on the pin TxD1 indicates a bus Wake-Up event (see Figure 4). The RxD1 pin signals if a Wake-
Up event or the Power-Up event occurred. A “Low” signal on the RxD1 pin reports a local or bus Wake-Up event,
a logical “High” signal on RxD1 indicates a Power-Up event. A “Low” signal on the RxD2 pin indicates a Wake-Up
event on the pin BUS2.
4.9 Mode Transition via EN pin
Figure 10 Mode Transition via EN pin
It is also possible to change from Sleep mode to Normal Operation mode by setting the EN pin to logical
“High”.This feature is useful if the external microcontroller is continuously powered and not connected to the INH1
pin or the INH2 pin. The EN pin has an integrated pull-down resistor to ensure the device remains in Sleep or
Stand-By mode even if the voltage on the EN pin is floating. The EN pin has an integrated hysteresis to avoid the
toggling of the operation modes during the transition of the EN signal (see Figure 10).
A transition from logical “High” to logical “Low” on the EN pin changes the operation mode from Normal Operation
mode to Sleep mode. If the TLE7269G is already in Sleep mode, changing the EN from “Low” to “High” results into
VWK
VWK,L
WK Signal
Sleep Mode Stand-By Mode
INH1/
INH2
tWK
VEN
EN Signal
VEN,OFF
Sleep Mode /
Stand-By Mode
tMODE
VEN,ON
EN Hysteresis
Sleep ModeNormal Operation Mode
tMODE
Power On reset Supply voltage Vs
Data Sheet 16 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Functional Description
a mode change from Sleep mode to Normal Operation mode. If the device is in Stand-By mode a change from
“Low” to “High” on the EN pin changes the mode to Normal Operation mode (see Figure 4).
4.10 Power-On Reset
Figure 11 Power-on reset and Under-Voltage situation
A dropping power supply VS or a dropping microcontroller supply VIO on a local ECU can effect the communication
of the whole LIN network. To avoid any blocking of the LIN network by a local ECU the TLE7269G has an
integrated Power-On reset at the supply VS and an Under-Voltage detection at the supply VS and the supply VIO.
In case the supply voltage VS is dropping below the Power-On reset level VS < VS,UV,PON, the TLE7269G changes
the operation mode to Stand-By mode. In Stand-By mode the output stage of the TLE7269G is disabled and no
communication to the LIN bus is possible. The internal bus termination remains active as well as the INH pins (see
Figure 11 and Figure 4).
In Stand-By mode the RxD1 pin signals the low power supply condition with a “High” signal. A logical “High” on
the EN pin changes the operation mode back to Normal Operation mode.
In case the supply voltage VS is dropping below the specified operation range (see Table 5), the TLE7269G
disables the output and receiver stages. This feature secures the communication on the LIN bus. If the power
Supply voltage Vs
Power on reset level VS,UV,PON
Power On reset
Normal Operation
Mode
Reset and
Communication
blocked
Stand-By
Mode
Blanking time tblank,UV
Supply voltage Vs
Power on reset level VS,UV,PON
Normal Operation
Mode Communication
blocked
Blanking time tblank,UV
Undervoltage level VS,UV,BLK
Normal Operation
Mode
Under Voltage
Detection VS
Supply voltage VIO
Normal Operation
Mode Communication
blocked
Blanking time tblank,UV
Undervoltage level VIO,UV
Normal Operation
Mode
Under Voltage
Detection VIO
@neon
Data Sheet 17 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Functional Description
supply VS reaches a higher level as the Under-Voltage level VS > VS,UV,BLK the TLE7269G continues with normal
operation. A mode change only applies if the power supply VS drops below the power on reset level (VS <
VS,UV,PON).
If the power supply VIO drops below the Under-Voltage level VIO > VIO,UV the output and receiver stages will be
disabled as well. When VIO reaches a higher level as the Under-Voltage VIO > VIO,UV level the TLE7269G continues
with normal operation and data transmission.
4.11 TxD Time Out function
If the TxD1 or TxD2 signal is dominant for a time t > ttimeout the TxD time-out function deactivates the transmission
of the LIN signal to the bus and disables both, the output stage 1 and the output stage 2. This is realized to prevent
the bus from being blocked by a permanent “Low” signal on the TxD1 or TxD2 pin, caused by an error on the
external microcontroller (see Figure 12).
The transmission is released again, after a rising edge at TxD1 or TxD2 has been detected.
Figure 12 TxD Time-Out function
4.12 Over Temperature protection
The TLE7269G has one integrated over temperature sensor to protect the device against thermal overstress on
the output stage 1 and output stage 2. In case of an over temperature event, the temperature sensor will disable
both output stages (see Figure 1). An over temperature event will not cause any mode change nor will it be
signaled by either the RxD pins or the TxD pins. When the junction temperature falls below the thermal shut down
TxD1
ttorec
BUS1
TxD2
BUS2
ttimeout
Normal Communication
Normal Communication
TxD Time-Out due to
microcontroller error Release after TxD
Time-out
Recovery of the
microcontroller error
ttorec
ttimeout
Normal Communication
Normal Communication
TxD Time-Out due to
microcontroller error Release after TxD
Time-out
Recovery of the
microcontroller error
t
t
t
t
@neon
Data Sheet 18 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Functional Description
level TJ < TjSD, the output stages are re-enabled and data communication can start again on BUS1 and BUS2. A
10°C hysteresis avoids toggling during the temperature shut down.
4.13 3.3 V and 5 V Logic Capability
The TLE7269G can be used for 3.3 V and 5 V microcontrollers. The inputs and the outputs are capable to operate
with both voltage levels. The logic level is defined by suppling 3.3V or 5V to the VIO. The inputs (TxD1, TxD2) take
the reference voltage from the VIO pin. The RxD1 output and RxD2 output are push-pull outputs, they work on the
voltage given by VIO pin. No external pull-up resistors are required.
The pin EN works without the voltage on the microcontroller supply VIO. The TLE7269G can be set from Sleep
mode to Normal Operation mode by setting EN to “High”, without supplying VIO.
4.14 BUS Short to GND Feature
The TLE7269G has a feature implemented to protect the battery from running out of charge in the case of BUS
short to GND failure.
In this failure case a normal master termination, a 1 kΩ resistor and diode between the LIN bus and the power
supply VS, would cause a constantly drawn current even in sleep mode. The resulting resistance of this short to
GND is in the range 1 kΩ. To avoid this current during a generator off state, like in a parked car, the TLE7269G
has a bus short to GND feature implemented, which is activated in Sleep mode.
This feature is only applicable, if the master termination of BUS1 is connected to INH1 pin and the master
termination of BUS2 is connected to INH2 pin, instead of being connected to the power supply VS (see Figure 17
and Figure 18). Internally, the 30 kΩ path is also switched off from the power supply VS (see Figure 1).
A separate Master Termination Switch is implemented at pins BUS1 and BUS2, to avoid a voltage drop on the
recessive level of LIN bus, in case of a dominant level or a short to ground on at the LIN bus.
4.15 LIN Specifications 1.2, 1.3, 2.0 and 2.1
The device fulfills the Physical Layer Specification of LIN 1.2, 1.3, 2.0 and 2.1.
The differences between LIN specification 1.2 and 1.3 is mainly the physical layer specification. The reason was
to improve the compatibility between the nodes.
The LIN specification 2.0 is a super set of the 1.3 version. The 2.0 version offers new features. However, it is
possible to use the LIN 1.3 slave node in a 2.0 node cluster, as long as the new features are not used. Vice versa
it is possible to use a LIN 2.0 node in the 1.3 cluster without using the new features.
In terms of the physical layer the LIN 2.1 Specification doesn’t include any changes and is fully compliant to the
LIN Specification 2.0.
LIN 2.1 is the latest version of the LIN specification, released in December 2006.
@neon
Data Sheet 19 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
General Product Characteristics
5 General Product Characteristics
5.1 Absolute Maximum Ratings
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Table 4 Absolute Maximum Ratings1)
All voltages with respect to ground; positive current flowing into pin;
(unless otherwise specified)
1) Not subject to production test, specified by design
Pos. Parameter Symbol Limit Values Unit Remarks
Min. Max.
Voltages
5.1.1 Battery supply voltage VS-0.3 40 V LIN Spec 2.1 Param. 10
5.1.2 Logic supply voltage VIO -0.3 5.5 V –
5.1.3 Bus and WK input voltage
versus GND
versus VS
VBUS,G
VBUS,Vs
-40
-40
40
40
V
V
5.1.4 Logic voltages at EN, W2O,
TxD1, TxD2, RxD1, RxD2
Vlogic -0.3 5.5 V –
5.1.5 INH1, INH2 voltage
versus GND
versus VS
VINH,G
VINH,Vs
-0.3
-40
40
0.3
V
V
Currents
5.1.6 Output current at INH1,
INH2
IINH -150 80 mA 2)
2) Output current is internally limited to -150 mA
Temperatures
5.1.7 Junction temperature Tj-40 150 °C–
5.1.8 Storage temperature Ts-55 150 °C–
ESD Resistivity
5.1.9 Electrostatic discharge
voltage at VS, BUS1, BUS2,
WK versus GND
VESD -6 6 kV Human Body Model
(100pF via 1.5 kΩ)3)
3) ESD susceptibility HBM according to EIA / JESD 22-A 114
5.1.10 Electrostatic discharge
voltage W2O versus VS
VESD -1 1 kV Human Body Model
(100pF via 1.5 kΩ)3)
5.1.11 Electrostatic discharge
voltage all pins except W2O
versus VS
VESD -2 2 kV Human Body Model
(100pF via 1.5 kΩ)3)
@neon
Data Sheet 20 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
General Product Characteristics
5.2 Functional Range
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
5.3 Thermal Characteristics
Table 5 Operating Range
Pos. Parameter Symbol Limit Values Unit Remarks
Min. Typ. Max.
Supply voltages
5.2.1 Supply Voltage Range for
Normal Operation
VS(nor) 7 27 V LIN Spec 2.1 Param. 10
5.2.2 Extended Supply Voltage
range for operation
VS(ext) 5 40 V Parameter deviations
possible
5.2.3 Supply voltage VIO VIO 3–5.5V
Thermal parameters
5.2.4 Junction temperature Tj-40 150 °C1)
1) Not subject to production test, specified by design
Table 6 Thermal Characteristics1)
1) Not subject to production test, specified by design
Pos. Parameter Symbol Limit Values Unit Remarks
Min. Typ. Max.
Thermal Resistance
5.3.1 Junction to Soldering
Point
RthJSP 25 K/W measured to pin 11
5.3.2 Junction to Ambient RthJA –130–K/W
2)
2) JESD 51-2, 51-3, FRA4 76,2 mm x 114,3 mm x 1,5 mm, 70 μm Cu, minimal footprint, Ta = 27°C
Thermal Shutdown Junction Temperature
5.3.3 Thermal shutdown temp. TjSD 150 170 190 °C–
5.3.4 Thermal shutdown hyst. ΔT–10–K
@neon
Data Sheet 21 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Electrical Characteristics
6 Electrical Characteristics
6.1 Functional Device Characteristics
Table 7 Electrical Characteristics
7.0 V < VS < 27 V; RL = 500 Ω; Vio = 5V; -40 °C < Tj < 150 °C; all voltages with respect to ground; positive current
flowing into pin; unless otherwise specified.
Pos. Parameter Symbol Limit Values Unit Remarks
Min. Typ. Max.
Current Consumption
6.1.1 Current consumption at
VS(both channels recessive)
IS,rec 0.5 1.6 3.0 mA
recessive state, without
R
L
;
VS = 13.5 V
VTxD = Vio
6.1.2 Current consumption normal
mode at Vio
IVIO,norm 10 50 µA Normal Operation mode.
VIO=5 V
6.1.3 Current consumption
at VS (both channels
dominant)
IS,dom 3 5.0 mA dominant state, without RL;
VS = 13.5 V;
VTxD = 0 V
6.1.4 Current consumption
in sleep mode at Vio
IVIO,Sleep 1 10 µA Sleep mode, VIO=5 V
6.1.5 Current consumption
in sleep mode
IS,Sleep 7 12 µA Sleep mode,
VS = 18 V;
VBUS= VWK = VS;
6.1.6 Current consumption in sleep
mode
IS,Sleep,typ 5 10 µA Sleep mode, Tj < 85 °C;
VS = 13.5 V;
VWK= VS= VBUS;
Under Voltage Detection
6.1.7 Blocking under voltage
detection at VS
(VS on the falling edge)
Vs,UV,BLK 3.5 5 V Communication blocked
no reset (see Figure 11)
6.1.8 Power ON under voltage
detection at VS
Vs,UV,PON 3.5 V Device reset to Stand-By-
Mode 1)(see Figure 11)
6.1.9 Under voltage detection at VIO VIO,UV 1.5 2.5 3 V Communication blocked
no reset (see Figure 11)
6.1.10 Under voltage blanking time tblankUV –5–µs
1)
Receiver Outputs: RxD1, RxD2
6.1.11 HIGH level output current IRD,H –10 -4 -2 mA VRD = 0.8 × VIO
6.1.12 LOW level output current IRD,L 2410mAVRD = 0.2 × VIO
@neon
Data Sheet 22 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Electrical Characteristics
Transmission Inputs: TxD1, TxD2
6.1.13 HIGH level input voltage
range
VTD,H 0.7 ×
VIO
VIO V Recessive state
6.1.14 Input hysteresis VTD,hys –0.12 ×
VIO
–V
1)
6.1.15 LOW level input voltage range VTD,L 0 0.3 ×
VIO
V Dominant state
6.1.16 Pull-down resistance RTD 100 350 800 kΩVTxD = Vio
6.1.17 Low level leakage current ITD –010µAVEN = 0 V;
VTxD = 0 V
6.1.18 Dominant current standby
mode after Wake-Up
ITD,L 1.5 3 10 mA VTxD = 0.9 V; WK = 0 V;
VS = 13.5 V.
Only valid for TxD 1
6.1.19 Input capacitance Ci 5 pF 1)
W2O Input
6.1.20 HIGH level input voltage
range
VW2O,H 0.7 ×
VIO
VIO V–
6.1.21 LOW level input voltage range VW2O,L 0 0.3 ×
Vio
V–
6.1.22 Input hysteresis VW2O,hys –0.12 ×
VIO
–V
1)
6.1.23 Pull-down resistance RW2O 15 35 60 kΩ
6.1.24 Input Capacitance Ci W2O –5–pF
1)
Enable Input: EN
6.1.25 HIGH level input voltage
range
VEN,on 2–
VIO V Normal Operation Mode
6.1.26 LOW level input voltage range VEN,off 0 0.8 V Sleep Mode or Stand-By
Mode
6.1.27 Input hysteresis VEN,hys 300 mV 1)
6.1.28 Pull-down resistance REN 15 30 60 kΩ
6.1.29 Input capacitance Ci EN –5–pF
1)
Inhibit, Master Termination Outputs: INH1, INH2
6.1.30 Inhibit Ron resistance RINH,on 22 36 50 ΩIINH = -15 mA
6.1.31 Maximum INH output current IINH -150 -40 mA VINH = 0 V
6.1.32 Leakage current IINH,lk -5.0 5.0 µA Sleep Mode;
VINH = 0 V
Table 7 Electrical Characteristics (cont’d)
7.0 V < VS < 27 V; RL = 500 Ω; Vio = 5V; -40 °C < Tj < 150 °C; all voltages with respect to ground; positive current
flowing into pin; unless otherwise specified.
Pos. Parameter Symbol Limit Values Unit Remarks
Min. Typ. Max.
@neon
Data Sheet 23 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Electrical Characteristics
Wake Input: WK
6.1.33 High level input voltage VWK,H VS - 1 V VS +
3V
VVS = 13.5 V;
6.1.34 Low level input voltage VWK,L -0.3 – VS - 4 V V VS = 13.5 V;
6.1.35 Pull-up current IWK,PU -60 -30 -3 µA VWK = 0V
6.1.36 High level leakage current IWK,H,leak -5 5 µA VS = 0 V;
VWK = 40 V
6.1.37 Dominant time for wake-up tWK 30 150 µs
6.1.38 Input Capacitance Ci WK –15–pF
1)
Bus Receiver: BUS1, BUS2
6.1.39 Receiver threshold voltage,
recessive to dominant edge
Vth_dom 0.4 × VS0.48 ×
VS
–V
6.1.40 Receiver dominant state VBUSdom VS -
40 V
–0.4 × VSV LIN Spec 2.1 (Par. 17) 2)
6.1.41 Receiver threshold voltage,
dominant to recessive edge
Vth_rec –0.52 ×
VS
0.6 × VSV–
6.1.42 Receiver recessive state VBUSrec 0.6 × VS–1.15 x
Vs
V LIN Spec 2.1 (Par. 18) 3)
6.1.43 Receiver center voltage VBUS_CNT 0.475 ×
VS
0.5 ×
VS
0.525 ×
VS
V LIN Spec 2.1 (Par. 19) 4)
6.1.44 Receiver hysteresis VHYS 0.02 ×
VS
0.04 ×
VS
0.175 ×
VS
V LIN Spec 2.1 (Par. 20) 5)
6.1.45 Wake-up threshold voltage VBUS,wk 0.40 ×
VS
0.5 ×
VS
0.6 × VSV–
6.1.46 Dominant time for bus wake-
up
tWK,bus 30 150 μs–
Bus Transmitter: BUS1, BUS2
6.1.47 Bus recessive output voltage VBUS,ro 0.8 × VSVSVVTxD = high Level
6.1.48 Bus dominant output voltage
maximum load
VBUS,do
1.2
0.2 x VS
2.0
V
V
V
VTxD = 0 V; RL = 500 Ω
6,0 VS 7,3 V;
7,3 < VS 10 V;
10 < VS 18 V;
(see Figure 14)
6.1.49 Bus short circuit current IBUS_LIM 40 100 150 mA VBUS = 13.5 V;
LIN Spec 2.1 (Par. 12);
6.1.50 Leakage current I
BUS_NO_GND
-1000 -450 μAVS = 0 V; VBUS = -12 V;
LIN Spec 2.1 (Par. 15)
6.1.51 Leakage current I
BUS_NO_BAT
–28μAVS = 0 V; VBUS = 18 V;
LIN Spec 2.1 (Par. 16)
Table 7 Electrical Characteristics (cont’d)
7.0 V < VS < 27 V; RL = 500 Ω; Vio = 5V; -40 °C < Tj < 150 °C; all voltages with respect to ground; positive current
flowing into pin; unless otherwise specified.
Pos. Parameter Symbol Limit Values Unit Remarks
Min. Typ. Max.
@neon
Data Sheet 24 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Electrical Characteristics
6.1.52 Leakage current I
BUS_PAS_dom
-1 mA VS = 18 V; VBUS = 0 V;
LIN Spec 2.1 (Par. 13)
6.1.53 Leakage current I
BUS_PAS_rec
––20μAVS = 8 V; VBUS = 18 V;
LIN Spec 2.1 (Par. 14)
6.1.54 Bus pull-up resistance Rslave 20 30 47 kΩNormal mode
LIN Spec 2.1 (Par. 26)
6.1.55 LIN output current IBUS -60 -30 -5 µA Sleep mode
VS= 13.5 V; VEN = 0 V
6.1.56 Input Capacitance Ci BUS –15–pF
1)
Dynamic Transceiver Characteristics: BUS1, BUS2
6.1.57 Propagation delay
LIN bus to RxD
Dominant to RxD Low
Recessive to RxD High
trx_pdf
trx_pdr
1
1
6
6
µs
µs
LIN Spec 2.1 (Par. 31)
Vio = 5 V;
CRxD = 20 pF
6.1.58 Receiver delay symmetry trx_sym -2 2 µs LIN Spec 2.1 (Par. 32)
trx_sym = trx_pdf- trx_pdr;
Vio = 5 V;
CRxD = 20 pF
6.1.59 Delay time for mode Change tMODE ––120µs
1) See Figure 5, Figure 6
6.1.60 TxD1 Setup time for mode
selection
tTXD,SET ––50µs
1) See Figure 5, Figure 6
6.1.61 TxD dominant time out ttimeout 61220msVTxD = 0 V
6.1.62 TxD dominant time out
recovery time
ttorec ––15µs
1)
6.1.63 EN toggling to enter the flash
mode
tfl1 25 35 50 µs 1) See Figure 7
6.1.64 TxD1 time for flash activation tfl2
tfl3
tfl4
5
10
10
µs 1) See Figure 7
Table 7 Electrical Characteristics (cont’d)
7.0 V < VS < 27 V; RL = 500 Ω; Vio = 5V; -40 °C < Tj < 150 °C; all voltages with respect to ground; positive current
flowing into pin; unless otherwise specified.
Pos. Parameter Symbol Limit Values Unit Remarks
Min. Typ. Max.
@neon
Data Sheet 25 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Electrical Characteristics
6.1.65 Duty cycle D1
(for worst case at 20 kBit/s)
D1 0.396 duty cycle 1 6)
THRec(max) = 0.744 × VS;
THDom(max) =0.581 × VS;
VS = 7.0 … 18 V;
tbit = 50 μs;
D1 = tbus_rec(min)/2 tbit;
LIN Spec 2.1 (Par. 27)
6.1.66 Duty cycle D2
(for worst case at 20 kBit/s)
D2 0.581 duty cycle 2 6)
THRec(min)= 0.422 × VS;
THDom(min)= 0.284 × VS
VS = 7.6 … 18 V;
tbit = 50 μs;
D2 = tbus_rec(max)/2 tbit;
LIN Spec 2.1 (Par. 28)
6.1.67 Duty cycle D3
(for worst case at 10.4 kBit/s)
Low Slope Mode
D3 0.417 duty cycle 3 6)
THRec(max) = 0.778 × VS;
THDom(max) =0.616 × VS
VS = 7.0 … 18 V;
tbit = 96μs;
D3 = tbus_rec(min)/2 tbit;
LIN Spec 2.1 (Par. 29)
6.1.68 Duty cycle D4
(for worst case at 10.4 kBit/s)
Low Slope Mode
D4 0.590 duty cycle 4 6)
THRec(min) = 0.389 × VS;
THDom(min) =0.251 × VS
VS = 7.6 … 18 V;
tbit = 96μs;
D4 = tbus_rec(max)/2 tbit;
LIN Spec 2.1 (Par. 30)
1) Not subject to production test, specified by design
2) Minimum limit specified by design
3) Maximum limit specified by design
4) VBUS_CNT =(V
th_dom -V
th rec)/2;
5) VHYS =V
BUSrec - VBUSdom
6) Bus load concerning LIN Spec 2.1:
Load 1 = 1 nF / 1 kΩ=CBUS /RBUS
Load 2 = 6,8 nF / 660 Ω=CBUS /RBUS
Load 3 = 10 nF / 500 Ω=CBUS /RBUS
Table 7 Electrical Characteristics (cont’d)
7.0 V < VS < 27 V; RL = 500 Ω; Vio = 5V; -40 °C < Tj < 150 °C; all voltages with respect to ground; positive current
flowing into pin; unless otherwise specified.
Pos. Parameter Symbol Limit Values Unit Remarks
Min. Typ. Max.
@neon _L I — T I T T I1 I ‘_L I — % I J. XZI T I Hi
Data Sheet 26 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Electrical Characteristics
6.2 Diagrams
Figure 13 Simplified test circuit for dynamic characteristics
Figure 14 Simplified test circuit for static characteristics
Bus1
EN
RxD1
100 nF
VS
CBus
INH1
TxD1
WK
GND
Bus2
W2O
RxD2
CBus
TxD2
INH2
Vio
RBus
RBus
CRxD
CRxD
Bus1
EN
RxD1
100 nF
VS
CBus
INH1
TxD1
WK
GND
Bus2
W2O
RxD2
CBus
TxD2
INH2
Vio
RBus
RBus
CRxD
CRxD
II )I I | I I I I I I I I I 5 :47 I I I I I E 4h I i I I I I I ———I I ___I I I I I I I I I I i 4».
Data Sheet 27 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Electrical Characteristics
Figure 15 Timing diagram for dynamic characteristics
tBit tBit tBit
tBus_dom(max) tBus_rec(min)
Thresholds of
receiving node 1
Thresholds of
receiving node 2
THRec(max)
THDom(max)
THRec(min)
THDom(min)
tBus_dom(min) tBus_rec(max)
trx_pdf(1) trx_pdr(1)
trx_pdf(2)
trx_pdr(2)
VSUP
(Transceiver supply
of transmitting
node)
TxD
(input to
transmitting node)
RxD
(output of receiving
node 1)
RxD
(output of receiving
node 2)
Duty Cycle 1 = tBUS_rec(min) / (2 x tBIT)
Duty Cycle 2 = tBUS_rec(max) / (2 x tBIT)
@fineon
Data Sheet 28 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Application Information
7 Application Information
7.1 ESD Robustness according to IEC61000-4-2
Test for ESD robustness according to IEC61000-4-2 “Gun test” (150 pF, 330 Ω) have been performed. The results
and test conditions are available in a separate test report.
7.2 Pin Compatibility to the Single LIN Transceivers
The Twin LIN Transceiver TLE7269G is pin and function compatible to Single LIN Transceivers like the TLE7259-
3GE, the TLE7258 and the TLE7257. The TLE7269G has a pin for the VIO supply. This supply pin is usually
connected to the power supply of the external microcontroller. The Single LIN Transceivers don’t have a VIO pin.
In order to provide the same functions, these Single LIN transceiver need an external pull-up resistor at the RxD
pin towards the microcontroller supply VIO.
Additionally the TLE7258 and the TLE7257 has no local Wake-Up Pin. Pin 3 is N.C. at these devices.
Figure 16 Pin configuration TLE7269G and TLE7259-3GE, TLE7258, TLE7257
Table 8 ESD Robustness according to IEC61000-4-2
Performed Test Result Unit Remarks
Electrostatic discharge voltage at pin VS, BUS1
and BUS2 versus GND
+9 kV 1)Positive pulse
1) ESD susceptibility “ESD GUN” according LIN EMC 1.3 Test Specification, Section 4.3. (IEC 61000-4-2) -Tested by external
test house (IBEE Zwickau, EMC Testreport Nr. 05-06-06).
Electrostatic discharge voltage at pin VS, BUS1
and BUS2 versus GND
-9 kV 1)Negative pulse
Electrostatic discharge voltage at pin WK versus
GND
+8 kV 1)Positive pulse
Electrostatic discharge voltage at pin WK versus
GND
-8 kV 1)Negative pulse
RxD1
1
2
3
4
5
6
78
EN
WK
TxD1
INH1
V
S
BUS1
GND
TxD2
V
IO
RxD2
BUS2
W2O
INH2
9
10
11
12
13
14
RxD 1
2
3
45
6
7
8
EN
WK / N.C.
TxD
INH
VS
BUS
GND
TLE7259-3GE
TLE7258
TLE7257
and other single LIN
transceivers
TLE7269G
@neon
Data Sheet 29 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Application Information
7.3 Master Termination
To achieve the required timings for the dominant to recessive transition of the bus signal an additional external
termination resistor of 1 kΩ is mandatory. It is recommended to place this resistor at the master node. To avoid
reverse currents from the bus line into the battery supply line it is recommended to place a diode in series with the
external pull-up. For small systems (low bus capacitance) the EMC performance of the system is supported by an
additional capacitor of at least 1 nF at the master node (see Figure 17 and Figure 18).The values for the Master
Termination resistor and the bus capacitance influence the performance of the LIN network. They depend on the
number of nodes inside the LIN network and on the parasitic cable capacitances of the LIN bus wiring.
7.4 External Capacitors
A capacitor of 10 μF at the supply voltage input VS buffers the input voltage. In combination with the required
reverse polarity diode this prevents the device from detecting a power down conditions in case of negative
transients on the supply line (see Figure 17 and Figure 18).
The 100 nF capacitor close to the VS pin and a 33 nF capacitor close to the VIO pin of the TLE7269G are required
to get the best EMC performance.
@neon H Micro CommIIer e.g XCZZXX
Data Sheet 30 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Application Information
7.5 Application Example
Figure 17 Simplified Application Circuit with Bus Short to GND Feature applied
TxD2
GND
TLE7269G
BUS2
Micro Controller
e.g XC22xx
GND
WK
INH1
VS
VQ
GNDINH
VI
RxD2
W2O
VBat
LIN
BUS1 Master Node for
Lin Bus1 &
LIN Bus2
TxD1
RxD1
EN
BUS1
VIO
INH2 33 nF
100 nF
10 µF
e.g. TLE4678
100 nF
22 µF 100 nF
1 nF1 nF
1 kΩ
5 V or 3.3V
ECU1
1 kΩ
TxD2
GND
TLE7269G
BUS2
Micro Controller
e.g XC22xx
GND
WK
INH1
VS
VQ
GNDINH
VI
RxD2
W2O
Slave Node for
Lin Bus1 &
LIN Bus2
TxD1
RxD1
EN
BUS1
VIO
INH2 33 nF
100 nF
10 µF
e.g. TLE4678
100 nF
22 µF 100 nF
220 pF
5 V or 3.3V
ECU X
220 pF
N.C.
LIN
BUS2
@neon H Micro CommIIer e.g XCZZXX
Data Sheet 31 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Application Information
Figure 18 Simplified application Circuit without Bus Short to GND Feature
N.C.
TxD2
GND
TLE7269G
BUS2
Micro Controller
e.g XC22xx
GND
WK
INH1
VS
VQ
GNDINH
VI
RxD2
W2O
VBat
LIN
BUS1
Master Node for
Lin Bus1 &
LIN Bus2
TxD1
RxD1
EN
BUS1
VIO
INH2 33 nF
100 nF
10 µF
e.g. TLE4678
100 nF
22 µF 100 nF
1 nF1 nF
1 kΩ
5 V or 3.3V
ECU1
1 kΩ
TxD2
GND
TLE7269G
BUS2
Micro Controller
e.g XC22xx
GND
WK
INH1
VS
VQ
GNDINH
VI
RxD2
W2O
Slave Node for
Lin Bus1 &
LIN Bus2
TxD1
RxD1
EN
BUS1
VIO
INH2 33 nF
100 nF
10 µF
e.g. TLE4678
100 nF
22 µF 100 nF
220 pF
5 V or 3.3V
ECU X
220 pF
LIN
BUS2
N.C.
@neon 0.33 x 45° OPTIONAL 115 MAX. 0?“ :3; _ 4.021) 917' '7 Jar 2' i a + :01 0 0.641025 «11 ”A. IKE-[31M + 8:0.2 f 01 MIN. 14 5 RRRNRRR ' uuuuuuu I 7 3.154,,” I Index Mavking 1) Does no! Include plasilc or metal prdruslon of 0.15 nax. per slde
Data Sheet 32 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Package Outlines
8 Package Outlines
Figure 19 PG-DSO-14 (Plastic Dual Small Outline PG-DSO-14)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.Dimensions in mm
@neon
Data Sheet 33 Rev. 1.4
2018-06-20
TLE7269G
Twin LIN Transceiver
Revision History
9 Revision History
Revision Date Changes
1.4 2018-06-20 Update package outline
Update compatible Single LIN Transceivers
Update Layout style
1.3 2011-04-21 Changed coverpage
Page 20 , editorial 5.3.1
Changed temperature range to: -40°C - 150°C
1.2 2007-10-02 Data Sheet created
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2018-06-20
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2018 Infineon Technologies AG.
All Rights Reserved.
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aspect of this document?
Email: erratum@infineon.com
IMPORTANT NOTICE
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event be regarded as a guarantee of conditions or
characteristics ("Beschaffenheitsgarantie").
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
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subject to customer's compliance with its obligations
stated in this document and any applicable legal
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customer's products and any use of the product of
Infineon Technologies in customer's applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
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