AT94K(05,10,40)AL Datasheet by Microchip Technology

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.1‘|_mEI.® 51M mm AV]?® A IIIEI.
1
Features
Monolithic Field Programmable System Level Integrated Circuit (FPSLIC)
AT40K SRAM-based FPGA with Embedded High-performance RISC AVR® Core,
Extensive Data and Instruction SRAM and JTAG ICE
5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM
2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM
High-performance DSP Optimized FPGA Core Cell
Dynamically Reconfigurable In-System – FPGA Configuration Access Available
On-chip from AVR Microcontroller Core to Support Cache Logic® Designs
Very Low Static and Dynamic Power Consumption – Ideal for Portable and
Handheld Applications
Patented AVR Enhanced RISC Architecture
120+ Powerful Instructions – Most Single Clock Cycle Execution
High-performance Hardware Multiplier for DSP-based Systems
Approaching 1 MIPS per MHz Performance
C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers
Low-power Idle, Power-save and Power-down Modes
100 µA Standby and Typical 2-3 mA per MHz Active
Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM
Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM
Up to 16 Kbytes x 8 Internal 15 ns Data SRAM
JTAG (IEEE std. 1149.1 Compliant) Interface
Extensive On-chip Debug Support
Limited Boundary-scan Capabilities According to the JTAG Standard (AVR Ports)
AVR Fixed Peripherals
Industry-standard 2-wire Serial Interface
Two Programmable Serial UARTs
Two 8-bit Timer/Counters with Separate Prescaler and PWM
One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture
Modes and Dual 8-, 9- or 10-bit PWM
Support for FPGA Custom Peripherals
AVR Peripheral Control – 16 Decoded AVR Address Lines Directly Accessible
to FPGA
FPGA Macro Library of Custom Peripherals
16 FPGA Supplied Internal Interrupts to AVR
Up to Four External Interrupts to AVR
8 Global FPGA Clocks
Two FPGA Clocks Driven from AVR Logic
FPGA Global Clock Access Available from FPGA Core
Multiple Oscillator Circuits
Programmable Watchdog Timer with On-chip Oscillator
Oscillator to AVR Internal Clock Circuit
Software-selectable Clock Frequency
Oscillator to Timer/Counter for Real-time Clock
VCC: 3.0V - 3.6V
3.3V 33 MHz PCI-compliant FPGA I/O
20 mA Sink/Source High-performance I/O Structures
All FPGA I/O Individually Programmable
High-performance, Low-power 0.35µ CMOS Five-layer Metal Process
State-of-the-art Integrated PC-based Software Suite including Co-verification
5V I/O Tolerant
5K - 40K Gates
of AT40K FPGA
with 8-bit
Microcontroller,
up to 36K Bytes
of SRAM and
On-chip
JTAG ICE
AT94KAL Series
Field
Programmable
System Level
Integrated
Circuit
Rev. 1138G–FPSLI–11/03
A IIIEI.
2AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Description The AT94KAL Series FPSLIC family shown in Table 1 is a combination of the popular Atmel
AT40K Series SRAM FPGAs and the high-performance Atmel AVR 8-bit RISC microcontroller
with standard peripherals. Extensive data and instruction SRAM as well as device control and
management logic are included on this monolithic device, fabricated on Atmel’s 0.35µ five-
layer metal CMOS process.
The AT40K FPGA core is a fully 3.3V PCI-compliant, SRAM-based FPGA with distributed
10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks,
Cache Logic ability (partially or fully reconfigurable without loss of data) and 5,000 to 40,000
usable gates.
Notes: 1. FPSLIC parts with JTAG ICE support can be identified by the letter “J” after the device date
code, e.g., 4201 (no ICE support) and 4201J (with ICE support), see Figure 1.
2. FPSLIC devices should be laid out during PCB design to support a split power supply.
Please refer to the “Designing in Split Power Supply Support for AT94KAL and AT94SAL
Devices” application note, available on the Atmel web site at
http://www.atmel.com/atmel/acrobat/doc2308.pdf.
Table 1. The AT94K Series Characteristics
Device AT94K05AL AT94K10AL AT94K40AL
FPGA Gates 5K 10K 40K
FPGA Core Cells 256 576 2304
FPGA SRAM Bits 2048 4096 18432
FPGA Registers (Total) 436 846 2862
Maximum FPGA User I/O 96 144 288
AVR Programmable I/O Lines 8 16 16
Program SRAM 4 Kbytes - 16 Kbytes 20 Kbytes - 32 Kbytes 20 Kbytes - 32 Kbytes
Data SRAM 4 Kbytes - 16 Kbytes 4 Kbytes- 16 Kbytes 4 Kbytes - 16 Kbytes
Hardware Multiplier (8-bit) Yes Yes Yes
2-wire Serial Interface Yes Yes Yes
UARTs 2 2 2
Watchdog Timer Yes Yes Yes
Timer/Counters 3 3 3
Real-time Clock Yes Yes Yes
JTAG ICE Yes(1) Ye s (1) Ye s(1)
Ty pi ca l AV R
throughput
@ 25 MHz 19 MIPS 19 MIPS 19 MIPS
Operating
Volt ag e(2) AL 3.0 - 3.6V(2) 3.0 - 3.6V(2) 3.0 - 3.6V(2)
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3
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Figure 1. FPSLIC Device Date Code with JTAG ICE Support
The AT94K series architecture is shown in Figure 2.
Figure 2. AT94K Series Architecture
AT94K40AL-25DQC
0H1230
4201J Date Code
"J" indicates JTAG ICE support
®
5 - 40K Gates FPGA
Up to
16K x 8
Data
SRAM
Up to 16K x 16
Program
SRAM Memory
PROGRAMMABLE I/O
with
Multiply Two 8-bit
Timer/Counters
16 Prog. I/O
Lines
I/O
I/O
I/O
2-wire Serial
Unit
Up to 16 Interrupt Lines
Up to 16
Addr Decoder
4 Interrupt Lines
JTAG ICE
A IIIEI.
4AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
The embedded AVR core achieves throughputs approaching 1 MIPS per MHz by executing
powerful instructions in a single-clock cycle, and allows system designers to optimize power
consumption versus processing speed. The AVR core is based on an enhanced RISC archi-
tecture that combines a rich instruction set with 32 general-purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code-efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers at the same clock frequency. The AVR executes out of on-
chip SRAM. Both the FPGA configuration SRAM and the AVR instruction code SRAM can be
automatically loaded at system power-up using Atmel’s In-System Programmable (ISP) AT17
Series EEPROM Configuration Memories or ATFS FPSLIC Support Devices.
State-of-the-art FPSLIC design tools, System Designer, were developed in conjunction with
the FPSLIC architecture to help reduce overall time-to-market by integrating microcontroller
development and debug, FPGA development and Place and Route, and complete system
co-verification in one easy-to-use software tool.
Table 2. ATFS FPSLIC Support Devices
FPSLIC Device FPSLIC Support Device Configuration Data Spare Memory
AT94K05 ATFS05 226520 Bits 35624 Bits
AT94K10 ATFS10 430488 Bits 93800 Bits
AT94K40 ATFS40 815382 Bits 233194 Bits
41m
5
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
FPGA Core
The AT40K core can be used for high-performance designs, by implementing a variety of com-
pute-intensive arithmetic functions. These include adaptive finite impulse response (FIR)
filters, fast Fourier transforms (FFT), convolvers, interpolators, and discrete-cosine transforms
(DCT) that are required for video compression and decompression, encryption, convolution
and other multimedia applications.
Fast, Flexible and
Efficient SRAM
The AT40K core offers a patented distributed 10 ns SRAM capability where the RAM can be
used without losing logic resources. Multiple independent, synchronous or asynchronous,
dual-port or single-port RAM functions (FIFO, scratch pad, etc.) can be created using Atmel’s
macro generator tool.
Fast, Efficient
Array and Vector
Multipliers
The AT40K cores patented 8-sided core cell with direct horizontal, vertical and diagonal cell-
to-cell connections implements ultra-fast array multipliers without using any busing resources.
The AT40K core’s Cache Logic capability enables a large number of design coefficients and
variables to be implemented in a very small amount of silicon, enabling vast improvement in
system speed.
Cache Logic
Design
The AT40K FPGA core is capable of implementing Cache Logic (dynamic full/partial logic
reconfiguration, without loss of data, on-the-fly) for building adaptive logic and systems. As
new logic functions are required, they can be loaded into the logic cache without losing the
data already there or disrupting the operation of the rest of the chip; replacing or complement-
ing the active logic. The AT40K FPGA core can act as a reconfigurable resource within the
FPSLIC environment.
Automatic
Component
Generators
The AT40K is capable of implementing user-defined, automatically generated, macros; speed
and functionality are unaffected by the macro orientation or density of the target device. This
enables the fastest, most predictable and efficient FPGA design approach and minimizes
design risk by reusing already proven functions. The Automatic Component Generators work
seamlessly with industry-standard schematic and synthesis tools to create fast, efficient
designs.
The patented AT40K architecture employs a symmetrical grid of small yet powerful cells con-
nected to a flexible busing network. Independently controlled clocks and resets govern every
column of four cells. The FPSLIC device is surrounded on three sides by programmable I/Os.
Core usable gate counts range from 5,000 to 40,000 gates and 436 to 2,864 registers. Pin
locations are consistent throughout the FPSLIC family for easy design migration in the same
package footprint.
The Atmel AT40K FPGA core architecture was developed to provide the highest levels of per-
formance, functional density and design flexibility. The cells in the FPGA core array are small,
efficient and can implement any pair of Boolean functions of (the same) three inputs or any
single Boolean function of four inputs. The cell’s small size leads to arrays with large numbers
of cells. A simple, high-speed busing network provides fast, efficient communication over
medium and long distances.
The Symmetrical
Array
At the heart of the Atmel FPSLIC architecture is a symmetrical array of identical cells. The
array is continuous from one edge to the other, except for bus repeaters spaced every four
cells, see Figure 3. At the intersection of each repeater row and column is a 32 x 4 RAM block
accessible by adjacent buses. The RAM can be configured as either a single-ported or dual-
ported RAM, with either synchronous or asynchronous operation.
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6AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
The Busing
Network
Figure 3. Busing Network
Figure 4 depicts one of five identical FPGA busing planes. Each plane has three bus
resources: a local-bus resource (the middle bus) and two express-bus resources. Bus
resources are connected via repeaters. Each repeater has connections to two adjacent local-
bus segments and two express-bus segments. Each local-bus segment spans four cells and
connects to consecutive repeaters. Each express-bus segment spans eight cells and
bypasses a repeater. Repeaters regenerate signals and can connect any bus to any other bus
(all pathways are legal) on the same plane. Although not shown, a local bus can bypass a
repeater via a programmable pass gate, allowing long on-chip tri-state buses to be created.
Local/local turns are implemented through pass gates in the cell-bus interface.
Express/express turns are implemented through separate pass gates distributed throughout
the array.
= I/O Pad
= AT40K Cell
= Repeater Row
= Repeater
= RAM Block
Interface to AVR
A IIIEI.
7
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Figure 4. Busing Plane (One of Five)
= Local/local or Express/express Turn Point
= AT40K Core Cell
= Row Repeater
= Column
8AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Cell Connections Figure 5(a) depicts direct connections between an FPGA cell and its eight nearest neighbors.
Figure 5(b) shows the connections between a cell five horizontal local buses (one per busing
plane) and five vertical local buses (one per busing plane).
Figure 5. Cell Connections
The Cell Figure 6 depicts the AT40K FPGA embedded core logic cell. Configuration bits for separate
muxes and pass gates are independent. All permutations of programmable muxes and pass
gates are legal. Vn is connected to the vertical local bus in plane n. Hn is connected to the hor-
izontal local bus in plane n. A local/local turn in plane n is achieved by turning on the two pass
gates connected to Vn and Hn. Up to five simultaneous local/local turns are possible.
The logic cell can be configured in several “modes”. The logic cell flexibility makes the FPGA
architecture well suited to all digital design application areas, see Figure 7. The IDS layout tool
automatically optimizes designs to utilize the cell flexibility.
(a) Cell-to-Cell Connections (b) Cell-to-Bus Connections
W
X
Y
Z
L
WXYZL
Y
X
Y
Y
Y
X
XX
CELL CELL CELL
CELL CELL CELL
CELL CELL CELL
CELL
H; E; ‘ i 41m
9
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Figure 6. The Cell
OUT OUT
RESET/SET
CLOCK
FB
X = Diagonal Direct Connect or Bus
Y = Orthogonal Direct Connect or Bus
W = Bus Connection
Z = Bus Connection
FB = Internal Feedback
10
Z
D
Q
"1" NW NE SE SW "1"
"1"
"1""0"
XWY
XZWY
"1" N E S W
8 X 1 LUT 8 X 1 LUT
XY
NW NE SE SW N E S W
V1
H1
V2
H2
V3
H3
V4
H4
V5
H5
"1" OE
H
OE
V
L
10 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Figure 7. Some Single Cell Modes
RAM There are two types of RAM in the FPSLIC device: the FreeRAM distributed through the
FPGA Core and the SRAM shared by the AVR and FPGA. The SRAM is described in
“FPGA/AVR Interface and System Control” on page 21. The 32 x 4 dual-ported FPGA Fre-
eRAM blocks are dispersed throughout the array and are connected in each sector as shown
in Figure 8. A four-bit Input Data bus connects to four horizontal local buses (Plane 1) distrib-
uted over four sector rows. A four-bit Output Data bus connects to four horizontal local buses
(Plane 2) distributed over four sector rows. A five-bit Input-address bus connects to five verti-
cal express buses in the same sector column (column 3). A five-bit Output-address bus
connects to five vertical express buses in the same column. WAddr (Write Address) and
RAddr (Read Address) alternate positions in horizontally aligned RAM blocks. For the left-
3 LUT3 LUT 4 LUT2:1MUX 3 LUT3 LUT
DQ
DQ
Q
Q (Registered)
DQ
Synthesis Mode
Arithmetic Mode
DSP/Multiplier Mode
Counter Mode
Tri-State/Mux Mode
A
B
C
D
A
B
C
A
B
C
D
A
B
C
EN
Q
Q
SUM (Registered)
SUM
and/or
PRODUCT
or
CARRY
PRODUCT (Registered)
CARRY
CARRY
CARRY IN
and/or
or
and/or
and/or
DQ
3 LUT3 LUT
41m
11
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
most RAM blocks, RAddr is on the left and WAddr is on the right. For the right-most RAM
blocks, WAddr is on the left and RAddr is tied off. For single-ported RAM, WAddr is the
READ/WRITE address port and Din is the (bi-directional) data port. The right-most RAM
blocks can be used only for single-ported memories. WE and OE connect to the vertical
express buses in the same column on Plane V1 and V2, respectively. WAddr, RAddr, WE and
OE connect to express buses that are full length at array edge.
Reading and writing the 32 x 4 dual-port RAM are independent of each other. Reading the 32
x 4 dual-port RAM is completely asynchronous. Latches are transparent; when Load is logic 1,
data flows through; when Load is logic 0, data is latched. Each bit in the 32 x 4 dual-port RAM
is also a transparent latch. The front-end latch and the memory latch together and form an
edge-triggered flip-flop. When a bit nibble is (Write) addressed and LOAD is logic 1 and WE is
logic 0, DATA flows through the bit. When a nibble is not (Write) addressed or LOAD is logic 0
or WE is logic 1, DATA is latched in the nibble. The two CLOCK muxes are controlled
together; they both select CLOCK or they both select “1”. CLOCK is obtained from the clock
for the sector-column immediately to the left and immediately above the RAM block. Writing
any value to the RAM Clear Byte during configuration clears the RAM, see Figure 5 and
Figure 6.
Figure 8. FPGA RAM Connections (One RAM Block)
32X4 RAM
Din
WAddr
WE
OE
Dout
RAddr
CLK
CLK
CLK
CLK
CLK
Sector Clock Mux
A IIIEI. Data
12 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Figure 9. FreeRAM Logic(1)
Note: 1. For dual port, the switches on READ ADDR and DATA OUT would be on. The other two would be off. The reverse is true for
single port.
Write
Data Data
Read
"1""1"
Write
RAM-Clear
DATA
"1"
CLOCK
Load
5
READ ADDR
WRITE ADDR
WE
DATA IN
Load
Latch
Load
Latch
Load
Latch
Clear
32 x 4
Dual-port
RAM
OE
4
4
5
A IIIEI.
13
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Figure 10. FreeRAM Example: 128 x 8 Dual-ported RAM (Asynchronous)(1)
Note: 1. These layouts can be generated automatically using the Macro Generators.
2-to-4
Decoder
Dout(4)
Dout(5)
Dout(6)
Dout(7)
Din Dout
WE
OE
RAddr WAddr
Din Dout Din Dout
WE
OE
Din Dout
WAddr RAddr
WE
OE
RAddr WAddr
WE
OE
WAddr RAddr
Din Dout
WAddr RAddr
WE
OE
Din Dout
WE
OE
RAddr WAddr
Din Dout
WAddr RAddr
WE
OE
Din Dout
WE
OE
RAddr WAddr
2-to-4
Decoder
Local Buses
Express Buses
Dedicated Connections
Read
Address
Din(0)
Din(1)
Din(2)
Din(3)
Din(4)
Din(5)
Din(6)
Din(7)
Write
Address
WE
Dout(0)
Dout(1)
Dout(2)
Dout(3)
41m
14 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Clocking and
Set/Reset
Six of the eight dedicated Global Clock buses (1, 2, 3, 4, 7 and 8) are connected to a dual-use
Global Clock pin. In addition, two Global Clock buses (5 and 6) are driven from clock signals
generated within the AVR microcontroller core, see Figure 11.
An FPGA core internal signal can be placed on any Global Clock bus by routing that signal to
a Global Clock access point in the corners of the embedded core. Each column of the array
has a Column Clock selected from one of the eight Global Clock buses. The left edge Column
Clock mux has two additional inputs from dual-use pins FCK1, see Figure 8, and FCK2 to pro-
vide fast clocking to left-side I/O. Each sector column of four cells can be clocked from a
(Plane 4) express bus or from the Column Clock. Clocking to the 4 cells of a sector can be dis-
abled. The Plane 4 express bus used for clocking is half length at the array edge. The clock
provided to each sector column of four cells can be either inverted or not inverted. The register
in each cell is triggered on a rising clock edge. On power-up, constant “0” is provided to each
register’s clock pins. A dedicated Global Set/Reset bus, see Figure 9, can be driven by any
USER I/O pad, except those used for clocking, Global or Fast. An internal signal can be
placed on the Global Set/Reset bus by routing that signal to the pad programmed as the Glo-
bal Set/Reset input. Global Set/Reset is distributed to each column of the array. Each sector
column of four cells can be Set/Reset by a (Plane 5) express bus or by the Global Set/Reset.
The Plane 5 express bus used for Set/Reset is half length at array edge. The Set/Reset pro-
vided to each sector column of four cells can be either inverted or not inverted. The function of
the Set/Reset input of a register (either Set or Reset) is determined by a configuration bit for
each cell. The Set/Reset input of a register is Active Low (logic 0). Setting or resetting of a reg-
ister is asynchronous. On power-up, a logic 1 (High) is provided by each register, i.e., all
registers are set at power-up.
Figure 11. FPGA Clocks from AVR
AVR SYSTEM CLOCK (AVR CLK)
TIMER OSC TOSC1 (AS2 SET IN ASSR)
AVR SYSTEM
CLOCK
(AVR CLK)
WATCHDOG CLOCK
"1"
GCK6
TO FPGA
CORE GCK5
TO FPGA
CORE GCK6
41m
15
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
The FPGA clocks from the AVR are effected differently in the various sleep modes of the AVR,
see Table 3.
The source clock into the FPGA GCK5 and GCK6 will determine what happens during the var-
ious power-down modes of the AVR.
If the XTAL clock input is used as an FPGA clock (GCK5 or GCK6) in Idle mode, it will still be
running. In Power-down/save mode the XTAL clock input will be off.
If the TOSC clock input is used as an FPGA clock (GCK6) in Idle mode, it will still be running in
Power-save mode but will be off in Power-down mode.
If the Watchdog Timer is used as an FPGA clock (GCK6) and was enabled in the AVR, it will
be running in all sleep modes.
Table 3. Clock Activity in Various Modes
Mode Clock Source GCK5 GCK6
Idle
XTAL Active Active
TOSC Not Available Active
WDT Not Available Active
Power-save
XTAL Inactive Inactive
TOSC Not Available Active
WDT Not Available Active
Power-down
XTAL Inactive Inactive
TOSC Not Available Inactive
WDT Not Available Active
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16 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Figure 12. Clocking (for One Column of Cells)
Note: 1. Two on left edge column of the embedded FPGA array only.
Global Clock Line (Buried)
Express Bus
(Plane 4; Half Length at Edge)
GCK1 GCK8
Repeater
}
}
"1"
"1"
"1"
"1"
FCK(1)
J , ,C EJw L C U C :Gm C C C K 3 E
17
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Figure 13. Set/Reset (for One Column of Cells)
Some of the bus resources on the embedded FPGA core are used as dual-function resources.
Table 4 shows which buses are used in a dual-function mode and which bus plane is used.
The FPGA software tools are designed to automatically accommodate dual-function buses in
an efficient manner.
Each Cell has a Programmable Set or Reset
Global Set/Reset Line (Buried)
Repeater
Express Bus
(Plane 5; Half Length at Edge)
Any User I/O can Drive Global Set/Reset Line
"1"
"1"
"1"
"1"
A IIIEI.
18 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Figure 14. Primary I/O
Table 4. Dual-function Buses
Function Type Plane(s) Direction Comments
Cell Output Enable Local 5 Horizontal
and
Ver tical
FreeRAM Output
Enable
Express 2 Vertical Bus full length at array edge bus in first
column to left of RAM block
FreeRAM Write
Enable
Express 1 Vertical Bus full length at array edge bus in first
column to left of RAM block
FreeRAM Address Express 1 - 5 Vertical Buses full length at array edge
buses in second column to left of
RAM block
FreeRAM
Data In
Local 1 Horizontal
FreeRAM
Data Out
Local 2 Horizontal
Clocking Express 4 Vertical Bus full length at array edge
Set/Reset Express 5 Vertical Bus full length at array edge
"0"
"1"
DRIVE
TRI-STATE
"0"
"1"
TTL/ CMO S
SCHMITT
DELAY
PULL-DOWN
PULL-UP
GND VCC
PAD
CELL
CELL
CELL
CLK
RST
RST
CLK
19
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Figure 15. Secondary I/O
Figure 16. Primary and Secondary I/Os
CELL
"0"
"1"
DRIVE
TRI-STATE
"0"
"1"
TTL/CMOS
SCHMITT
DELAY
PULL-DOWN
PULL-UP
GND VCC
PAD
CELL
CLK
RST
RST
CLK
cell cell
cell cell
cell cell
cell cell
cell cell
cell cell
pp
pp
pp
p
p
p
p
p
p
ss s
s
s
ss
s
p
s
s = secondary I/O
p = primary I/O
cell
p
s
cell
p
20 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Figure 17. Corner I/Os
DRIVE
TRI-STATE
TTL/CMOS
SCHMITT
DELAY
PULL-DOWN
PULL-UP
GNDVCC
PAD
DRIVE
TRI-STATE
TTL/CMOS
SCHMITT
DELAY
PULL-DOWN
PULL-UP
GNDVCC
PAD
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
DRIVE
TRI-STATE
TTL/ CMO S
SCHMITT
DELAY
PULL-DOWN
PULL-UP
GND VCC
PAD
"0"
"1"
"0"
"1"
CELL
CELL
CELL
CELL
CLK
RST
CLK
RST
RST
CLK
RST
CLK
CLK
RST
RST
CLK
41m
21
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
FPGA/AVR Interface and System Control
The FPGA and AVR share a flexible interface which allows for many methods of system
integration.
Both FPGA and AVR share access to the 15 ns dual-port SRAM.
The AVR data bus interfaces directly into the FPGA busing resources, effectively treating
the FPGA as a large I/O device. Users have complete flexibility on the types of additional
peripherals which are placed and routed inside the FPGA user logic.
Up to 16 decoded address lines are provided into the FPGA.
Up to 16 interrupts are available from the FPGA to the AVR.
The AVR can reprogram the FPGA during operation to create a dynamic reconfigurable
system (Cache Logic).
FPGA/AVR
Interface–
Memory-mapped
Peripherals
The FPGA core can be directly accessed by the AVR core, see Figure 18. Four memory loca-
tions in the AVR memory map are decoded into 16 select lines (8 for AT94K05) and are
presented to the FPGA along with the AVR 8-bit data bus. The FPGA can be used to create
additional custom peripherals for the AVR microcontroller through this interface. In addition
there are 16 interrupt lines (8 for AT94K05) from the FPGA back into the AVR interrupt control-
ler. Programmable peripherals or regular logic can use these interrupt lines. Full support for
programmable peripherals is available within the System Designer tool suite.
Figure 18. FPGA/AVR Interface: Interrupts and Addressing
The FPGA I/O selection is controlled by the AVR. This is described in detail beginning on
page 53. The FPGA I/O interrupts are described beginning on page 57.
EMBEDDED
FPGA CORE
EMBEDDED
AVR CORE
ADDRESS
DECODER
4:16
DECODE
Up to 16 Memory-mapped
Decoded Address
Lines from 4 I/O Memory
Space Addresses I/O Memory Address Bus
FPGAIORE
FPGAIOWE
Up to 16 Interrupt Lines from FPGA to AVR – Various Priority Levels
8-bit Bi-directional Data Bus
8-bit
Data Out
8-bit
Data In
A IIIEI.
22 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Program and
Data SRAM
Up to 36 Kbytes of 15 ns dual-port SRAM reside between the FPGA and the AVR. This SRAM
is used by the AVR for program instruction and general-purpose data storage. The AVR is
connected to one side of this SRAM; the FPGA is connected to the other side. The port con-
nected to the FPGA is used to store data without using up bandwidth on the AVR system data
bus.
The FPGA core communicates directly with the data SRAM(1) block, viewing all SRAM mem-
ory space as 8-bit memory.
Note: 1. The unused bits for the FPGA-SRAM address must tie to ‘0’ because there is no pull-down
circuitry.
For the AT94K10 and AT94K40, the internal program and data SRAM is divided into three
blocks: 10 Kbytes x 16 dedicated program SRAM, 4 Kbytes x 8 dedicated data SRAM and 6
Kbytes x 16 or 12 Kbytes x 8 configurable SRAM, which may be swapped between program
and data memory spaces in 2 Kbytes x 16 or 4 Kbytes x 8 partitions.
For the AT94K05, the internal program and data SRAM is divided into three blocks: 4 Kbytes
16 dedicated program SRAM, 4 Kbytes x 8 dedicated data SRAM and 6 Kbytes x 16 or 12
Kbytes x 8 configurable SRAM, which may be swapped between program and data memory
spaces in 2 Kbytes x 16 or 4 Kbytes x 8 partitions.
The addressing scheme for the configurable SRAM partitions prevents program instructions
from overwriting data words and vice versa. Once configured (SCR41:40 – See “System Con-
trol Register – FPGA/AVR on page 30.), the program memory space remains isolated from
the data memory space. SCR41:40 controls internal muxes. Write enable signals allow the
memory to be safely segmented. Figure 19 shows the FPSLIC configurable allocation SRAM
memory.
41m
23
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Figure 19. FPSLIC Configurable Allocation SRAM Memory(1)(2)
Notes: 1. The Soft “BOOT BLOCK” is an area of memory that is first loaded when the part is powered
up and configured. The remainder of the memory can be reprogrammed while the device is
in operation for switching functions in and out of memory. The Soft “BOOT BLOCK” can only
be programmed by a full device configuration on power-up.
2. The lower portion of the Data memory is not shared between the AVR and FPGA. The AVR
uses addresses $0000 - $001F for the AVR CPU general working registers. $001F - $005F
are the addresses used for Memory Mapped I/O and store the information in dedicated reg-
isters. Therefore, on the FPGA side $0000 - $005F are available for data that is only needed
by the FPGA.
$0000
$07FF
$27FF
$3FFF
$3800
$3000
$37FF
$2800
$2FFF
$0FFF
$1000
$1FFF
$2000
$2FFF
$3000
$3FFF
$005F
Memory Partition
is User Defined
during Development FIXED
10K x 16
4 Kbytes x 16 (94K05)
OPTIONAL
2 Kbytes x 16
OPTIONAL
2 Kbytes x 16
OPTIONAL
2 Kbytes x 16
OPTIONAL
4 Kbytes x 8
OPTIONAL
4 Kbytes x 8
OPTIONAL
4 Kbytes x 8
Program SRAM Memory
Data SRAM Memory
FIXED
4 Kbytes x 8
$0000
DATA
SRAM
FPGA
ACCESS
ONLY
$001F
AVR REG.
SPACE
SOFT “BOOT BLOCK”
AVR
MEMORY
MAPPED
I/O
(1)
(2)
A IIIEI.
24 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Data SRAM
Access by FPGA –
FPGAFrame Mode
The FPGA user logic has access to the data SRAM directly through the FPGA side of the
dual-port memory, see Figure 20. A single bit in the configuration control register (SCR63 –
see “System Control Register – FPGA/AVR” on page 30) enables this interface. The interface
is disabled during configuration downloads. Express buses on the East edge of the array are
used to interface the memory. Full read and write access is available. To allow easy imple-
mentation, the interface itself is dedicated in routing resources, and is controlled in the System
Designer software suite using the AVR FPGA interface dialog.
Figure 20. Internal SRAM Access – Normal Use
Once the SCR63 bit is set there is no additional read enable from the FPGA side. This means
that the read is always enabled. You can also perform a read or write from the AVR at the
same time as an FPGA read or write. If there is a possibility of a write address being accessed
by both devices at the same time, the designer should add arbitration to the FPGA Logic to
control who has priority. In most cases the AVR would be used to restrict access by the FPGA
using the FMXOR bit, see “Software Control Register – SFTCR” on page 51. You can read
from the same location from both sides simultaneously.
SCR bit 38 controls the polarity of the clock to the SRAM from the AT40K FPGA.
SRAM Access
by FPGA/AVR
This option is used to allow for code (Program Memory) changes.
Accessing and
Modifying the
Program Memory
from the AVR
The FPSLIC SRAM is up to 36 x 8 Kbytes of dual port, see Figure 19):
The A side (port) is accessed by the AVR.
The B side (port) is accessed by the FPGA/Configuration Logic.
The B side (port) can be accessed by the AVR with ST and LD instructions in DBG mode
for code self-modify.
Structurally, the [(n 2) Kbytes 8] memory is built from (n)2 Kbytes 8 blocks, numbered
SRAM0 through SRAM(n).
EMBEDDED
FPGA CORE
EMBEDDED
AVR CORE
16 Address Lines:
FPGA Edge Express Buses 16-bit Data Address Bus
CLK AVR
WE AVR
RE AVR
8-bit Data Write
8-bit Data Read/Write
CLK FPGA
WE FPGA
8-bit Data Read
SCR38
DATA SRAM
4 Kbytes x 8
UP TO
16 Kbytes x 8
B Side A Side
41m
25
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
A Side The A side is partitioned into Program memory and Data memory:
Program memory is 16-bit words.
Program memory address $0000 always starts in the highest two SRAMs (n - 1, n)
[SRAMn - 1 (low byte) and SRAMn (high byte)] (SRAM labels are for layout, the
addressing scheme is transparent to the AVR PC).
System configuration determines the higher addresses for program memory:
– SCR bits 41 = 0 : 40 = 0, program memory extended from $2800 - $3FFF
– SCR bits 41 = 0 : 40 = 1, program memory extended from $2800 - $37FF
– SCR bits 41 = 1 : 40 = 0, program memory extended from $2800 - $2FFF
– SCR bits 41 = 1 : 40 = 1, no extra program memory
Extended program memory is always lost to extended data memory from SRAM2/3 down
to SRAM6/7, see Table 5.
Data memory is 8-bit words.
Data memory address $0000 always starts in SRAM0 (SRAM labels are for layout, the
addressing scheme is transparent to AVR data read/write).
System configuration determines the higher address for data memory:
SCR bits 41 = 0 : 40 = 0, no extra data memory
SCR bits 41 = 0 : 40 = 1, data memory extended from $1000 - $1FFF
SCR bits 41 = 1 : 40 = 0, data memory extended from $1000 - $2FFF
SCR bits 41 = 1 : 40 = 1, data memory extended from $1000 - $3FFF
Extended data memory is always lost to extended program memory from SRAM7 up to
SRAM2 in 2 x SRAM blocks, see Table 6.
Table 5. AVR Program Decode for SRAM 2:7 (16K16)
Address Range SRAM Comments
$3FFF - $3800
$3FFF - $3800
02
03 CR41:40 = 00
$37FF - $3000
$37FF - $3000
04
05 CR41:40 = 00,01
$2FFF - $2800
$2FFF - $2800
06
07 CR41:40 = 00,01,10
$27FF - $2000
$27FF - $2000
$1FFF - $1800
$1FFF - $1800
$17FF - $1000
$17FF - $1000
$0FFF - $0800
$0FFF - $0800
$07FF - $0000
$07FF - $0000
08
09
10
11
12
13
14
15
16
n = 17
AVR Program Read-only
AVR Program Read-only
AVR Program Read-only
AVR Program Read-only
AVR Program Read-only
AVR Program Read-only
AVR Program Read-only
AVR Program Read-only
AVR Program Read-only
AVR Program Read-only
A IIIEI.
26 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
B Side The B side is not partitioned; the FPGA (and AVR debug mode) views the memory space as
36 x 8 Kbytes.
The B side is accessed by the FPGA/Configuration Logic.
The B side is accessed by the AVR with ST and LD instructions in DBG mode for code
self-modify.
To activate the debug mode and allow the AVR to access the program code space (with
ST – see Figure 21 – and LD – see Figure 22 – instructions), the DBG bit (bit 1) of the
SFTCR $3A ($5A) register has to be set. When this bit is set, SCR36 and SCR37 are
ignored – you can overwrite anything in the AVR program memory.
The FPGA memory access interface should be disabled while in debug mode. This is to
ensure that there is no contention between the FPGA address and data signals and the
AVR-generated address and data signals. To ensure the AVR has control over the “B
side” memory interface, the FMXOR bit (bit 3) of the SFTCR $3A ($5A) register should be
used in conjunction with the SCR63 system control register bit.
The FMXOR bit is XORed with the System Control Register’s Enable FPGA SRAM Inter-
face bit (SCR63). The behavior when this bit is set to 1 is dependent on how the SCR was
initialized. If the Enable FPGA SRAM Interface bit (SCR63) in the SCR is 0, the FMXOR
bit enables the FPGA SRAM Interface when set to 1. If the Enable FPGA SRAM Interface
bit in the SCR is 1, the FMXOR bit disables the FPGA SRAM Interface when set to 1. Dur-
ing AVR reset, the FMXOR bit is cleared by the hardware.
Even though the FPGA (and AVR debug mode) views the memory space as
36 x 8 Kbytes, an awareness of the 2K x 8 partitions (or SRAM labels) is required if Frame
(and AVR debug mode) read/writes are to be meaningful to the AVR.
AVR data to FPGA addressing is 1:1 mapping.
AVR program to FPGA addressing requires 16-bit to 8-bit mapping and an understanding
of the partitions in Table 7.
Table 6. AVR Data Decode for SRAM 0:17 (16K8)
Address Range SRAM Comments
$07FF – $0000
$0FFF – $0800
00
01
AVR Data Read/Write
AVR Data Read/Write
$17FF – $1000
$1FFF – $1800
02
03 CR41:40 = 11,10,01
$27FF – $2000
$2FFF – $2800
04
05 CR41:40 = 11,10
$37FF – $3000
$3FFF – $3800
06
07 CR41:40 = 11
Table 7. Summary Table for AVR and FPGA SRAM Addressing
SRAM
FPGA and AVR DBG
Address Range
AVR Data
Address Range AVR PC Address Range
00 $0000 - $07FF $0000 - $07FF
01 $0800 - $0FFF $0800 - $0FFF
02(1) $1000 - $17FF $1000 - $17FF $3800 - $3FFF (LS Byte)
03(1) $1800 - $1FFF $1800 - $1FFF $3800 - $3FFF (MS Byte)
04(1) $2000 - $27FF $2000 - $27FF $3000 - $37FF (LS Byte)
41m
27
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Note: 1. Whether these SRAMs are “Data” or “Program” depends on the SCR40 and SCR41 values.
Example: Frame (and AVR debug mode) write of instructions to associated AVR PC
addresses, see Table 8 and Table 9.
05(1) $2800 - $2FFF $2800 - $2FFF $3000 - $37FF (MS Byte)
06(1) $3000 - $37FF $3000 - $37FF $2800 - $2FFF (LS Byte)
07(1) $3800 - $3FFF $3800 - $3FFF $2800 - $2FFF (MS Byte)
08 $4000 - $47FF $2000 - $27FF (LS Byte)
09 $4800 - $4FFF $2000 - $27FF (MS Byte)
10 $5000 - $57FF $1800 - $1FFF (LS Byte)
11 $5800 - $5FFF $1800 - $1FFF (MS Byte)
12 $6000 - $67FF $1000 - $17FF (LS Byte)
13 $6800 - $6FFF $1000 - $17FF (MS Byte)
14 $7000 - $77FF $0800 - $0FFF (LS Byte)
15 $7800 - $7FFF $0800 - $0FFF (MS Byte)
16 $8000 - $87FF $0000 - $07FF (LS Byte)
17 = n $8800 - $8FFF $0000 - $07FF (MS Byte)
Table 8. AVR PC Addresses
AVR PC Instruction
0FFE 9B28
0FFF CFFE
1000 B300
1001 9A39
Table 9. Frame Addresses
Frame Address Frame Data
77FE 28
77FF FE
6000 00
6001 39
7FFE 9B
7FFF CF
6800 B3
6801 9A
Table 7. Summary Table for AVR and FPGA SRAM Addressing (Continued)
SRAM
FPGA and AVR DBG
Address Range
AVR Data
Address Range AVR PC Address Range
A IIIEI.
28 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Figure 21. AVR SRAM Data Memory Write Using “ST” Instruction
Figure 22. AVR SRAM Data Memory Read Using “LD” Instruction
CLOCK
RAMWE
RAMADR
DBUS
DBUSOUT
(REGISTERED)
VALID
ST cycle 1 ST cycle 2 next instruction
VALID
VALID
CLOCK
RAMRE
RAMADR
DBUS
VALID
LD cycle 1 LD cycle 2 next instruction
VALID
A IIIEI.
29
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
AVR Cache Mode The AVR has the ability to cache download the FPGA memory. The AVR has direct access to
the data buses of the FPGA’s configuration SRAM and is able to download bitstreams. AVR
Cache access of configuration SRAM is not available during normal configuration downloads.
The Cache Logic port in the AVR is located in the I/O memory map. Three registers, FPGAX,
FPGAY FPGAZ, control the address written to inside the FPGA; and FPGAD in the AVR mem-
ory map controls the Data. Registers FPGAX, FPGAY and FPGAZ are write only, see
Figure 23.
Figure 23. Internal FPGA Configuration Access
The AVR Cache Logic access mode is write only. Transfers may be aborted at any time due to
AVR program wishes or external interrupts.
The FPGA CHECK function is not supported by the AVR Cache mode.
A typical application for this mode is for the AVR to accept serial data through a UART for
example, and port it as configuration data to the FPGA, thereby affecting a download, or allow-
ing reconfigurable systems where the FPGA is updated algorithmically by the AVR. For more
information, refer to the “AT94K Series Configuration” application note available on the Atmel
web site, at: http://www.atmel.com/atmel/acrobat/doc2313.pdf.
Resets The user must have the flexibility to issue resets and reconfiguration commands to separate
portions of the device. There are two Reset pins on the FPSLIC device. The first, RESET,
results in a clearing of all FPGA configuration SRAM and the System Control Register, and ini-
tiates a download if in mode 0. The AVR will stop and be reset.
A second reset pin, AVRReset, is implemented to reset the AVR portion of the FPSLIC func-
tional blocks. This is described in the “Reset Sources” on page 61.
EMBEDDED
FPGA CORE
(Operation is not
interrupted during
Cache Logic
loading)
EMBEDDED
AVR CORE
32-BIT CONFIGURATION WORD
Configuration Logic
FPGAD [7:0]
8-bit Configuration
Memory Write Data
24-bit Address Write
FPGAX [7:0]
FPGAY [7:0]
FPGAZ [7:0]
Configuration Clock – Each tick is generated when the Memory-
mapped I/O location FPGAD is written to inside the AVR.
Memory-mapped
Location
Memory-mapped
Location
Memory-mapped
Location
Memory-mapped
Location
CACHEIOWE
A IIIEI.
30 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
System Control
Configuration Modes The AT94K family has four configuration modes controlled by mode pins M0 and M2, see
Table 10.
Modes 2 and 3 are reserved and are used for factory test.
Modes 0 and 1 are pin-compatible with the appropriate AT40K counterpart. AVR I/O will be
taken over by the configuration logic for the CHECK pin during both modes.
Refer to the “AT94K Series Configuration” application note for details on downloading
bitstreams.
System Control
Register – FPGA/AVR
The configuration control register in the FPSLIC consists of 8 bytes of data, which are loaded
with the FPGA/Prog. Code at power-up from external nonvolatile memory. FPSLIC System
Control Register values, see Table 11, can be set in the System Designer software. Recom-
mended defaults are included in the software.
Table 10. Configuration Modes
M2 M0 Name
0 0 Mode 0 - Master Serial
0 1 Mode 1 - Slave Serial Cascade
1 0 Mode 2 - Reserved
1 1 Mode 3 - Reserved
Table 11. FPSLIC System Control Register
Bit Description
SCR0 - SCR1 Reserved
SCR2 0 = Enable Cascading
1 = Disable Cascading
SCR2 controls the operation of the dual-function I/O CSOUT. When SCR2 is set,
the CSOUT pin is not used by the configuration during downloads, set this bit for
configurations where two or more devices are cascaded together. This applies for
configuration to another FPSLIC device or to an FPGA.
SCR3 0 = Check Function Enabled
1 = Check Function Disabled
SCR3 controls the operation of the CHECK pin and enables the Check Function.
When SCR3 is set, the dual use AVR I/O/CHECK pin is not used by the
configuration during downloads, and can be used as AVR I/O.
SCR4 0 = Memory Lockout Disabled
1 = Memory Lockout Enabled
SCR4 is the Security Flag and controls the writing and checking of configuration
memory during any subsequent configuration download. When SCR4 is set, any
subsequent configuration download initiated by the user, whether a normal
download or a CHECK function download, causes the INIT pin to immediately
activate. CON is released, and no further configuration activity takes place. The
download sequence during which SCR4 is set is NOT affected. The Control
Register write is also prohibited, so bit SCR4 may only be cleared by a power-on
reset or manual reset.
SCR5 Reserved
41m
31
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
SCR6 0 = OTS Disabled
1 = OTS Enabled
Setting SCR6 makes the OTS (output tri-state) pin an input which controls the
global tri-state control for all user I/O. This junction allows the user at any time to
tristate all user I/O and isolate the chip.
SCR7 - SCR12 Reserved
SCR13 0 = CCLK Normal Operation
1 = CCLK Continues After Configuration.
Setting bit SCR13 allows the CCLK pin to continue to run after configuration
download is completed. This bit is valid for Master mode, mode 0 only. The CCLK
is not available internally on the device. If it is required in the design, it must be
connected to another device I/O.
SCR14 - SCR15 Reserved
SCR16 - SCR23 0 = GCK 0:7 Always Enabled
1 = GCK 0:7 Disabled During Internal and External Configuration Download.
Setting SCR16:SCR23 allows the user to disable the input buffers driving the
global clocks. The clock buffers are enabled and disabled synchronously with the
rising edge of the respective GCK signal, and stop in a High “1” state. Setting one
of these bits disables the appropriate GCK input buffer only and has no effect on
the connection from the input buffer to the FPGA array.
SCR24 - SCR25 0 = FCK 0:1 Always Enabled
1 = FCK 0:1 Disabled During Internal and External Configuration Download.
Setting SCR24:SCR25 allows the user to disable the input buffers driving the fast
clocks. The clock buffers are enabled and disabled synchronously with the rising
edge of the respective FCK signal, and stop in a High “1” state. Setting one of
these bits disables the appropriate FCK input buffer only and has no effect on the
connection from the input buffer to the FPGA array.
SCR26 0 = Disable On-chip Debugger
1 = Enable On-chip Debugger.
JTAG Enable, SCR27, must also be set (one) and the configuration memory
lockout, SCR4, must be clear (zero) for the user to have access to internal scan
chains.
SCR27 0 = Disable TAP at user FPGA I/O Ports
1 = Enable TAP at user FPGA I/O Ports.
Device ID scan chain and AVR I/O boundary scan chain are available. The user
must set (one) the On-chip Debug Enable, SCR26, and must keep the
configuration memory lockout, SCR4, clear (zero) for the user to have access to
internal scan chains.
SCR28 - SCR29 Reserved
SCR30 0 = Global Set/Reset Normal
1 = Global Set/Reset Active (Low) During Internal and External Configuration
Download.
SCR30 allows the Global set/reset to hold the core DFFs in reset during any
configuration download. The Global set/reset net is released at the end of
configuration download on the rising edge of CON, if set.
SCR31 0 = Disable I/O Tri-state
1 = I/O Tri-state During (Internal and External) Configuration Download.
SCR31 forces all user defined I/O pins to go tri-state during configuration
download. Tri-state is released at the end of configuration download on the rising
edge of CON, if set.
Table 11. FPSLIC System Control Register
Bit Description
A IIIEI.
32 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
SCR32 - SCR34 Reserved
SCR35 0 = AVR Reset Pin Disabled
1 = AVR Reset Pin Enabled (active Low Reset)
SCR35 allows the AVR Reset pin to reset the AVR only.
SCR36 0 = Protect AVR Program SRAM
1 = Allow Writes to AVR Program SRAM (Excluding Boot Block)
SCR36 protects AVR program code from writes by the FPGA.
SCR37 0 = AVR Program SRAM Boot Block Protect
1 = AVR Program SRAM Boot Block Allows Overwrite
SCR38 0 = (default) Frame Clock Inverted to AVR Data/Program SRAM
1 = Non-inverting Clock Into AVR Data/Program SRAM
SCR39 Reserved
SCR40 - SCR41 SCR41 = 0, SCR40 = 0 16 Kbytes x 16 Program/4 Kbytes x 8 Data
SCR41 = 0, SCR40 = 1 14 Kbytes x 16 Program/8 Kbytes x 8 Data
SCR41 = 1, SCR40 = 0 12 Kbytes x 16 Program/12 Kbytes x 8 Data
SCR41 = 1, SCR40 = 1 10 Kbytes x 16 Program/16 Kbytes x 8 Data
SCR40 : SCR41 AVR program/data SRAM partitioning (set by using the AT94K
Device Options in System Designer).
SCR 42 -
SCR47
Reserved
SCR48 0 = EXT-INT0 Driven By Port E<4>
1 = EXT-INT0 Driven By INTP0 pad
SCR48 : SCR53 Defaults dependent on package selected.
SCR49 0 = EXT-INT1 Driven By Port E<5>
1 = EXT-INT1 Driven By INTP1 pad
SCR48 : SCR53 Defaults dependent on package selected.
SCR50 0 = EXT-INT2 Driven By Port E<6>
1 = EXT-INT2 Driven By INTP2 pad
SCR48 : SCR53 Defaults dependent on package selected.
SCR51 0 = EXT-INT3 Driven By Port E<7>
1 = EXT-INT3 Driven By INTP3 pad
SCR48 : SCR53 Defaults dependent on package selected.
SCR52 0 = UART0 Pins Assigned to Port E<1:0>
1 = UART0 Pins Assigned to UART0 pads
SCR48 : SCR53 Defaults dependent on package selected.
SCR53 0 = UART1 Pins Assigned to Port E<3:2>
1 = UART1 Pins Assigned to UART1 pads
SCR48 : SCR53 Defaults dependent on package selected.
On packages less than 144-pins, there is reduced access to AVR ports. Port D is
not available externally in the smallest package and Port E becomes dual-purpose
I/O to maintain access to the UARTs and external interrupt pins. The Pin List (East
Side) on page 177 shows exactly which pins are available in each package.
SCR54 0 = AVR Port D I/O With 6 mA Drive
1 = AVR Port D I/O With 20 mA Drive
SCR55 0 = AVR Port E I/O With 6 mA Drive
1 = AVR Port E I/O With 20 mA Drive
Table 11. FPSLIC System Control Register
Bit Description
41m
33
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
SCR56 0 = Disable XTAL Pin (Rfeedback)
1 = Enable XTAL Pin (Rfeedback)
SCR57 0 = Disable TOSC2 Pin (Rfeedback)
1 = Enable TOSC2 Pin (Rfeedback)
SCR58 - SCR59 Reserved
SCR60 - SCR61 SCR61 = 0, SCR60 = 0 “1”
SCR61 = 0, SCR60 = 1 AVR System Clock
SCR61 = 1, SCR60 = 0 Timer Oscillator Clock (TOSC1)(1)
SCR61 = 1, SCR60 = 1 Watchdog Clock
Global Clock 6 mux select (set by using the AT94K Device Options in System
Designer).
Note: 1. The AS2 bit must be set in the ASSR register.
SCR62 0 = Disable CacheLogic Writes to FPGA by AVR
1 = Enable CacheLogic Writes to FPGA by AVR
SCR63 0 = Disable Access (Read and Write) to SRAM by FPGA
1 = Enable Access (Read and Write) to SRAM by FPGA
Table 11. FPSLIC System Control Register
Bit Description
A IIIEI.
34 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
AVR Core and Peripherals
•AVR Core
Watchdog Timer/On-chip Oscillator
Oscillator-to-Internal Clock Circuit
Oscillator-to-Timer/Counter for Real-time Clock
16-bit Timer/Counter and Two 8-bit Timer/Counters
Interrupt Unit
• Multiplier
•UART (0)
•UART (1)
I/O Port D (full 8 bits available on 144-pin or higher devices)
I/O Port E
The embedded AVR core is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. The embedded AVR core achieves throughputs approaching 1 MIPS per MHz by
executing powerful instructions in a single-clock-cycle, and allows the system architect to opti-
mize power consumption versus processing speed.
The AVR core is based on an enhanced RISC architecture that combines a rich instruction set
with 32 x 8 general-purpose working registers. All the 32 x 8 registers are directly connected to
the Arithmetic Logic Unit (ALU), allowing two independent register bytes to be accessed in one
single instruction executed in one clock cycle. The resulting architecture is more code efficient
while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The embedded AVR core provides the following features: 16 general-purpose I/O lines, 32 x 8
general-purpose working registers, Real-time Counter (RTC), 3 flexible timer/counters with
compare modes and PWM, 2 UARTs, programmable Watchdog Timer with internal oscillator,
2-wire serial port, and three software-selectable Power-saving modes. The Idle mode stops
the CPU while allowing the SRAM, timer/counters, two-wire serial port, and interrupt system to
continue functioning. The Power-down mode saves the register contents but freezes the oscil-
lator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save
mode, the timer oscillator continues to run, allowing the user to maintain a timer base while the
rest of the device is sleeping.
The embedded AVR core is supported with a full suite of program and system development
tools, including C compilers, macro assemblers, program debugger/simulators and evaluation
kits.
41m
35
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Instruction Set
Nomenclature
(Summary)
The complete “AVR Instruction Set” document is available on the Atmel web site, at
http://www.atmel.com/atmel/acrobat/doc0856.pdf.
Status Register
(SREG)
SREG: Status register
C: Carry flag in status register
Z: Zero flag in status register
N: Negative flag in status register
V: Two’s complement overflow indicator
S: N V, For signed tests
H: Half-carry flag in the status register
T: Transfer bit used by BLD and BST instructions
I: Global interrupt enable/disable flag
Registers and
Operands
Rd: Destination (and source) register in the register file
Rr: Source register in the register file
R: Result after instruction is executed
K: Constant data
k: Constant address
b: Bit in the register file or I/O register (0 b 7)
s: Bit in the status register (0 s 2)
X,Y,Z: Indirect address register (X = R27:R26, Y = R29:R28 and Z = R31:R30)
A: I/O location address
q: Displacement for direct addressing (0 q 63)
I/O Registers
Stack
STACK: Stack for return address and pushed registers
SP: Stack Pointer to STACK
Flags
: Flag affected by instruction
0: Flag cleared by instruction
1: Flag set by instruction
-: Flag not affected by instruction
The instructions EIJMP, EICALL, ELPM, GPM, ESPM (from the megaAVR Instruction Set) are
not supported in the FPSLIC device.
A IIIEI.
36 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Complete Instruction Set Summary
Conditional Branch Summary
Test Boolean Mnemonic Complementary Boolean Mnemonic Comment
Rd > Rr Z(N V) = 0 BRLT Rd Rr Z+(N V) = 1 BRGE Signed
Rd Rr (N V) = 0 BRGE Rd < Rr (N V) = 1 BRLT Signed
Rd = Rr Z = 1 BREQ Rd Rr Z = 0 BRNE Signed
Rd Rr Z+(N V) = 1 BRGE Rd > Rr Z(N V) = 0 BRLT Signed
Rd < Rr (N V) = 1 BRLT Rd Rr (N V) = 0 BRGE Signed
Rd > Rr C + Z = 0 BRLO Rd Rr C + Z = 1 BRSH Unsigned
Rd Rr C = 0 BRSH/BRCC Rd < Rr C = 1 BRLO/BRCS Unsigned
Rd = Rr Z = 1 BREQ Rd Rr Z = 0 BRNE Unsigned
Rd Rr C + Z = 1 BRSH Rd > Rr C + Z = 0 BRLO Unsigned
Rd < Rr C = 1 BRLO/BRCS Rd Rr C = 0 BRSH/BRCC Unsigned
Carry C = 1 BRCS No Carry C = 0 BRCC Simple
Negative N = 1 BRMI Positive N = 0 BRPL Simple
Overflow V = 1 BRVS No Overflow V = 0 BRVC Simple
Zero Z = 1 BREQ Not Zero Z = 0 BRNE Simple
Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clock
Arithmetic and Logic Instructions
ADD Rd, Rr Add without Carry Rd Rd + Rr Z,C,N,V,S,H 1
ADC Rd, Rr Add with Carry Rd Rd + Rr + C Z,C,N,V,S,H 1
ADIW Rd, K Add Immediate to Word Rd+1:Rd Rd+1:Rd + K Z,C,N,V,S 2
SUB Rd, Rr Subtract without Carry Rd Rd - Rr Z,C,N,V,S,H 1
SUBI Rd, K Subtract Immediate Rd Rd - K Z,C,N,V,S,H 1
SBC Rd, Rr Subtract with Carry Rd Rd - Rr - C Z,C,N,V,S,H 1
SBCI Rd, K Subtract Immediate with Carry Rd Rd - K - C Z,C,N,V,S,H 1
SBIW Rd, K Subtract Immediate from Word Rd+1:Rd Rd+1:Rd - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Rd Rd Rr Z,N,V,S 1
ANDI Rd, K Logical AND with Immediate Rd Rd K Z,N,V,S 1
OR Rd, Rr Logical OR Rd Rd v Rr Z,N,V,S 1
ORI Rd, K Logical OR with Immediate Rd Rd v K Z,N,V,S 1
EOR Rd, Rr Exclusive OR Rd Rd Rr Z,N,V,S 1
COM Rd One’s Complement Rd $FF - Rd Z,C,N,V,S 1
NEG Rd Two’s Complement Rd $00 - Rd Z,C,N,V,S,H 1
SBR Rd, K Set Bit(s) in Register Rd Rd v K Z,N,V,S 1
41m
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AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
CBR Rd, K Clear Bit(s) in Register Rd Rd ($FFh - K) Z,N,V,S 1
INC Rd Increment Rd Rd + 1 Z,N,V,S 1
DEC Rd Decrement Rd Rd - 1 Z,N,V,S 1
TST Rd Test for Zero or Minus Rd Rd Rd Z,N,V,S 1
CLR Rd Clear Register Rd Rd Rd Z,N,V,S 1
SER Rd Set Register Rd $FF None 1
MUL Rd, Rr Multiply Unsigned R1:R0 Rd × Rr (UU) Z,C 2
MULS Rd, Rr Multiply Signed R1:R0 Rd × Rr (SS) Z,C 2
MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 Rd × Rr (SU) Z,C 2
FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 (Rd × Rr)<<1 (UU) Z,C 2
FMULS Rd, Rr Fractional Multiply Signed R1:R0 (Rd × Rr)<<1 (SS) Z,C 2
FMULSU Rd, Rr Fractional Multiply Signed with
Unsigned
R1:R0 (Rd × Rr)<<1 (SU) Z,C 2
Branch Instructions
RJMP k Relative Jump PC PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC(15:0) Z None 2
JMP k Jump PC k None 3
RCALL k Relative Call Subroutine PC PC + k + 1 None 3
ICALL Indirect Call to (Z) PC(15:0) Z None 3
CALL k Call Subroutine PC k None 4
RET Subroutine Return PC STACK None 4
RETI Interrupt Return PC STACK I 4
CPSE Rd, Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1 / 2 / 3
CP Rd, Rr Compare Rd - Rr Z,C,N,V,S,H 1
CPC Rd, Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1
CPI Rd, K Compare with Immediate Rd - K Z,C,N,V,S,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC PC + 2 or 3 None 1 / 2 / 3
SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC PC + 2 or 3 None 1 / 2 / 3
SBIC A, b Skip if Bit in I/O Register Cleared if(I/O(A,b) = 0) PC PC + 2 or 3 None 1 / 2 / 3
SBIS A, b Skip if Bit in I/O Register Set If(I/O(A,b) = 1) PC PC + 2 or 3 None 1 / 2 / 3
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC PC+k+1 None 1 / 2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC PC+k+1 None 1 / 2
BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1 / 2
BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1 / 2
BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1 / 2
BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1 / 2
Instruction Set Summary (Continued)
Mnemonics Operands Description Operation Flags #Clock
A IIIEI.
38 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1 / 2
BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1 / 2
BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1 / 2
BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1 / 2
BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1 / 2
BRLT k Branch if Less Than, Signed if (N V= 1) then PC PC + k + 1 None 1 / 2
BRHS k Branch if Half-carry Flag Set if (H = 1) then PC PC + k + 1 None 1 / 2
BRHC k Branch if Half-carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1 / 2
BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1 / 2
BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1 / 2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1 / 2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1 / 2
BRIE k Branch if Interrupt Enabled if (I = 1) then PC PC + k + 1 None 1 / 2
BRID k Branch if Interrupt Disabled if (I = 0) then PC PC + k + 1 None 1 / 2
Data Transfer Instructions
MOV Rd, Rr Copy Register Rd Rr None 1
MOVW Rd, Rr Copy Register Pair Rd+1:Rd Rr+1:Rr None 1
LDI Rd, K Load Immediate Rd K None 1
LDS Rd, k Load Direct from Data Space Rd (k) None 2
LD Rd, X Load Indirect Rd (X) None 2
LD Rd, X+ Load Indirect and Post-Increment Rd (X), X X + 1 None 2
LD Rd, -X Load Indirect and Pre-Decrement X X - 1, Rd (X) None 2
LD Rd, Y Load Indirect Rd (Y) None 2
LD Rd, Y+ Load Indirect and Post-Increment Rd (Y), Y Y + 1 None 2
LD Rd, -Y Load Indirect and Pre-Decrement Y Y - 1, Rd (Y) None 2
LDD Rd, Y+q Load Indirect with Displacement Rd (Y + q) None 2
LD Rd, Z Load Indirect Rd (Z) None 2
LD Rd, Z+ Load Indirect and Post-Increment Rd (Z), Z Z+1 None 2
LD Rd, -Z Load Indirect and Pre-Decrement Z Z - 1, Rd (Z) None 2
LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2
STS k, Rr Store Direct to Data Space Rd (k) None 2
ST X, Rr Store Indirect (X) Rr None 2
ST X+, Rr Store Indirect and Post-Increment (X) Rr, X X + 1 None 2
ST -X, Rr Store Indirect and Pre-Decrement X X - 1, (X) Rr None 2
ST Y, Rr Store Indirect (Y) Rr None 2
ST Y+, Rr Store Indirect and Post-Increment (Y) Rr, Y Y + 1 None 2
Instruction Set Summary (Continued)
Mnemonics Operands Description Operation Flags #Clock
41m
39
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
ST -Y, Rr Store Indirect and Pre-Decrement Y Y - 1, (Y) Rr None 2
STD Y+q, Rr Store Indirect with Displacement (Y + q) Rr None 2
ST Z, Rr Store Indirect (Z) Rr None 2
ST Z+, Rr Store Indirect and Post-Increment (Z) Rr, Z Z + 1 None 2
ST -Z, Rr Store Indirect and Pre-Decrement Z Z - 1, (Z) Rr None 2
STD Z+q, Rr Store Indirect with Displacement (Z + q) Rr None 2
LPM Load Program Memory R0 (Z) None 3
LPM Rd, Z Load Program Memory Rd (Z) None 3
LPM Rd, Z+ Load Program Memory and Post-
Increment
Rd (Z), Z Z + 1 None 3
IN Rd, A In From I/O Location Rd I/O(A) None 1
OUT A, Rr Out To I/O Location I/O(A) Rr None 1
PUSH Rr Push Register on Stack STACK Rr None 2
POP Rd Pop Register from Stack Rd STACK None 2
Bit and Bit-test Instructions
LSL Rd Logical Shift Left Rd(n+1)Rd(n),Rd(0)0,CRd(7) Z,C,N,V,H 1
LSR Rd Logical Shift Right Rd(n)Rd(n+1),Rd(7)0,CRd(0) Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1)Rd(n),CRd(7) Z,C,N,V,H 1
ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n)Rd(n+1),CRd(0) Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0) Rd(7..4) None 1
BSET s Flag Set SREG(s) 1SREG(s)1
BCLR s Flag Clear SREG(s) 0 SREG(s) 1
SBI A, b Set Bit in I/O Register I/O(A, b) 1 None 2
CBI A, b Clear Bit in I/O Register I/O(A, b) 0 None 2
BST Rr, b Bit Store from Register to T T Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) T None 1
SEC Set Carry C 1C1
CLC Clear Carry C 0 C 1
SEN Set Negative Flag N 1N1
CLN Clear Negative Flag N 0 N 1
SEZ Set Zero Flag Z 1Z1
CLZ Clear Zero Flag Z 0 Z 1
SEI Global Interrupt Enable I 1I1
CLI Global Interrupt Disable I 0 I 1
SES Set Signed Test Flag S 1S1
Instruction Set Summary (Continued)
Mnemonics Operands Description Operation Flags #Clock
A IIIEI.
40 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Pin Descriptions
VCC Supply voltage
GND Ground
PortD (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal programmable pull-up resistors. The Port
D output buffers can be programmed to sink/source either 6 or 20 mA (SCR54 – see “System
Control Register – FPGA/AVR” on page 30). As inputs, Port D pins that are externally pulled
Low will source current if the programmable pull-up resistors are activated.
The Port D pins are input with pull-up when a reset condition becomes active, even if the clock
is not running. On lower pin count packages Port D may not be available. Check the Pin List
for details.
PortE (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal programmable pull-up resistors. The Port
E output buffers can be programmed to sink/source either 6 or 20 mA (SCR55 – see “System
Control Register – FPGA/AVR” on page 30). As inputs, Port E pins that are externally pulled
Low will source current if the pull-up resistors are activated.
Port E also serves the functions of various special features. See Table 47 on page 149.
The Port E pins are input with pull-up when a reset condition becomes active, even if the clock
is not running
RX0 Input (receive) to UART(0) – See SCR52
TX0 Output (transmit) from UART(0) – See SCR52
RX1 Input (receive) to UART(1) – See SCR53
TX1 Output (transmit) from UART(1) – See SCR53
XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
CLS Clear Signed Test Flag S 0 S 1
SEV Set Two’s Complement Overflow V 1V1
CLV Clear Two’s Complement Overflow V 0 V 1
SET Set T in SREG T 1T1
CLT Clear T in SREG T 0 T 1
SEH Set Half-carry Flag in SREG H 1H1
CLH Clear Half-carry Flag in SREG H 0 H 1
NOP No Operation None 1
SLEEP Sleep (See specific description for Sleep) None 1
WDR Watchdog Reset (See specific description for WDR) None 1
BREAK Break For on-chip debug only None N/A
Instruction Set Summary (Continued)
Mnemonics Operands Description Operation Flags #Clock
% A lDT. ““‘ 5 41m
41
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
XTAL2 Output from the inverting oscillator amplifier
TOSC1 Input to the inverting timer/counter oscillator amplifier
TOSC2 Output from the inverting timer/counter oscillator amplifier
SCL 2-wire serial input/output clock
SDA 2-wire serial input/output data
Clock Options
Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier, which can be
configured for use as an on-chip oscillator, as shown in Figure 24. Either a quartz crystal or a
ceramic resonator may be used.
Figure 24. Oscillator Connections
External Clock To drive the device from an external clock source, XTAL2 should be left unconnected while
XTAL1 is driven as shown in Figure 25.
Figure 25. External Clock Drive Configuration
XTAL2
XTAL1
GND
C2
C1
MAX 1 HC BUFFER
HC
RBIAS C1 = 33 pf
C2 = 27 pf
XTAL2
XTAL1
GND
NC
EXTERNAL
OSCILLATOR
SIGNAL
A IIIEI. , if? T
42 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
No Clock/Oscillator
Source
When not in use, for low static IDD, add a pull-down resistor to XTAL1.
Figure 26. No Clock/Oscillator Connections
Timer Oscillator For the timer oscillator pins, TOSC1 and TOSC2, the crystal is connected directly between the
pins. The oscillator is optimized for use with a 32.768 kHz watch crystal. An external clock sig-
nal applied to this pin goes through the same amplifier having a bandwidth of 1 MHz. The
external clock signal should therefore be in the range
0Hz–1MHz.
Figure 27. Time Oscillator Connections
Architectural
Overview
The AVR uses a Harvard architecture concept – with separate memories and buses for pro-
gram and data. The program memory is accessed with a single level pipeline. While one
instruction is being executed, the next instruction is pre-fetched from the program memory.
This concept enables instructions to be executed in every clock-cycle. The program memory is
in-system programmable SRAM memory. With a few exceptions, AVR instructions have a sin-
gle 16-bit word format, meaning that every program memory address contains a single 16-bit
instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on
the stack. The stack is effectively allocated in the general data SRAM, as a consequence, the
stack size is only limited by the total SRAM size and the usage of the SRAM. All user pro-
grams must initialize the Stack Pointer (SP) in the reset routine (before subroutines or
interrupts are executed). The 16-bit stack pointer is read/write accessible in the I/O space.
The data SRAM can be easily accessed through the five different addressing modes sup-
ported in the AVR architecture.
A flexible interrupt module has its control registers in the I/O space with an additional global
interrupt enable bit in the status register. All the different interrupts have a separate interrupt
vector in the interrupt vector table at the beginning of the program memory. The different inter-
rupts have priority in accordance with their interrupt vector position. The lower the interrupt
vector address, the higher the priority.
The memory spaces in the AVR architecture are all linear and regular memory maps.
XTAL2
XTAL1
GND
NC
RPD
RPD = 4.7 K
TOSC2
TOSC1
C1
C2
RB
RS
C1= 33 pF
C2= 27 pF
RB= 10M
RS= 200K
41m
43
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
General-purpose
Register File
Figure 28 shows the structure of the 32 x 8 general-purpose working registers in the CPU.
Figure 28. AVR CPU General-purpose Working Registers
All the register operating instructions in the instruction set have direct- and single-cycle access
to all registers. The only exception is the five constant arithmetic and logic instructions SBCI,
SUBI, CPI, ANDI and ORI between a constant and a register and the LDI instruction for load-
immediate constant data. These instructions apply to the second half of the registers in the
register file – R16..R31. The general SBC, SUB, CP, AND and OR and all other operations
between two registers or on a single-register apply to the entire register file.
As shown in Figure 28 each register is also assigned a data memory address, mapping the
registers directly into the first 32 locations of the user Data Space. Although not being physi-
cally implemented as SRAM locations, this memory organization provides great flexibility in
access of the registers, as the X, Y and Z registers can be set to index any register in the file.
The 4 to 16 Kbytes of data SRAM, as configured during FPSLIC download, are available for
general data are implemented starting at address $0060 as follows:
Addresses beyond the maximum amount of data SRAM are unavailable for write or read and
will return unknown data if accessed. Ghost memory is not implemented.
7 0 Addr.
R0 $00
R1 $01
R2 $02
. . .
R13 $0D
General-purpose
Working Registers
R14 $0E
R15 $0F
R16 $10
R17 $11
. . .
R26 $1A AVR X-register Low Byte
R27 $1B AVR X-register High Byte
R28 $1C AVR Y-register Low Byte
R29 $1D AVR Y-register High Byte
R30 $1E AVR Z-register Low Byte
R31 $1F AVR Z-register High Byte
4 Kbytes $0060 : $0FFF
8 Kbytes $0060 : $1FFF
12 Kbytes $0060 : $2FFF
16 Kbytes $0060 : $3FFF
A IIIEI.
44 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
X-register,
Y-register and
Z-register
Registers R26..R31 have some added functions to their general-purpose usage. These regis-
ters are address pointers for indirect addressing of the SRAM. The three indirect address
registers X, Y and Z have functions as fixed displacement, automatic increment and decre-
ment (see the descriptions for the different instructions).
ALU – Arithmetic
Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general-purpose
working registers. Within a single clock cycle, ALU operations between registers in the register
file are executed. The ALU operations are divided into three main categories – arithmetic, log-
ical and bit-functions.
Multiplier Unit The high-performance AVR Multiplier operates in direct connection with all the 32 general-pur-
pose working registers. This unit performs 8 x 8 multipliers every two clock cycles. See
multiplier details on page 106.
SRAM Data
Memory
External data SRAM (or program) cannot be used with the FPSLIC AT94K family.
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the register
file, registers R26 to R31 feature the indirect addressing pointer registers.
The Indirect with Displacement mode features a 63 address locations reach from the base
address given by the Y- or Z-register.
When using register indirect addressing modes with automatic Pre-decrement and Post-incre-
ment, the address registers X, Y and Z are decremented and incremented.
The entire data address space including the 32 general-purpose working registers and the 64
I/O registers are all accessible through all these addressing modes. See the next section for a
detailed description of the different addressing modes.
Program and Data
Addressing Modes
The embedded AVR core supports powerful and efficient addressing modes for access to the
program memory (SRAM) and data memory (SRAM, Register File and I/O Memory). This sec-
tion describes the different addressing modes supported by the AVR architecture.
Register Direct, Single-register Rd
The operand is contained in register d (Rd).
Register Direct, Two Registers Rd and Rr
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).
I/O Direct
Operand address is contained in 6 bits of the instruction word.
n
is the destination or source
register address.
Data Direct
A 16-bit data address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the
destination or source register.
Data Indirect with Displacement
Operand address is the result of the Y- or Z-register contents added to the address contained
in 6 bits of the instruction word.
41m
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AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Data Indirect
Operand address is the contents of the X-, Y- or the Z-register.
Data Indirect with Pre-decrement
The X-, Y- or the Z-register is decremented before the operation. Operand address is the dec-
remented contents of the X, Y or the Z-register.
Data Indirect with Post-increment
The X-, Y- or the Z-register is incremented after the operation. The operand address is the
content of the X-, Y- or the Z-register prior to incrementing.
Direct Program Address, JMP and CALL
Program execution continues at the address immediate in the instruction words.
Indirect Program Addressing, IJMP and ICALL
Program execution continues at address contained by the Z-register (i.e., the PC is loaded
with the contents of the Z-register).
Relative Program Addressing, RJMP and RCALL
Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047.
Memory Access Times
and Instruction
Execution Timing
This section describes the general access timing concepts for instruction execution and inter-
nal memory access.
The AVR CPU is driven by the XTAL1 input directly generated from the external clock crystal
for the chip. No internal clock division is used.
Figure 29 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast-access register file concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks and functions per power-unit.
A IIIEI.
46 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Figure 29. The Parallel Instruction Fetches and Instruction Executions
Figure 30 shows the internal timing concept for the register file. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 30. Single Cycle ALU Operation
The internal data SRAM access is performed in two system clock cycles as described in
Figure 31.
Figure 31. On-chip Data SRAM Access Cycles
AVR CLK
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
AVR CLK
Total ExecutionTime
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
AVR CLK
WR
RD
Data
Data
Address Address
T1 T2 T3 T4
Prev. Address
Read Write
41m
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AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Memory-mapped I/O
The I/O space definition of the embedded AVR core is shown in the following table:
AT94K Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference
Page
$3F ($5F) SREG I T H S V N Z C 51
$3E ($5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 57
$3D ($5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 51
$3C ($5C) Reserved
$3B ($5B) EIMF INTF3 INTF2 INTF1 INTF0 INT3 INT2 INT1 INT0 62
$3A ($5A) SFTCR FMXOR WDTS DBG SRST 51
$39 ($59) TIMSK TOIE1 OCIE1A OCIE1B TOIE2 TICIE1 OCIE2 TOIE0 OCIE0 62
$38 ($58) TIFR TOV1 OCF1A OCF1B TOV2 ICF1 OCF2 TOV0 OCF0 63
$37 ($57) Reserved
$36 ($56) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE 110
$35 ($55) MCUR JTRF JTD SE SM1 SM0 PORF WDRF EXTRF 51
$34 ($54) Reserved
$33 ($53) TCCR0 FOC0 PWM0 COM01 COM00 CTC0 CS02 CS01 CS00 69
$32 ($52) TCNT0 Timer/Counter0 (8-bit) 70
$31 ($51) OCR0 Timer/Counter0 Output Compare Register 71
$30 ($50) SFIOR PSR2 PSR10 66
$2F ($4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B PWM11 PWM10 76
$2E ($4E) TCCR1B ICNC1 ICES1 ICPE CTC1 CS12 CS11 CS10 77
$2D ($4D) TCNT1H Timer/Counter1 - Counter Register High Byte 78
$2C ($4C) TCNT1L Timer/Counter1 - Counter Register Low Byte 78
$2B ($4B) OCR1AH Timer/Counter1 - Output Compare Register A High Byte 79
$2A ($4A) OCR1AL Timer/Counter1 - Output Compare Register A Low Byte 79
$29 ($49) OCR1BH Timer/Counter1 - Output Compare Register B High Byte 79
$28 ($48) OCR1BL Timer/Counter1 - Output Compare Register B Low Byte 79
$27 ($47) TCCR2 FOC2 PWM2 COM21 COM20 CTC2 CS22 CS21 CS20 69
$26 ($46) ASSR AS2 TCN20B OCR2UB TCR2UB 73
$25 ($45) ICR1H Timer/Counter1 - Input Capture Register High Byte 80
$24 ($44) ICR1L Timer/Counter1 - Input Capture Register Low Byte 80
$23 ($43) TCNT2 Timer/Counter2 (8-bit) 70
$22 ($42) OCR2 Timer/Counter 2 Output Compare Register 71
$21 ($41) WDTCR WDTOE WDE WDP2 WDP1 WDP0 83
$20 ($40) UBRRHI UART1 Baud Rate High Nibble [11..8] UART0 Baud Rate Low Nibble [11..8] 105
$1F ($3F) TWDR 2-wire Serial Data Register 111
$1E ($3E) TWAR 2-wire Serial Address Register 112
$1D ($3D) TWSR 2-wire Serial Status Register 112
$1C ($3C) TWBR 2-wire Serial Bit Rate Register 109
$1B ($3B) FPGAD FPGA Cache Data Register (D7 - D0) 52
$1A ($3A) FPGAZ FPGA Cache Z Address Register (T3 - T0) (Z3 - Z0) 53
$19 ($39) FPGAY FPGA Cache Y Address Register (Y7 - Y0) 53
$18 ($38) FPGAX FPGA Cache X Address Register (X7 - X0) 53
$17 ($37) FISUD FPGA I/O Select, Interrupt Mask/Flag Register D (Reserved on AT94K05) 54, 56
A IIIEI.
48 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Note: 1. The On-chip Debug Register (OCDR) is detailed on the “FPSLIC On-chip Debug System” distributed within Atmel and select
third-party vendors only under Non-Disclosure Agreement (NDA). Contact fpslic@atmel.com for a copy of this document.
The embedded AVR core I/Os and peripherals, and all the virtual FPGA peripherals are placed in the I/O space. The differ-
ent I/O locations are directly accessed by the IN and OUT instructions transferring data between the 32 x 8 general-
purpose working registers and the I/O space. I/O registers within the address range $00 – $1F are directly bit-accessible
using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC
instructions. When using the I/O specific instructions IN, OUT, the I/O register address $00 – $3F are used, see Figure 32.
When addressing I/O registers as SRAM, $20 must be added to this address. All I/O register addresses throughout this
document are shown with the SRAM address in parentheses.
$16 ($36) FISUC FPGA I/O Select, Interrupt Mask/Flag Register C (Reserved on AT94K05) 54, 56
$15 ($35) FISUB FPGA I/O Select, Interrupt Mask/Flag Register B 54, 56
$14 ($34) FISUA FPGA I/O Select, Interrupt Mask/Flag Register A 54, 56
$13 ($33) FISCR FIADR XFIS1 XFIS0 53
$12 ($32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 124
$11 ($31) DDRD DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 124
$10 ($30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 124
$0F ($2F) Reserved
$0E ($2E) Reserved
$0D ($2D) Reserved
$0C ($2C) UDR0 UART0 I/O Data Register 101
$0B ($2B) UCSR0A RXC0 TXC0 UDRE0 FE0 OR0 U2X0 MPCM0 101
$0A ($2A) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 CHR90 RXB80 TXB80 103
$09 ($29) UBRR0 UART0 Baud-rate Register 105
$08 ($28) OCDR
(Reserved) IDRD Reserved(1)
$07 ($27) PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 126
$06 ($26) DDRE DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 126
$05 ($25) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 126
$04 ($24) Reserved
$03 ($23) UDR1 UART1 I/O Data Register 101
$02 ($22) UCSR1A RXC1 TXC1 UDRE1 FE1 OR1 U2X1 MPCM1 101
$01 ($21) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 CHR91 RXB81 TXB81 103
$00 ($20) UBRR1 UART1 Baud-rate Register 105
AT94K Register Summary (Continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference
Page
41m
49
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Figure 32. Memory-mapped I/O
For single-cycle access (In/Out Commands) to I/O, the instruction has to be less than 16 bits:
In the data SRAM, the registers are located at memory addresses $00 - $1F and the I/O space
is located at memory addresses $20 - $5F.
As there are only 6 bits available to refer to the I/O space, the address is shifted down 2 bits.
This means the In/Out commands access $00 to $3F which goes directly to the I/O and maps
to $20 to $5F in SRAM. All other instructions access the I/O space through the $20 - $5F
addressing.
For compatibility with future devices, reserved bits should be written zero if accessed.
Reserved I/O memory addresses should never be written.
The status flags are cleared by writing a logic 1 to them. Note that the CBI and SBI instructions
will operate on all bits in the I/O register, writing a one back into any flag read as set, thus
clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
opcode register address
5 bits
r0 - 31 ($1F)
5 bits
r0 - 63 ($3F)
6 bits
$00
$1F
$5F
SRAM Space
I/O Space
$00
$3F Memory-mapped
I/O
Registers r0 - r31
Used for In/Out
Instructions
Used for all
Other Instructions
A IIIEI.
50 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Status Register – SREG
The AVR status register(1)SREG – at I/O space location $3F ($5F) is defined as:
Note: 1. Note that the status register is not automatically stored when entering an interrupt routine
and restored when returning from an interrupt routine. This must be handled by software.
Bit 7 - I: Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individ-
ual interrupt enable control is then performed in separate control registers. If the global
interrupt enable register is cleared (zero), none of the interrupts are enabled independent of
the individual interrupt enable settings. The I-bit is cleared by the hardware after an interrupt
has occurred, and is set by the RETI instruction to enable subsequent interrupts.
Bit 6 - T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and des-
tination for the operated bit. A bit from a register in the register file can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the register file by the
BLD instruction.
Bit 5 - H: Half-carry Flag
The half-carry flag H indicates a half-carry in some arithmetic operations.
Bit 4 - S: Sign Bit, S = N V
The S-bit is always an exclusive or between the negative flag N and the two’s complement
overflow flag V.
Bit 3 - V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetics.
Bit 2 - N: Negative Flag
The negative flag N indicates a negative result from an arithmetical or logical operation.
Bit 1 - Z: Zero Flag
The zero flag Z indicates a zero result from an arithmetical or logical operation.
Bit 0 - C: Carry Flag
The carry flag C indicates a carry in an arithmetical or logical operation.
Stack Pointer – SP
The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O
space locations $3E ($5E) and $3D ($5D). Future versions of FPSLIC may support up to 64K
Bytes of memory; therefore, all 16 bits are used.
Bit 76543210
$3F ($5F) I THSVNZCSREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 1514131211109 8
$3E ($5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value00000000
00000000
41m
51
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program
before any subroutine calls are executed or interrupts are enabled. The stack pointer must be
set to point above $60. The Stack Pointer is decremented by one when data is pushed onto
the Stack with the PUSH instruction, and it is decremented by two when an address is pushed
onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one
when data is popped from the Stack with the POP instruction, and it is incremented by two
when an address is popped from the Stack with return from subroutine RET or return from
interrupt RETI.
Software Control
of System
Configuration
The software control register will allow the software to manage select system level configura-
tion bits.
Software Control Register – SFTCR
Bits 7..4 - Res: Reserved Bits
These bits are reserved in the AT94K and always read as zero.
Bit 3 - FMXOR: Frame Mode XOR (Enable/Disable)
This bit is XORed with the System Control Register’s Enable Frame Interface bit. The behavior
when this bit is set to 1 is dependent on how the SCR was initialized. If the Enable Frame
Interface bit in the SCR is 0, the FMXOR bit enables the Frame Interface when set to 1. If the
Enable Frame Interface bit in the SCR is 1, the FMXOR bit disables the Frame Interface when
set to 1. During AVR reset, the FMXOR bit is cleared by the hardware.
Bit 2 - WDTS: Software Watchdog Test Clock Select
When this bit is set to 1, the test clock signal is selected to replace the AVR internal oscillator
into the associated watchdog timer logic. During AVR reset, the WDTS bit is cleared by the
hardware.
Bit 1 - DBG: Debug Mode
When this bit is set to 1, the AVR can write its own program SRAM. During AVR reset, the
DBG bit is cleared by the hardware.
Bit 0 - SRST: Software Reset
When this bit is set (one), a reset request is sent to the system configuration external to the
AVR. Appropriate reset signals are generated back into the AVR and configuration download
is initiated. A software reset will cause the EXTRF bit in the MCUR register to be set (one),
which remains set throughout the AVR reset and may be read by the restarted program upon
reset complete. The external reset flag is set (one) since the requested reset is issued from
the system configuration external to the AVR core. During AVR reset, the SRST bit is cleared
by the hardware.
Bit 76543210
$3A ($5A) ----
FMXOR
WDTS DBG SRST SFTCR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
A IIIEI.
52 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
MCU Control Status/Register – MCUR
The MCU Register contains control bits for general MCU functions and status bits to indicate
the source of an MCU reset.
Bit 7 - JTRF: JTAG Reset Flag
This flag is set (one) upon issuing the AVR_RESET ($C) JTAG instruction. The flag can only
be cleared (zero) by writing a zero to the JTRF bit or by a power-on reset. The bit will not be
cleared by hardware during AVR reset.
Bit 6 - JTD: JTAG Disable
When this bit is cleared (zero), and the System Control Register JTAG Enable bit is set (one),
the JTAG interface is disabled. To avoid unintentional disabling or enabling of the JTAG inter-
face, a timed sequence must be followed when changing this bit: the application software must
write this bit to the desired value twice within four cycles to change its value.
Bit 5 - SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the Sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the Sleep mode unless it is the program-
mers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of
the SLEEP instruction.
Bits 4, 3 - SM1/SM0: Sleep Mode Select Bits 1 and 0
This bit selects between the three available Sleep modes as shown in Table 12.
Bit 2 - PORF: Power-on Reset Flag
This flag is set (one) upon power-up of the device. The flag can only be cleared (zero) by writ-
ing a zero to the PORF bit. The bit will not be cleared by the hardware during AVR reset.
Bit 1 - WDRF: Watchdog Reset Flag
This bit is set if a watchdog reset occurs. The bit is cleared by writing a logic 0 to the flag.
Bit 0 - EXTRF: External (Software) Reset Flag
This flag is set (one) in three separate circumstances: power-on reset, use of Resetn/AVRRe-
setn and writing a one to the SRST bit in the Software Control Register – SFTCR. The PORF
flag can be checked to eliminate power-on reset as a cause for this flag to be set. There is no
way to differentiate between use of Resetn/AVRResetn and software reset. The flag can only
be cleared (zero) by writing a zero to the EXTRF bit. The bit will not be cleared by the hard-
ware during AVR reset.
Bit 76543210
$35 ($55) JTRF JTD SE SM1 SM0 PORF WDRF EXTRF MCUR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 1 0 1
Table 12. Sleep Mode Select
SM1 SM0 Sleep Mode
00Idle
01Reserved
1 0 Power-down
11Power-save
41m
53
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
FPGA Cache Logic FPGA Cache Data Register – FPGAD
The FPGAD I/O Register address is
not
supported by a physical register; it is simply the I/O
address that, if written to, generates the FPGA Cache I/O write strobe. The CACHEIOWE sig-
nal is a qualified version of the AVR IOWE signal. It will only be active if an OUT or ST (store
to) instruction references the FPGAD I/O address. The FPGAD I/O address is write-sensitive-
only; an I/O read to this location is ignored. If the AVR Cache Interface bit in the SCR [BIT62]
is set (one), the data being “written” to this address is cached to the FPGA address specified
by the FPGAX..Z registers (see below) during the active CACHEIOWE strobe.
FPGA Cache Z Address Registers – FPGAX..Z
The three FPGA Cache address registers combine to form the 24-bit address, CAC-
HEADDR[23:0], delivered to the FPGA cache logic outside the AVR block during a write to the
FPGAD I/O Register (see above).
FPGA I/O
Selection by AVR
Sixteen select signals are sent to the FPGA for I/O addressing. These signals are decoded
from four I/O registry addresses (FISUA...D) and extended to sixteen with two bits from the
FPGA I/O Select Control Register (FISCR). In addition, the FPGAIORE and FPGAIOWE sig-
nals are qualified versions of the IORE and IOWE signals. Each will only be active if one of the
four base I/O addresses are referenced. It is necessary for the FPGA design to implement any
required registers for each select line; each qualified with either the FPGAIORE or
FPGAIOWE strobe. Refer to the FPGA/AVR Interface section for more details. Only the
FISCR registers physically exist. The FISUA...D I/O addresses for the purpose of FPGA I/O
selection are NOT supported by AVR Core I/O space registers; they are simply I/O addresses
(available to 1 cycle IN/OUT instructions) which trigger appropriate enabling of the FPGA
select lines and the FPGA IORE/IOWE strobes (see Figure 18 on page 21).
FPGA I/O Select Control Register – FISCR
Bit 7 - FIADR: FPGA Interrupt Addressing Enable
When FIADR is set (one), the four dual-purpose I/O addresses, FISUA..D, are mapped to four
physical registers that provide memory space for FPGA interrupt masking and interrupt flag
status. When FIADR is cleared (zero), and I/O read or write to one of the four dual-purpose I/O
addresses, FISUA..D, will access its associated group of four FPGA I/O select lines. The
XFIS1 and XFIS0 bits (see Table 13) further determine which one select line in the accessed
group is set (one). A read will assign the FPGA I/O read enable to the AVR I/O read enable
(FPGAIORE IORE) and a write, the FPGA I/O write enable to the AVR I/O write enable
Bit 76543210
$1B ($3B) MSB LSB FPGAD
Read/WriteWWWWWWWW
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 76543210
$18 ($38) FCX7 FCX6 FCX5 FCX4 FCX3 FCX2 FCX1 FCX0 FPGAX
$19 ($39) FCY7 FCY6 FCY5 FCY4 FCY3 FCY2 FCY1 FCY0 FPGAY
$1A ($3A) FCT3 FCT2 FCT1 FCT0 FCZ3 FCZ2 FCZ1 FCZ0 FPGAZ
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
$13 ($33) FIADR-----XFIS1XFIS0FISCR
Read/WriteR/WRRRRRR/WR/W
Initial Value 0 0 0 0 0 0 0 0
A IIIEI.
54 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
(FPGAIOWE IOWE). FPGA macros utilizing one or more FPGA I/O select lines must use
the FPGA I/O read/write enables, FPGAIORE or FPGAIOWE, to qualify each select line. The
FIADR bit will be cleared (zero) during AVR reset.
Bits 6..2 - Res: Reserved Bits
These bits are reserved and always read as zero.
Bits 1, 0 - XFIS1, 0: Extended FPGA I/O Select Bits 1, 0
XFIS[1:0] determines which one of the four FPGA I/O select lines will be set (one) within the
accessed group. An I/O read or write to one of the four dual-purpose I/O addresses, FISUA..D,
will access one of four groups. Table 13 details the FPGA I/O selection scheme.
Note: 1. Not available on AT94K05.
In summary, 16 select signals are sent to the FPGA for I/O addressing. These signals are
decoded from four base I/O Register addresses (FISUA..D) and extended to 16 with two bits
from the FPGA I/O Select Control Register, XFIS1 and XFIS0. The FPGA I/O read and write
signals, FPGAIORE and FPGAIOWE, are qualified versions of the AVR IORE and IOWE sig-
nals. Each will only be active if one of the four base I/O addresses is accessed.
Reset: all select lines become active and an FPGAIOWE strobe is enabled. This is to allow the
FPGA design to load zeros (8’h00) from the D-bus into appropriate registers.
Table 13. FPGA I/O Select Line Scheme
Read or Write
I/O Address
FISCR Register FPGA I/O Select Lines
XFIS1 XFIS0 15..12 11..8 7..4 3..0
FISUA $14 ($34)
0 0 0000 0000 0000 0001
0 1 0000 0000 0000 0010
1 0 0000 0000 0000 0100
1 1 0000 0000 0000 1000
FISUB $15 ($35)
0 0 0000 0000 0001 0000
0 1 0000 0000 0010 0000
1 0 0000 0000 0100 0000
1 1 0000 0000 1000 0000
FISUC $16 ($36)(1)
0 0 0000 0001 0000 0000
0 1 0000 0010 0000 0000
1 0 0000 0100 0000 0000
1 1 0000 1000 0000 0000
FISUD $17 ($37)(1)
0 0 0001 0000 0000 0000
0 1 0010 0000 0000 0000
1 0 0100 0000 0000 0000
1 1 1000 0000 0000 0000
41m
55
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
General AVR/FPGA I/O
Select Procedure
I/O select depends on the FISCR register setup and the FISUA..D register written to or read
from.
The following FISCR setups and writing data to the FISUA..D registers will result in the shown
I/O select lines and data presented on the 8-bit AVR–FPGA data bus.
Note: 1. IOSEL 15..8 are not available on AT94K05.
;---------------------------------------------
io_select0_write:
ldi r16,0x00 ;FIADR=0,XFIS1=0,XFIS0=0 ->I/O select line=0
out FISCR,r16 ;load I/O select values into FISCR register
out FISUA,r17; ;select line 0 high. Place data on AVR<->FPGA bus
; from r17 register. (out going data is assumed
; to be present in r17 before calling this subroutine)
ret
;---------------------------------------------
io_select13_read:
ldi r16,0x01 ;FIADR=0,XFIS1=0,XFIS0=1 ->I/O select line=13
out FISCR,r16 ;load I/O select values into FISCR register
in r18,FISUD ;select line 13 high. Read data on AVR<->FPGA bus
;which was placed into register FISUD.
ret
Table 14. FISCR Register Setups and I/O Select Lines.
FISCR Register I/O Select Lines(1)
FIADR(b7)
b6-2
XFIS1(b1)
XFIS0(b0)
FISUA FISUB FISUC FISUD
0 - 0 0 IOSEL 0 IOSEL 4 IOSEL 8 IOSEL 12
0 - 0 1 IOSEL 1 IOSEL 5 IOSEL 9 IOSEL 13
0 - 1 0 IOSEL 2 IOSEL 6 IOSEL 10 IOSEL 14
0 - 1 1 IOSEL 3 IOSEL 7 IOSEL 11 IOSEL 15
56 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Figure 33. Out Instruction – AVR Writing to the FPGA
Note: 1. AVR expects Write to be captured by the FPGA upon posedge of the AVR clock.
Figure 34. In Instruction – AVR Reading FPGA
Notes: 1. AVR captures read data upon posedge of the AVR clock.
2. At the end of an FPGA read cycle, there is a chance for the AVR data bus contention
between the FPGA and another peripheral to start to drive (active IORE at new address ver-
sus FPGAIORE + Select “n”), but since the AVR clock would have already captured the data
from AVR DBUS (= FPGA Data Out), this is adon’t care situation.
AVR INST
AVR CLOCK
AVR IOWE
AVR IOADR
(FISUA, B, C or D)
AVR DBUS
(FPGA DATA IN)
FPGA IOWE
FPGA I/O
SELECT "n"
FPGA CLOCK
(SET TO AVR
SYSTEM CLOCK)
WRITE DATA VALID
(1)
OUT INSTRUCTION
AVR INST
AVR CLOCK
AVR IORE
AVR IOADR
(FISUA, B, C or D)
AVR DBUS
(FPGA DATA OUT)
FPGA IORE
FPGA I/O
SELECT "n"
READ DATA VALID
(1)
IN INSTRUCTION
(2)
(2)
41m
57
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
FPGA I/O Interrupt
Control by AVR
This is an alternate memory space for the FPGA I/O Select addresses. If the FIADR bit in the
FISCR register is set to logic 1, the four I/O addresses, FISUA - FISUD, are mapped to physi-
cal registers and provide memory space for FPGA interrupt masking and interrupt flag status.
If the FIADR bit in the FISCR register is cleared to a logic 0, the I/O register addresses will be
decoded into FPGA select lines.
All FPGA interrupt lines into the AVR are negative edge triggered. See page 58 for interrupt
priority.
Interrupt Control RegistersFISUA..D
Bits 7..4 - FIF3 - 0: FPGA Interrupt Flags 3 - 0
The 16 FPGA interrupt flag bits all work the same. Each is set (one) by a valid negative edge
transition on its associated interrupt line from the FPGA. Valid transitions are defined as any
change in state preceded by at least two cycles of the old state and succeeded by at least two
cycles of the new state. Therefore, it is required that interrupt lines transition from 1 to 0 at
least two cycles after the line is stable High; the line must then remain stable Low for at least
two cycles following the transition. Each bit is cleared by the hardware when executing the cor-
responding interrupt handling vector. Alternatively, each bit will be cleared by writing a logic 1
to it. When the I-bit in the Status Register, the corresponding FPGA interrupt mask bit and the
given FPGA interrupt flag bit are set (one), the associated interrupt is executed.
Bits 7..4 - FIF7 - 4: FPGA Interrupt Flags 7 - 4
See
Bits 7..4 - FIF3 - 0: FPGA Interrupt Flags 3 - 0
.
Bits 7..4 - FIF11 - 8: FPGA Interrupt Flags 11 - 8
See
Bits 7..4 - FIF3 - 0: FPGA Interrupt Flags 3 - 0
. Not available on the AT94K05.
Bits 7..4 - FIF15 - 12: FPGA Interrupt Flags 15 - 12
See
Bits 7..4 - FIF3 - 0: FPGA Interrupt Flags 3 - 0
. Not available on the AT94K05.
Bits 3..0 - FINT3 - 0: FPGA Interrupt Masks 3 - 0(1)
The 16 FPGA interrupt mask bits all work the same. When a mask bit is set (one) and the I-bit
in the Status Register is set (one), the given FPGA interrupt is enabled. The corresponding
interrupt handling vector is executed when the given FPGA interrupt flag bit is set (one) by a
negative edge transition on the associated interrupt line from the FPGA.
Note: 1. FPGA interrupts 3 - 0 will cause a wake-up from the AVR Sleep modes. These interrupts are
treated as low-level triggered in the Power-down and Power-save modes, see “Sleep
Modes” on page 66.
Bits 3..0 - FINT7 - 4: FPGA Interrupt Masks 7 - 4
See
Bits 3..0 - FINT3 - 0: FPGA Interrupt Masks 3 - 0.
Bits 3..0 - FINT11 - 8: FPGA Interrupt Masks 11 - 8
See
Bits 3..0 - FINT3 - 0: FPGA Interrupt Masks 3 - 0.
Not available on the AT94K05.
Bits 3..0 - FINT15 - 12: FPGA Interrupt Masks 15 -12
See
Bits 3..0 - FINT3 - 0: FPGA Interrupt Masks 3 - 0.
Not available on the AT94K05.
Bit 76543210
$14 ($34) FIF3 FIF2 FIF1 FIF0 FINT3 FINT2 FINT1 FINT0 FISUA
$15 ($35) FIF7 FIF6 FIF5 FIF4 FINT7 FINT6 FINT5 FINT4 FSUB
$16 ($36) FIF11 FIF10 FIF9 FIF8 FINT11 FINT10 FINT9 FINT8 FISUC
$17 ($37) FIF15 FIF14 FIF13 FIF12 FINT15 FINT14 FINT13 FINT12 FISUD
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
A IIIEI.
58 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Reset and
Interrupt Handling
The embedded AVR and FPGA core provide 35 different interrupt sources. These interrupts
and the separate reset vector each have a separate program vector in the program memory
space. All interrupts are assigned individual enable bits (masks) which must be set (one)
together with the I-bit in the status register in order to enable the interrupt.
The lowest addresses in the program memory space must be defined as the Reset and Inter-
rupt vectors. The complete list of vectors is shown in Table 15. The list also determines the
priority levels of the different interrupts. The lower the address the higher the priority level.
RESET has the highest priority, and next is FPGA_INT0 – the FPGA Interrupt Request 0 etc.
Table 15. Reset and Interrupt Vectors
Vector No.
(hex)
Program
Address Source Interrupt Definition
01 $0000 RESET Reset Handle: Program
Execution Starts Here
02 $0002 FPGA_INT0 FPGA Interrupt0 Handle
03 $0004 EXT_INT0 External Interrupt0 Handle
04 $0006 FPGA_INT1 FPGA Interrupt1 Handle
05 $0008 EXT_INT1 External Interrupt1 Handle
06 $000A FPGA_INT2 FPGA Interrupt2 Handle
07 $000C EXT_INT2 External Interrupt2 Handle
08 $000E FPGA_INT3 FPGA Interrupt3 Handle
09 $0010 EXT_INT3 External Interrupt3 Handle
0A $0012 TIM2_COMP Timer/Counter2 Compare
Match Interrupt Handle
0B $0014 TIM2_OVF Timer/Counter2 Overflow
Interrupt Handle
0C $0016 TIM1_CAPT Timer/Counter1 Capture
Event Interrupt Handle
0D $0018 TIM1_COMPA Timer/Counter1 Compare
Match A Interrupt Handle
0E $001A TIM1_COMPB Timer/Counter1 Compare
Match B Interrupt Handle
0F $001C TIM1_OVF Timer/Counter1 Overflow
Interrupt Handle
10 $001E TIM0_COMP Timer/Counter0 Compare
Match Interrupt Handle
11 $0020 TIM0_OVF Timer/Counter0 Overflow
Interrupt Handle
12 $0022 FPGA_INT4 FPGA Interrupt4 Handle
13 $0024 FPGA_INT5 FPGA Interrupt5 Handle
14 $0026 FPGA_INT6 FPGA Interrupt6 Handle
15 $0028 FPGA_INT7 FPGA Interrupt7 Handle
16 $002A UART0_RXC UART0 Receive Complete
Interrupt Handle
41m
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AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
17 $002C UART0_DRE UART0 Data Register Empty
Interrupt Handle
18 $002E UART0_TXC UART0 Transmit Complete
Interrupt Handle
19 $0030 FPGA_INT8 FPGA Interrupt8 Handle
(not available on AT94K05)
1A $0032 FPGA_INT9 FPGA Interrupt9 Handle
(not available on AT94K05)
1B $0034 FPGA_INT10 FPGA Interrupt10 Handle
(not available on AT94K05)
1C $0036 FPGA_INT11 FPGA Interrupt11 Handle
(not available on AT94K05)
1D $0038 UART1_RXC UART1 Receive Complete
Interrupt Handle
1E $003A UART1_DRE UART1 Data Register Empty
Interrupt Handle
1F $003C UART1_TXC UART1 Transmit Complete
Interrupt Handle
20 $003E FPGA_INT12 FPGA Interrupt12 Handle
(not available on AT94K05)
21 $0040 FPGA_INT13 FPGA Interrupt13 Handle
(not available on AT94K05)
22 $0042 FPGA_INT14 FPGA Interrupt14 Handle
(Not Available on AT94K05)
23 $0044 FPGA_INT15 FPGA Interrupt15 Handle
(not available on AT94K05)
24 $0046 TWS_INT 2-wire Serial Interrupt
Table 15. Reset and Interrupt Vectors (Continued)
Vector No.
(hex)
Program
Address Source Interrupt Definition
A IIIEI.
60 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
The most typical program setup for the Reset and Interrupt Vector Addresses are:
Note: 1. Not Available on AT94K05. However, the vector jump table positions must be maintained for
appropriate UART and 2-wire serial interrupt jumps.
Address
Labels Code Comments
$0000 jmp RESET Reset Handle: Program Execution Starts Here
$0002 jmp FPGA_INT0 ; FPGA Interrupt0 Handle
$0004 jmp EXT_INT0 ; External Interrupt0 Handle
$0006 jmp FPGA_INT1 ; FPGA Interrupt1 Handle
$0008 jmp EXT_INT1 ; External Interrupt1 Handle
$000A jmp FPGA_INT2 ; FPGA Interrupt2 Handle
$000C jmp EXT_INT2 ; External Interrupt2 Handle
$000E jmp FPGA_INT3 ; FPGA Interrupt3 Handle
$0010 jmp EXT_INT3 ; External Interrupt3 Handle
$0012 jmp TIM2_COMP
; Timer/Counter2 Compare Match Interrupt Handle
$0014 jmp TIM2_OVF
; Timer/Counter2 Overflow Interrupt Handle
$0016 jmp TIM1_CAPT
; Timer/Counter1 Capture Event Interrupt Handle
$0018 jmp TIM1_COMPA
; Timer/Counter1 Compare Match A Interrupt Handle
$001A jmp TIM1_COMPB
; Timer/Counter1 Compare Match B Interrupt Handle
$001C jmp TIM1_OVF ; Timer/Counter1 Overflow Interrupt Handle
$001E jmp TIM0_COMP
; Timer/Counter0 Compare Match Interrupt Handle
$0020 jmp TIM0_OVF ; Timer/Counter0 Overflow Interrupt Handle
$0022 jmp FPGA_INT4 ; FPGA Interrupt4 Handle
$0024 jmp FPGA_INT5 ; FPGA Interrupt5 Handle
$0026 jmp FPGA_INT6 ; FPGA Interrupt6 Handle
$0028 jmp FPGA_INT7 ; FPGA Interrupt7 Handle
$002A jmp UART0_RXC ; UART0 Receive Complete Interrupt Handle
$002C jmp UART0_DRE
; UART0 Data Register Empty Interrupt Handle
$002E jmp UART0_TXC ; UART0 Transmit Complete Interrupt Handle
$0030 jmp FPGA_INT8 ; FPGA Interrupt8 Handle(1)
$0032 jmp FPGA_INT9 ; FPGA Interrupt9 Handle(1)
$0034 jmp FPGA_INT10 ; FPGA Interrupt10 Handle(1)
$0036 jmp FPGA_INT11 ; FPGA Interrupt11 Handle(1)
$0038 jmp UART1_RXC ; UART1 Receive Complete Interrupt Handle
$003A jmp UART1_DRE
; UART1 Data Register Empty Interrupt Handle
$003C jmp UART1_TXC ; UART1 Transmit Complete Interrupt Handle
$003E jmp FPGA_INT12 ; FPGA Interrupt12 Handle(1)
$0040 jmp FPGA_INT13 ; FPGA Interrupt13 Handle(1)
$0042 jmp FPGA_INT14 ; FPGA Interrupt14 Handle(1)
$0044 jmp FPGA_INT15 ; FPGA Interrupt15 Handle(1)
$0046 jmp TWS_INT ; 2-wire Serial Interrupt
;
RESET:
$0048 ldi
r16,high(RAMEND)
; Main program start
$0049 out SPH,r16
$004A ldi
r16,low(RAMEND)
$004B out SPL,r16
$004C <instr> xxx
... ... ...
A IIIEI.
61
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Reset Sources The embedded AVR core has five sources of reset:
External Reset. The MCU is reset immediately when a low-level is present on the RESET
or AVR RESET pin.
Power-on Reset. The MCU is reset upon chip power-up and remains in reset until the
FPGA configuration has entered Idle mode.
Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the
watchdog is enabled.
Software Reset. The MCU is reset when the SRST bit in the Software Control register is
set (one).
JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register,
one of the scan chains of the JTAG system. See “IEEE 1149.1 (JTAG) Boundary-scan” on
page 73.
During reset, all I/O registers except the MCU Status register are then set to their Initial Val-
ues, and the program starts execution from address $0000. The instruction placed in address
$0000 must be a JMP absolute jump instruction to the reset handling routine. If the program
never enables an interrupt source, the interrupt vectors are not used, and regular program
code can be placed at these locations. The circuit diagram in Figure 35 shows the reset logic.
Table 16 defines the timing and electrical parameters of the reset circuitry.
Figure 35. Reset Logic
MCU STATUS
DATA BUS
RESET/
AVR RESET
WATCHDOG
TIMER
INTERNAL
OSCILLATOR
SYSTEM
CLOCK
DELAY COUNTERS
QS
R
INTERNAL
RESET
POR
COUNTER RESET
SEL [4:0] CONTROLLED
BY FPGA CONFIGURATION
FULL
FPGA
CONFIG
LOGIC
EXTRF
WDRF
SFTCR
BIT 0
PORF
JTAG RESET
REGISTER
JT RF
A IIIEI.
62 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Note: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling).
Power-on Reset A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As shown in
Figure 35, an internal timer clocked from the Watchdog Timer oscillator prevents the MCU
from starting until after a certain period after VCC has reached the Power-on Threshold voltage
– VPOT, regardless of the VCC rise time (see Figure 36 and Figure 37).
Figure 36. MCU Start-up, RESET Tied to VCC
Figure 37. Watchdog Reset during Operation
Table 16. Reset Characteristics (VCC = 3.3V)
Symbol Parameter Minimum Typical Maximum Units
VPOT(1)
Power-on Reset Threshold
(Rising) 1.0 1.4 1.8 V
Power-on Reset Threshold
(Falling) 0.4 0.6 0.8 V
VRST
RESET Pin Threshold
Voltage VCC/2 V
TTOUT Reset Delay Time-out Period
5CPU
cycles
0.4
3.2
12.8
0.5
4.0
16.0
0.6
4.8
19.2
ms
V
CC
RESET
TIME-OUT
INTERNAL RESET
t
TOUT
V
POT
V
RST
RESET (HIGH)
RESET TIME-OUT
INTERNAL RESET
WDT TIME-OUT
tTOUT
1 XTAL CYCLE
VCC (HIGH)
41m
63
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
The MCU after five CPU clock-cycles, and can be used when an external clock signal is
applied to the XTAL1 pin. This setting does not use the WDT oscillator, and enables very fast
start-up from the Sleep, Power-down or Power-save modes if the clock signal is present dur-
ing sleep.
RESET can be connected to VCC directly or via an external pull-up resistor. By holding the pin
Low for a period after VCC has been applied, the Power-on Reset period can be extended.
Refer to Figure 38 for a timing example on this.
Figure 38. MCU Start-up, RESET Controlled Externally
External Reset An external reset is generated by a low-level on the AVRRESET pin. When the applied signal
reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay timer starts the
MCU after the Time-out period tTOUT has expired.
Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration.
On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT.
Time-out period tTOUT is approximately 3 µs – at VCC = 3.3V. the period of the time out is volt-
age dependent.
Software Reset See “Software Control of System Configuration” on page 51.
Interrupt Handling The embedded AVR core has one dedicated 8-bit Interrupt Mask control register: TIMSK
Timer/Counter Interrupt Mask Register. In addition, other enable and mask bits can be found
in the peripheral control registers.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts
are disabled. The user software can set (one) the I-bit to enable nested interrupts. The I-bit is
set (one) when a Return from Interrupt instruction (RETI) is executed.
When the Program Counter is vectored to the actual interrupt vector in order to execute the
interrupt handling routine, the hardware clears the corresponding flag that generated the inter-
rupt. Some of the interrupt flags can also be cleared by writing a logic 1 to the flag bit
position(s) to be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero),
the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero),
the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable
bit is set (one), and will be executed by order of priority.
The status register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt routine. This must be handled by software.
RESET
TIME-OUT
INTERNAL RESET
tTOUT
VRST
VCC VPOT
A IIIEI.
64 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
External Interrupt Mask/Flag Register – EIMF
Bits 3..0 - INT3, 2, 1, 0: External Interrupt Request 3, 2, 1, 0 Enable
When an INT3 - INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the corresponding external pin interrupt is enabled. The external interrupts are always nega-
tive edge triggered interrupts, see “Sleep Modes” on page 66.
Bits 7..4 - INTF3, 2, 1, 0: External Interrupt 3, 2, 1, 0 Flags
When a falling edge is detected on the INT3, 2, 1, 0 pins, an interrupt request is triggered. The
corresponding interrupt flag, INTF3, 2, 1, 0 becomes set (one). If the I-bit in SREG and the
corresponding interrupt enable bit, INT3, 2, 1, 0 in EIMF, are set (one), the MCU will jump to
the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively,
the flag is cleared by writing a logic 1 to it.
Timer/Counter Interrupt Mask Register – TIMSK
Bit 7 - TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Inter-
rupt Flag Register – TIFR.
Bit 6 - OCIE1A: Timer/Counter1 Output CompareA Match Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt is exe-
cuted if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the
Timer/Counter Interrupt Flag Register – TIFR.
Bit 5 - OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt is exe-
cuted if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the
Timer/Counter Interrupt Flag Register – TIFR.
Bit 4 - TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter inter-
rupt flag register – TIFR.
Bit 3 - TICIE1: Timer/Counter1 Input Capture Interrupt Enable
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 input capture event interrupt is enabled. The corresponding interrupt is exe-
cuted if a capture-triggering event occurs on pin 29, (IC1), i.e., when the ICF1 bit is set in the
Timer/Counter interrupt flag register – TIFR.
Bit 76543210
$3B ($5B) INTF3 INTF2 INTF1 INTF0 INT3 INT2 INT1 INT0 EIMF
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
$39 ($39) TOIE1
OCIE1A OCIE1B
TOIE2 TICIE1 OCIE2 TOIE0 OCIE0 TIMSK
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
41m
65
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Bit 2 - OCIE2: Timer/Counter2 Output Compare Interrupt Enable
When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is executed
if a Compare match in Timer/Counter2 occurs, i.e., when the OCF2 bit is set in the
Timer/Counter interrupt flag register – TIFR.
Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Inter-
rupt Flag Register – TIFR.
Bit 0 - OCIE0: Timer/Counter0 Output Compare Interrupt Enable
When the OCIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed
if a Compare match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in the
Timer/Counter Interrupt Flag Register – TIFR.
Timer/Counter Interrupt Flag Register – TIFR
Bit 7 - TOV1: Timer/Counter1 Overflow Flag
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by the
hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is
cleared by writing a logic 1 to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1
Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is
executed. In PWM mode, this bit is set when Timer/Counter1 advances from $0000.
Bit 6 - OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the
data in OCR1A – Output Compare Register 1A. OCF1A is cleared by the hardware when exe-
cuting the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a
logic 1 to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare Interrupt
Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is
executed.
Bit 5 - OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the
data in OCR1B – Output Compare Register 1B. OCF1B is cleared by the hardware when exe-
cuting the corresponding interrupt handling vector. Alternatively, OCF1B is cleared by writing a
logic 1 to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match
Interrupt Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Inter-
rupt is executed.
Bit 4 - TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by the
hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is
cleared by writing a logic 1 to the flag. When the I-bit in SREG, and TOIE2 (Timer/Counter1
Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow Interrupt is
executed. In PWM mode, this bit is set when Timer/Counter2 advances from $00.
Bit 76543210
$38 ($58) TOV1 OCF1A OCF1B TOV2 ICF1 OCF2 TOV0 OCF0 TIFR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
A IIIEI.
66 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Bit 3 - ICF1: Input Capture Flag 1
The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1
value has been transferred to the input capture register – ICR1. ICF1 is cleared by the hard-
ware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is
cleared by writing a logic 1 to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1
Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt
is executed.
Bit 2 - OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when compare match occurs between Timer/Counter2 and the data
in OCR2 – Output Compare Register 2. OCF2 is cleared by the hardware when executing the
corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic 1 to
the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2 Compare Interrupt Enable), and
the OCF2 are set (one), the Timer/Counter2 Output Compare Interrupt is executed.
Bit 1 - TOV0: Timer/Counter0 Overflow Flag
The TOV0 bit is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by the
hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is
cleared by writing a logic 1 to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0
Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is
executed. In PWM mode, this bit is set when Timer/Counter0 advances from $00.
Bit 0 - OCF0: Output Compare Flag 0
The OCF0 bit is set (one) when compare match occurs between Timer/Counter0 and the data
in OCR0 – Output Compare Register 0. OCF0 is cleared by the hardware when executing the
corresponding interrupt handling vector. Alternatively, OCF0 is cleared by writing a logic 1 to
the flag. When the I-bit in SREG, and OCIE0 (Timer/Counter2 Compare Interrupt Enable), and
the OCF0 are set (one), the Timer/Counter0 Output Compare Interrupt is executed.
Interrupt Response
Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-
mum. Four clock cycles after the interrupt flag has been set, the program vector address for
the actual interrupt handling routine is executed. During this four clock-cycle period, the Pro-
gram Counter (2 bytes) is pushed onto the Stack, and the Stack Pointer is decremented by 2.
The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If
an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed
before the interrupt is serviced.
A return from an interrupt handling routine (same as for a subroutine call routine) takes four
clock cycles. During these four clock cycles, the Program Counter (2 bytes) is popped back
from the Stack, and the Stack Pointer is incremented by 2. When the AVR exits from an inter-
rupt, it will always return to the main program and execute one more instruction before any
pending interrupt is serviced.
Sleep Modes To enter any of the three Sleep modes, the SE bit in MCUR must be set (one) and a SLEEP
instruction must be executed. The SM1 and SM0 bits in the MCUR register select which Sleep
mode (Idle, Power-down, or Power-save) will be activated by the SLEEP instruction, see
Table 12 on page 52.
In Power-down and Power-save modes, the four external interrupts, EXT_INT0...3, and FPGA
interrupts, FPGA INT0...3, are triggered as low level-triggered interrupts. If an enabled inter-
rupt occurs while the MCU is in a Sleep mode, the MCU awakes, executes the interrupt
routine, and resumes execution from the instruction following SLEEP. The contents of the reg-
ister file, SRAM, and I/O memory are unaltered. If a reset occurs during Sleep mode, the MCU
wakes up and executes from the Reset vector
41m
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AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
Idle Mode When the SM1/SM0 bits are set to 00, the SLEEP instruction makes the MCU enter the Idle
mode, stopping the CPU but allowing UARTs, Timer/Counters, Watchdog 2-wire Serial and
the Interrupt System to continue operating. This enables the MCU to wake-up from external
triggered interrupts as well as internal ones like the Timer Overflow and UART Receive Com-
plete interrupts. When the MCU wakes up from Idle mode, the CPU starts program execution
immediately.
Power-down Mode When the SM1/SM0 bits are set to 10, the SLEEP instruction makes the MCU enter the
Power-down mode. In this mode, the external oscillator is stopped, while the external inter-
rupts and the watchdog (if enabled) continue operating. Only an external reset, a watchdog
reset (if enabled), or an external level interrupt can wake-up the MCU.
In Power-down and Power-save modes, the four external interrupts, EXT_INT0...3, and FPGA
interrupts, FPGA_INT0...3, are treated as low-level triggered interrupts.
If a level-triggered interrupt is used for wake-up from Power-down mode, the changed level
must be held for some time to wake-up the MCU. This makes the MCU less sensitive to noise.
The changed level is sampled twice by the watchdog oscillator clock, and if the input has the
required level during this time, the MCU will wake-up. The period of the watchdog oscillator is
1 µs (nominal) at 3.3V and 25°C. The frequency of the watchdog oscillator is
voltage dependent.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same time-set bits that define the
reset time-out period. The wake-up period is equal to the clock reset period, as shown in
Figure 22 on page 89.
If the wake-up condition disappears before the MCU wakes up and starts to execute, the inter-
rupt causing the wake-up will not be executed.
Power-save Mode When the SM1/SM0 bits are 11, the SLEEP instruction makes the MCU enter the Power-save
mode. This mode is identical to power-down, with one exception:
If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set, Timer/Counter2
will run during sleep. In addition to the power-down wake-up sources, the device can also
wake-up from either Timer Overflow or Output Compare event from Timer/Counter2 if the cor-
responding Timer/Counter2 interrupt enable bits are set in TIMSK. To ensure that the part
executes the Interrupt routine when waking up, also set the global interrupt enable bit in
SREG.
When waking up from Power-save mode by an external interrupt, two instruction cycles are
executed before the interrupt flags are updated. When waking up by the asynchronous timer,
three instruction cycles are executed before the flags are updated. During these cycles, the
processor executes instructions, but the interrupt condition is not readable, and the interrupt
routine has not started yet. See Table 3 on page 15 for clock activity during Power-down,
Power-save and Idle modes.
A IIIEI.
68 AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
JTAG Interface and
On-chip Debug
System
Features JTAG (IEEE std. 1149.1 Compliant) Interface
AVR I/O Boundary-scan Capabilities According to the JTAG Standard
Debugger Access to:
All Internal Peripheral Units
AVR Program and Data SRAM
The Internal Register File
Program Counter/Instruction
FPGA/AVR Interface
Extensive On-chip Debug Support for Break Conditions, Including
Break on Change of Program Memory Flow
Single Step Break
Program Memory Breakpoints on Single Address or Address Range
Data Memory Breakpoints on Single Address or Address Range
FPGA Hardware Break
Frame Memory Breakpoint on Single Address
On-chip Debugging Supported by AVR Studio version 4 or above
Overview The AVR IEEE std. 1149.1 compliant JTAG interface is used for on-chip debugging.
The On-Chip Debug support is considered being private JTAG instructions, and distributed
within ATMEL and to selected third-party vendors only.
Figure 39 shows a block diagram of the JTAG interface and the On-Chip Debug system. The
TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller
selects either the JTAG Instruction Register or one of several Data Registers as the scan
chain (shift register) between the TDI - input and TDO - output. The Instruction Register holds
JTAG instructions controlling the behavior of a Data Register.
Of the Data Registers, the ID-Register, Bypass Register, and the AVR I/O Boundary-Scan
Chain are used for board-level testing. The Internal Scan Chain and Break-Point Scan Chain
are used for On-Chip debugging only.
The Test Access
Port TAP
The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these
pins constitute the Test Access Port - TAP. These pins are:
TMS: Test Mode Select. This pin is used for navigating through the TAP-controller state
machine.
TCK: Test Clock. JTAG operation is synchronous to TCK
TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data
Register (Scan Chains)
TDO: Test Data Out. Serial output data from Instruction register or Data Register
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST - Test ReSeT - which is not
provided.
When the JTAGEN bit is unprogrammed, these four TAP pins revert to normal operation.
When programmed, the input TAP signals are internally pulled High and the JTAG is enabled
for Boundary-Scan. System Designer sets this bit by default.
For the On-Chip Debug system, in addition the RESET pin is monitored by the debugger to be
able to detect external reset sources. The debugger can also pull the RESET pin Low to reset
the whole system, assuming only open collectors on reset line are used in the application.
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Figure 39. Block Diagram
TAP
CONTROLLER
T
DI
T
DO
T
CK
T
MS
AVR CPU
DIGITAL
PERIPHERAL
UNITS
OCD / AVR CORE
COMMUNICATION
INTERFACE
BREAKPOINT
UNIT FLOW CONTROL
UNIT
OCD STATUS
AND CONTROL
INTERNAL
SCAN
CHAIN
M
U
X
JTAG INSTRUCTION
REGISTER
DEVICE ID
REGISTER
BYPASS
REGISTER
PC
Instruction
BREAKPOINT
SCAN CHAIN
ADDRESS
DECODER
PORT E
2-wire Serial
AVR BOUNDARY-SCAN CHAIN
DEVICE BOUNDARY
PROGRAM/DATA
SRAM
M
U
X
AVR RESET
SCAN CHAIN
FPGA-AVR
SCAN CHAIN
FPGA-SRAM
SCAN CHAIN
RESET CONTROL
UNIT
70 AT94KAL Series FPSLIC
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Figure 40. TAP Controller State Diagram
TAP Controller
The TAP controller is a 16-state finite state machine that controls the operation of the Bound-
ary-Scan circuitry and On-Chip Debug system. The state transitions depicted in Figure 40
depend on the signal present on TMS (shown adjacent to each state transition) at the time of
the rising edge at TCK. The initial state after a Power-On Reset is Test-Logic-Reset.
As a definition in this document, the LSB is shifted in and out first for all shift registers.
Test-Logic-Reset
Run-Test/Idle
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
Select-DR Scan
Capture-DR
0
1
011 1
00
00
11
10
1
1
0
1
0
0
10
1
1
0
1
0
0
00
11
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Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is
At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the
Shift Instruction Register - Shift-IR state. While TMS is Low, shift the 4 bit JTAG
instructions into the JTAG instruction register from the TDI input at the rising edge of TCK,
while the captured IR-state 0x01 is shifts out on the TDO pin. The JTAG Instruction
selects a particular Data Register as path between TDI and TDO and controls the circuitry
surrounding the selected Data Register.
Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is
latched onto the parallel output from the shift register path in the Update-IR state. The
Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine.
At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift
Data Register - Shift-DR state. While TMS is Low, upload the selected Data Register
(selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI
input at the rising edge of TCK. At the same time, the parallel inputs to the Data Register
captured in the Capture-DR state shifts out on the TDO pin.
Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data
Register has a latched parallel-output, the latching takes place in the Update-DR state.
The Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state
machine.
As shown in Figure 40 on page 70, the Run-Test/Idle(1) state need not be entered between
selecting JTAG instruction and using Data Registers, and some JTAG instructions may select
certain functions to be performed in the Run-Test/Idle, making it unsuitable as an Idle state.
Note: 1. Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always
be entered by holding TMS High for 5 TCK clock periods.
Using the
Boundary-scan Chain
A complete description of the Boundary-Scan capabilities are given in the section “IEEE
1149.1 (JTAG) Boundary-scan” on page 73.
Using the On-chip
Debug System
As shown in Figure 39, the hardware support for On-Chip Debugging consists mainly of
A scan chain on the interface between the internal AVR CPU and the internal peripheral
units
A breakpoint unit
A communication interface between the CPU and JTAG system
A scan chain on the interface between the internal AVR CPU and the FPGA
A scan chain on the interface between the internal Program/Data SRAM and the FPGA
All read or modify/write operations needed for implementing the Debugger are done by apply-
ing AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an
I/O memory mapped location which is part of the communication interface between the CPU
and the JTAG system.
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The Breakpoint Unit implements Break on Change of Program Flow, Single Step Break, 2 Pro-
gram Memory Breakpoints, and 2 combined break points. Together, the 4 break-points can be
configured as either:
4 single Program Memory break points
3 Single Program Memory break point + 1 single Data Memory break point
2 single Program Memory break points + 2 single Data Memory break points
2 single Program Memory break points + 1 Program Memory break point with mask
(‘range break point’)
2 single Program Memory break points + 1 Data Memory break point with mask (‘range
break point’)
1 single Frame Memory break point is available parallel to all the above combinations
A list of the On-Chip Debug specific JTAG instructions is given in “On-chip Debug Specific
JTAG Instructions”. Atmel supports the On-Chip Debug system with the AVR Studio front-end
software for PCs. The details on hardware implementation and JTAG instructions are there-
fore irrelevant for the user of the On-Chip Debug system.
The JTAG Enable bit must be set (one) in the System Control Register to enable the JTAG
Test Access Port. In addition, the On-chip Debug Enable bit must be set (one).
The AVR Studio enables the user to fully control execution of programs on an AVR device with
On-Chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR Instruction Set Simula-
tor. AVR Studio supports source level execution of Assembly programs assembled with Atmel
Corporation’s AVR Assembler and C programs compiled with third-party vendors’ compilers.
AVR Studio runs under Microsoft Windows® 95/98/2000 and Microsoft WindowsNT®.
All necessary execution commands are available in AVR Studio, both on source level and on
disassembly level. The user can execute the program, single step through the code either by
tracing into or stepping over functions, step out of functions, place the cursor on a statement
and execute until the statement is reached, stop the execution, and reset the execution target.
In addition, the user can have up to 2 data memory breakpoints, alternatively combined as a
mask (range) break-point.
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On-chip Debug
Specific JTAG
Instructions
The On-Chip debug support is considered being private JTAG instructions, and distributed
within ATMEL and to selected third-party vendors only. Table 17 lists the instruction opcode.
IEEE 1149.1
(JTAG)
Boundary-scan
Features JTAG (IEEE std. 1149.1 compliant) Interface
Boundary-scan Capabilities According to the JTAG Standard
Full Scan of All Port Functions
Supports the Optional IDCODE Instruction
Additional Public AVR_RESET Instruction to Reset the AVR
System Overview The Boundary-Scan chain has the capability of driving and observing the logic levels on the
AVR’s digital I/O pins. At system level, all ICs having JTAG capabilities are connected serially
by the TDI/TDO signals to form a long shift register. An external controller sets up the devices
to drive values at their output pins, and observe the input values received from other devices.
The controller compares the received data with the expected result. In this way, Boundary-
Scan provides a mechanism for testing interconnections and integrity of components on
Printed Circuits Boards by using the 4 TAP signals only.
The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAM-
PLE/PRELOAD, and EXTEST, as well as the AVR specific public JTAG instruction
AVR_RESET can be used for testing the Printed Circuit Board. Initial scanning of the data reg-
ister path will show the ID-code of the device, since IDCODE is the default JTAG instruction. It
may be desirable to have the AVR device in reset during test mode. If not reset, inputs to the
device may be determined by the scan operations, and the internal software may be in an
Table 17. JTAG Instruction and Code
JTAG Instruction 4-bit Code Selected Scan Chain # Bits
EXTEST $0 (0000) AVR I/O Boundary 69
IDCODE $1 (0001) Device ID 32
SAMPLE_PRELOAD $2 (0010) AVR I/O Boundary 69
RESERVED $3 (0011) N/A
PRIVATE $4 (0100) FPSLIC On-chip Debug System
PRIVATE $5 (0101) FPSLIC On-chip Debug System
PRIVATE $6 (0110) FPSLIC On-chip Debug System
RESERVED $7 (0111) N/A
PRIVATE $8 (1000) FPSLIC On-chip Debug System
PRIVATE $9 (1001) FPSLIC On-chip Debug System
PRIVATE $A (1010) FPSLIC On-chip Debug System
PRIVATE $B (1011) FPSLIC On-chip Debug System
AVR_RESET $C (1100) AVR Reset 1
RESERVED $D (1101) N/A
RESERVED $E (1110) N/A
BYPASS $F (1111) Bypass 1
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undetermined state when exiting the test mode. If needed, the BYPASS instruction can be
issued to make the shortest possible scan chain through the device. The AVR can be set in
the reset state either by pulling the external AVR RESET pin Low, or issuing the AVR_RESET
instruction with appropriate setting of the Reset Data Register.
The EXTEST instruction is used for sampling external pins and loading output pins with data.
The data from the output latch will be driven out on the pins as soon as the EXTEST instruc-
tion is loaded into the JTAG IR-register. Therefore, the SAMPLE/PRELOAD should also be
used for setting initial values to the scan ring, to avoid damaging the board when issuing the
EXTEST instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snap-
shot of the AVR’s external pins during normal operation of the part.
The JTAG Enable bit must be programmed and the JTD bit in the I/O register MCUR must be
cleared to enable the JTAG Test Access Port.
When using the JTAG interface for Boundary-Scan, using a JTAG TCK clock frequency higher
than the internal chip frequency is possible. The chip clock is not required to run.
Data Registers The Data Registers are selected by the JTAG instruction registers described in section
“Boundary-scan Specific JTAG Instructions” on page 75. The data registers relevant for
Boundary-Scan operations are:
Bypass Register
Device Identification Register
AVR Reset Register
AVR Boundary-Scan Chain
Bypass Register The Bypass register consists of a single shift-register stage. When the Bypass register is
selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-
DR controller state. The Bypass register can be used to shorten the scan chain on a system
when the other devices are to be tested.
Device
Identification
Register
Figure 41 shows the structure of the Device Identification register.
Figure 41. The format of the Device Identification Register
Version
Version is a 4-bit number identifying the revision of the component. The relevant version num-
bers are shown in Table 18.
MSB LSB
Bit 312827 12 11 1 0
Device ID Version Part Number Manufacturer ID 1
4 bits 16 bits 11 bits 1 bit
Table 18. JTAG Part Version
Device Version (Binary Digits)
AT94K05 –
AT94K10 0010
AT94K40 –
fig} F
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AT94KAL Series FPSLIC
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Part Number
The part number is a 16 bit code identifying the component. The JTAG Part Number for AVR
devices is listed in Table 19.
Manufacturer ID
The manufacturer ID for ATMEL is 0x01F (11 bits).
AVR Reset
Register
The AVR Reset Register is a Test Data Register used to reset the AVR. A high value in the
Reset Register corresponds to pulling the external AVRResetn Low. The AVR is reset as long
as there is a high value present in the AVR Reset Register. Depending on the Bit settings for
the clock options, the CPU will remain reset for a Reset Time-Out Period after releasing the
AVR Reset Register. The output from this Data Register is not latched, so the reset will take
place immediately, see Figure 42.
Figure 42. Reset Register
Boundary-scan Chain
The Boundary-scan Chain has the capability of driving and observing the logic levels on the
AVR’s digital I/O pins.
See “Boundary-scan Chain” on page 76 for a complete description.
Boundary-scan
Specific
JTAG Instructions
The instruction register is 4-bit wide, supporting up to 16 instructions. Listed below are the
JTAG instructions useful for Boundary-Scan operation. Note that the optional HIGHZ instruc-
tion is not implemented.
As a definition in this data sheet, the LSB is shifted in and out first for all shift registers.
The OPCODE for each instruction is shown behind the instruction name in hex format. The
text describes which data register is selected as path between TDI and TDO for each
instruction.
Table 19. JTAG Part Number
Device Part Number (Hex)
AT94K05 0xdd77
AT94K10 0xdd73
AT94K40 0xdd76
DQ
From
TDI
ClockDR · AVR_RESET
To
TDO
From other internal and
external reset sources
Internal AVR Reset
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EXTEST; $0
Mandatory JTAG instruction for selecting the Boundary-Scan Chain as Data Register for test-
ing circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control,
Output Data, and Input Data are all accessible in the scan chain. For Analog circuits having
off-chip connections, the interface between the analog and the digital logic is in the scan
chain. The contents of the latched outputs of the Boundary-Scan chain are driven out as soon
as the JTAG IR-register is loaded by the EXTEST instruction.
The active states are:
Capture-DR: Data on the external pins are sampled into the Boundary-Scan Chain.
Shift-DR: The Internal Scan Chain is shifted by the TCK input.
Update-DR: Data from the scan chain is applied to output pins.
IDCODE; $1
Optional JTAG instruction selecting the 32-bit ID register as Data Register. The ID register
consists of a version number, a device number and the manufacturer code chosen by JEDEC.
This is the default instruction after power-up.
The active states are:
Capture-DR: Data in the IDCODE register is sampled into the Boundary-Scan Chain.
Shift-DR: The IDCODE scan chain is shifted by the TCK input.
SAMPLE_PRELOAD; $2
Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the
input/output pins without affecting the system operation. However, the output latches are not
connected to the pins. The Boundary-Scan Chain is selected as Data Register.
The active states are:
Capture-DR: Data on the external pins are sampled into the Boundary-Scan Chain.
Shift-DR: The Boundary-Scan Chain is shifted by the TCK input.
Update-DR: Data from the Boundary-Scan chain is applied to the output latches. However,
the output latches are not connected to the pins.
AVR_RESET; $C
The AVR specific public JTAG instruction for forcing the AVR device into the Reset Mode or
releasing the JTAG reset source. The TAP controller is not reset by this instruction. The one
bit Reset Register is selected as Data Register. Note that the reset will be active as long as
there is a logic “1” in the Reset Chain. The output from this chain is not latched.
The active state is:
Shift-DR: The Reset Register is shifted by the TCK input.
BYPASS; $F
Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
Capture-DR: Loads a logic “0” into the Bypass Register.
Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
Boundary-scan Chain The Boundary-Scan chain has the capability of driving and observing the logic levels on the
AVR’s digital I/O pins.
Scanning the Digital
Port Pins
Figure 43 shows the boundary-scan cell for bi-directional port pin