NLSX3018 Datasheet by onsemi

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Fe - Wide High—Side vCC Operating Range: 1.3 v [0 4.5 v Wide Low—Side VL Operating Range: 0.9 v m (vcc — [1.4) v Low Bit—m—Bii Skew Overvollage Toleram Enable and 1/0 Pins Nun—preferemia] Powerup Sequencing Small packaging: 4.0 mm x 2.0 mm UDFNZII This a Pb—Free Device Typical Applications I Mobile Phones, PDAs, Other Ponable Devices PIN ASSIGNMENT I/O V0 7::3 C 20’ I/O Vcci J C I I/0 Veez J C Is: I/0 Veei 1 C I I/0 Vee4 J C I Vcc 1 C : GND 3 C : I/O VCCS j C : I/O Vega 3 C 3 I/O Vcc7 1 C :L ”0 Vcea (Top View) m Semennnnnnmnmnaaeminnnsanes. LLC.2ma I July. 201: — Rev. 2 High—Speed with 100 Mb/s Guaranteed Dale Rifle for VL > 1.6 V 0N Semiconductor® HHHHHHHHHH @ ., IHHHHHHHHHH HHHIIIIHIIII o HHHHHHHH (Nola. Microdot may be in em ORDERING INFORMA See mam omenng and smppmg mama dimensucms semen on page 9 ohms data Publicaiio
© Semiconductor Components Industries, LLC, 2013
July, 2013 Rev. 2
1Publication Order Number:
NLSX3018/D
NLSX3018
8-Bit 100 Mb/s Configurable
Dual-Supply Level
Translator
The NLSX3018 is a 8bit configurable dualsupply bidirectional
level translator without a direction control pin. The I/O VCC and I/O
VLports are designed to track two different power supply rails, VCC
and VL respectively. The VCC supply rail is configurable from 1.3 V
to 4.5 V while the VL supply rail is configurable from 0.9 V to (VCC
0.4) V. This allows lower voltage logic signals on the VL side to be
translated into higher voltage logic signals on the VCC side, and
viceversa. Both I/O ports are autosensing; thus, no direction pin is
required.
The Output Enable (EN) input, when Low, disables both I/O ports
by putting them in 3state. This significantly reduces the supply
currents from both VCC and VL. The EN signal is designed to track
VL.
Features
Wide HighSide VCC Operating Range: 1.3 V to 4.5 V
Wide LowSide VL Operating Range: 0.9 V to (VCC 0.4) V
HighSpeed with 100 Mb/s Guaranteed Date Rate for VL > 1.6 V
Low BittoBit Skew
Overvoltage Tolerant Enable and I/O Pins
Nonpreferential Powerup Sequencing
Small packaging: 4.0 mm x 2.0 mm UDFN20
This is a PbFree Device
Typical Applications
Mobile Phones, PDAs, Other Portable Devices
PIN ASSIGNMENT
(Top View)
I/O VL2
I/O VL3
I/O VL4
VL
I/O VCC1
I/O VCC2
I/O VCC3
I/O VCC4
VCC
I/O VL1
I/O VCC8I/O VL8
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
EN
I/O VL5
I/O VL6
I/O VL7
GND
I/O VCC5
I/O VCC6
I/O VCC7
MARKING
DIAGRAMS
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UDFN20
MU SUFFIX
CASE 517AK
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
LA = Specific Device Code
M = Date Code
G= PbFree Package
(Note: Microdot may be in either location)
LAM
G
20
1
NLSX3018
AWLYYWWG
SOIC20
DW SUFFIX
CASE 751D
NLSX
3018
ALYWG
G
TSSOP20
DT SUFFIX
CASE 948E
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= PbFree Package
TT; gammy:
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VLVCC GND
EN
I/O VL1
I/O VL2
I/O VL3
I/O VL4
I/O VCC1
I/O VCC2
I/O VCC3
I/O VCC4
Figure 1. Logic Diagram
I/O VL5
I/O VL6
I/O VL7
I/O VL8
I/O VCC5
I/O VCC6
I/O VCC7
I/O VCC8
III—1H H VL Vcc 7 NLSXaOiB M a V System E HOW I we vg U0 vccw I : I/On v0 VLn l/O vccn I’ | | GND EN EN GND | |——l IJ I __ f L. E Figure 2. Typical Application C
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Figure 2. Typical Application Circuit
I/O VL1
I/O VLn
ENEN
I/On
I/O1
GND
+1.8 V System
+1.8V +3.6V
+3.6 V System
I/On
I/O1
GNDGND
NLSX3018
I/O VCC1
I/O VCCn
VLVCC
Figure 3. Simplified Functional Diagram (1 I/O Line)
(EN = 1)
P
OneShot
N
OneShot
P
OneShot
N
OneShot
VL
I/O VLI/O VCC
VCC
4 kW
4 kW
PIN ASSIGNMENT
Pins Description
VCC VCC Input Voltage
VLVL Input Voltage
GND Ground
EN Output Enable
I/O VCCnI/O Port, Referenced to VCC
I/O VLnI/O Port, Referenced to VL
FUNCTION TABLE
EN Operating Mode
L HiZ
HI/O Buses Connected
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MAXIMUM RATINGS
Symbol Parameter Value Condition Unit
VCC VCC Supply Voltage 0.5 to +5.5 V
VLVL Supply Voltage 0.5 to +5.5 V
I/O VCC VCCReferenced DC Input/Output Voltage 0.5 to (VCC + 0.3) V
I/O VLVLReferenced DC Input/Output Voltage 0.5 to (VL + 0.3) V
VEN Enable Control Pin DC Input Voltage 0.5 to +5.5 V
IIK Input Diode Clamp Current 50 VI < GND mA
IOK Output Diode Clamp Current 50 VO < GND mA
ICC DC Supply Current Through VCC $100 mA
ILDC Supply Current Through VL$100 mA
IGND DC Ground Current Through Ground Pin $100 mA
TSTG Storage Temperature 65 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC VCC Supply Voltage 1.3 4.5 V
VLVL Supply Voltage 0.9 VCC 0.4 V
VEN Enable Control Pin Voltage GND 4.5 V
VIO Bus Input/Output Voltage I/O VCC
I/O VL
GND
GND
4.5
4.5
V
TAOperating Temperature Range 40 +85 °C
DI/DVInput Transition Rise or Rate
VI, VIO from 30% to 70% of VCC; VCC = 3.3 V $ 0.3 V
0 10 ns
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DC ELECTRICAL CHARACTERISTICS
Symbol Parameter
Test Conditions
(Note 1)
VCC (V)
(Note 2)
VL (V)
(Note 3)
405C to +855C
Unit
Min
Typ
(Note 4) Max
VIHC I/O VCC Input HIGH
Voltage
1.3 to 4.5 0.9 to (VCC – 0.4) 0.8 *
VCC
V
VILC I/O VCC Input LOW
Voltage
1.3 to 4.5 0.9 to (VCC – 0.4) 0.2 *
VCC
V
VIHL I/O VL Input HIGH
Voltage
1.3 to 4.5 0.9 to (VCC – 0.4) 0.8 * VL V
VILL I/O VL Input LOW
Voltage
1.3 to 4.5 0.9 to (VCC – 0.4) 0.2 * VLV
VIH Control Pin Input HIGH
Voltage
TA = +25°C1.3 to 4.5 0.9 to (VCC – 0.4) 0.8 * VL V
VIL Control Pin Input LOW
Voltage
TA = +25°C1.3 to 4.5 0.9 to (VCC – 0.4) 0.2 * VLV
VOHC I/O VCC Output HIGH
Voltage
I/O VCC Source Current =
20 mA
1.3 to 4.5 0.9 to (VCC – 0.4) 0.8 *
VCC
V
VOLC I/O VCC Output LOW
Voltage
I/O VCC Sink Current = 20 mA1.3 to 4.5 0.9 to (VCC – 0.4) 0.2 *
VCC
V
VOHL I/O VL Output HIGH
Voltage
I/O VL Source Current = 20 mA1.3 to 4.5 0.9 to (VCC – 0.4) 0.8 * VL V
VOLL I/O VL Output LOW
Voltage
I/O VL Sink Current = 20 mA1.3 to 4.5 0.9 to (VCC – 0.4) 0.2 * VLV
1. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified.
2. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions.
3. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC – 0.4) V during normal operation. However,
during startup and shutdown conditions, VL can be greater than (VCC – 0.4) V.
4. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating
temperature range are guaranteed by design.
POWER CONSUMPTION
Symbol Parameter
Test Conditions
(Note 5)
VCC (V)
(Note 6)
VL (V)
(Note 7)
405C to +855C
Unit
Min Typ Max
IQVCC Supply Current from
VCC
EN = VL; I/O VCCn = 0 V, I/O VLn = 0 V,
I/O VCCn = VCC or I/O VLn = VL and Io = 0
1.3 to 3.6 0.9 to (VCC – 0.4) 1.0 mA
IQVL Supply Current from
VL
EN = VL; I/O VCCn = 0 V, I/O VLn = 0 V,
I/O VCCn = VCC or I/O VLn = VL and Io = 0
1.3 to 3.6 0.9 to (VCC – 0.4) 1.0 mA
EN = VL, I/O VCCn = 0 V, I/O VLn = 0 V,
I/O VCCn = VCC or I/O VLn = (VCC
0.2 V) and Io = 0
< (VCC – 0.2) 2.0
ITSVCC VCC Tristate Output
Mode Supply
Current
EN = 0 V 1.3 to 3.6 0.9 to (VCC – 0.4) 1.0 mA
ITSVL VL Tristate Output
Mode Supply
Current
EN = 0 V 1.3 to 3.6 0.9 to (VCC – 0.4) 0.2 mA
EN = 0 V VCC 0.2 2.0
IOZ I/O Tristate Output
Mode Leakage
Current
EN = 0 V 1.3 to 3.6 0.9 to (VCC – 0.4) 0.15 mA
EN = 0 V VCC – 0.2 2.0
IEN Output Enable Pin
Input Current
1.3 to 3.6 0.9 to (VCC – 0.4) 1.0 mA
5. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified.
6. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 3.6 V.
7. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC – 0.4) V during normal operation. However,
during startup and shutdown conditions, VL can be greater than (VCC – 0.4) V.
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TIMING CHARACTERISTICS
Symbol Parameter
Test Conditions
(Note 8)
VCC (V)
(Note 9)
VL (V)
(Note 10)
405C to +855C
Unit
Min
Typ
(Note 11) Max
tRVCC I/O VCC Rise Time
(Output = I/O_VCC)
CIOVCC = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 0.7 2.4 ns
tFVCC I/O VCC Falltime
(Output = I/O_VCC)
CIOVCC = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 0.5 1.0 ns
tRVL I/O VL Risetime
(Output = I/O_VL)
CIOVL = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 1.0 3.8 ns
tFVL I/O VL Falltime
(Output = I/O_VL)
CIOVL = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 0.6 1.2 ns
ZOVCC I/O VCC OneShot
Output Impedance
1.3 to 4.5 0.9 to (VCC – 0.4) 30 W
ZOVL I/O VL OneShot
Output Impedance
1.3 to 4.5 0.9 to (VCC – 0.4) 30 W
tPD_VLVCC Propagation Delay
(Output = I/O_VCC,
tPHL, tPLH)
CIOVCC = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 4.5 9.3 ns
tPD_VCCVL Propagation Delay
(Output = I/O_VL,
tPHL, tPLH)
CIOVL = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 3.0 6.5 ns
tSK VLVCC ChanneltoChannel
Skew (Output =
I/O_VCC)
CIOVCC = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 0.2 0.3 nS
tSK_VCCVL ChanneltoChannel
Skew
(Output = I/O_VL)
CIOVCC = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 0.2 0.3 nS
MDR Maximum Data Rate (Output = I/O_VCC,
CIOVCC = 15 pF)
(Output = I/O_VL,
CIOVL = 15 pF)
1.3 to 4.5 0.9 to (VCC – 0.4) 110 Mb/s
> 2.2 > 1.8 140
8. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified.
9. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions.
10.VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC – 0.4) V during normal operation. However,
during startup and shutdown conditions, VL can be greater than (VCC – 0.4) V.
11. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating
temperature range are guaranteed by design.
t No \/CC ‘FrVCC |chc Figure 4. Driving |/O VL Test Circuit and Timing http://onsemi.com 7
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ENABLE / DISABLE TIME MEASUREMENTS
Symbol Parameter
Test Conditions
(Note 12)
VCC (V)
(Note 13)
VL (V)
(Note 14)
405C to +855C
Unit
Min
Typ
(Note 15) Max
tENVCC TurnOn Enable Time (Output =
I/O_VCC, tpZH)
CIOVCC = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 130 180 ns
TurnOn Enable Time (Output =
I/O_VCC, tpZL)
CIOVL = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 100 150 ns
tENVL TurnOn Enable Time (Output =
I/O_VL, tpZH)
CIOVCC = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 95 185 ns
TurnOn Enable Time (Output =
I/O_VL, tpZL)
CIOVL = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 70 110 ns
tDISVCC TurnOff Disable Time (Output =
I/O_VCC, tpHZ)
CIOVCC = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 175 250 ns
Propagation Delay (Output =
I/O_VCC, tPLZ)
CIOVL = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 150 190 ns
tDISVL TurnOff Disable Time (Output =
I/O_VL, tpHZ)
CIOVCC = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 180 250 ns
Propagation Delay (Output = I/O_VL,
tPLZ)
CIOVL = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 160 220 ns
12. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified.
13.VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions.
14.VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC – 0.4) V during normal operation. However,
during startup and shutdown conditions, VL can be greater than (VCC – 0.4) V.
15.Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25 °C. All units are production tested at TA = +25 °C. Limits over the operating
temperature range are guaranteed by design.
NLSX3018
EN
I/O VL
VLVCC
CIOVCC
tRISE/FALL v
3 ns
I/O VL
I/O VCC
tPD_VLVCC
90%
50%
10%
90%
50%
10%
tPD_VLVCC
tFVCC tRVCC
Figure 4. Driving I/O VL Test Circuit and Timing
I/O VCC
NLSX3018
EN
I/O VL
VLVCC
CIOVL
Source
tRISE/FALL v 3 nsI/O VCC
I/O VL
tPD_VCCVL
90%
50%
10%
90%
50%
10%
tPD_VCCVL
tFVL tRVL
Figure 5. Driving I/O VCC Test Circuit and Timing
I/O VCC
Source
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OPEN
PULSE
GENERATOR
RT
DUT
VCC
RL
R1
CL
2xVCC
Test Switch
tPZH, tPHZ Open
tPZL, tPLZ 2 x VCC
CL = 15 pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 50 kW or equivalent
RT = ZOUT of pulse generator (typically 50 W)
Figure 6. Test Circuit for Enable/Disable Time Measurement
VCC
GND
tF
tR
10%
50%
90%
10%
50%
90%
tR
tPLH tPHL
tF
50%
50%
90%
10%
tPZL tPLZ
tPZH tPHZ
GND
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
Figure 7. Timing Definitions for Propagation Delays and Enable/Disable Measurement
EN
Input
50% VL
Output
Output
Output
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IMPORTANT APPLICATIONS INFORMATION
Level Translator Architecture
The NLSX3018 auto sense translator provides
bidirectional voltage level shifting to transfer data in
multiple supply voltage systems. This device has two
supply voltages, VL and VCC, which set the logic levels on
the input and output sides of the translator. When used to
transfer data from the VL to the VCC ports, input signals
referenced to the VL supply are translated to output signals
with a logic level matched to VCC. In a similar manner, the
VCC to VL translation shifts input signals with a logic level
compatible to VCC to an output signal matched to VL.
The NLSX3018 consists of four bidirectional channels
that independently determine the direction of the data flow
without requiring a directional pin. The oneshot circuits
are used to detect the rising or falling input signals. In
addition, the one shots decrease the rise and fall time of the
output signal for hightolow and lowtohigh transitions.
Input Driver Requirements
For proper operation, the input driver to the auto sense
translator should be capable of driving 2.0 mA of peak
output current.
Output Load Requirements
The NLSX3018 is designed to drive CMOS inputs.
Resistive pullup or pulldown loads of less than 50 kW
should not be used with this device. The NLSX3373 or
NLSX3378 opendrain auto sense translators are alternate
translator options for an application such as the I2C bus that
requires pullup resistors.
Enable Input (EN)
The NLSX3018 has an Enable pin (EN) that provides
tristate operation at the I/O pins. Driving the Enable pin
to a low logic level minimizes the power consumption of
the device and drives the I/O VCC and I/O VL pins to a high
impedance state. Normal translation operation occurs
when the EN pin is equal to a logic high signal. The EN pin
is referenced to the VL supply and has OverVoltage
Tolerant (OVT) protection.
UniDirectional versus BiDirectional Translation
The NLSX3018 can function as a noninverting
unidirectional translator. One advantage of using the
translator as a unidirectional device is that each I/O pin
can be configured as either an input or output. The
configurable input or output feature is especially useful in
applications such as SPI that use multiple unidirectional
I/O lines to send data to and from a device. The flexible I/O
port of the auto sense translator simplifies the trace
connections on the PCB.
Power Supply Guidelines
It is recommended that the VL supply should be less than
or equal to the value of the VCC minus 0.4 V. The
sequencing of the power supplies will not damage the
device during the power up operation; however, the current
consumption of the device will increase if VL exceeds VCC
minus 0.4 V. In addition, the I/O VCC and I/O VL pins are
in the high impedance state if either supply voltage is equal
to 0 V.
For optimal performance, 0.01 to 0.1 mF decoupling
capacitors should be used on the VL and VCC power supply
pins. Ceramic capacitors are a good design choice to filter
and bypass any noise signals on the power supply voltage
lines to the ground plane of the PCB. The noise immunity
will be maximized by placing the capacitors as close as
possible to the supply and ground pins, along with
minimizing the PCB connection traces.
ORDERING INFORMATION
Device Package Shipping
NLSX3018MUTAG UDFN20
(PbFree)
3000 / Tape & Reel
NLSX3018DTR2G TSSOP20
(PbFree)
2500 / Tape & Reel
NLSX3018DWR2G SOIC20
(PbFree)
1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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PACKAGE DIMENSIONS
UDFN20 4x2, 0.4P
CASE 517AK
ISSUE O
DIM MIN MAX
MILLIMETERS
A
A1 0.00 0.05
A3
b0.15 0.25
D4.00 BSC
E2.00 BSC
e0.40 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. MOLD FLASH ALLOWED ON TERMINALS
ALONG EDGE OF PACKAGE. FLASH MAY
NOT EXCEED 0.03 ONTO BOTTOM
SURFACE OF TERMINALS.
5. DETAIL A SHOWS OPTIONAL
CONSTRUCTION FOR TERMINALS.
0.13 REF
b
L
PIN 1
1
11
10
D
E
BA
C0.15
C0.15
2X
2X
20
e
19X
20X
NOTE 3
A
20X
C
A1
(A3)
SEATING
PLANE
C0.08
C0.10 0.45 0.55
L0.50 0.60
REFERENCE
e/2
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTE 5
L1
DETAIL A
0.22
0.88
19X
2.30
0.40 PITCH
0.78
DIMENSIONS: MILLIMETERS
MOUNTING FOOTPRINT*
20X
1
SOLDERMASK DEFINED
DETAIL A
BAC
C
M
0.10
M
0.05
(L2)
L1 0.00 0.03
L2 0.60 0.70
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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PACKAGE DIMENSIONS
TSSOP20
CASE 948E02
ISSUE C
DIM
A
MIN MAX MIN MAX
INCHES
6.60 0.260
MILLIMETERS
B4.30 4.50 0.169 0.177
C1.20 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.27 0.37 0.011 0.015
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE W.
110
1120
PIN 1
IDENT
A
B
T
0.100 (0.004)
C
DGH
SECTION NN
K
K1
JJ1
N
N
M
F
W
SEATING
PLANE
V
U
S
U
M
0.10 (0.004) V S
T
20X REFK
L
L/22X
S
U0.15 (0.006) T
DETAIL E
0.25 (0.010)
DETAIL E
6.40 0.252
--- ---
S
U0.15 (0.006) T
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
HHHHHWHHHH : 7777 777 E ‘Q {17 .,. L \ HHHHH‘HHHHH W I 41 m5 '3 \ / \ N mmmcmm J a sum
NLSX3018
http://onsemi.com
12
PACKAGE DIMENSIONS
SOIC20 WB
CASE 751D05
ISSUE G
20
1
11
10
B20X
H10X
C
L
18X A1
A
SEATING
PLANE
q
hX 45_
E
D
M
0.25 M
B
M
0.25 S
AS
B
T
eT
B
A
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D12.65 12.95
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
q0 7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
__
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
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NLSX3018/D
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 8002829855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81358171050
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