dsPIC30F1010/202x Datasheet by Microchip Technology

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Q ‘MICROCHIP S
2006-2014 Microchip Technology Inc. DS70000178D-page 1
dsPIC30F1010/202X
High-Performance Modified RISC CPU:
Modified Harvard architecture
C compiler optimized instruction set architecture
83 base instructions with flexible addressing
modes
24-bit wide instructions, 16-bit wide data path
12 Kbytes on-chip Flash program space
512 bytes on-chip data RAM
16 x 16-bit working register array
Up to 30 MIPS operation:
- Dual Internal RC
- 9.7 and 14.55 MHz (±1%) Industrial Temp
- 6.4 and 9.7 MHz (±1%) Extended Temp
- 32X PLL with 480 MHz VCO
- PLL inputs ±3%
- External EC clock 6.0 to 14.55 MHz
- HS Crystal mode 6.0 to 14.55 MHz
32 interrupt sources
Three external interrupt sources
8 user-selectable priority levels for each interrupt
4 processor exceptions and software traps
DSP Engine Features:
Modulo and Bit-Reversed modes
Two 40-bit wide accumulators with optional
saturation logic
17-bit x 17-bit single-cycle hardware fractional/
integer multiplier
Single-cycle Multiply-Accumulate (MAC)
operation
40-stage Barrel Shifter
Dual data fetch
Peripheral Features:
High-current sink/source I/O pins: 25 mA/25 mA
Three 16-bit timers/counters; optionally pair up
16-bit timers into 32-bit timer modules
One 16-bit Capture input functions
Two 16-bit Compare/PWM output functions
- Dual Compare mode available
3-wire SPI modules (supports 4 Frame modes)
•I
2CTM module supports Multi-Master/Slave mode
and 7-bit/10-bit addressing
UART Module:
- Supports RS-232, RS-485 and LIN 1.2
- Supports IrDA® with on-chip hardware endec
- Auto wake-up on Start bit
- Auto-Baud Detect
- 4-level FIFO buffer
Power Supply PWM Module Features:
Four PWM generators with 8 outputs
Each PWM generator has independent time base
and duty cycle
Duty cycle resolution of 1.1 ns at 30 MIPS
Individual dead time for each PWM generator:
- Dead-time resolution 4.2 ns at 30 MIPS
- Dead time for rising and falling edges
Phase-shift resolution of 4.2 ns @ 30 MIPS
Frequency resolution of 8.4 ns @ 30 MIPS
PWM modes supported:
- Complementary
-Push-Pull
- Multi-Phase
- Variable Phase
- Current Reset
- Current-Limit
Independent Current-Limit and Fault Inputs
Output Override Control
Special Event Trigger
PWM generated ADC Trigger
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
28/44-Pin dsPIC30F1010/202X Enhanced Flash
SMPS 16-Bit Digital Signal Controller
dsPIC30F1010/202X
DS70000178D-page 2 2006-2014 Microchip Technology Inc.
Analog Features:
ADC
10-bit resolution
2000 Ksps conversion rate
Up to 12 input channels
“Conversion pairing” allows simultaneous conver-
sion of two inputs (i.e., current and voltage) with a
single trigger
PWM control loop:
- Up to six conversion pairs available
- Each conversion pair has up to four PWM
and seven other selectable trigger sources
Interrupt hardware supports up to 1M interrupts
per second
COMPARATOR
Four Analog Comparators:
- 20 ns response time
- 10-bit DAC reference generator
- Programmable output polarity
- Selectable input source
- ADC sample and convert capable
PWM module interface
- PWM Duty Cycle Control
- PWM Period Control
- PWM Fault Detect
Special Event Trigger
PWM-generated ADC Trigger
Special Microcontroller Features:
Enhanced Flash program memory:
- 10,000 erase/write cycle (min.) for
industrial temperature range, 100k (typical)
Self-reprogrammable under software control
Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
Flexible Watchdog Timer (WDT) with on-chip low
power RC oscillator for reliable operation
Fail-Safe clock monitor operation
Detects clock failure and switches to on-chip low
power RC oscillator
Programmable code protection
In-Circuit Serial Programming™ (ICSP™)
Selectable Power Management modes
- Sleep, Idle and Alternate Clock modes
CMOS Technology:
Low-power, high-speed Flash technology
3.3V and 5.0V operation (±10%)
Industrial and Extended temperature ranges
Low power consumption
dsPIC30F SWITCH MODE POWER SUPPLY FAMILY
Product
Pins
Packaging
Program
Memory
(Bytes)
Data SRAM
(Bytes)
Timers
Capture
Compare
UART
SPI
I2C™
PWM
ADCs
S & H
A/D
Inputs
Analog
Comparators
GPIO
dsPIC30F101028SDIP 6K 2562011112x2136 ch 2 21
dsPIC30F101028SOIC 6K 2562011112x2136 ch 2 21
dsPIC30F1010 28
QFN-S
6K 2562011112x2136 ch 2 21
dsPIC30F202028SDIP12K5123121114x2158 ch 4 21
dsPIC30F202028SOIC12K5123121114x2158 ch 4 21
dsPIC30F2020 28
QFN-S
12K5123121114x2158 ch 4 21
dsPIC30F202344QFN12K5123121114x21512 ch4 35
dsPIC30F202344TQFP12K5123121114x21512 ch4 35
333333333333] EEEEEEEEEEEEE
2006-2014 Microchip Technology Inc. DS70000178D-page 3
dsPIC30F1010/202X
Pin Diagrams
28-Pin SDIP and SOIC
dsPIC30F1010
MCLR
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
RE4
RE5V
SS
V
DD
AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
AV
DD
AV
SS
AN2/CMP1C/CMP2A/CN4/RB2
PGD2/EMUD2/SCK1/SFLT3/INT2/RF6 PGC2/EMUC2/OC1/SFLT1/INT1/RD0
PGC1/EMUC1/EXTREF/T1CK/U1ARX/CN0/RE6
PGD1/EMUD1/T2CK/U1ATX/CN1/RE7
V
SS
OSC2/CLKO/RB7
OSC1/CLKI/RB6 V
DD
SFLT2/INT0/OCFLTA/RA9
PGC/EMUC/SDI1/SDA/U1RX/RF7
PGD/EMUD/SDO1/SCL/U1TX/RF8
AN5/CMP2D/CN7/RB5
AN4/CMP2C/CN6/RB4
AN3/CMP1D/CMP2B/CN5/RB3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-Pin QFN-S
10 11
2
3
6
1
18
19
20
21
22
12 13 14 15
8
716
17
232425262728
9
dsPIC30F1010
PGD1/EMUD1/T2CK/U1ATX/CN1/RE7
5
4
AV
DD
AV
SS
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
RE4
RE5
V
DD
V
SS
PGC/EMUC/SDI1/SDA/U1RX/RF7
PGD/EMUD/SDO1/SCL/U1TX/RF8
SFLT2/INT0/OCFLTA/RA9
PGC2/EMUC2/OC1/SFLT1/INT1/RD0
MCLR
AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
AN4/CMP2C/CN6/RB4
AN5/CMP2D/CN7/RB5
V
SS
OSC1/CLKI/RB6
OSC2/CLKO/RB7
PGC1/EMUC1/EXTREF/T1CK/U1ARX/CN0/RE6
V
DD
PGD2/EMUD2/SCK1/SFLT3/INT2/RF6
3333333333333 DDDDDDDDDDDDD
dsPIC30F1010/202X
DS70000178D-page 4 2006-2014 Microchip Technology Inc.
Pin Diagrams
28-Pin SDIP and SOIC
dsPIC30F2020
MCLR
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5V
SS
V
DD
AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
AV
DD
AV
SS
AN2/CMP1C/CMP2A/CN4/RB2
PGD2/EMUD2/SCK1/SFLT3/OC2/INT2/RF6 PGC2/EMUC2/OC1/SFLT1/IC1/INT1/RD0
PGC1/EMUC1/EXTREF/PWM4L/T1CK/U1ARX/CN0/RE6
PGD1/EMUD1/PWM4H/T2CK/U1ATX/CN1/RE7
V
SS
AN7/CMP3D/CMP4B/OSC2/CLKO/RB7
AN6/CMP3C/CMP4A/OSC1/CLKI/RB6 V
DD
SFLT2/INT0/OCFLTA/RA9
PGC/EMUC/SDI1/SDA/U1RX/RF7
PGD/EMUD/SDO1/SCL/U1TX/RF8
AN5/CMP2D/CMP3B/CN7/RB5
AN4/CMP2C/CMP3A/CN6/RB4
AN3/CMP1D/CMP2B/CN5/RB3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-Pin QFN-S
1011
2
3
6
1
18
19
20
21
22
12 13 14 15
8
716
17
232425262728
9
dsPIC30F2020
PGD1/EMUD1/PWM4H/T2CK/U1ATX/CN1/RE7
5
4
AV
DD
AV
SS
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
V
DD
V
SS
PGC/EMUC/SDI1/SDA/U1RX/RF7
PGD/EMUD/SDO1/SCL/U1TX/RF8
SFLT2/INT0/OCFLTA/RA9
PGC2/EMUC2/OC1/SFLT1/IC1/INT1/RD0
MCLR
AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
AN4/CMP2C/CMP3A/CN6/RB4
AN5/CMP2D/CMP3B/CN7/RB5
V
SS
AN6/CMP3C/CMP4A/OSC1/CLKI/RB6
AN7/CMP3D/CMP4B/OSC2/CLKO/RB7
PGC1/EMUC1/EXTREF/PWM4L/T1CK/U1ARX/CN0/RE6
V
DD
PGD2/EMUD2/SCK1/SFLT3/OC2/INT2/RF6
2006-2014 Microchip Technology Inc. DS70000178D-page 5
dsPIC30F1010/202X
Pin Diagrams
44-PIN QFN
44
dsPIC30F2023
43 42 41 40 39 38 37 36 35
12 13 14 15 16 17 18 19 20 21
3
30
29
28
27
26
25
24
23
4
5
7
8
9
10
11
1
232
31
6
22
33
34
AN4/CMP2C/CMP3A/CN6/RB4
AN5/CMP2D/CMP3B/CN7/RB5
AN6/CMP3C/CMP4A/OSC1/CLKI/RB6
AN7/CMP3D/CMP4B/OSC2/CLKO/RB7
AN8/CMP4C/RB8
AN10/IFLT4/RB10
V
DD
AN11/IFLT2/RB11
V
SS
PGD/EMUD/SDO1/RF8
AN9/EXTREF/CMP4D/RB9
PGC2/EMUC2/OC1/IC1/INT1/RD0
V
DD
PGC1/EMUC1/PWM4L/T1CK/U1ARX/CN0/RE6
OC2/RD1
V
SS
SFLT2/INT0/OCFLTA/RA9
PGD2/EMUD2/SCK1/INT2/RF6
SFLT1/RA8
PGD1/EMUD1
/
PWM4H/T2CK/U1ATX/CN1/RE7
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
V
DD
V
SS
SYNCO/SS1/RF15
SDA/RG3
SFLT4/RA11
SFLT3/RA10
PGC/EMUC/SDI1/RF7
PWM2L/RE2
AN3/CMP1D/CMP2B/CN5/RB3
AN2/CMP1C/CMP2A/CN4/RB2
AN1/CMP1B/CN3/RB1
AN0/CMP1A/CN2/RB0
MCLR
U1RX/RF2
AV
DD
AV
SS
PWM1L/RE0
PWM1H/RE1
SYNCI/RF14
U1TX/RF3
SCL/ RG2
EMUC/SDI
dsPIC30F1010/202X
DS70000178D-page 6 2006-2014 Microchip Technology Inc.
Pin Diagrams
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
PGD/EMUD/SDO1/RF8
AN9/EXTREF/CMP4D/RB9
PGC2/EMUC2/OC1/IC1/INT1/RD0
V
DD
PGC1/EMUC1/PWM4L/T1CK/U1ARX/CN0/RE6
SYNCI/RF14
V
SS
SFLT2/INT0/OCFLTA/RA9
PGD2/EMUD2/SCK1/INT2/RF6
SFLT1/RA8
AN3/CMP1D/CMP2B/CN5/RB3
AN2/CMP1C/CMP2A/CN4/RB2
AN1/CMP1B/CN3/RB1
AN0/CMP1A/CN2/RB0
MCLR
U1RX/RF2
AV
DD
AV
SS
PWM1L/RE0
PWM1H/RE1
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
V
DD
V
SS
SDA/RG3
SFLT4/RA11
SFLT3/RA10
PGC/EMUC/SDI1/RF7
AN4/CMP2C/CMP3A/CN6/RB4
AN5/CMP2D/CMP3B/CN7/RB5
AN6/CMP3C/CMP4A/OSC1/CLKI/RB6
AN7/CMP3D/CMP4B/OSC2/CLKO/RB7
AN8/CMP4C/RB8
SYNCO/SS1/RF15
V
DD
V
SS
SCL/RG2
U1TX/RF3
PGD1/EMUD1/PWM4H/T2CK/U1ATX/CN1/RE7
dsPIC30F2023
PWM2L/RE2
OC2/RD1
AN11/IFLT2/RB11
AN10/IFLT4/RB10
44-Pin TQFP
2006-2014 Microchip Technology Inc. DS70000178D-page 7
dsPIC30F1010/202X
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 CPU Architecture Overview........................................................................................................................................................ 19
3.0 Memory Organization................................................................................................................................................................. 29
4.0 Address Generator Units............................................................................................................................................................ 41
5.0 Interrupts .................................................................................................................................................................................... 47
6.0 I/O Ports ..................................................................................................................................................................................... 77
7.0 Flash Program Memory.............................................................................................................................................................. 81
8.0 Timer1 Module ........................................................................................................................................................................... 87
9.0 Timer2/3 Module ........................................................................................................................................................................ 91
10.0 Input Capture Module................................................................................................................................................................. 97
11.0 Output Compare Module.......................................................................................................................................................... 101
12.0 Power Supply PWM ................................................................................................................................................................. 107
13.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 145
14.0 I2C™ Module ........................................................................................................................................................................... 153
15.0 Universal Asynchronous Receiver Transmitter (UART) Module .............................................................................................. 161
16.0 10-bit 2 Msps Analog-to-Digital Converter (ADC) Module........................................................................................................ 169
17.0 SMPS Comparator Module ...................................................................................................................................................... 191
18.0 System Integration ................................................................................................................................................................... 197
19.0 Instruction Set Summary.......................................................................................................................................................... 219
20.0 Development Support............................................................................................................................................................... 227
21.0 Electrical Characteristics.......................................................................................................................................................... 231
22.0 Package Marking Information................................................................................................................................................... 267
Appendix A: Revision History............................................................................................................................................................. 275
Index ................................................................................................................................................................................................. 277
dsPIC30F1010/202X
DS70000178D-page 8 2006-2014 Microchip Technology Inc.
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2006-2014 Microchip Technology Inc. DS70000178D-page 9
dsPIC30F1010/202X
1.0 DEVICE OVERVIEW This document contains device specific information for
the dsPIC30F1010/202X SMPS devices. These devices
contain extensive Digital Signal Processor (DSP) func-
tionality within a high-performance 16-bit microcontroller
(MCU) architecture, as reflected in the following block
diagrams. Figure 1-1 and Table 1-1 describe the
dsPIC30F1010 SMPS device, Figure 1-2 and Table 1-2
describe the dsPIC30F2020 device and Figure 1-3 and
Table 1-3 describe the dsPIC30F2023 SMPS device.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
é gtgHtgi H H 3 g 3 X
dsPIC30F1010/202X
DS70000178D-page 10 2006-2014 Microchip Technology Inc.
FIGURE 1-1: dsPIC30F1010 BLOCK DIAGRAM
Power-up
Timer
Oscillator
Start-up Timer
POR
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLK1
MCLR
AN4/CMP2C/CN6/RB4
UART1SPI1 SMPS
PWM
Timing
Generation
AN5/CMP2D/CN7/RB5
16
PCH PCL
Program Counter
ALU<16>
16
Address Latch
Program Memory
(12 Kbytes)
Data Latch
24
24
24
24
X Data Bus
IR
I2C™
Comparator
PCU
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
RE4
10-bit ADC
Timers
RE5
PGC1/EMUC1/EXTREF/T1CK/
Output
Compare
Module
SFLT2/INT0/OCFLTA/RA9
PORTB
PGC/EMUC/SDI1/SDA/U1RX/RF7
PGD/EMUD/SD01/SCL/U1TX/RF8
PORTF
PORTD
16
16 16
16 x 16
W Reg Array
Divide
Unit
Engine
DSP
Decode
ROM Latch
16
Y Data Bus
Effective Address
X RAGU
X WAGU
Y AGU AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
16
16
16
16
16
PORTA
PORTE
16
16
16
16
8
Interrupt
Controller
PSV & Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data LatchData Latch
Y Data
(256 bytes)
RAM X Data
(256 bytes)
RAM
Address
Latch
Address
Latch
Control Signals
to Various Blocks
PGC2/EMUC2/OC1/SFLT1/
16
16
OSC1/CLKI/RB6
OSC2/CLKO/RB7
INT1/RD0
PGD2/EMUD2/SCK1/SFLT3/
INT2/RF6
PGD1/EMUD1/T2CK/U1ATX/
Module
Input
Change
Notification
U1ARX/CN0/RE6
CN1/RE7
2006-2014 Microchip Technology Inc. DS70000178D-page 11
dsPIC30F1010/202X
Table 1-1 provides a brief description of device I/O pin-
outs for the dsPIC30F1010 and the functions that may
be multiplexed to a port pin. Multiple functions may
exist on one port pin. When multiplexing occurs, the
peripheral module’s functional requirements may force
an override of the data direction of the port pin.
TABLE 1-1: PINOUT I/O DESCRIPTIONS FOR dsPIC30F1010
Pin Name Pin
Type Buffer
Type Description
AN0-AN5 I Analog Analog input channels.
AVDD P P Positive supply for analog module.
AVSS P P Ground reference for analog module.
CLKI
CLKO I
OST/CMOS
External clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always
associated with OSC2 pin function.
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ICD Primary Communication Channel data input/output pin.
ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Communication Channel data input/output pin.
ICD Tertiary Communication Channel clock input/output pin.
INT0
INT1
INT2
I
I
I
ST
ST
ST
External interrupt 0
External interrupt 1
External interrupt 2
SFLT1
SFLT2
SFLT3
PWM1L
PWM1H
PWM2L
PWM2H
I
I
I
O
O
O
O
ST
ST
ST
Shared Fault Pin 1
Shared Fault Pin 2
Shared Fault Pin 3
PWM 1 Low output
PWM 1 High output
PWM 2 Low output
PWM 2 High output
MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an
active low Reset to the device.
OC1 O Compare outputs.
OCFLTA I ST Output Compare Fault Pin
OSC1
OSC2 I
I/O CMOS
Oscillator crystal input.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in FRC and EC modes.
PGD
PGC
PGD1
PGC1
PGD2
PGC2
I/O
I
I/O
I
I/0
I
ST
ST
ST
ST
ST
ST
In-Circuit Serial Programming™ data input/output pin.
In-Circuit Serial Programming clock input pin.
In-Circuit Serial Programming data input/output pin 1.
In-Circuit Serial Programming clock input pin 1.
In-Circuit Serial Programming data input/output pin 2.
In-Circuit Serial Programming clock input pin 2.
RB0-RB7 I/O ST PORTB is a bidirectional I/O port.
RA9 I/O ST PORTA is a bidirectional I/O port.
RD0 I/O ST PORTD is a bidirectional I/O port.
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Trigger input with CMOS levels O = Output
I = Input P = Power
dsPIC30F1010/202X
DS70000178D-page 12 2006-2014 Microchip Technology Inc.
RE0-RE7 I/O ST PORTE is a bidirectional I/O port.
RF6, RF7, RF8
I/O ST PORTF is a bidirectional I/O port.
SCK1
SDI1
SDO1
I/O
I
O
ST
ST
Synchronous serial clock input/output for SPI #1.
SPI #1 Data In.
SPI #1 Data Out.
SCL
SDA I/O
I/O ST
ST Synchronous serial clock input/output for I2C™.
Synchronous serial data input/output for I2C.
T1CK
T2CK I
IST
ST Timer1 external clock input.
Timer2 external clock input.
U1RX
U1TX
U1ARX
U1ATX
I
O
I
O
ST
ST
UART1 Receive.
UART1 Transmit.
Alternate UART1 Receive.
Alternate UART1 Transmit.
CMP1A
CMP1B
CMP1C
CMP1D
CMP2A
CMP2B
CMP2C
CMP2D
I
I
I
I
I
I
I
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Comparator 1 Channel A
Comparator 1 Channel B
Comparator 1 Channel C
Comparator 1 Channel D
Comparator 2 Channel A
Comparator 2 Channel B
Comparator 2 Channel C
Comparator 2 Channel D
CN0-CN7 I ST Input Change notification inputs
Can be software programmed for internal weak pull-ups on all inputs.
VDD P Positive supply for logic and I/O pins.
VSS P Ground reference for logic and I/O pins.
EXTREF I Analog External reference to Comparator DAC
TABLE 1-1: PINOUT I/O DESCRIPTIONS FOR dsPIC30F1010 (CONTINUED)
Pin Name Pin
Type Buffer
Type Description
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Trigger input with CMOS levels O = Output
I = Input P = Power
JL J; 7% M ‘ $3 H fl H J‘, y 24 i H 7 j‘ as I:‘ U, U” gfilw M HM ”H W k 1 Q[ j[ fit ‘H_: 2% fitiwflvfifi 0 "1X 4 0%
2006-2014 Microchip Technology Inc. DS70000178D-page 13
dsPIC30F1010/202X
FIGURE 1-2: dsPIC30F2020 BLOCK DIAGRAM
Power-up
Timer
Oscillator
Start-up Timer
POR
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLK1
MCLR
AN4/CMP2C/CMP3A/CN6/RB4
UART1SPI1 SMPS
PWM
Timing
Generation
AN5/CMP2D/CMP3B/CN7/RB5
16
PCH PCL
Program Counter
ALU<16>
16
Address Latch
Program Memory
(12 Kbytes)
Data Latch
24
24
24
24
X Data Bus
IR
I2C™
Comparator
PCU
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
10-bit ADC
Timers
PWM3H/RE5
PGC1/EMUC1/EXTREF/PWM4L/
Input
Capture
Module
Output
Compare
Module
SFLT2/INT0/OCFLTA/RA9
PORTB
PGC/EMUC/SDI1/SDA/U1RX/RF7
PGD/EMUD/SD01/SCL/U1TX/RF8
PORTF
PORTD
16
16 16
16 x 16
W Reg Array
Divide
Unit
Engine
DSP
Decode
ROM Latch
16
Y Data Bus
Effective Address
X RAGU
X WAGU
Y AGU AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
16
16
16
16
16
PORTA
PORTE
16
16
16
16
8
Interrupt
Controller
PSV & Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data LatchData Latch
Y Data
(256 bytes)
RAM X Data
(256 bytes)
RAM
Address
Latch
Address
Latch
Control Signals
to Various Blocks
PGC2/EMUC2/OC1/SFLT1/IC1/
16
16
AN6/CMP3C/CMP4A/
AN7/CMP3D/CMP4B/
OSC1/CLKI/RB6
OSC2/CLKO/RB7
INT1/RD0
PGD2/EMUD2/SCK1/SFLT3/OC2/
INT2/RF6
PGD1/EMUD1/PWM4H/T2CK/
Module
Input
Change
Notification
U1ARX/CN0/RE6
U1ATX/CN1/RE7
T1CK/
dsPIC30F1010/202X
DS70000178D-page 14 2006-2014 Microchip Technology Inc.
Table 1-2 provides a brief description of device I/O pin-
outs for the dsPIC30F2020 and the functions that may
be multiplexed to a port pin. Multiple functions may
exist on one port pin. When multiplexing occurs, the
peripheral module’s functional requirements may force
an override of the data direction of the port pin.
TABLE 1-2: PINOUT I/O DESCRIPTIONS FOR dsPIC30F2020
Pin Name Pin
Type Buffer
Type Description
AN0-AN7 I Analog Analog input channels.
AVDD P P Positive supply for analog module.
AVSS P P Ground reference for analog module.
CLKI
CLKO I
OST/CMOS
External clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always
associated with OSC2 pin function.
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ICD Primary Communication Channel data input/output pin.
ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Communication Channel data input/output pin.
ICD Tertiary Communication Channel clock input/output pin.
IC1 I ST Capture input.
INT0
INT1
INT2
I
I
I
ST
ST
ST
External interrupt 0
External interrupt 1
External interrupt 2
SFLT1
SFLT2
SFLT3
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM4L
PWM4H
I
I
I
O
O
O
O
O
O
O
O
ST
ST
ST
Shared Fault Pin 1
Shared Fault Pin 2
Shared Fault Pin 3
PWM 1 Low output
PWM 1 High output
PWM 2 Low output
PWM 2 High output
PWM 3 Low output
PWM 3 High output
PWM 4 Low output
PWM 4 High output
MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an
active low Reset to the device.
OC1-OC2
OCFLTA O
I Compare outputs.
Output Compare Fault pin
OSC1
OSC2 I
I/O CMOS
Oscillator crystal input.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in FRC and EC modes.
PGD
PGC
PGD1
PGC1
PGD2
PGC2
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
In-Circuit Serial Programming™ data input/output pin.
In-Circuit Serial Programming clock input pin.
In-Circuit Serial Programming data input/output pin 1.
In-Circuit Serial Programming clock input pin 1.
In-Circuit Serial Programming data input/output pin 2.
In-Circuit Serial Programming clock input pin 2.
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Trigger input with CMOS levels O = Output
I = Input P = Power
2006-2014 Microchip Technology Inc. DS70000178D-page 15
dsPIC30F1010/202X
RB0-RB7 I/O ST PORTB is a bidirectional I/O port.
RA9 I/O ST PORTA is a bidirectional I/O port.
RD0 I/O ST PORTD is a bidirectional I/O port.
RE0-RE7 I/O ST PORTE is a bidirectional I/O port.
RF6, RF7, RF8
I/O ST PORTF is a bidirectional I/O port.
SCK1
SDI1
SDO1
I/O
I
O
ST
ST
Synchronous serial clock input/output for SPI #1.
SPI #1 Data In.
SPI #1 Data Out.
SCL
SDA I/O
I/O ST
ST Synchronous serial clock input/output for I2C™.
Synchronous serial data input/output for I2C.
T1CK
T2CK I
IST
ST Timer1 external clock input.
Timer2 external clock input.
U1RX
U1TX
U1ARX
U1ATX
I
O
I
O
ST
ST
O
UART1 Receive.
UART1 Transmit.
Alternate UART1 Receive.
Alternate UART1 Transmit.
CMP1A
CMP1B
CMP1C
CMP1D
CMP2A
CMP2B
CMP2C
CMP2D
CMP3A
CMP3B
CMP3C
CMP3D
CMP4A
CMP4B
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Comparator 1 Channel A
Comparator 1 Channel B
Comparator 1 Channel C
Comparator 1 Channel D
Comparator 2 Channel A
Comparator 2 Channel B
Comparator 2 Channel C
Comparator 2 Channel D
Comparator 3 Channel A
Comparator 3 Channel B
Comparator 3 Channel C
Comparator 3 Channel D
Comparator 4 Channel A
Comparator 4 Channel B
CN0-CN7 I ST Input Change notification inputs
Can be software programmed for internal weak pull-ups on all inputs.
VDD P Positive supply for logic and I/O pins.
VSS P Ground reference for logic and I/O pins.
EXTREF I Analog External reference to Comparator DAC
TABLE 1-2: PINOUT I/O DESCRIPTIONS FOR dsPIC30F2020 (CONTINUED)
Pin Name Pin
Type Buffer
Type Description
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Trigger input with CMOS levels O = Output
I = Input P = Power
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dsPIC30F1010/202X
DS70000178D-page 16 2006-2014 Microchip Technology Inc.
FIGURE 1-3: dsPIC30F2023 BLOCK DIAGRAM
Power-up
Timer
Oscillator
Start-up Timer
POR
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLK1
MCLR
AN4/CMP2C/CMP3A/CN6/RB4
UART1SPI1 Power Supply
PWM
Timing
Generation
AN5/CMP2D/CMP3B/CN7/RB5
16
PCH PCL
Program Counter
ALU<16>
16
Address Latch
Program Memory
(12 Kbytes)
Data Latch
24
24
24
24
X Data Bus
IR
I2C™
Comparator
PCU
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
10-bit ADC
Timers
PWM3H/RE5
PGC1/EMUC1/PWM4L/T1CK/
Input
Capture
Module
Output
Compare
Module
PORTB
SCL/RG2
SDA/RG3
PORTG
PORTD
16
16 16
16 x 16
W Reg Array
Divide
Unit
Engine
DSP
Decode
ROM Latch
16
Y Data Bus
Effective Address
X RAGU
X WAGU
Y AGU AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
16
16
16
16
16
PORTA
PORTE
16
16
16
16
8
Interrupt
Controller
PSV & Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data LatchData Latch
Y Data
(256 bytes)
RAM X Data
(256 bytes)
RAM
Address
Latch
Address
Latch
Control Signals
to Various Blocks
OC2/RD1
16
16
AN6/CMP3C/CMP4A/
AN7/CMP3D/CMP4B/
OSC1/CLKI/RB6
OSC2/CLKO/RB7
PGD1/EMUD1/PWM4H/T2CK/
Module
SFLT1/RA8
SFLT2/INT0/OCFLTA/RA9
SFLT3/RA10
PGC/EMUC/SDI1/RF7
PGD/EMUD/SD01/RF8
PORTF
PGD2/EMUD2/SCK1/INT2/RF6
AN8/CMP4C/RB8
AN9/EXTREF/CMP4D/RB9
AN10/IFLT4/RB10
AN11/IFLT2/RB11
SYNCI/RF14
PGC2/EMUC2/OC1/IC1/INT1/
SFLT4/RA11
SYNCO/SSI/RF15
U1TX/RF3
U1RX/RF2
Input
Change
Notification
U1ARX/CN0/RE6
U1ATX/CN1/RE7
RD0
2006-2014 Microchip Technology Inc. DS70000178D-page 17
dsPIC30F1010/202X
Table 1-3 provides a brief description of device I/O pin-
outs for the dsPIC30F2023 and the functions that may
be multiplexed to a port pin. Multiple functions may
exist on one port pin. When multiplexing occurs, the
peripheral module’s functional requirements may force
an override of the data direction of the port pin.
TABLE 1-3: PINOUT I/O DESCRIPTIONS FOR dsPIC30F2023
Pin Name Pin
Type Buffer
Type Description
AN0-AN11 I Analog Analog input channels.
AVDD P P Positive supply for analog module.
AVSS P P Ground reference for analog module.
CLKI
CLKO I
OST/CMOS
External clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always
associated with OSC2 pin function.
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ICD Primary Communication Channel data input/output pin.
ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Communication Channel data input/output pin.
ICD Tertiary Communication Channel clock input/output pin.
IC1 I ST Capture input.
INT0
INT1
INT2
I
I
I
ST
ST
ST
External interrupt 0
External interrupt 1
External interrupt 2
SFLT1
SFLT2
SFLT3
SFLT4
IFLT2
IFLT4
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM4L
PWM4H
I
I
I
I
I
I
O
O
O
O
O
O
O
O
ST
ST
ST
ST
ST
ST
Shared Fault 1
Shared Fault 2
Shared Fault 3
Shared Fault 4
Independent Fault 2
Independent Fault 4
PWM 1 Low output
PWM 1 High output
PWM 2 Low output
PWM 2 High output
PWM 3 Low output
PWM 3 High output
PWM 4 Low output
PWM 4 High output
SYNCO
SYNCI O
I
ST PWM SYNC output
PWM SYNC input
MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an
active low Reset to the device.
OC1-OC2
OCFLTA O
I
ST Compare outputs.
Output Compare Fault condition.
OSC1
OSC2 I
I/O CMOS
Oscillator crystal input.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in FRC and EC modes.
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Trigger input with CMOS levels O = Output
I = Input P = Power
dsPIC30F1010/202X
DS70000178D-page 18 2006-2014 Microchip Technology Inc.
PGD
PGC
PGD1
PGC1
PGD2
PGC2
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
In-Circuit Serial Programming™ data input/output pin.
In-Circuit Serial Programming clock input pin.
In-Circuit Serial Programming data input/output pin 1.
In-Circuit Serial Programming clock input pin 1.
In-Circuit Serial Programming data input/output pin 2.
In-Circuit Serial Programming clock input pin 2.
RA8-RA11 I/O ST PORTA is a bidirectional I/O port.
RB0-RB11 I/O ST PORTB is a bidirectional I/O port.
RD0,RD1 I/O ST PORTD is a bidirectional I/O port.
RE0-RE7 I/O ST PORTE is a bidirectional I/O port.
RF2, RF3,
RF6-RF8, RF14,
RF15
I/O ST PORTF is a bidirectional I/O port.
RG2, RG3 I/O ST PORTG is a bidirectional I/O port.
SCK1
SDI1
SDO1
SS1
I/O
I
O
I
ST
ST
ST
Synchronous serial clock input/output for SPI #1.
SPI #1 Data In.
SPI #1 Data Out.
SPI #1 Slave Synchronization.
SCL
SDA I/O
I/O ST
ST Synchronous serial clock input/output for I2C.
Synchronous serial data input/output for I2C.
T1CK
T2CK I
IST
ST Timer1 external clock input.
Timer2 external clock input.
U1RX
U1TX
U1ARX
U1ATX
I
O
I
O
ST
ST
UART1 Receive.
UART1 Transmit.
Alternate UART1 Receive.
Alternate UART1 Transmit
CMP1A
CMP1B
CMP1C
CMP1D
CMP2A
CMP2B
CMP2C
CMP2D
CMP3A
CMP3B
CMP3C
CMP3D
CMP4A
CMP4B
CMP4C
CMP4D
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Comparator 1 Channel A
Comparator 1 Channel B
Comparator 1 Channel C
Comparator 1 Channel D
Comparator 2 Channel A
Comparator 2 Channel B
Comparator 2 Channel C
Comparator 2 Channel D
Comparator 3 Channel A
Comparator 3 Channel B
Comparator 3 Channel C
Comparator 3 Channel D
Comparator 4 Channel A
Comparator 4 Channel B
Comparator 4 Channel C
Comparator 4 Channel D
CN0-CN7 I ST Input Change notification inputs
Can be software programmed for internal weak pull-ups on all inputs.
VDD P Positive supply for logic and I/O pins.
VSS P Ground reference for logic and I/O pins.
EXTREF I Analog External reference to Comparator DAC
TABLE 1-3: PINOUT I/O DESCRIPTIONS FOR dsPIC30F2023 (CONTINUED)
Pin Name Pin
Type Buffer
Type Description
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Trigger input with CMOS levels O = Output
I = Input P = Power
2006-2014 Microchip Technology Inc. DS70000178D-page 19
dsPIC30F1010/202X
2.0 CPU ARCHITECTURE
OVERVIEW
2.1 Core Overview
The core has a 24-bit instruction word. The Program
Counter (PC) is 23 bits wide with the Least Significant
bit (LSb) always clear (see Section 3.1 “Program
Address Space), and the Most Significant bit (MSb)
is ignored during normal program execution, except for
certain specialized instructions. Thus, the PC can
address up to 4M instruction words of user program
space. An instruction prefetch mechanism is used to
help maintain throughput. Program loop constructs,
free from loop count management overhead, are sup-
ported using the DO and REPEAT instructions, both of
which are interruptible at any point.
The working register array consists of 16x16-bit regis-
ters, each of which can act as data, address or offset
registers. One working register (W15) operates as a
software Stack Pointer for interrupts and calls.
The data space is 64 Kbytes (32K words) and is split
into two blocks, referred to as X and Y data memory.
Each block has its own independent Address Genera-
tion Unit (AGU). Most instructions operate solely
through the X memory AGU, which provides the
appearance of a single unified data space. The
Multiply-Accumulate (MAC) class of dual source DSP
instructions operate through both the X and Y AGUs,
splitting the data address space into two parts (see
Section 3.2 “Data Address Space”). The X and Y
data space boundary is device-specific and cannot be
altered by the user. Each data word consists of 2 bytes,
and most instructions can address data either as words
or bytes.
There are two methods of accessing data stored in
program memory:
The upper 32 Kbytes of data space memory can be
mapped into the lower half (user space) of program
space at any 16K program word boundary, defined
by the 8-bit Program Space Visibility Page
(PSVPAG) register. This lets any instruction access
program space as if it were data space, with a limita-
tion that the access requires an additional cycle.
Moreover, only the lower 16 bits of each instruction
word can be accessed using this method.
Linear indirect access of 32K word pages within
program space is also possible using any working
register, via table read and write instructions.
Table read and write instructions can be used to
access all 24 bits of an instruction word.
Overhead-free circular buffers (modulo addressing)
are supported in both X and Y address spaces. This is
primarily intended to remove the loop overhead for
DSP algorithms.
The X AGU also supports Bit-Reversed Addressing
mode on destination effective addresses, to greatly
simplify input or output data reordering for radix-2 FFT
algorithms. Refer to Section 4.0 “Address Generator
Units” for details on modulo and Bit-Reversed
Addressing.
The core supports Inherent (no operand), Relative, Lit-
eral, Memory Direct, Register Direct, Register Indirect,
Register Offset and Literal Offset Addressing modes.
Instructions are associated with predefined Addressing
modes, depending upon their functional requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working reg-
ister (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, 3-operand instructions are supported, allowing
C = A + B operations to be executed in a single cycle.
A DSP engine has been included to significantly
enhance the core arithmetic capability and throughput.
It features a high-speed 17-bit by 17-bit multiplier, a
40-bit ALU, two 40-bit saturating accumulators and a
40-bit bidirectional barrel shifter. Data in the accumula-
tor or any working register can be shifted up to 15 bits
right or 16 bits left in a single cycle. The DSP instruc-
tions operate seamlessly with all other instructions and
have been designed for optimal real-time performance.
The MAC class of instructions can concurrently fetch
two data operands from memory, while multiplying two
W registers. To enable this concurrent fetching of data
operands, the data space has been split for these
instructions and linear for all others. This has been
achieved in a transparent and flexible manner, by
dedicating certain working registers to each address
space for the MAC class of instructions.
The core does not support a multi-stage instruction
pipeline. However, a single stage instruction prefetch
mechanism is used, which accesses and partially
decodes instructions a cycle ahead of execution, in
order to maximize available execution time. Most
instructions execute in a single cycle, with certain
exceptions.
The core features a vectored exception processing
structure for traps and interrupts, with 62 independent
vectors. The exceptions consist of up to 8 traps (of
which 4 are reserved) and 54 interrupts. Each interrupt
is prioritized based on a user-assigned priority between
1 and 7 (1 being the lowest priority and 7 being the
highest) in conjunction with a predetermined ‘natural
order’. Traps have fixed priorities, ranging from 8 to 15.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
dsPIC30F1010/202X
DS70000178D-page 20 2006-2014 Microchip Technology Inc.
2.2 Programmers Model
The programmer’s model is shown in Figure 2-1 and
consists of 16x16-bit working registers (W0 through
W15), 2x40-bit accumulators (ACCA and ACCB),
STATUS register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT), and Program
Counter (PC). The working registers can act as data,
address or offset registers. All registers are memory
mapped. W0 acts as the W register for file register
addressing.
Some of these registers have a shadow register asso-
ciated with each of them, as shown in Figure 2-1. The
shadow register is used as a temporary holding register
and can transfer its contents to or from its host register
upon the occurrence of an event. None of the shadow
registers are accessible directly. The following rules
apply for transfer of registers into and out of shadows.
PUSH.S and POP.S
W0, W1, W2, W3, SR (DC, N, OV, Z and C bits
only) are transferred.
DO instruction
DOSTART, DOEND, DCOUNT shadows are
pushed on loop start, and popped on loop end.
When a byte operation is performed on a working reg-
ister, only the Least Significant Byte (LSB) of the target
register is affected. However, a benefit of memory
mapped working registers is that both the Least and
Most Significant Bytes (MSBs) can be manipulated
through byte wide data memory space accesses.
2.2.1 SOFTWARE STACK POINTER/
FRAME POINTER
The dsPIC® DSC devices contain a software stack.
W15 is the dedicated software Stack Pointer (SP), and
will be automatically modified by exception processing
and subroutine calls and returns. However, W15 can be
referenced by any instruction in the same manner as all
other W registers. This simplifies the reading, writing
and manipulation of the Stack Pointer (e.g., creating
stack frames).
W15 is initialized to 0x0800 during a Reset. The user
may reprogram the SP during initialization to any
location within data space.
W14 has been dedicated as a Stack Frame Pointer as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.
2.2.2 STATUS REGISTER
The dsPIC DSC core has a 16-bit STATUS Register
(SR), the LSB of which is referred to as the SR Low
Byte (SRL) and the MSB as the SR High Byte (SRH).
See Figure 2-1 for SR layout.
SRL contains all the MCU ALU operation status flags
(including the Z bit), as well as the CPU Interrupt Prior-
ity Level Status bits, IPL<2:0>, and the REPEAT active
Status bit, RA. During exception processing, SRL is
concatenated with the MSB of the PC to form a
complete word value, which is then stacked.
The upper byte of the STATUS register contains the
DSP Adder/Subtracter status bits, the DO Loop Active
bit (DA) and the Digit Carry (DC) Status bit.
2.2.3 PROGRAM COUNTER
The Program Counter is 23 bits wide. Bit 0 is always
clear. Therefore, the PC can address up to 4M
instruction words.
Note: In order to protect against misaligned
stack accesses, W15<0> is always clear.
Viiiiiiw LiiiiiiJ S |:| |:| ‘ n ‘ n \\\\\\\H\\\
2006-2014 Microchip Technology Inc. DS70000178D-page 21
dsPIC30F1010/202X
FIGURE 2-1: PROGRAMMERS MODEL
TABPAG
PC22 PC0
7 0
D0D15
Program Counter
Data Table Page Address
STATUS Register
Working Registers
DSP Operand
Registers
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
DSP Address
Registers
AD39 AD0AD31
DSP
Accumulators ACCA
ACCB
PSVPAG
7 0
Program Space Visibility Page Address
Z
0
OA OB SA SB
RCOUNT
15 0
REPEAT Loop Counter
DCOUNT
15 0
DO Loop Counter
DOSTART
22 0
DO Loop Start Address
IPL2 IPL1
SPLIM Stack Pointer Limit Register
AD15
SRL
PUSH.S Shadow
DO Shadow
OAB SAB
15 0
Core Configuration Register
Legend
CORCON
DA DC RA N
TBLPAG
PSVPAG
IPL0 OV
W0/WREG
SRH
DO Loop End Address
DOEND
22
C
dsPIC30F1010/202X
DS70000178D-page 22 2006-2014 Microchip Technology Inc.
2.3 Divide Support
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and 16/
16-bit signed and unsigned integer divide operations, in
the form of single instruction iterative divides. The
following instructions and data sizes are supported:
1. DIVF – 16/16 signed fractional divide
2. DIV.sd – 32/16 signed divide
3. DIV.ud – 32/16 unsigned divide
4. DIV.sw – 16/16 signed divide
5. DIV.uw – 16/16 unsigned divide
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g. a series
of discrete divide instructions) will not function correctly
because the instruction flow depends on RCOUNT.
The divide instruction does not automatically set up the
RCOUNT value, and it must, therefore, be explicitly
and correctly specified in the REPEAT instruction, as
shown in Table 2-1 (REPEAT will execute the target
instruction {operand value + 1} times). The REPEAT
loop count must be set up for 18 iterations of the DIV/
DIVF instruction. Thus, a complete divide operation
requires 19 cycles.
TABLE 2-1: DIVIDE INSTRUCTIONS
Note: The Divide flow is interruptible. However,
the user needs to save the context as
appropriate.
Instruction Function
DIVF Signed fractional divide: Wm/Wn W0; Rem W1
DIV.sd Signed divide: (Wm + 1:Wm)/Wn W0; Rem W1
DIV.ud Unsigned divide: (Wm + 1:Wm)/Wn W0; Rem W1
DIV.sw Signed divide: Wm/Wn W0; Rem W1
DIV.uw Unsigned divide: Wm/Wn W0; Rem W1
2006-2014 Microchip Technology Inc. DS70000178D-page 23
dsPIC30F1010/202X
2.4 DSP Engine
The DSP engine consists of a high speed 17-bit x
17-bit multiplier, a barrel shifter, and a 40-bit adder/sub-
tracter (with two target accumulators, round and
saturation logic).
The DSP engine also has the capability to perform inher-
ent accumulator-to-accumulator operations, which
require no additional data. These instructions are ADD,
SUB and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Configuration Register
(CORCON), as listed below:
1. Fractional or integer DSP multiply (IF).
2. Signed or unsigned DSP multiply (US).
3. Conventional or convergent rounding (RND).
4. Automatic saturation on/off for ACCA (SATA).
5. Automatic saturation on/off for ACCB (SATB).
6. Automatic saturation on/off for writes to data
memory (SATDW).
7. Accumulator Saturation mode selection
(ACCSAT).
A block diagram of the DSP engine is shown in
Figure 2-2.
Note: For CORCON layout, see Table 3-3.
TABLE 2-2: DSP INSTRUCTION SUMMARY
Instruction Algebraic Operation ACC WB?
CLR A = 0 Yes
ED A = (x – y)2No
EDAC A = A + (x – y)2No
MAC A = A + (x * y) Yes
MAC A = A + x2No
MOVSAC No change in A Yes
MPY A = x * y No
MPY.N A = – x * y No
MSC A = A – x * y Yes
dsPIC30F1010/202X
DS70000178D-page 24 2006-2014 Microchip Technology Inc.
FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM
Zero Backfill
Sign-Extend
Barrel
Shifter
40-bit Accumulator A
40-bit Accumulator B Round
Logic
X Data Bus
To/From W Array
Adder
Saturate
Negate
32
32
33
16
16 16
16
40 40
40 40
S
a
t
u
r
a
t
e
Y Data Bus
40
Carry/Borrow Out
Carry/Borrow In
16
40
Multiplier/Scaler
17-bit
2006-2014 Microchip Technology Inc. DS70000178D-page 25
dsPIC30F1010/202X
2.4.1 MULTIPLIER
The 17x17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the mul-
tiplier input value. The output of the 17x17-bit multiplier/
scaler is a 33-bit value, which is sign-extended to 40
bits. Integer data is inherently represented as a signed
two’s complement value, where the MSB is defined as
a sign bit. Generally speaking, the range of an N-bit
two’s complement integer is -2N-1 to 2N-1 – 1. For a 16-
bit integer, the data range is -32768 (0x8000) to 32767
(0x7FFF), including 0. For a 32-bit integer, the data
range is -2,147,483,648 (0x8000 0000) to
2,147,483,645 (0x7FFF FFFF).
When the multiplier is configured for fractional multipli-
cation, the data is represented as a two’s complement
fraction, where the MSB is defined as a sign bit and the
radix point is implied to lie just after the sign bit (QX for-
mat). The range of an N-bit two’s complement fraction
with this implied radix point is -1.0 to (1-21-N). For a
16-bit fraction, the Q15 data range is -1.0 (0x8000) to
0.999969482 (0x7FFF), including 0, and has a preci-
sion of 3.01518x10-5. In Fractional mode, a 16x16 mul-
tiply operation generates a 1.31 product, which has a
precision of 4.65661x10-10.
The same multiplier is used to support the MCU multi-
ply instructions, which include integer 16-bit signed,
unsigned and mixed sign multiplies.
The MUL instruction may be directed to use byte or
word sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
2.4.2 DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its pre-
accumulation source and post-accumulation destina-
tion. For the ADD and LAC instructions, the data to be
accumulated or loaded can be optionally scaled via the
barrel shifter, prior to accumulation.
2.4.2.1 Adder/Subtracter, Overflow and
Saturation
The adder/subtracter is a 40-bit adder with an optional
zero input into one side and either true or complement
data into the other input. In the case of addition, the
carry/borrow input is active high and the other input is
true data (not complemented), whereas in the case of
subtraction, the carry/borrow input is active low and the
other input is complemented. The adder/subtracter
generates overflow Status bits SA/SB and OA/OB,
which are latched and reflected in the STATUS register.
Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block which
controls accumulator data saturation, if selected. It
uses the result of the adder, the overflow Status bits
described above, and the SATA/B (CORCON<7:6>)
and ACCSAT (CORCON<4>) mode control bits to
determine when and to what value to saturate.
Six STATUS register bits have been provided to
support saturation and overflow; they are:
1. OA:
ACCA overflowed into guard bits
2. OB:
ACCB overflowed into guard bits
3. SA:
ACCA saturated (bit 31 overflow and saturation)
or
ACCA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
4. SB:
ACCB saturated (bit 31 overflow and saturation)
or
ACCB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
5. OAB:
Logical OR of OA and OB
6. SAB:
Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the correspond-
ing overflow trap flag enable bit (OVATE, OVBTE) in
the INTCON1 register (refer to Section 5.0 “Inter-
rupts”) is set. This allows the user to take immediate
action, for example, to correct system gain.
dsPIC30F1010/202X
DS70000178D-page 26 2006-2014 Microchip Technology Inc.
The SA and SB bits are modified each time data passes
through the adder/subtracter, but can only be cleared by
the user. When set, they indicate that the accumulator
has overflowed its maximum range (bit 31 for 32-bit sat-
uration, or bit 39 for 40-bit saturation) and will be satu-
rated (if saturation is enabled). When saturation is not
enabled, SA and SB default to bit 39 overflow and thus
indicate that a catastrophic overflow has occurred. If the
COVTE bit in the INTCON1 register is set, SA and SB
bits will generate an arithmetic warning trap when
saturation is disabled.
The overflow and saturation Status bits can optionally
be viewed in the STATUS Register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). This allows programmers to check
one bit in the STATUS Register to determine if either
accumulator has overflowed, or one bit to determine if
either accumulator has saturated. This is useful for
complex number arithmetic, which typically uses both
the accumulators.
The device supports three Saturation and Overflow
modes.
1. Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
(0x7FFFFFFFFF) or maximally negative 9.31
value (0x8000000000) into the target accumula-
tor. The SA or SB bit is set and remains set until
cleared by the user. This is referred to as ‘super
saturation’ and provides protection against erro-
neous data or unexpected algorithm problems
(e.g., gain calculations).
2. Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive
1.31 value (0x007FFFFFFF) or maximally nega-
tive 1.31 value (0x0080000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user. When this Saturation
mode is in effect, the guard bits are not used (so
the OA, OB or OAB bits are never set).
3. Bit 39 Catastrophic Overflow
The bit 39 overflow Status bit from the adder is
used to set the SA or SB bit, which remain set
until cleared by the user. No saturation operation
is performed and the accumulator is allowed to
overflow (destroying its sign). If the COVTE bit in
the INTCON1 register is set, a catastrophic
overflow can initiate a trap exception.
2.4.2.2 Accumulator ‘Write Back’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following addressing modes are supported:
1. W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a 1.15
fraction.
2. [W13] + = 2, Register Indirect with Post-Incre-
ment: The rounded contents of the non-target
accumulator are written into the address pointed
to by W13 as a 1.15 fraction. W13 is then
incremented by 2 (for a word write).
2.4.2.3 Round Logic
The round logic is a combinational block, which per-
forms a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It generates a 16-bit, 1.15 data
value which is passed to the data space write saturation
logic. If rounding is not indicated by the instruction, a
truncated 1.15 data value is stored and the least
significant word (lsw) is simply discarded.
Conventional rounding takes bit 15 of the accumulator,
zero-extends it and adds it to the ACCxH word (bits 16
through 31 of the accumulator). If the ACCxL word (bits
0 through 15 of the accumulator) is between 0x8000
and 0xFFFF (0x8000 included), ACCxH is incre-
mented. If ACCxL is between 0x0000 and 0x7FFF,
ACCxH is left unchanged. A consequence of this
algorithm is that over a succession of random rounding
operations, the value will tend to be biased slightly
positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. If this is the case, the LSb (bit
16 of the accumulator) of ACCxH is examined. If it is ‘1’,
ACCxH is incremented. If it is ‘0, ACCxH is not modi-
fied. Assuming that bit 16 is effectively random in
nature, this scheme will remove any rounding bias that
may accumulate.
The SAC and SAC.R instructions store either a trun-
cated (SAC) or rounded (SAC.R) version of the contents
of the target accumulator to data memory, via the X bus
(subject to data saturation, see Section 2.4.2.4 “Data
Space Write Saturation”). Note that for the MAC class
of instructions, the accumulator write back operation
will function in the same manner, addressing combined
MCU (X and Y) data space though the X bus. For this
class of instructions, the data is always subject to
rounding.
2006-2014 Microchip Technology Inc. DS70000178D-page 27
dsPIC30F1010/202X
2.4.2.4 Data Space Write Saturation
In addition to adder/subtracter saturation, writes to data
space may also be saturated, but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15 frac-
tional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These are
combined and used to select the appropriate 1.15 frac-
tional value as output to write to data space memory.
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly. For input data greater than
0x007FFF, data written to memory is forced to the max-
imum positive 1.15 value, 0x7FFF. For input data less
than 0xFF8000, data written to memory is forced to the
maximum negative 1.15 value, 0x8000. The MSb of the
source (bit 39) is used to determine the sign of the
operand being tested.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
2.4.3 BARREL SHIFTER
The barrel shifter is capable of performing up to 15-bit
arithmetic or logic right shifts, or up to 16-bit left shifts
in a single cycle. The source can be either of the two
DSP accumulators or the X bus (to support multi-bit
shifts of register or memory data).
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value will shift the operand
right. A negative value will shift the operand left. A
value of ‘0’ will not modify the operand.
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is pre-
sented to the barrel shifter between bit positions 16 to
31 for right shifts, and bit positions 0 to 15 for left shifts.
dsPIC30F1010/202X
DS70000178D-page 28 2006-2014 Microchip Technology Inc.
NOTES:
Reset 7 Term Addvess Ex‘ 05:: Fan Trap
2006-2014 Microchip Technology Inc. DS70000178D-page 29
dsPIC30F1010/202X
3.0 MEMORY ORGANIZATION
3.1 Program Address Space
The program address space is 4M instruction words. It
is addressable by a 24-bit value from either the 23-bit
PC, table instruction Effective Address (EA), or data
space EA, when program space is mapped into data
space, as defined by Table 3-1. Note that the program
space address is incremented by two between succes-
sive program words, in order to provide compatibility
with data space addressing.
User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE), for all accesses other than TBLRD/TBLWT,
which use TBLPAG<7> to determine user or configura-
tion space access. In Table 3-1, Read/Write instruc-
tions, bit 23 allows access to the Device ID, the User ID
and the Configuration bits. Otherwise, bit 23 is always
clear.
FIGURE 3-1: PROGRAM SPACE
MEMORY MAP FOR
dsPIC30F1010/202X
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
Note: The address map shown in Figure 3-1 is
conceptual, and the actual memory con-
figuration may vary across individual
devices depending on available memory.
Reset – Target Address
User Memory
Space
000000
7FFFFE
00007E
Ext. Osc. Fail Trap
000002
000080
User Flash
Program Memory
002000
001FFE
Address Error Trap
Stack Error Trap
Arithmetic Warn. Trap
Reserved
Reserved
Reserved
Vector 0
Vector 1
Vector 52
Vector 53
(4K instructions)
Reserved
(Read 0’s)
0000FE
000100
000014
Alternate Vector Table
Reset – GOTO Instruction
000004
Reserved
Device Configuration
Configuration Memory
Space
800000
F80000
Registers F8000E
F80010
DEVID (2)
FEFFFE
FF0000
FFFFFE
Reserved F7FFFE
8005FE
800600
UNITID (32 instr.)
8005BE
8005C0
Reserved
Reserved
Vector Tables
dsPIC30F1010/202X
DS70000178D-page 30 2006-2014 Microchip Technology Inc.
TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION
FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Access Type Access
Space
Program Space Address
<23> <22:16> <15> <14:1> <0>
Instruction Access User 0 PC<22:1> 0
TBLRD/TBLWT User
(TBLPAG<7> = 0)TBLPAG<7:0> Data EA <15:0>
TBLRD/TBLWT Configuration
(TBLPAG<7> = 1)TBLPAG<7:0> Data EA <15:0>
Program Space Visibility User 0 PSVPAG<7:0> Data EA <14:0>
0Program Counter
23 bits
1
PSVPAG Reg
8 bits
EA
15 bits
Program
Using
Select
TBLPAG Reg
8 bits
EA
16 bits
Using
Byte
24-bit EA
0
0
1/0
Select
User/
Configuration
Table
Instruction
Program
Space
Counter
Using
Space
Select
Note: Program Space Visibility cannot be used to access bits <23:16> of a word in program memory.
Visibility
XOOODOA XOOOOOG
2006-2014 Microchip Technology Inc. DS70000178D-page 31
dsPIC30F1010/202X
3.1.1 DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
This architecture fetches 24-bit wide program memory.
Consequently, instructions are always aligned. How-
ever, as the architecture is modified Harvard, data can
also be present in program space.
There are two methods by which program space can
be accessed; via special table instructions, or through
the remapping of a 16K word program space page into
the upper half of data space (see Section 3.1.2 “Data
Access from Program Memory Using Program
Space Visibility”). The TBLRDL and TBLWTL instruc-
tions offer a direct method of reading or writing the least
significant word (lsw) of any address within program
space, without going through data space. The TBLRDH
and TBLWTH instructions are the only method whereby
the upper 8 bits of a program space word can be
accessed as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the Least Significant
Data Word, and TBLRDH and TBLWTH access the
space which contains the Most Significant Data Byte.
Figure 3-2 shows how the EA is created for table oper-
ations and data space accesses (PSV = 1). Here,
P<23:0> refers to a program space word, whereas
D<15:0> refers to a data space word.
A set of Table Instructions is provided to move byte or
word sized data to and from program space.
1. TBLRDL: Table Read Low
Word: Read the lsw of the program address;
P<15:0> maps to D<15:0>.
Byte: Read one of the LSBs of the program
address;
P<7:0> maps to the destination byte when byte
select = 0;
P<15:8> maps to the destination byte when byte
select = 1.
2. TBLWTL: Table Write Low (refer to Section 7.0
“Flash Program Memory” for details on Flash
Programming).
3. TBLRDH: Table Read High
Word: Read the most significant word of the
program address;
P<23:16> maps to D<7:0>; D<15:8> always
be = 0.
Byte: Read one of the MSBs of the program
address;
P<23:16> maps to the destination byte when
byte select = 0;
The destination byte will always be = 0 when
byte select = 1.
4. TBLWTH: Table Write High (refer to Section 7.0
“Flash Program Memory” for details on Flash
Programming).
FIGURE 3-3: PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD)
0
8
16
PC Address
0x000000
0x000002
0x000004
0x000006
23
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(Read as ‘0’).
TBLRDL.W
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
xoooom 00°00 xoooooe one one
dsPIC30F1010/202X
DS70000178D-page 32 2006-2014 Microchip Technology Inc.
FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE)
3.1.2 DATA ACCESS FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word program space page. This
provides transparent access of stored constant data
from X data space, without the need to use special
instructions (i.e., TBLRDL/H, TBLWTL/H instructions).
Program space access through the data space occurs
if the MSb of the data space EA is set and program
space visibility is enabled, by setting the PSV bit in the
Core Control register (CORCON). The functions of
CORCON are discussed in Section 2.4 “DSP
Engine”.
Data accesses to this area add an additional cycle to
the instruction being executed, since two program
memory fetches are required.
Note that the upper half of addressable data space is
always part of the X data space. Therefore, when a
DSP operation uses program space mapping to access
this memory region, Y data space should typically con-
tain state (variable) data for DSP operations, whereas
X data space should typically contain coefficient
(constant) data.
Although each data space address, 0x8000 and higher,
maps directly into a corresponding program memory
address (see Figure 3-5), only the lower 16-bits of the
24-bit program word are used to contain the data. The
upper 8 bits should be programmed to force an illegal
instruction to maintain machine robustness. Refer to
the “dsPIC30F/33F Programmer’s Reference Manual”
(DS70157) for details on instruction encoding.
Note that by incrementing the PC by 2 for each pro-
gram memory word, the Least Significant 15 bits of
data space addresses directly map to the Least Signif-
icant 15 bits in the corresponding program space
addresses. The remaining bits are provided by the Pro-
gram Space Visibility Page register, PSVPAG<7:0>, as
shown in Figure 3-5.
For instructions that use PSV which are executed
outside a REPEAT loop:
The following instructions will require one instruc-
tion cycle in addition to the specified execution
time:
-MAC class of instructions with data operand
prefetch
-MOV instructions
-MOV.D instructions
All other instructions will require two instruction
cycles in addition to the specified execution time
of the instruction.
For instructions that use PSV which are executed
inside a REPEAT loop:
The following instances will require two instruction
cycles in addition to the specified execution time
of the instruction:
- Execution in the first iteration
- Execution in the last iteration
- Execution prior to exiting the loop due to an
interrupt
- Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow
the instruction, accessing data using PSV, to
execute in a single cycle.
Note: PSV access is temporarily disabled during
Table Reads/Writes.
x0
2006-2014 Microchip Technology Inc. DS70000178D-page 33
dsPIC30F1010/202X
FIGURE 3-5: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION
3.2 Data Address Space
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instruc-
tions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
3.2.1 DATA SPACE MEMORY MAP
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.
When executing any instruction other than one of the
MAC class of instructions, the X block consists of the
256 byte data address space (including all Y
addresses). When executing one of the MAC class of
instructions, the X block consists of the 256 bytes data
address space excluding the Y address block (for data
reads only). In other words, all other instructions regard
the entire data memory as one composite address
space. The MAC class instructions extract the Y
address space from data space and address it using
EAs sourced from W10 and W11. The remaining X data
space is addressed using W8 and W9. Both address
spaces are concurrently accessed only with the MAC
class instructions.
A data space memory map is shown in Figure 3-6.
23 15 0
PSVPAG(1)
15
15
EA<15> =
0
EA<15> = 1
16
Data
Space
EA
Data Space Program Space
8
15 23
0x0000
0x8000
0xFFFF
0x00
0x100100
0x001FFE
Data Read
Upper half of Data
Space is mapped
into Program Space
Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address
(i.e., it defines the page in program space to which the upper half of data space is being mapped).
0x001200
Address
Concatenation
BSET CORCON,#2 ; PSV bit set
MOV #0x00, W0 ; Set PSVPAG register
MOV W0, PSVPAG
MOV 0x9200, W0 ; Access program memory location
; using a data space access
dsPIC30F1010/202X
DS70000178D-page 34 2006-2014 Microchip Technology Inc.
FIGURE 3-6: DATA SPACE MEMORY MAP
0x0000
0x07FE
0x08FE
0xFFFE
LSB
Address
16 bits
LSBMSB
MSB
Address
0x0001
0x07FF
0x08FF
0xFFFF
0x8001 0x8000
Optionally
Mapped
into Program
Memory
0x09FF 0x09FE
0x0801 0x0800
0x0901 0x0900
Near
Data
SFR Space
512 bytes
SRAM Space
2560 bytes
Note: Unimplemented SFR or SRAM locations read as ‘0’.
Space
Unimplemented (X)
X Data
SFR Space
X Data RAM (X)
Y Data RAM (Y)
(Note)
256 bytes
256 bytes
(See Note)
0x0A00
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dsPIC30F1010/202X
FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS
SFR SPACE
(Y SPACE)
X SPACE
SFR SPACE
UNUSED
X SPACE
X SPACE
Y SPACE
UNUSED
UNUSED
Non-MAC Class Ops (Read/Write) MAC Class Ops Read-Only
Indirect EA using any W Indirect EA using W10, W11
MAC Class Ops (Write)
Indirect EA using W8, W9
dsPIC30F1010/202X
DS70000178D-page 36 2006-2014 Microchip Technology Inc.
3.2.2 DATA SPACES
The X data space is used by all instructions and sup-
ports all Addressing modes. There are separate read
and write data buses. The X read data bus is the return
data path for all instructions that view data space as
combined X and Y address space. It is also the X
address space data path for the dual operand read
instructions (MAC class). The X write data bus is the
only write path to data space for all instructions.
The X data space also supports modulo addressing for
all instructions, subject to Addressing mode restric-
tions. Bit-Reversed Addressing is only supported for
writes to X data space.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to pro-
vide two concurrent data read paths. No writes occur
across the Y bus. This class of instructions dedicates
two W register pointers, W10 and W11, to always
address Y data space, independent of X data space,
whereas W8 and W9 always address X data space.
Note that during accumulator write back, the data
address space is considered a combination of X and Y
data spaces, so the write occurs across the X bus.
Consequently, the write can be to any address in the
entire data space.
The Y data space can only be used for the data
prefetch operation associated with the MAC class of
instructions. It also supports modulo addressing for
automated circular buffers. Of course, all other instruc-
tions can access the Y data address space through the
X data path, as part of the composite linear space.
The boundary between the X and Y data spaces is
defined as shown in Figure 3-6 and is not user pro-
grammable. Should an EA point to data outside its own
assigned address space, or to a location outside phys-
ical memory, an all-zero word/byte will be returned. For
example, although Y address space is visible by all
non-MAC instructions using any Addressing mode, an
attempt by a MAC instruction to fetch data from that
space, using W8 or W9 (X space pointers), will return
0x0000.
TABLE 3-2: EFFECT OF INVALID
MEMORY ACCESSES
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words.
3.2.3 DATA SPACE WIDTH
The core data width is 16 bits. All internal registers are
organized as 16-bit wide words. Data space memory is
organized in byte addressable, 16-bit wide blocks.
3.2.4 DATA ALIGNMENT
To help maintain backward compatibility with PIC®
MCU devices and improve data space memory usage
efficiency, the dsPIC30F instruction set supports both
word and byte operations. Data is aligned in data mem-
ory and registers as words, but all data space EAs
resolve to bytes. Data byte reads will read the complete
word, which contains the byte, using the LSb of any EA
to determine which byte to select. The selected byte is
placed onto the LSB of the X data path (no byte
accesses are possible from the Y data path as the MAC
class of instruction can only fetch words). That is, data
memory and registers are organized as two parallel
byte-wide entities with shared (word) address decode,
but separate write lines. Data byte writes only write to
the corresponding side of the array or register which
matches the byte address.
As a consequence of this byte accessibility, all effective
address calculations (including those generated by the
DSP operations, which are restricted to word sized
data) are internally scaled to step through word-aligned
memory. For example, the core would recognize that
Post-Modified Register Indirect Addressing mode,
[Ws++], will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word opera-
tions, or translating from 8-bit MCU code. Should a mis-
aligned read or write be attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed, whereas if it
occurred on a write, the instruction will be executed but
the write will not occur. In either case, a trap will then
be executed, allowing the system and/or user to exam-
ine the machine state prior to execution of the address
fault.
FIGURE 3-8: DATA ALIGNMENT
Attempted Operation Data Returned
EA = an unimplemented address 0x0000
W8 or W9 used to access Y data
space in a MAC instruction 0x0000
W10 or W11 used to access X
data space in a MAC instruction 0x0000
15 8 7 0
0001
0003
0005
0000
0002
0004
Byte 1 Byte 0
Byte 3 Byte 2
Byte 5 Byte 4
LSBMSB
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dsPIC30F1010/202X
All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
A Sign-Extend (SE) instruction is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
Zero-Extend (ZE) instruction on the appropriate
address.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions, including the DSP instructions, operate
only on words.
3.2.5 NEAR DATA SPACE
An 8 Kbyte ‘near’ data space is reserved in X address
memory space between 0x0000 and 0x1FFF, which is
directly addressable via a 13-bit absolute address field
within all memory direct instructions. The remaining X
address space and all of the Y address space is
addressable indirectly. Additionally, the whole of X data
space is addressable using MOV instructions, which
support memory direct addressing with a 16-bit
address field.
3.2.6 SOFTWARE STACK
The dsPIC DSC device contains a software stack. W15
is used as the Stack Pointer.
The Stack Pointer always points to the first available
free word and grows from lower addresses towards
higher addresses. It pre-decrements for stack pops and
post-increments for stack pushes, as shown in
Figure 3-9. Note that for a PC push during any CALL
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear.
There is a Stack Pointer Limit register (SPLIM) associ-
ated with the Stack Pointer. SPLIM is uninitialized at
Reset. As is the case for the Stack Pointer, SPLIM<0>
is forced to ‘0’, because all stack operations must be
word-aligned. Whenever an Effective Address (EA) is
generated using W15 as a source or destination
pointer, the address thus generated is compared with
the value in SPLIM. If the contents of the Stack Pointer
(W15) and the SPLIM register are equal and a push
operation is performed, a stack error trap will not occur.
The stack error trap will occur on a subsequent push
operation. Thus, for example, if it is desirable to cause
a stack error trap when the stack grows beyond
address 0x2000 in RAM, initialize the SPLIM with the
value, 0x1FFE.
Similarly, a Stack Pointer Underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800, thus preventing the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 3-9: CALL STACK FRAME
3.2.7 DATA RAM PROTECTION
The dsPIC30F1010/202X devices support data RAM
protection features which enable segments of RAM to
be protected when used in conjunction with Boot Code
Segment Security. BSRAM (Secure RAM segment for
BS) is accessible only from the Boot Segment Flash
code when enabled. See Table 3-3 for the BSRAM
SFR.
Note: A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
<Free Word>
PC<15:0>
000000000
015
W15 (before CALL)
W15 (after CALL)
Stack Grows Towards
Higher Address
PUSH: [W15++]
POP: [--W15]
0x0000
PC<22:16>
dsPIC30F1010/202X
DS70000178D-page 38 2006-2014 Microchip Technology Inc.
TABLE 3-3: CORE REGISTER MAP
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
W0 0000 W0/WREG 0000 0000 0000 0000
W1 0002 W1 0000 0000 0000 0000
W2 0004 W2 0000 0000 0000 0000
W3 0006 W3 0000 0000 0000 0000
W4 0008 W4 0000 0000 0000 0000
W5 000A W5 0000 0000 0000 0000
W6 000C W6 0000 0000 0000 0000
W7 000E W7 0000 0000 0000 0000
W8 0010 W8 0000 0000 0000 0000
W9 0012 W9 0000 0000 0000 0000
W10 0014 W10 0000 0000 0000 0000
W11 0016 W11 0000 0000 0000 0000
W12 0018 W12 0000 0000 0000 0000
W13 001A W13 0000 0000 0000 0000
W14 001C W14 0000 0000 0000 0000
W15 001E W15 0000 1000 0000 0000
SPLIM 0020 SPLIM 0000 0000 0000 0000
ACCAL 0022 ACCAL 0000 0000 0000 0000
ACCAH 0024 ACCAH 0000 0000 0000 0000
ACCAU 0026 Sign-Extension (ACCA<39>) ACCAU 0000 0000 0000 0000
ACCBL 0028 ACCBL 0000 0000 0000 0000
ACCBH 002A ACCBH 0000 0000 0000 0000
ACCBU 002C Sign-Extension (ACCB<39>) ACCBU 0000 0000 0000 0000
PCL 002E PCL 0000 0000 0000 0000
PCH 0030 — — — — —PCH0000 0000 0000 0000
TBLPAG 0032 — — — — —TBLPAG0000 0000 0000 0000
PSVPAG 0034 — — — — PSVPAG 0000 0000 0000 0000
RCOUNT 0036 RCOUNT uuuu uuuu uuuu uuuu
DCOUNT 0038 DCOUNT uuuu uuuu uuuu uuuu
DOSTARTL 003A DOSTARTL 0uuuu uuuu uuuu uuu0
DOSTARTH 003C — — — — —DOSTARTH0000 0000 0uuu uuuu
DOENDL 003E DOENDL 0uuuu uuuu uuuu uuu0
DOENDH 0040 — — — — DOENDH 0000 0000 0uuu uuuu
SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 0000 0000 0000
CORCON 0044 US EDT DL2 DL1 DL0 SATA SATB
SATDW
ACCSAT IPL3 PSV RND IF 0000 0000 0010 0000
Legend: u = uninitialized bit
2006-2014 Microchip Technology Inc. DS70000178D-page 39
dsPIC30F1010/202X
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
MODCON 0046 XMODEN YMODEN — BWM<3:0> YWM<3:0> XWM<3:0> 0000 0000 0000 0000
XMODSRT 0048 XS<15:1> 0uuuu uuuu uuuu uuu0
XMODEND 004A XE<15:1> 1uuuu uuuu uuuu uuu1
YMODSRT 004C YS<15:1> 0uuuu uuuu uuuu uuu0
YMODEND 004E YE<15:1> 1uuuu uuuu uuuu uuu1
XBREV 0050 BREN XB<14:0> uuuu uuuu uuuu uuuu
DISICNT 0052 DISICNT<13:0> 0000 0000 0000 0000
BSRAM 0750 — — — —
IW_BSR
IR_BSR
RL_BSR
0000 0000 0000 0000
TABLE 3-3: CORE REGISTER MAP (CONTINUED)
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Legend: u = uninitialized bit
dsPIC30F1010/202X
DS70000178D-page 40 2006-2014 Microchip Technology Inc.
NOTES:
2006-2014 Microchip Technology Inc. DS70000178D-page 41
dsPIC30F1010/202X
4.0 ADDRESS GENERATOR UNITS
The dsPIC DSC core contains two independent
address generator units: the X AGU and Y AGU. The Y
AGU supports word sized data reads for the DSP MAC
class of instructions only. The dsPIC DSC AGUs
support three types of data addressing:
Linear Addressing
Modulo (Circular) Addressing
Bit-Reversed Addressing
Linear and Modulo Data Addressing modes can be
applied to data space or program space. Bit-Reversed
Addressing is only applicable to data space addresses.
4.1 Instruction Addressing Modes
The Addressing modes in Table 4-1 form the basis of
the Addressing modes optimized to support the specific
features of individual instructions. The Addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
4.1.1 FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (near data space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register, or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
TABLE 4-1: FUNDAMENTAL ADDRESSING MODES SUPPORTED
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
Addressing Mode Description
File Register Direct The address of the file register is specified explicitly.
Register Direct The contents of a register are accessed directly.
Register Indirect The contents of Wn forms the EA.
Register Indirect Post-modified The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-modified Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.
dsPIC30F1010/202X
DS70000178D-page 42 2006-2014 Microchip Technology Inc.
4.1.2 MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where Operand 1 is always a working register (i.e., the
Addressing mode can only be register direct), which is
referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or an address
location. The following Addressing modes are
supported by MCU instructions:
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
5-bit or 10-bit Literal
4.1.3 MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions and the DSP Accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
Addressing modes supported by most MCU instruc-
tions, move and accumulator instructions also support
Register Indirect with Register Offset Addressing
mode, also referred to as Register Indexed mode.
In summary, the following Addressing modes are
supported by move and accumulator instructions:
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-bit Literal
16-bit Literal
4.1.4 MAC INSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also
referred to as MAC instructions, utilize a simplified set of
Addressing modes to allow the user to effectively
manipulate the data pointers through register indirect
tables.
The two source operand prefetch registers must be a
member of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 will always be directed to the X
RAGU and W10 and W11 will always be directed to the
Y AGU. The effective addresses generated (before and
after modification) must, therefore, be valid addresses
within X data space for W8 and W9 and Y data space
for W10 and W11.
In summary, the following Addressing modes are
supported by the MAC class of instructions:
Register Indirect
Register Indirect Post-modified by 2
Register Indirect Post-modified by 4
Register Indirect Post-modified by 6
Register Indirect with Register Offset (Indexed)
4.1.5 OTHER INSTRUCTIONS
Besides the various Addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ADD Acc, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as NOP, do not have any
operands.
Note: Not all instructions support all the
Addressing modes given above. Individual
instructions may support different subsets
of these Addressing modes.
Note: For the MOV instructions, the Addressing
mode specified in the instruction can differ
for the source and destination EA. How-
ever, the 4-bit Wb (Register Offset) field is
shared between both source and
destination (but typically only used by
one).
Note: Not all instructions support all the
Addressing modes given above. Individual
instructions may support different subsets
of these Addressing modes.
Note: Register Indirect with Register Offset
Addressing is only available for W9 (in X
space) and W11 (in Y space).
2006-2014 Microchip Technology Inc. DS70000178D-page 43
dsPIC30F1010/202X
4.2 Modulo Addressing
Modulo addressing is a method of providing an auto-
mated means to support circular data buffers using
hardware. The objective is to remove the need for soft-
ware to perform data address boundary checks when
executing tightly looped code, as is typical in many
DSP algorithms.
Modulo addressing can operate in either data or pro-
gram space (since the data pointer mechanism is essen-
tially the same for both). One circular buffer can be
supported in each of the X (which also provides the
pointers into program space) and Y data spaces. Modulo
addressing can operate on any W register pointer. How-
ever, it is not advisable to use W14 or W15 for modulo
addressing, since these two registers are used as the
Stack Frame Pointer and Stack Pointer, respectively.
In general, any particular circular buffer can only be
configured to operate in one direction, as there are cer-
tain restrictions on the buffer start address (for incre-
menting buffers) or end address (for decrementing
buffers) based upon the direction of the buffer.
The only exception to the usage restrictions is for buf-
fers which have a power-of-2 length. As these buffers
satisfy the start and end address criteria, they may
operate in a Bidirectional mode, (i.e., address bound-
ary checks will be performed on both the lower and
upper address boundaries).
4.2.1 START AND END ADDRESS
The modulo addressing scheme requires that a
starting and an end address be specified and loaded
into the 16-bit modulo buffer address registers:
XMODSRT, XMODEND, YMODSRT and YMODEND
(see Table 3-3).
The length of a circular buffer is not directly specified. It
is determined by the difference between the corre-
sponding start and end addresses. The maximum
possible length of the circular buffer is 32K words
(64 Kbytes).
4.2.2 W ADDRESS REGISTER
SELECTION
The Modulo and Bit-Reversed Addressing Control reg-
ister MODCON<15:0> contains enable flags as well as
a W register field to specify the W address registers.
The XWM and YWM fields select which registers will
operate with modulo addressing. If XWM = 15, X RAGU
and X WAGU modulo addressing are disabled.
Similarly, if YWM = 15, Y AGU modulo addressing is
disabled.
The X Address Space Pointer W register (XWM) to
which modulo addressing is to be applied, is stored in
MODCON<3:0> (see Table 3-3). Modulo addressing is
enabled for X data space when XWM is set to any value
other than 15 and the XMODEN bit is set at
MODCON<15>.
The Y Address Space Pointer W register (YWM) to
which modulo addressing is to be applied, is stored in
MODCON<7:4>. Modulo addressing is enabled for Y
data space when YWM is set to any value other than 15
and the YMODEN bit is set at MODCON<14>.
Note: Y-space modulo addressing EA calcula-
tions assume word sized data (LSb of
every EA is always clear).
L‘J
dsPIC30F1010/202X
DS70000178D-page 44 2006-2014 Microchip Technology Inc.
FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE
0x1100
0x1163
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 words
Byte
Address MOV #0x1100,W0
MOV W0, XMODSRT ;set modulo start address
MOV #0x1163,W0
MOV W0,MODEND ;set modulo end address
MOV #0x8001,W0
MOV W0,MODCON ;enable W1, X AGU for modulo
MOV #0x0000,W0 ;W0 holds buffer fill value
MOV #0x1110,W1 ;point W1 to buffer
DO AGAIN,#0x31 ;fill the 50 buffer locations
MOV W0, [W1++] ;fill the next location
AGAIN: INC W0,W0 ;increment the fill value
EMU
2006-2014 Microchip Technology Inc. DS70000178D-page 45
dsPIC30F1010/202X
4.2.3 MODULO ADDRESSING
APPLICABILITY
Modulo addressing can be applied to the Effective
Address (EA) calculation associated with any W regis-
ter. It is important to realize that the address boundar-
ies check for addresses less than or greater than the
upper (for incrementing buffers) and lower (for decre-
menting buffers) boundary addresses (not just equal
to). Address changes may, therefore, jump beyond
boundaries and still be adjusted correctly.
4.3 Bit-Reversed Addressing
Bit-Reversed Addressing is intended to simplify data
re-ordering for radix-2 FFT algorithms. It is supported
by the X AGU for data writes only.
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed.
The address source and destination are kept in normal
order. Thus, the only operand requiring reversal is the
modifier.
4.3.1 BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing is enabled when:
1. BWM (W register selection) in the MODCON
register is any value other than 15 (the stack can
not be accessed using Bit-Reversed
Addressing) and
2. the BREN bit is set in the XBREV register and
3. the Addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
If the length of a bit-reversed buffer is M = 2N bytes,
then the last ‘N’ bits of the data buffer start address
must be zeros.
XB<14:0> is the bit-reversed address modifier or ‘pivot
point’ which is typically a constant. In the case of an
FFT computation, its value is equal to half of the FFT
data buffer size.
When enabled, Bit-Reversed Addressing will only be
executed for register indirect with pre-increment or
post-increment addressing and word sized data writes.
It will not function for any other Addressing mode or for
byte sized data, and normal addresses will be gener-
ated instead. When Bit-Reversed Addressing is active,
the W Address Pointer will always be added to the
address modifier (XB) and the offset associated with
the register Indirect Addressing mode will be ignored.
In addition, as word sized data is a requirement, the
LSb of the EA is ignored (and always clear).
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, then a write to
the XBREV register should not be immediately followed
by an indirect read operation using the W register that
has been designated as the bit-reversed pointer.
FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE
Note: The modulo corrected effective address is
written back to the register only when Pre-
Modify or Post-Modify Addressing mode is
used to compute the Effective Address.
When an address offset (e.g., [W7 + W2])
is used, modulo address correction is per-
formed, but the contents of the register
remains unchanged.
Note: All Bit-Reversed EA calculations assume
word sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Note: Modulo addressing and Bit-Reversed
Addressing should not be enabled
together. In the event that the user
attempts to do this, Bit-Reversed Address-
ing will assume priority when active for the
X WAGU, and X WAGU modulo address-
ing will be disabled. However, modulo
addressing will continue to function in the
X RAGU.
b3 b2 b1 0
b2 b3 b4 0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
Bit-Reversed Address
XB = 0x0008 for a 16 word Bit-Reversed Buffer
b7 b6 b5 b1
b7 b6 b5 b4b11 b10 b9 b8
b11 b10 b9 b8
b15 b14 b13 b12
b15 b14 b13 b12
Sequential Address
Pivot Point
dsPIC30F1010/202X
DS70000178D-page 46 2006-2014 Microchip Technology Inc.
TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER
Normal
Address Bit-Reversed
Address
A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal
0000 00000 0
0001 11000 8
0010 20100 4
0011 31100 12
0100 40010 2
0101 51010 10
0110 60110 6
0111 71110 14
1000 80001 1
1001 91001 9
1010 10 0101 5
1011 11 1101 13
1100 12 0011 3
1101 13 1011 11
1110 14 0111 7
1111 15 1111 15
Buffer Size (Words) XB<14:0> Bit-Reversed Address Modifier Value(1)
32768 0x4000
16384 0x2000
8192 0x1000
4096 0x0800
2048 0x0400
1024 0x0200
512 0x0100
256 0x0080
128 0x0040
64 0x0020
32 0x0010
16 0x0008
80x0004
40x0002
20x0001
Note 1: Modifier values greater than 256 words exceed the data memory available on the dsPIC30F1010/202X device
2006-2014 Microchip Technology Inc. DS70000178D-page 47
dsPIC30F1010/202X
5.0 INTERRUPTS
The dsPIC30F1010/202X device has up to 35 interrupt
sources and 4 processor exceptions (traps), which
must be arbitrated based on a priority scheme.
The CPU is responsible for reading the Interrupt Vec-
tor Table (IVT) and transferring the address contained
in the interrupt vector to the Program Counter (PC).
The interrupt vector is transferred from the program
data bus into the Program Counter, via a 24-bit wide
multiplexer on the input of the Program Counter.
The Interrupt Vector Table and Alternate Interrupt Vec-
tor Table (AIVT) are placed near the beginning of pro-
gram memory (0x000004). The IVT and AIVT are
shown in Figure 5-1.
The interrupt controller is responsible for pre-
processing the interrupts and processor exceptions,
prior to their being presented to the processor core.
The peripheral interrupts and traps are enabled, priori-
tized and controlled using centralized special function
registers:
IFS0<15:0>, IFS1<15:0>, IFS2<15:0>
All interrupt request flags are maintained in these
three registers. The flags are set by their respec-
tive peripherals or external signals, and they are
cleared via software.
IEC0<15:0>, IEC1<15:0>, IEC2<15:0>
All interrupt enable control bits are maintained in
these three registers. These control bits are used
to individually enable interrupts from the
peripherals or external signals.
IPC0<15:0>... IPC11<7:0>
The user-assignable priority level associated with
each of these interrupts is held centrally in these
twelve registers.
IPL<3:0> The current CPU priority level is explic-
itly stored in the IPL bits. IPL<3> is present in the
CORCON register, whereas IPL<2:0> are present
in the STATUS Register (SR) in the processor
core.
INTCON1<15:0>, INTCON2<15:0>
Global interrupt control functions are derived from
these two registers. INTCON1 contains the con-
trol and status flags for the processor exceptions.
The INTCON2 register controls the external inter-
rupt request signal behavior and the use of the
alternate vector table.
The INTTREG register contains the associated
interrupt vector number and the new CPU inter-
rupt priority level, which are latched into vector
number (VECNUM<6:0>) and Interrupt level
(ILR<3:0>) bit fields in the INTTREG register. The
new interrupt priority level is the priority of the
pending interrupt.
All interrupt sources can be user assigned to one of 7
priority levels, 1 through 7, via the IPCx registers.
Each interrupt source is associated with an interrupt
vector, as shown in Figure 5-1. Levels 7 and 1 repre-
sent the highest and lowest maskable priorities,
respectively.
If the NSTDIS bit (INTCON1<15>) is set, nesting of
interrupts is prevented. Thus, if an interrupt is currently
being serviced, processing of a new interrupt is
prevented, even if the new interrupt is of higher priority
than the one currently being serviced.
Certain interrupts have specialized control bits for
features like edge or level triggered interrupts, inter-
rupt-on-change, etc. Control of these features remains
within the peripheral module that generates the
interrupt.
The DISI instruction can be used to disable the
processing of interrupts of priorities 6 and lower for a
certain number of instructions, during which the DISI bit
(INTCON2<14>) remains set.
When an interrupt is serviced, the PC is loaded with the
address stored in the vector location in Program Mem-
ory that corresponds to the interrupt. There are 63 dif-
ferent vectors within the IVT (refer to Figure 5-1). These
vectors are contained in locations 0x000004 through
0x0000FE of program memory (refer to Figure 5-1).
These locations contain 24-bit addresses, and, in order
to preserve robustness, an address error trap will take
place should the PC attempt to fetch any of these
words during normal execution. This prevents execu-
tion of random data as a result of accidentally decre-
menting a PC into vector space, accidentally mapping
a data space address into vector space, or the PC roll-
ing over to 0x000000 after reaching the end of imple-
mented program memory space. Execution of a GOTO
instruction to this vector space will also generate an
address error trap.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157). Note: Interrupt flag bits get set when an Interrupt
condition occurs, regardless of the state of
its corresponding enable bit. User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
Note: Assigning a priority level of 0 to an inter-
rupt source is equivalent to disabling that
interrupt.
Note: The IPL bits become read-only whenever
the NSTDIS bit has been set to ‘1’.
dsPIC30F1010/202X
DS70000178D-page 48 2006-2014 Microchip Technology Inc.
5.1 Interrupt Priority
The user-assignable Interrupt Priority (IP<2:0>) bits for
each individual interrupt source are located in the Least
Significant 3 bits of each nibble, within the IPCx
register(s). Bit 3 of each nibble is not used and is read
as a ‘0’. These bits define the priority level assigned to
a particular interrupt by the user.
Since more than one interrupt request source may be
assigned to a specific user specified priority level, a
means is provided to assign priority within a given level.
This method is called “Natural Order Priority” and is
final.
Natural order priority is determined by the position of an
interrupt in the vector table, and only affects interrupt
operation when multiple interrupts with the same user-
assigned priority become pending at the same time.
Table 5-1 lists the interrupt numbers and interrupt
sources for the dsPIC DSC devices and their
associated vector numbers.
The ability for the user to assign every interrupt to one
of seven priority levels implies that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority. The INT0 (external interrupt
0) may be assigned to priority level 1, thus giving it a
very low effective priority.
TABLE 5-1: dsPIC30F1010/202X
INTERRUPT VECTOR TABLE
Note: The user selectable priority levels start at
0, as the lowest priority, and level 7, as the
highest priority.
Note 1: The natural order priority scheme has 0
as the highest priority and 53 as the
lowest priority.
2: The natural order priority number is the
same as the INT number.
INT
Number Vector
Number Interrupt Source
Highest Natural Order Priority
0 8 INT0 – External Interrupt 0
1 9 IC1 – Input Capture 1
2 10 OC1 – Output Compare 1
3 11 T1 – Timer 1
4 12 Reserved
5 13 OC2 – Output Compare 2
6 14 T2 – Timer 2
7 15 T3 – Timer 3
8 16 SPI1
9 17 U1RX – UART1 Receiver
10 18 U1TX – UART1 Transmitter
11 19 ADC – ADC Convert Done
12 20 NVM – NVM Write Complete
13 21 SI2C – I2C™ Slave Event
14 22 MI2C – I2C Master Event
15 23 Reserved
16 24 INT1 – External Interrupt 1
17 25 INT2 – External Interrupt 2
18 26 PWM Special Event Trigger
19 27 PWM Gen#1
20 28 PWM Gen#2
21 29 PWM Gen#3
22 30 PWM Gen#4
23 31 Reserved
24 32 Reserved
25 33 Reserved
26 34 Reserved
27 35 CN – Input Change Notification
28 36 Reserved
29 37 Analog Comparator 1
30 38 Analog Comparator 2
31 39 Analog Comparator 3
32 40 Analog Comparator 4
33 41 Reserved
34 42 Reserved
35 43 Reserved
36 44 Reserved
37 45 ADC Pair 0 Conversion Done
38 46 ADC Pair 1 Conversion Done
39 47 ADC Pair 2 Conversion Done
40 48 ADC Pair 3 Conversion Done
41 49 ADC Pair 4 Conversion Done
42 50 ADC Pair 5 Conversion Done
43 51 Reserved
44 52 Reserved
45-53 53-61 Reserved
Lowest Natural Order Priority
2006-2014 Microchip Technology Inc. DS70000178D-page 49
dsPIC30F1010/202X
5.2 Reset Sequence
A Reset is not a true exception, because the interrupt
controller is not involved in the Reset process. The pro-
cessor initializes its registers in response to a Reset,
which forces the PC to zero. The processor then begins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory loca-
tion, immediately followed by the address target for the
GOTO instruction. The processor executes the GOTO to
the specified address and then begins operation at the
specified target (start) address.
5.2.1 RESET SOURCES
In addition to External Reset and Power-on Reset
(POR), there are 6 sources of error conditions which
‘trap’ to the Reset vector.
Watchdog Time-out:
The watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.
Uninitialized W Register Trap:
An attempt to use an uninitialized W register as
an Address Pointer will cause a Reset.
Illegal Instruction Trap:
Attempted execution of any unused opcodes will
result in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
Trap Lockout:
Occurrence of multiple Trap conditions
simultaneously will cause a Reset.
5.3 Traps
Traps can be considered as non-maskable interrupts
indicating a software or hardware error, which adhere
to a predefined priority as shown in Figure 5-1. They
are intended to provide the user a means to correct
erroneous operation during debug and when operating
within the application.
Note that many of these trap conditions can only be
detected when they occur. Consequently, the question-
able instruction is allowed to complete prior to trap
exception processing. If the user chooses to recover
from the error, the result of the erroneous action that
caused the trap may have to be corrected.
There are 8 fixed priority levels for traps: Level 8
through Level 15, which implies that the IPL3 is always
set during processing of a trap.
If the user is not currently executing a trap, and he sets
the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all
interrupts are disabled, but traps can still be processed.
5.3.1 TRAP SOURCES
The following traps are provided with increasing prior-
ity. However, since all traps can be nested, priority has
little effect.
Math Error Trap:
The Math Error trap executes under the following four
circumstances:
1. Should an attempt be made to divide by zero,
the divide operation will be aborted on a cycle
boundary and the trap taken.
2. If enabled, a Math Error trap will be taken when
an arithmetic operation on either accumulator A
or B causes an overflow from bit 31 and the
accumulator guard bits are not utilized.
3. If enabled, a Math Error trap will be taken when
an arithmetic operation on either accumulator A
or B causes a catastrophic overflow from bit 39
and all saturation is disabled.
4. If the shift amount specified in a shift instruction
is greater than the maximum allowed shift
amount, a trap will occur.
Note: If the user does not intend to take correc-
tive action in the event of a Trap Error con-
dition, these vectors must be loaded with
the address of a default handler that sim-
ply contains the RESET instruction. If, on
the other hand, one of the vectors contain-
ing an invalid address is called, an
address error trap is generated.
eserv or Intcrm a Vector menu ector menu \ actor Reserved Vector eserv ector Intcrm a Vector
dsPIC30F1010/202X
DS70000178D-page 50 2006-2014 Microchip Technology Inc.
Address Error Trap:
This trap is initiated when any of the following
circumstances occurs:
1. A misaligned data word access is attempted.
2. A data fetch from our unimplemented data
memory location is attempted.
3. A data access of an unimplemented program
memory location is attempted.
4. An instruction fetch from vector space is
attempted.
5. Execution of a “BRA #literal” instruction or a
GOTO #literal” instruction, where literal
is an unimplemented program memory address.
6. Executing instructions after modifying the PC to
point to unimplemented program memory
addresses. The PC may be modified by loading
a value into the stack and executing a RETURN
instruction.
Stack Error Trap:
This trap is initiated under the following conditions:
1. The Stack Pointer is loaded with a value which
is greater than the (user-programmable) limit
value written into the SPLIM register (stack
overflow).
2. The Stack Pointer is loaded with a value which
is less than 0x0800 (simple stack underflow).
Oscillator Fail Trap:
This trap is initiated if the external oscillator fails and
operation becomes reliant on an internal RC backup.
5.3.2 HARD AND SOFT TRAPS
It is possible that multiple traps can become active
within the same cycle (e.g., a misaligned word stack
write to an overflowed address). In such a case, the
fixed priority shown in Figure 5-1 is implemented,
which may require the user to check if other traps are
pending, in order to completely correct the fault.
‘Soft’ traps include exceptions of priority level 8 through
level 11, inclusive. The arithmetic error trap (level 11)
falls into this category of traps.
‘Hard’ traps include exceptions of priority level 12
through level 15, inclusive. The address error (level
12), stack error (level 13) and oscillator error (level 14)
traps fall into this category.
Each hard trap that occurs must be acknowledged
before code execution of any type may continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, acknowledged, or is being processed,
a hard trap conflict will occur.
The device is automatically Reset in a hard trap conflict
condition. The TRAPR Status bit (RCON<15>) is set
when the Reset occurs, so that the condition may be
detected in software.
FIGURE 5-1: TRAP VECTORS
Note: In the MAC class of instructions, wherein
the data space is split into X and Y data
space, unimplemented X space includes
all of Y space, and unimplemented Y
space includes all of X space.
Address Error Trap Vector
Oscillator Fail Trap Vector
Stack Error Trap Vector
Reserved Vector
Math Error Trap Vector
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
Interrupt 52 Vector
Interrupt 53 Vector
Math Error Trap Vector
Decreasing
Priority
0x000000
0x000014
Reserved
Stack Error Trap Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
Interrupt 52 Vector
Interrupt 53 Vector
IVT
AIVT
0x000080
0x00007E
0x0000FE
Reserved
0x000094
Reset - GOTO Instruction
Reset - GOTO Address 0x000002
Reserved 0x000082
0x000084
0x000004
Reserved Vector
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dsPIC30F1010/202X
5.4 Interrupt Sequence
All interrupt event flags are sampled in the beginning of
each instruction cycle by the IFSx registers. A pending
interrupt request (IRQ) is indicated by the flag bit being
equal to a ‘1’ in an IFSx register. The IRQ will cause an
interrupt to occur if the corresponding bit in the interrupt
enable (IECx) register is set. For the remainder of the
instruction cycle, the priorities of all pending interrupt
requests are evaluated.
If there is a pending IRQ with a priority level greater
than the current processor priority level in the IPL bits,
the processor will be interrupted.
The processor then stacks the current Program
Counter and the low byte of the processor STATUS
Register (SRL), as shown in Figure 5-2. The low byte
of the STATUS register contains the processor priority
level at the time, prior to the beginning of the interrupt
cycle. The processor then loads the priority level for
this interrupt into the STATUS register. This action will
disable all lower priority interrupts until the completion
of the Interrupt Service Routine (ISR).
FIGURE 5-2: INTERRUPT STACK
FRAME
The RETFIE (Return from Interrupt) instruction will
unstack the Program Counter and status registers to
return the processor to its state prior to the interrupt
sequence.
5.5 Alternate Vector Table
In Program Memory, the IVT is followed by the AIVT, as
shown in Figure 5-1. Access to the Alternate Vector
Table is provided by the ALTIVT bit in the INTCON2
register. If the ALTIVT bit is set, all interrupt and excep-
tion processes will use the alternate vectors instead of
the default vectors. The alternate vectors are organized
in the same manner as the default vectors. The AIVT
supports emulation and debugging efforts by providing
a means to switch between an application and a sup-
port environment, without requiring the interrupt vec-
tors to be reprogrammed. This feature also enables
switching between applications for evaluation of
different software algorithms at run time.
If the AIVT is not required, the program memory allo-
cated to the AIVT may be used for other purposes.
AIVT is not a protected section and may be freely
programmed by the user.
5.6 Fast Context Saving
A context saving option is available using shadow reg-
isters. Shadow registers are provided for the DC, N,
OV, Z and C bits in SR, and the registers W0 through
W3. The shadows are only one level deep. The shadow
registers are accessible using the PUSH.S and POP.S
instructions only.
When the processor vectors to an interrupt, the
PUSH.S instruction can be used to store the current
value of the aforementioned registers into their
respective shadow registers.
If an ISR of a certain priority uses the PUSH.S and
POP.S instructions for fast context saving, then a
higher priority ISR should not include the same instruc-
tions. Users must save the key registers in software
during a lower priority interrupt, if the higher priority ISR
uses fast context saving.
5.7 External Interrupt Requests
The interrupt controller supports three external inter-
rupt request signals, INT0-INT2. These inputs are edge
sensitive; they require a low-to-high or a high-to-low
transition to generate an interrupt request. The INT-
CON2 register has three bits, INT0EP-INT2EP, that
select the polarity of the edge detection circuitry.
5.8 Wake-up from Sleep and Idle
The interrupt controller may be used to wake-up the
processor from either Sleep or Idle modes, if Sleep or
Idle mode is active when the interrupt is generated.
If an enabled interrupt request of sufficient priority is
received by the interrupt controller, then the standard
interrupt request is presented to the processor. At the
same time, the processor will wake-up from Sleep or
Idle and begin execution of the Interrupt Service
Routine needed to process the interrupt request.
Note 1: The user can always lower the priority
level by writing a new value into SR. The
Interrupt Service Routine must clear the
interrupt flag bits in the IFSx register
before lowering the processor interrupt
priority, in order to avoid recursive
interrupts.
2: The IPL3 bit (CORCON<3>) is always
clear when interrupts are being pro-
cessed. It is set only during execution of
traps.
<Free Word>
015
W15 (before CALL)
W15 (after CALL)
Stack Grows Towards
Higher Address
PUSH : [W15++]
POP : [--W15]
0x0000
PC<15:0>
SRL IPL3 PC<22:16>
dsPIC30F1010/202X
DS70000178D-page 52 2006-2014 Microchip Technology Inc.
REGISTER 5-1: INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
SFTACERR DIV0ERR MATHERR ADDRERR STKERR OSCFAIL
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 NSTDIS: Interrupt Nesting Disable bit
1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
bit 14 OVAERR: Accumulator A Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator A
0 = Trap was not caused by overflow of Accumulator A
bit 13 OVBERR: Accumulator B Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator B
0 = Trap was not caused by overflow of Accumulator B
bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Enable bit
1 = Trap was caused by catastrophic overflow of Accumulator A
0 = Trap was not caused by catastrophic overflow of Accumulator A
bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Enable bit
1 = Trap was caused by catastrophic overflow of Accumulator B
0 = Trap was not caused by catastrophic overflow of Accumulator B
bit 10 OVATE: Accumulator A Overflow Trap Enable bit
1 = Trap overflow of Accumulator A
0 = Trap disabled
bit 9 OVBTE: Accumulator B Overflow Trap Enable bit
1 = Trap overflow of Accumulator B
0 = Trap disabled
bit 8 COVTE: Catastrophic Overflow Trap Enable bit
1 = Trap on catastrophic overflow of Accumulator A or B enabled
0 = Trap disabled
bit 7 SFTACERR: Shift Accumulator Error Status bit
1 = Math error trap was caused by an invalid accumulator shift
0 = Math error trap was not caused by an invalid accumulator shift
bit 6 DIV0ERR: Arithmetic Error Status bit
1 = Math error trap was caused by a divided by zero
0 = Math error trap was not caused by an invalid accumulator shift
bit 5 Unimplemented: Read as ‘0
bit 4 MATHERR: Arithmetic Error Status bit
1 = Overflow trap has occurred
0 = Overflow trap has not occurred
bit 3 ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred
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dsPIC30F1010/202X
bit 2 STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred
0 = Stack error trap has not occurred
bit 1 OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred
bit 0 Unimplemented: Read as ‘0
REGISTER 5-1: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)
dsPIC30F1010/202X
DS70000178D-page 54 2006-2014 Microchip Technology Inc.
REGISTER 5-2: INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0
ALTIVT DISI — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
INT2EP INT1EP INT0EP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit
1 = Use alternate vector table
0 = Use standard (default) vector table
bit 14 DISI: DISI Instruction Status bit
1 = DISI instruction is active
0 = DISI instruction is not active
bit 13-3 Unimplemented: Read as ‘0
bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
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dsPIC30F1010/202X
REGISTER 5-3: IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
T3IF T2IF OC2IF T1IF OC1IF IC1IF INT0IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0
bit 14 MI2CIF: I2C Master Events Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13 SI2CIF: I2C Slave Events Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12 NVMIF: Nonvolatile Memory Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 11 ADIF: ADC Conversion Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10 U1TXIF: UART1 Transmitter Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 9 U1RXIF: UART1 Receiver Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8 SPI1IF: SPI1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7 T3IF: Timer3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6 T2IF: Timer2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4 Unimplemented: Read as ‘0
bit 3 T1IF: Timer1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
dsPIC30F1010/202X
DS70000178D-page 56 2006-2014 Microchip Technology Inc.
bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0 INT0IF: External Interrupt 0 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
REGISTER 5-3: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)
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dsPIC30F1010/202X
REGISTER 5-4: IFS1: INTERRUPT FLAG STATUS REGISTER 1
R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0
AC3IF AC2IF AC1IF — CNIF — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWM4IF PWM3IF PWM2IF PWM1IF PSEMIF INT2IF INT1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 AC3IF: Analog Comparator #3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 14 AC2IF: Analog Comparator #2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13 AC1IF: Analog Comparator #1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12 Unimplemented: Read as ‘0
bit 11 CNIF: Input Change Notification Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10-7 Unimplemented: Read as ‘0
bit 6 PWM4IF: Pulse Width Modulation Generator #4 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5 PWM3IF: Pulse Width Modulation Generator #3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4 PWM2IF: Pulse Width Modulation Generator #2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3 PWM1IF: Pulse Width Modulation Generator #1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2 PSEMIF: PWM Special Event Match Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1 INT2IF: External Interrupt 2 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0 INT1IF: External Interrupt 1 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
dsPIC30F1010/202X
DS70000178D-page 58 2006-2014 Microchip Technology Inc.
REGISTER 5-5: IFS2: INTERRUPT FLAG STATUS REGISTER 2
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-00 R/W-0
ADCP5IF ADCP4IF ADCP3IF
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0
ADCP2IF ADCP1IF ADCP0IF — — —AC4IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0
bit 10 ADCP5IF: ADC Pair 5 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 9 ADCP4IF: ADC Pair 4 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8 ADCP3IF: ADC Pair 3 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7 ADCP2IF: ADC Pair 2 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6 ADCP1IF: ADC Pair 1 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5 ADCP0IF: ADC Pair 0 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4-1 Unimplemented: Read as ‘0
bit 0 AC4IF: Analog Comparator #4 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
2006-2014 Microchip Technology Inc. DS70000178D-page 59
dsPIC30F1010/202X
REGISTER 5-6: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
T3IE T2IE OC2IE T1IE OC1IE IC1IE INT0IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0
bit 14 MI2CIE: I2C Master Events Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 13 SI2CIE: I2C Slave Events Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 12 NVMIE: Nonvolatile Memory Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 11 ADIE: ADC Conversion Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 10 U1TXIE: UART1 Transmitter Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 9 U1RXIE: UART1 Receiver Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 8 SPI1IE: SPI1 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 7 T3IE: Timer3 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 6 T2IE: Timer2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 5 OC2IE: Output Compare Channel 2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 4 Unimplemented: Read as ‘0
bit 3 T1IE: Timer1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
dsPIC30F1010/202X
DS70000178D-page 60 2006-2014 Microchip Technology Inc.
bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 0 INT0IE: External Interrupt 0 Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
REGISTER 5-6: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)
2006-2014 Microchip Technology Inc. DS70000178D-page 61
dsPIC30F1010/202X
REGISTER 5-7: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0
AC3IE AC2IE AC1IE — CNIE — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWM4IE PWM3IE PWM2IE PWM1IE PSEMIE INT2IE INT1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 AC3IE: Analog Comparator #3 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 14 AC2IE: Analog Comparator #2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 13 AC1IE: Analog Comparator #1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 12 Unimplemented: Read as ‘0
bit 11 CNIE: Input Change Notification Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 10-7 Unimplemented: Read as ‘0
bit 6 PWM4IE: Pulse Width Modulation Generator #4 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 5 PWM3IE: Pulse Width Modulation Generator #3 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 4 PWM2IE: Pulse Width Modulation Generator #2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 3 PWM1IE: Pulse Width Modulation Generator #1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 2 PSEMIE: PWM Special Event Match Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 1 INT2IE: External Interrupt 2 Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 0 INT1IE: External Interrupt 1 Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
dsPIC30F1010/202X
DS70000178D-page 62 2006-2014 Microchip Technology Inc.
REGISTER 5-8: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
ADCP5IE ADCP4IE ADCP3IE
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0
ADCP2IE ADCP1IE ADCP0IE — — —AC4IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0
bit 10 ADCP5IE: ADC Pair 5 Conversion done Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 9 ADCP4IE: ADC Pair 4 Conversion done Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 8 ADCP3IE: ADC Pair 3 Conversion done Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 7 ADCP2IE: ADC Pair 2 Conversion done Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 6 ADCP1IE: ADC Pair 1 Conversion done Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 5 ADCP0IE: ADC Pair 0 Conversion done Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 4-1 Unimplemented: Read as ‘0
bit 0 AC4IE: Analog Comparator #4 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
2006-2014 Microchip Technology Inc. DS70000178D-page 63
dsPIC30F1010/202X
REGISTER 5-9: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
T1IP<2:0> — OC1IP<2:0>
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
IC1IP<2:0> — INT0IP<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0
bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0
bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0
bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0
bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
dsPIC30F1010/202X
DS70000178D-page 64 2006-2014 Microchip Technology Inc.
REGISTER 5-10: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
T3IP<2:0> — T2IP<2:0>
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
—OC2IP<2:0> — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0
bit 14-12 T3IP<2:0>: Timer3 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0
bit 10-8 T2IP<2:0>: Timer2 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0
bit 6-4 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as ‘0
2006-2014 Microchip Technology Inc. DS70000178D-page 65
dsPIC30F1010/202X
REGISTER 5-11: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
ADIP<2:0> — U1TXIP<2:0>
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
U1RXIP<2:0> — SPI1IP<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0
bit 14-12 ADIP<2:0>: ADC Conversion Complete Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0
bit 10-8 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0
bit 6-4 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0
bit 2-0 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
dsPIC30F1010/202X
DS70000178D-page 66 2006-2014 Microchip Technology Inc.
REGISTER 5-12: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0
—MI2CIP<2:0>
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
—SI2CIP<2:0>— NVMIP<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0
bit 10-8 MI2CIP<2:0>: I2C Master Events Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0
bit 6-4 SI2CIP<2:0>: I2C Slave Events Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0
bit 2-0 NVMIP<2:0>: Nonvolatile Memory Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
2006-2014 Microchip Technology Inc. DS70000178D-page 67
dsPIC30F1010/202X
REGISTER 5-13: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
PWM1IP<2:0> — PSEMIP<2:0>
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
INT2IP<2:0> — INT1IP<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0
bit 14-12 PWM1IP<2:0>: PWM Generator #1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0
bit 10-8 PSEMIP<2:0>: PWM Special Event Match Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0
bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0
bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
dsPIC30F1010/202X
DS70000178D-page 68 2006-2014 Microchip Technology Inc.
REGISTER 5-14: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0
— PWM4IP<2:0>
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
PWM3IP<2:0> — PWM2IP<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0
bit 10-8 PWM4IP<2:0>: PWM Generator #4 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0
bit 6-4 PWM3IP<2:0>: PWM Generator #3 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0
bit 2-0 PWM2IP<2:0>: PWM Generator #2 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
2006-2014 Microchip Technology Inc. DS70000178D-page 69
dsPIC30F1010/202X
REGISTER 5-15: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
—CNIP<2:0> — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0
bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11-0 Unimplemented: Read as ‘0
dsPIC30F1010/202X
DS70000178D-page 70 2006-2014 Microchip Technology Inc.
REGISTER 5-16: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
AC3IP<2:0> — AC2IP<2:0>
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
AC1IP<2:0> — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0
bit 14-12 AC3IP<2:0>: Analog Comparator 3 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0
bit 10-8 AC2IP<2:0>: Analog Comparator 2 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0
bit 6-4 AC1IP<2:0>: Analog Comparator 1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as ‘0