TPS54060 Datasheet by Texas Instruments

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C033
V = 12 V
V = 3.3 V
ƒ = 500 kHz
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sw
PH
VIN
GND
BOOT
VSENSE
COMP
TPS54060
EN
RT /CLK
SS /TR
PWRGD
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TPS54060
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TPS54060 0.5-A, 60-V Step Down DC-DC Converter with Eco-Mode™
1 Features 3 Description
The TPS54060 device is a 60-V, 0.5-A, step-down
1 3.5-V to 60-V Input Voltage Range regulator with an integrated high-side MOSFET.
• 200-mHigh-Side MOSFET Current-mode control provides simple external
High Efficiency at Light Loads with a Pulse compensation and flexible component selection. A
Skipping Eco-Mode™ low ripple pulse skip mode reduces the no load,
regulated output supply current to 116 μA. Using the
• 116-μA Operating Quiescent Current enable pin, shutdown supply current is reduced to 1.3
• 1.3-μA Shutdown Current μA, when the enable pin is low.
100-kHz to 2.5-MHz Switching Frequency VIN undervoltage lockout is internally set at 2.5 V, but
Synchronizes to External Clock can be increased using the enable pin. The output
Adjustable Slow Start and Sequencing voltage startup ramp is controlled by the slow start
pin that can also be configured for
UV and OV Power Good Output sequencing/tracking. An open-drain power good
Adjustable UVLO Voltage and Hysteresis signal indicates the output is within 94% to 107% of
0.8-V Internal Voltage Reference its nominal voltage.
10-Pin HVSSOP With PowerPAD™ Package and A wide switching frequency range allows efficiency
3-mm × 3-mm 10-Pin VSON Package and external component size to be optimized.
Supported by WEBENCH™ and SwitcherPro™ Frequency fold back and thermal shutdown protects
Software Tool the part during an overload condition.
The TPS54060 is available in 10-pin thermally
2 Applications enhanced HVSSOP PowerPAD™ package and 10-
pin 3-mm × 3-mm VSON package.
12-V, 24-V, and 48-V Industrial and Commercial
Low Power Systems Device Information(1)
Aftermarket Auto Accessories: Video, GPS, PART NUMBER PACKAGE BODY SIZE (NOM)
Entertainment VSON (10) 3.00 mm × 3.00 mm
TPS54060 HVSSOP (10) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic Efficiency vs Load Current
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
7.2 Functional Block Diagram ....................................... 12
1 Features.................................................................. 17.3 Feature Description................................................. 12
2 Applications ........................................................... 17.4 Device Functional Modes........................................ 20
3 Description ............................................................. 18 Application and Implementation ........................ 22
4 Revision History..................................................... 28.1 Application Information............................................ 22
5 Pin Configuration and Functions......................... 38.2 Typical Applications ............................................... 30
6 Specifications......................................................... 49 Power Supply Recommendations...................... 40
6.1 Absolute Maximum Ratings ..................................... 410 Layout................................................................... 41
6.2 ESD Ratings.............................................................. 410.1 Layout Guidelines ................................................. 41
6.3 Recommended Operating Conditions....................... 410.2 Layout Example .................................................... 41
6.4 Thermal Information.................................................. 511 Device and Documentation Support ................. 42
6.5 Electrical Characteristics........................................... 511.1 Device Support...................................................... 42
6.6 Timing Resistor and External Clock (RT/CLK Pin)
Timing Requirements................................................. 611.2 Documentation Support ........................................ 42
6.7 Timing Resistor and External Clock (RT/CLK PIN) 11.3 Trademarks........................................................... 42
Switching Characteristics........................................... 611.4 Electrostatic Discharge Caution............................ 42
6.8 Typical Characteristics.............................................. 711.5 Glossary................................................................ 42
7 Detailed Description............................................ 11 12 Mechanical, Packaging, and Orderable
7.1 Overview ................................................................. 11 Information ........................................................... 42
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2014) to Revision C Page
Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.................................................................................................. 1
Changes from Revision A (July 2010) to Revision B Page
Deleted SWIFT from the data sheet Title and Features......................................................................................................... 1
Changes from Original (January 2009) to Revision A Page
Added the DRC package option to the Features and Description. ........................................................................................ 1
Added the DRC Pin Configuration.......................................................................................................................................... 3
Replaced the PACKAGE DISSIPATION RATINGS table with the Thermal Information Table ............................................. 5
Updated Figure 63................................................................................................................................................................ 39
Added Figure 64................................................................................................................................................................... 40
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{9 TEXAS INSTRUMENTS
PH
GND
COMP
VSENSE
BOOT
VIN
EN
SS/TR
1
2
3
4
10
9
8
7
4
PWRGDRT/CLK 6
5
Thermal
Pad
(11)
PH
GND
COMP
VSENSE
BOOT
VIN
EN
SS/TR
1
2
3
4
10
9
8
7
4
PWRGDRT/CLK 6
5
Thermal
Pad
(11)
TPS54060
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5 Pin Configuration and Functions
DGQ Package
10-Pin VSSOP
Top View
DRC Package
10-Pin VSON
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
BOOT 1 I minimum required by the integrated gate driver for the high-side power MOSFET, the output is forced to
switch off until the capacitor is refreshed.
Error amplifier output and input to the output switch current comparator. Connect frequency compensation
COMP 8 I components to this pin.
Enable pin, internal pull-up current source. Pull below 1.2V to disable. Float to enable. Adjust the input
EN 3 I undervoltage lockout with resistor divider.
GND 9 – Ground
PH 10 O The source of the internal high-side power MOSFET.
Thermal pad 11 GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.
An open drain output, asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage or
PWRGD 6 O EN shut down.
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,
RT/CLK 5 I a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and
the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-
enabled and the mode returns to a resistor set function.
Slow-start and Tracking. An external capacitor connected to this pin sets the output rise time. Since the
SS/TR 4 I voltage on this pin overrides the internal reference, it can be used for tracking and sequencing.
VIN 2 I Input supply voltage, 3.5 V to 60 V.
VSENSE 7 I Inverting node of the transconductance (gm) error amplifier.
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6 Specifications
6.1 Absolute Maximum Ratings(1)
Over operating temperature range (unless otherwise noted).
MIN MAX UNIT
VIN –0.3 65
EN –0.3 5
VSENSE –0.3 3
COMP –0.3 3
PWRGD –0.3 6
Voltage V
SS/TR –0.3 3
RT/CLK –0.3 3.6
BOOT-PH –0.3 8
PH –0.6 65
PH, 10-ns Transient –2 65
Voltage Thermal PAD to GND ±200 mV
Difference
EN 100 μA
BOOT 100 mA
Source current VSENSE 10 μA
PH Current Limit A
RT/CLK 100 μA
VIN Current Limit A
COMP 100 μA
Sink current PWRGD 10 mA
SS/TR 200 μA
Operating junction temperature –40 150 °C
Storage temperature –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply input voltage, VVIN 3.5 60 V
Output voltage, VO0.8 57 V
Output current, IO0 0.5 A
Operating junction temperature, TJ-40 150 °C
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6.4 Thermal Information
TPS54060
THERMAL METRIC(1)(2)(2) DGQ (VSSOP) DRC (VSON) UNIT
10 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance (standard board) 62.5 40 °C/W
RθJA Junction-to-ambient thermal resistance (custom board) (3) 57 56.5 °C/W
ψJT Junction-to-top characterization parameter 1.7 0.6 °C/W
ψJB Junction-to-board characterization parameter 20.1 7.5 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 83 65 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance 21 7.8 °C/W
RθJB Junction-to-board thermal resistance 28 8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.
(3) Test boards conditions:
(a) 3 inches x 3 inches, 2 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground plane, bottom layer
(d) 6 thermal vias (13mil) located under the device package
6.5 Electrical Characteristics
TJ= –40°C to 150°C, VIN = 3.5 to 60 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 3.5 60 V
Internal undervoltage lockout No voltage hysteresis, rising and falling 2.5 V
threshold
Shutdown supply current EN = 0 V, 25°C, 3.5 V VIN 60 V 1.3 4
μA
Operating : nonswitching supply VSENSE = 0.83 V, VIN = 12 V, 25°C 116 136
current
ENABLE AND UVLO (EN PIN)
Enable threshold voltage No voltage hysteresis, rising and falling, 25°C 0.9 1.25 1.55 V
Enable threshold +50 mV –3.8
Input current μA
Enable threshold –50 mV –0.9
Hysteresis current –2.9 μA
VOLTAGE REFERENCE
TJ= 25°C 0.792 0.8 0.808
Voltage reference V
0.784 0.8 0.816
HIGH-SIDE MOSFET
VIN = 3.5 V, BOOT-PH = 3 V 300
On-resistance m
VIN = 12 V, BOOT-PH = 6 V 200 410
ERROR AMPLIFIER
Input current 50 nA
Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V 97 μS
–2 μA < ICOMP < 2 μA, VCOMP = 1 V,
Error amplifier transconductance (gM)26 μS
during slow start VVSENSE = 0.4 V
Error amplifier dc gain VVSENSE = 0.8 V 10,000 V/V
Error amplifier bandwidth 2700 kHz
Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive ±7 μA
COMP to switch current 1.9 A/V
transconductance
CURRENT LIMIT
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Electrical Characteristics (continued)
TJ= –40°C to 150°C, VIN = 3.5 to 60 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current limit threshold VIN = 12 V, TJ= 25°C 0.6 0.94 A
THERMAL SHUTDOWN
Thermal shutdown 182 °C
SLOW START AND TRACKING (SS/TR)
Charge current VSS/TR = 0.4 V 2 μA
SS/TR-to-VSENSE matching VSS/TR = 0.4 V 45 mV
SS/TR-to-reference crossover 98% nominal 1.0 V
SS/TR discharge current (overload) VSENSE = 0 V, V(SS/TR) = 0.4 V 112 μA
SS/TR discharge voltage VSENSE = 0 V 54 mV
POWER GOOD (PWRGD PIN)
VSENSE falling 92%
VSENSE rising 94%
VVSENSE VSENSE threshold VSENSE rising 109%
VSENSE falling 107%
Hysteresis VSENSE falling 2%
Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C 10 nA
On resistance I(PWRGD) = 3 mA, VSENSE < 0.79 V 50
Minimum VIN for defined output V(PWRGD) < 0.5 V, II(PWRGD) = 100 μA 0.95 1.5 V
6.6 Timing Resistor and External Clock (RT/CLK Pin) Timing Requirements
MIN TYP MAX UNIT
Minimum CLK input pulse width 40 ns
RT/CLK falling edge to PH rising edge delay 60 ns
6.7 Timing Resistor and External Clock (RT/CLK PIN) Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSW Switching frequency RT= 200 k450 581 720 kHz
Switching Frequency Range using 100 2500 kHz
RT mode
Switching frequency range using 300 2200 kHz
CLK mode
PLL lock in time Measured at 500 kHz 100 μs
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TEXAS INSTRUMENTS sou u m s / / / / / / / / f. / // // I 1 S1 0 \ \ \\ 2500 500 \\\
550
570
580
590
600
610
–50 –25 0 25 50 75 100 125 150
Switching Frequency (kHz)
560
Junction Temperature (°C) C004
0.7
0.8
0.9
1.1
–50 –25 0 25 50 75 100 125 150
Switch Current (A)
Junction Temperature (°C)
1
C003
0
125
250
375
500
–50 –25 0 25 50 75 100 125 150
Junction Temperature (°C)
Static Drain-Source On-State Resistance (mW)
BOOT-PH = 3 V
BOOT-PH = 6 V
C001
0.784
0.792
0.800
0.808
0.816
–50 –25 0 25 50 75 100 125 150
Voltage Reference (V)
Junction Temperature (°C) C002
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6.8 Typical Characteristics
Figure 1. ON Resistance vs Junction Temperature Figure 2. Voltage Reference vs Junction Temperature
Figure 3. Switch Current Limit vs Junction Temperature Figure 4. Switching Frequency vs Junction Temperature
Figure 5. Switching Frequency vs RT/CLK Resistance High Figure 6. Switching Frequency vs RT/CLK Resistance Low
Frequency Range Frequency Range
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l TEXAS INSTRUMENTS AU mu MD 73 25
–3
–2.5
–2
–1.5
–1
–50 –25 0 25 50 75 100 125 150
I ( A)
(SS/TR) μ
Junction Temperature (°C) C012
–1
–0.95
–0.9
–0.85
–0.8
–50 –25 0 25 50 75 100 125 150
I ( A)
(EN) μ
Junction Temperature (°C) C011
–4.25
–4
–3.75
–3.5
3.25
–50 –25 0 25 50 75 100 125 150
I ( A)
(EN) μ
Junction Temperature (°C) C010
10
20
30
40
–50 –25 0 25 50 75 100 125 150
gm ( A/V)μ
Junction Temperature (°C) C007
50
70
90
110
130
150
–50 –25 0 25 50 75 100 125 150
gm ( A/V)μ
Junction Temperature (°C) C008
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Typical Characteristics (continued)
Figure 7. EA Transconductance During Slow Start vs Figure 8. EA Transconductance vs Junction Temperature
Junction Temperature
Figure 9. EN Pin Voltage vs Junction Temperature Figure 10. EN Pin Current vs Junction Temperature
Figure 11. EN Pin Current vs Junction Temperature Figure 12. SS/TR Charge Current vs Junction Temperature
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l TEXAS INSTRUMENTS 100 \ 2 —‘ 140 140 —_,_./
90
100
110
120
130
140
–50 –25 0 25 50 75 100 125 150
I ( A)
(VIN) μ
Junction Temperature (°C) C017
90
100
110
120
130
140
0 20 40 60
I ( A)
(VIN) μ
Input Voltage (V) C018
0
0.5
1
1.5
2
–50 –25 0 25 50 75 100 125 150
I ( A)
(VIN) μ
Junction Temperature (°C) C015
0
0.5
1
1.5
2
0 10 20 30 40 50 60
Input Voltage (V)
I ( A)
(VIN) μ
C016
100
105
110
115
120
–50 –25 0 25 50 75 100 125 150
I ( A)
I(SS/TR) μ
Junction Temperature (°C) C013
0
20
40
60
80
100
0 0.2 0.4 0.6 0.8
V (V)
SENSE
% of Nominal fsw
C014
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Typical Characteristics (continued)
Figure 13. SS/TR Discharge Current vs Junction Figure 14. Switching Frequency vs VSENSE
Temperature
Figure 15. Shutdown Supply Current vs Junction Figure 16. Shutdown Supply Current vs Input Voltage (Vin)
Temperature
Figure 17. VIN Supply Current vs Junction Temperature Figure 18. VIN Supply Current vs Input Voltage
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0
100
200
300
400
500
0 100 200 300 400 500 600 700 800
VSENSE (mV)
Offset (mV)
C023
30
35
40
45
50
55
60
–50 –25 0 25 50 75 100 125 150
Offset (mV)
Junction Temperature (°C) C024
2
2.25
2.50
2.75
3
-50 -25 0 25 50 75 100 125 150
V (V)
I(VIN)
Junction Temperature (°C) C022
1.5
1.75
2
2.25
2.5
–50 –25 0 25 50 75 100 125 150
V (V)
I(BOOT-PH)
Junction Temperature (°C) C021
0
20
40
60
80
100
–50 –25 0 25 50 75 100 125 150
RDSON ( )W
Junction Temperature (°C) C019
85
90
95
100
105
110
115
–50 –25 0 25 50 75 100 125 150
PWRGD Threshold (% of Vref)
VSENSE Falling
VSENSE Rising
Junction Temperature (°C)
VSENSE Rising
VSENSE Falling
C020
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Typical Characteristics (continued)
Figure 19. PWRGD ON Resistance vs Junction Temperature Figure 20. PWRGD Threshold vs Junction Temperature
Figure 21. BOOT-PH UVLO vs Junction Temperature Figure 22. Input Voltage (UVLO) vs Junction Temperature
Figure 23. SS/TR TO VSENSE Offset vs VSENSE Figure 24. SS/TR TO VSENSE Offset vs Temperature
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7 Detailed Description
7.1 Overview
The TPS54060 device is a 60-V, 0.5-A, step-down (buck) regulator with an integrated high side n-channel
MOSFET. To improve performance during line and load transients the device implements a constant frequency,
current mode control which reduces output capacitance and simplifies external frequency compensation design.
The wide switching frequency of 100kHz to 2500kHz allows for efficiency and size optimization when selecting
the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin.
The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power
switch turn on to a falling edge of an external system clock.
The TPS54060 has a default VIN start up voltage of approximately 2.5V. The EN pin has an internal pull-up
current source that can be used to adjust the input voltage under voltage lockout (UVLO) threshold with two
external resistors. In addition, the pull up current provides a default condition. When the EN pin is floating the
device will operate. The operating current is 116μA when not switching and under no load. When the device is
disabled, the supply current is 1.3μA.
The integrated 200mhigh side MOSFET allows for high efficiency power supply designs capable of delivering
0.5 amperes of continuous current to a load. The TPS54060 reduces the external component count by
integrating the boot recharge diode. The bias voltage for the integrated high side MOSFET is supplied by a
capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the
high side MOSFET off when the boot voltage falls below a preset threshold. The TPS54060 can operate at high
duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8V
reference.
The TPS54060 has a power good comparator (PWRGD) which asserts when the regulated output voltage is less
than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open drain output which
deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage allowing the
pin to transition high when a pull-up resistor is used.
The TPS54060 minimizes excessive output overvoltage (OV) transients by taking advantage of the OV power
good comparator. When the OV comparator is activated, the high side MOSFET is turned off and masked from
turning on until the output voltage is lower than 107%.
The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor should be coupled to the pin to adjust the slow start time. A resistor
divider can be coupled to the pin for critical power supply sequencing requirements. The SS/TR pin is discharged
before the output powers up. This discharging ensures a repeatable restart after an over-temperature fault,
UVLO fault or a disabled condition.
The TPS54060, also, discharges the slow start capacitor during overload conditions with an overload recovery
circuit. The overload recovery circuit will slow start the output from the fault voltage to the nominal regulation
voltage once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during
startup and overcurrent fault conditions to help control the inductor current.
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4E] I, E; l
ERROR
AMPLIFIER
Boot
Charge
Boot
UVLO
UVLO
Current
Sense
Oscillator
withPLL
Frequency
Shift
Logic
And
PWMLatch
Slope
Compensation
PWM
Comparator
Minimum
Clamp
Pulse
Skip
Maximum
Clamp
Voltage
Reference
Overload
Recovery
VSENSE
SS/TR
COMP
RT/CLK
PH
BOOT
VIN
Thermal
Shutdown
EN
Enable
Comparator
Shutdown
Logic
Shutdown
Enable
Threshold
TPS54060 BlockDiagram
Logic
Shutdown
PWRGD
Shutdown
OV
GND
POWERPAD
7
4
8
5
9
11
10
1
2
3
6
UV
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7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Fixed Frequency PWM Control
The TPS54060 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output
is compared to the high side power switch current. When the power switch current reaches the level set by the
COMP voltage, the power switch is turned off. The COMP pin voltage will increase and decrease as the output
current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a
maximum level. The Eco-Mode™ is implemented with a minimum clamp on the COMP pin.
7.3.2 Slope Compensation Output Current
The TPS54060 adds a compensating ramp to the switch current signal. This slope compensation prevents sub-
harmonic oscillations. The available peak inductor current remains constant over the full duty cycle range.
7.3.3 Pulse Skip Eco-mode
The TPS54060 operates in a pulse skip Eco mode at light load currents to improve efficiency by reducing
switching and gate drive losses. The TPS54060 is designed so that if the output voltage is within regulation and
the peak switch current at the end of any switching cycle is below the pulse skipping current threshold, the
device enters Eco mode. This current threshold is the current level corresponding to a nominal COMP voltage or
500mV.
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Feature Description (continued)
When in Eco-mode, the COMP pin voltage is clamped at 500mV and the high side MOSFET is inhibited. Further
decreases in load current or in output voltage can not drive the COMP pin below this clamp voltage level.
Since the device is not switching, the output voltage begins to decay. As the voltage control loop compensates
for the falling output voltage, the COMP pin voltage begins to rise. At this time, the high side MOSFET is enabled
and a switching pulse initiates on the next switching cycle. The peak current is set by the COMP pin voltage. The
output voltage re-charges the regulated value (see Figure 25), then the peak switch current starts to decrease,
and eventually falls below the Eco mode threshold at which time the device again enters Eco mode.
For Eco mode operation, the TPS54060 senses peak current, not average or load current, so the load current
where the device enters Eco mode is dependent on the output inductor value. For example, the circuit in
Figure 50 enters Eco mode at about 20 mA of output current. When the load current is low and the output
voltage is within regulation, the device enters a sleep mode and draws only 116μA input quiescent current. The
average input current will be slightly higher than the non-switching input quiescent current because some
switching is required to keep the output voltage regulated. The average input current will vary between
applications. The internal PLL remains operating when in sleep mode. When operating at light load currents in
the pulse skip mode, the switching transitions occur synchronously with the external clock signal.
Figure 25. Pulse Skip Mode Operation
7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)
The TPS54060 has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and
PH pins to provide the gate drive voltage for the high side MOSFET. The BOOT capacitor is refreshed when the
high side MOSFET is off and the low side diode conducts. The value of this ceramic capacitor should be 0.1μF.
A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10V or higher is recommended
because of the stable characteristics overtemperature and voltage.
To improve drop out, the TPS54060 is designed to operate at 100% duty cycle as long as the BOOT to PH pin
voltage is greater than 2.1V. When the voltage from BOOT to PH drops below 2.1V, the high side MOSFET is
turned off using an UVLO circuit which allows the low side diode to conduct and refresh the charge on the BOOT
capacitor. Since the supply current sourced from the BOOT capacitor is low, the high side MOSFET can remain
on for more switching cycles than are required to refresh the capacitor, thus the effective duty cycle of the
switching regulator is high.
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: TPS54060
l TEXAS INSTRUMENTS 56 .-.....u. ...--- ._ ...-
3
3.2
3.4
3.6
3.8
4
0 0.05 0.10 0.15 0.20
Output Current (A)
Input Voltage (V)
Stop
Start
C025
4.6
4.8
5
5.2
5.4
5.6
0 0.05 0.10 0.15 0.20
Output Current (A)
Input Voltage (V)
C026
Stop
Start
TPS54060
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
www.ti.com
Feature Description (continued)
The effective duty cycle during dropout of the regulator is mainly influenced by the voltage drops across the
power MOSFET, inductor resistance, low side diode and printed circuit board resistance. During operating
conditions in which the input voltage drops and the regulator is operating in continuous conduction mode, the
high side MOSFET can remain on for 100% of the duty cycle to maintain output regulation, until the BOOT to PH
voltage falls below 2.1V.
Attention must be taken in maximum duty cycle applications which experience extended time periods with light
loads or no load. When the voltage across the BOOT capacitor falls below the 2.1V UVLO threshold, the high
side MOSFET is turned off, but there may not be enough inductor current to pull the PH pin down to recharge the
BOOT capacitor. The high side MOSFET of the regulator stops switching because the voltage across the BOOT
capacitor is less than 2.1V. The output capacitor then decays until the difference in the input voltage and output
voltage is greater than 2.1V, at which point the BOOT UVLO threshold is exceeded, and the device starts
switching again until the desired output voltage is reached. This operating condition persists until the input
voltage and/or the load current increases. It is recommended to adjust the VIN stop voltage greater than the
BOOT UVLO trigger condition at the minimum load of the application using the adjustable VIN UVLO feature with
resistors on the EN pin.
The start and stop voltages for typical 3.3V and 5V output applications are shown in Figure 26 and Figure 27.
The voltages are plotted versus load current. The start voltage is defined as the input voltage needed to regulate
the output within 1%. The stop voltage is defined as the input voltage at which the output drops by 5% or stops
switching.
During high duty cycle conditions, the inductor current ripple increases while the BOOT capacitor is being
recharged resulting in an increase in ripple voltage on the output. This is due to the recharge time of the boot
capacitor being longer than the typical high side off time when switching occurs every cycle.
Figure 26. 3.3-V Start/Stop Voltage Figure 27. 5.0-V Start/Stop Voltage
7.3.5 Error Amplifier
The TPS54060 has a transconductance amplifier for the error amplifier. The error amplifier compares the
VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8V voltage reference. The
transconductance (gm) of the error amplifier is 97μA/V during normal operation. During the slow start operation,
the transconductance is a fraction of the normal operating gm. When the voltage of the VSENSE pin is below
0.8V and the device is regulating using the SS/TR voltage, the gm is 25μA/V.
The frequency compensation components (capacitor, series resistor and capacitor) are added to the COMP pin
to ground.
7.3.6 Voltage Reference
The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output
of a temperature stable bandgap circuit.
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Product Folder Links: TPS54060
l TEXAS INSTRUMENTS Tek-uzsokS/s 1 Aqu [ T 1 W W + Iv cm 2.00V ChZ 2.00V M20.0ms Ch1J' Louv Ioov 2.oov
EN
SS/TR
VSENSE
VOUT
Tss(ms) Iss( A)
Css(nF) = Vref (V) 0.8
m´
´
TPS54060
www.ti.com
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
Feature Description (continued)
7.3.7 Slow Start/Tracking Pin (SS/TR)
The TPS54060 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as
the power-supply's reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to
ground implements a slow start time. The TPS54060 has an internal pull-up current source of 2μA that charges
the external slow start capacitor. The calculations for the slow start time (10% to 90%) are shown in Equation 1.
The voltage reference (VREF) is 0.8 V and the slow start current (ISS) is 2μA. The slow start capacitor should
remain lower than 0.47μF and greater than 0.47nF.
(1)
At power up, the TPS54060 will not start switching until the slow start pin is discharged to less than 40 mV to
ensure a proper power up, see Figure 28.
Also, during normal operation, the TPS54060 will stop switching and the SS/TR must be discharged to 40 mV,
when the VIN voltage is below the VIN UVLO, EN pin pulled below 1.25V, or a thermal shutdown event occurs.
The VSENSE voltage will follow the SS/TR pin voltage with a 45mV offset up to 85% of the internal voltage
reference. When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as
the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see
Figure 23). The SS/TR voltage will ramp linearly until clamped at 1.7V.
Figure 28. Operation of SS/TR Pin when Starting
7.3.8 Overload Recovery Circuit
The TPS54060 has an overload recovery (OLR) circuit. The OLR circuit will slow start the output from the
overload voltage to the nominal regulation voltage once the fault condition is removed. The OLR circuit will
discharge the SS/TR pin to a voltage slightly greater than the VSENSE pin voltage using an internal pull down of
100μA when the error amplifier is changed to a high voltage from a fault condition. When the fault condition is
removed, the output will slow start from the fault voltage to nominal output voltage.
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TPS54060
l TEXAS INSTRUMENTS 2500 we
RT k
sw kHz 1.0888
206033
( W) =
¦ ( )
TPS54060
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
www.ti.com
Feature Description (continued)
7.3.9 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS54060 is adjustable over a wide range from approximately 100kHz to
2500kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5V and must have a
resistor to ground to set the switching frequency. To determine the timing resistance for a given switching
frequency, use Equation 2 or the curves in Figure 29 or Figure 30. To reduce the solution size one would
typically set the switching frequency as high as possible, but tradeoffs of the supply efficiency, maximum input
voltage and minimum controllable on time should be considered.
The minimum controllable on time is typically 130ns and limits the maximum operating input voltage.
The maximum switching frequency is also limited by the frequency shift circuit. More discussion on the details of
the maximum switching frequency is located below.
(2)
Figure 29. Switching Frequency vs RT/CLK Resistance Figure 30. Switching Frequency vs RT/CLK Resistance
High Frequency Range Low Frequency Range
7.3.10 Overcurrent Protection and Frequency Shift
The TPS54060 implements current mode control which uses the COMP pin voltage to turn off the high side
MOSFET on a cycle by cycle basis. Each cycle the switch current and COMP pin voltage are compared, when
the peak switch current intersects the COMP voltage, the high side switch is turned off. During overcurrent
conditions that pull the output voltage low, the error amplifier will respond by driving the COMP pin high,
increasing the switch current. The error amplifier output is clamped internally, which functions as a switch current
limit.
To increase the maximum operating switching frequency at high input voltages the TPS54060 implements a
frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on
VSENSE pin.
The device implements a digital frequency shift to enable synchronizing to an external clock during normal
startup and fault conditions. Since the device can only divide the switching frequency by 8, there is a maximum
input voltage limit in which the device operates and still have frequency shift protection.
During short-circuit events (particularly with high input voltage applications), the control loop has a finite minimum
controllable on time and the output has a low voltage. During the switch on time, the inductor current ramps to
the peak current limit because of the high input voltage and minimum on time. During the switch off time, the
inductor would normally not have enough off time and output voltage for the inductor to ramp down by the ramp
up amount. The frequency shift effectively increases the off time allowing the current to ramp down.
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TPS54060
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SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
Feature Description (continued)
7.3.11 Power Good (PWRGD Pin)
The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal
voltage reference the PWRGD pin is de-asserted and the pin floats. It is recommended to use a pull-up resistor
between the values of 10 and 100kto a voltage source that is 5.5V or less. The PWRGD is in a defined state
once the VIN input voltage is greater than 1.5V but with reduced current sinking capability. The PWRGD will
achieve full current sinking capability as VIN input voltage approaches 3V.
The PWRGD pin is pulled low when the VSENSE is lower than 92% or greater than 109% of the nominal internal
reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin
pulled low.
7.3.12 Overvoltage Transient Protection
The TPS54060 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot
when recovering from output fault conditions or strong unload transients on power supply designs with low value
output capacitance. For example, when the power supply output is overloaded the error amplifier compares the
actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal
reference voltage for a considerable time, the output of the error amplifier will respond by clamping the error
amplifier output to a high voltage. Thus, requesting the maximum output current. Once the condition is removed,
the regulator output rises and the error amplifier output transitions to the steady state duty cycle. In some
applications, the power supply output voltage can respond faster than the error amplifier output can respond, this
actuality leads to the possibility of an output overshoot. The OVTP feature minimizes the output overshoot, when
using a low value output capacitor, by implementing a circuit to compare the VSENSE pin voltage to OVTP
threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP
threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output
overshoot. When the VSENSE voltage drops lower than the OVTP threshold, the high side MOSFET is allowed
to turn on at the next clock cycle.
7.3.13 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 182°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 182°C, the device reinitiates the power up sequence
by discharging the SS/TR pin.
7.3.14 Small Signal Model for Loop Response
Figure 31 shows an equivalent model for the TPS54060 control loop which can be modeled in a circuit simulation
program to check frequency response and dynamic load response. The error amplifier is a transconductance
amplifier with a gmEA of 97 μA/V. The error amplifier can be modeled using an ideal voltage controlled current
source. The resistor Roand capacitor Comodel the open loop gain and frequency response of the amplifier. The
1mV ac voltage source between the nodes a and b effectively breaks the control loop for the frequency response
measurements. Plotting c/a shows the small signal response of the frequency compensation. Plotting a/b shows
the small signal response of the overall loop. The dynamic loop response can be checked by replacing RLwith a
current source with the appropriate load step amplitude and step rate in a time domain analysis. This equivalent
model is only valid for continuous conduction mode designs.
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TPS54060
VO
RESR
COUT
RL
VC
gmps
fp
fz
Adc
VSENSE
COMP
VO
R1
R3
C1
C2 R2
CO RO gmea
97 A/Vm
0.8V
PowerStage
gm 1.9 A/V
ps
PH
RESR
COUT
RL
b
a
c
TPS54060
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
www.ti.com
Feature Description (continued)
Figure 31. Small Signal Model for Loop Response
7.3.15 Simple Small Signal Model for Peak Current Mode Control
Figure 32 describes a simple small signal model that can be used to understand how to design the frequency
compensation. The TPS54060 power stage can be approximated to a voltage-controlled current source (duty
cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in Equation 3 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient of
the change in switch current and the change in COMP pin voltage (node c in Figure 31) is the power stage
transconductance. The gmPS for the TPS54060 is 1.9A/V. The low-frequency gain of the power stage frequency
response is the product of the transconductance and the load resistance as shown in Equation 4.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 5). The combined effect is highlighted by the dashed line in the right half of Figure 32.
As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover
frequency the same for the varying load conditions which makes it easier to design the frequency compensation.
The type of output capacitor chosen determines whether the ESR zero has a profound effect on the frequency
compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number frequency
compensation components needed to stabilize the overall loop because the phase margin increases from the
ESR zero at the lower frequencies (see Equation 6).
Figure 32. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
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Product Folder Links: TPS54060
_______________________
Vref
VO
R1
R3
C1
C2
R2 CO
RO
gmea COMP
VSENSE
Type2A Type2B Type1
C2
R3
C1
Z
OUT ESR
1
C R 2
=
´ ´ p
f
P
OUT L
1
f
C R 2
=
´ ´ p
ps L
Adc = gm R´
Z
OUT
C
P
s
1
2
VAdc
Vs
1
2
æ ö
+
ç ÷
p ´
è ø
= ´ æ ö
+
ç ÷
p ´
è ø
f
f
TPS54060
www.ti.com
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
Feature Description (continued)
(3)
(4)
(5)
(6)
7.3.16 Small Signal Model for Frequency Compensation
The TPS54060 uses a transconductance amplifier for the error amplifier and readily supports three of the
commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are
shown in Figure 33. Type 2 circuits most likely implemented in high bandwidth power-supply designs using low
ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum
electrolytic or tantalum capacitors.. Equation 7 and Equation 8 show how to relate the frequency response of the
amplifier to the small signal model in Figure 33. The open-loop gain and bandwidth are modeled using the RO
and COshown in Figure 33. See the application section for a design example using a Type 2A network with a
low ESR output capacitor.
Equation 7 through Equation 16 are provided as a reference for those who prefer to compensate using the
preferred methods. Those who prefer to use prescribed method use the method outlined in the application
section or use switched information.
Figure 33. Types of Frequency Compensation
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Product Folder Links: TPS54060
l TEXAS INSTRUMENTS ea gm R1 +R2 R1+R2
p ´ ´
O O
1
P2 = type 1
2 R (C2 + C )
p ´ ´
O O
1
P2 = type 2b
2 R3 | | R C
p ´ ´
O O
1
P2 = type 2a
2 R3 | | R (C2 + C )
1
Z1
2 R3 C1
=
p ´ ´
1
P1
2 Ro C1
=
p ´ ´
ea
R2
A1 = gm Ro| | R3 R1 + R2
´ ´
ea
R2
A0 = gm Ro R1 + R2
´ ´
f
f f
Z1
P1 P2
s
1
2
EA A0
s s
1 1
2 2
æ ö
+
ç ÷
p ´
è ø
= ´ æ ö æ ö
+ ´ +
ç ÷ ç ÷
p ´ p ´
è ø è ø
p ´
ea
O
gm
C = 2 BW (Hz)
ea
Aol(V/V)
Ro = gm
A0
A1
P1
Z1 P2
Aol
BW
TPS54060
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
www.ti.com
Feature Description (continued)
Figure 34. Frequency Response of the Type 2A and Type 2B Frequency Compensation
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
7.4 Device Functional Modes
The TPS54060 is designed to operate with input voltages above 3.5 V. When the VIN voltage is above the 2.5 V
typical UVLO threshold and the EN voltage is above the 1.25 V typical threshold the device is active. If the VIN
voltage falls below the typical 2.5-V UVLO threshold the device stops switching. If the EN voltage falls below the
1.25-V threshold the device stops switching and enters a shutdown mode with low supply current of 1.3 µA
typical.
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Device Functional Modes (continued)
The TPS54060 will operate in CCM when the output current is enough to keep the inductor current above 0 A at
the end of each switching period. As a non-synchronous converter it will enter DCM at low output currents when
the inductor current falls to 0 A before the end of a switching period. At very low output current the COMP
voltage will drop to the pulse skipping threshold and the device operates in a pulse-skipping Eco-mode. In this
mode the high-side MOSFET does not switch every switching period. This operating mode reduces power loss
while keeping the output voltage regulated. For more information on Eco-mode see the Pulse Skip Eco-mode
section.
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Product Folder Links: TPS54060
l TEXAS INSTRUMENTS
START STOP
HYS
V V
R1
I
-
=
EN
VIN
+
-
TPS54060
R1
R2
Ihys
I1
0.9 Am
1.25V
2.9 Am
Vout 0.8V
R1 = R2
0.8 V
-
æ ö
´ç ÷
è ø
TPS54060
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54060 device is a 60-V, 0.5-A, step-down regulator with an integrated high-side MOSFET. This device
typically converts a higher dc voltage to a lower dc voltage with a maximum available output current of 0.5 A.
Example applications are: 12-V, 24-V, and 48-V industrial, automotive and communication power systems. Use
the following design procedure to select component values for the TPS54060 device. The Excel®spreadsheet
(SLVC432) located on the product page can help on all calculations. Alternatively, use the WEBENCH software
to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a
comprehensive database of components when generating a design.
8.1.1 Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to
use 1% tolerance or better divider resistors. Start with a 10 kfor the R2 resistor and use the Equation 17 to
calculate R1. To improve efficiency at light loads consider using larger value resistors. If the values are too high
the regulator will be more susceptible to noise and voltage errors from the VSENSE input current will be
noticeable
(17)
8.1.2 Enable and Adjusting Undervoltage Lockout
The TPS54060 is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher
undervoltage lockout (UVLO), use the EN pin as shown in Figure 35 to adjust the input voltage UVLO by using
the two external resistors. Though it is not necessary to use the UVLO adjust registers, for operation it is highly
recommended to provide consistent power up behavior. The EN pin has an internal pull-up current source, I1, of
0.9μA that provides the default condition of the TPS54060 operating when the EN pin floats. Once the EN pin
voltage exceeds 1.25V, an additional 2.9μA of hysteresis, Ihys, is added. This additional current facilitates input
voltage hysteresis. Use Equation 18 to set the external hysteresis for the input voltage. Use Equation 19 to set
the input start voltage.
Figure 35. Adjustable Undervoltage Lockout (UVLO)
(18)
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Product Folder Links: TPS54060
l TEXAS INSTRUMENTS R3
SS /TR
TPS54060
EN
PWRGD
SS /TR
EN PWRGD
ENA
START ENA ENA
1
V
R2 V V V
I
R1 R3
=
-
+ -
START STOP
OUT
HYS
V V
R1 V
I
R3
-
=
+
EN
Ihys
VIN
+
-
TPS54060
R1
R2
VOUT
R3
I1
0.9 Am
2.9 Am
1.25V
ENA
START ENA
1
V
R2 V V I
R1
=
-
+
TPS54060
www.ti.com
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
Application Information (continued)
(19)
Another technique to add input voltage hysteresis is shown in Figure 36. This method may be used, if the
resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor R3
sources additional hysteresis current into the EN pin.
Figure 36. Adding Additional Hysteresis
(20)
(21)
8.1.3 Sequencing
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD
pins. The sequential method can be implemented using an open drain output of a power on reset pin of another
device. The sequential method is illustrated in Figure 37 using two TPS54060 devices. The power good is
coupled to the EN pin on the TPS54060 which will enable the second power supply once the primary supply
reaches regulation. If needed, a 1nF ceramic capacitor on the EN pin of the second power supply will provide a
1ms start up delay. Figure 38 shows the results of Figure 37.
Figure 37. Schematic for Sequential Start-Up Sequence
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Product Folder Links: TPS54060
l TEXAS INSTRUMENTS TeK 25‘0k5/é ’ 2 Afis [ T ] 1 : Ch1 1.00V chz 1.oov M2.00ms ch3.r 1.00V Ch3 2.00v C14 2.oov TeK-n 50.0kS/s 11 Acqs [ x 1 WWW + I W ch21.ouv MLooms char 1.00V
EN
TPS54160
3
SS/TR
4
PWRGD
6
EN
TPS54160
3
SS/TR4
PWRGD
6
TPS54060
TPS54060
EN1,EN2
VOUT1
VOUT2
EN1
PWRGD1
VOUT1
VOUT2
TPS54060
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www.ti.com
Application Information (continued)
Figure 38. Sequential Startup Using EN and PWRGD
Figure 39. Schematic for Ratiometric Start-Up Sequence Figure 40. Ratiometric Start-Up Using Coupled SS/TR Pins
Figure 39 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The
regulator outputs will ramp up and reach regulation at the same time. When calculating the slow start time the
pull up current source must be doubled in Equation 1.Figure 40 shows the results of Figure 39.
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Product Folder Links: TPS54060
l TEXAS INSTRUMENTS
SS/TR
TPS54060
EN
PWRGD
SS/ TR
EN
PWRGD
VOUT 1
VOUT 2
R 1
R 2
R3
R 4
TPS54060
TPS54060
www.ti.com
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
Application Information (continued)
Figure 41. Schematic for Ratiometric and Simultaneous Start-Up Sequence
Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network
of R1 and R2 shown in Figure 41 to the output of the power supply that needs to be tracked or another voltage
reference source. Using Equation 22 and Equation 23, the tracking resistors can be calculated to initiate the
Vout2 slightly before, after or at the same time as Vout1. Equation 24 is the voltage difference between Vout1
and Vout2 at the 95% of nominal output regulation.
The deltaV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to
VSENSE offset (Vssoffset) in the slow start circuit and the offset created by the pullup current source (Iss) and
tracking resistors, the Vssoffset and Iss are included as variables in the equations.
To design a ratio-metric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2
reaches regulation, use a negative number in Equation 22 through Equation 24 for deltaV. Equation 24 will result
in a positive number for applications which the Vout2 is slightly lower than Vout1 when Vout2 regulation is
achieved.
Since the SS/TR pin must be pulled below 40mV before starting after an EN, UVLO or thermal shutdown fault,
careful selection of the tracking resistors is needed to ensure the device will restart after a fault. Make sure the
calculated R1 value from Equation 22 is greater than the value calculated in Equation 25 to ensure the device
can recover from a fault.
As the SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger
as the slow start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR
pin voltage needs to be greater than 1.3V for a complete handoff to the internal voltage reference as shown in
Figure 23.
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l TEXAS INSTRUMENTS R R R x 7 x Tek 50.0kS/ls 4 Afis ] Tek 50.0kS/ls T 3 Acqs ] T cm LOUV ch; LUUV MLUDmS Ch3f LUDV cm LUUV ChZ Lnuv MLUnms ch31 Luuv LIS 2.uuv Lu 2.00V TeK-I 5n flkS/s 199 Am; I T l W + an -z— co co < ch2="" 1.00v="" mlimms="" ch="" i="" loov="">
EN
VOUT1
VOUT2
EN
VOUT1
VOUT2
EN
VOUT1
VOUT2
R1 > 2800 Vout1 180 deltaV´ - ´
deltaV = Vout1 Vout2-
VREF R1
R2 =
Vout2 + deltaV VREF
´
-
Vout2 + deltaV Vssoffset
R1 =
VREF Iss
´
TPS54060
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
www.ti.com
Application Information (continued)
(22)
(23)
(24)
(25)
Figure 42. Ratiometric Startup With Tracking Resistors Figure 43. Ratiometric Startup With Tracking Resistors
Figure 44. Simultaneous Startup With Tracking Resistor
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Skip
Shift
10 20 30 40 50 60
2500
2000
1500
1000
500
0
Switching Frequency (kHz)
Input Voltage (V) C027
( ) ( )
L OUTSC
SW shift ON IN L
(I Rdc V Vd)
div
tV I x Rhs Vd
æ ö
´ + +
ç ÷
= ´ ç ÷
- +
è ø
f
f
( ) ( )
( )
L OUT
SW max skip ON IN L
I Rdc V Vd
1
t V I Rhs Vd
æ ö
´ + +
æ ö
= ´ ç ÷
ç ÷ ç ÷
- ´ +
è ø è ø
f
TPS54060
www.ti.com
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
Application Information (continued)
8.1.4 Selecting the Switching Frequency
The switching frequency that is selected should be the lower value of the two equations, Equation 26 and
Equation 27.Equation 26 is the maximum switching frequency limitation set by the minimum controllable on time.
Setting the switching frequency above this value will cause the regulator to skip switching pulses.
Equation 27 is the maximum switching frequency limit set by the frequency shift protection. To have adequate
output short circuit protection at high input voltages, the switching frequency should be set to be less than the
fsw(maxshift) frequency. In Equation 27, to calculate the maximum switching frequency one must take into
account that the output voltage decreases from the nominal voltage to 0 volts, the fdiv integer increases from 1 to
8 corresponding to the frequency shift.
In Figure 45, the solid line illustrates a typical safe operating area regarding frequency shift and assumes the
output voltage is zero volts, and the resistance of the inductor is 0.130, FET on resistance of 0.2and the
diode voltage drop is 0.5V. The dashed line is the maximum switching frequency to avoid pulse skipping. Enter
these equations in a spreadsheet or other software or use the SwitcherPro design software to determine the
switching frequency.
(26)
(27)
ILinductor current
Rdc inductor resistance
VIN maximum input voltage
VOUT output voltage
VOUTSC output voltage during short
Vd diode voltage drop
RDS(on) switch on resistance
tON controllable on time
ƒDIV frequency divide equals (1, 2, 4, or 8)
Figure 45. Maximum Switching Frequency vs Input Voltage
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l TEXAS INSTRUMENTS
RT/CLK
TPS54060
Clock
Source
PLL
Rfset
10pF 4kW
50 W
EXT
TPS54060
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
www.ti.com
Application Information (continued)
8.1.5 How to Interface to RT/CLK Pin
The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the
synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in
Figure 46. The square wave amplitude must transition lower than 0.5V and higher than 2.2V on the RT/CLK pin
and have an on time greater than 40 ns and an off time greater than 40 ns. The synchronization frequency range
is 300 kHz to 2200 kHz. The rising edge of the PH will be synchronized to the falling edge of RT/CLK pin signal.
The external synchronization circuit should be designed in such a way that the device will have the default
frequency set resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. It is
recommended to use a frequency set resistor connected as shown in Figure 46 through a 50resistor to
ground. The resistor should set the switching frequency close to the external CLK frequency. It is recommended
to ac couple the synchronization signal through a 10 pF ceramic capacitor to RT/CLK pin and a 4kseries
resistor. The series resistor reduces PH jitter in heavy load applications when synchronizing to an external clock
and in applications which transition from synchronizing to RT mode. The first time the CLK is pulled above the
CLK threshold the device switches from the RT resistor frequency to PLL mode. The internal 0.5V voltage source
is removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Since
there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with the
external resistor. The device transitions from the resistor mode to the PLL mode and then will increase or
decrease the switching frequency until the PLL locks onto the CLK frequency within 100 microseconds.
When the device transitions from the PLL to resistor mode the switching frequency will slow down from the CLK
frequency to 150 kHz, then reapply the 0.5V voltage and the resistor will then set the switching frequency. The
switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The
device implements a digital frequency shift to enable synchronizing to an external clock during normal startup
and fault conditions. Figure 47,Figure 48 and Figure 49 show the device synchronized to an external system
clock in continuous conduction mode (ccm) discontinuous conduction (dcm) and pulse skip mode (psm).
Figure 46. Synchronizing to a System Clock
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l TEXAS INSTRUMENTS Tekma'fl worms/s 01x Atqs Tekman mums/s 73 Acqs I Y 1 I T 1 \L\ \J‘I N / x W 7 MW 2, “1 fig—I 7%? fl I ‘ L ;\ A E \ / i/ \ ‘ ”WI \\/l/fl\J/\:VJJ \V/AK/AV/ 4+ (J11 zuuv w 1u.uv “WM Suuns (J11 \ xuumv th LUUV m U11 quv w VI Suuns th \ xuumv L 4 ZUUlnA w zu.umA w Tek-fl 50.0MS/s 134 Acqs [ T . . . . . . . . . ] Ch] 2.00V Bu Ch2 MLOOHS Ch1'\. 800mV 1 C14 20. gas
EXT
IL
PH
EXT
IL
PH
IL
EXT
PH
TPS54060
www.ti.com
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
Application Information (continued)
Figure 47. Plot of Synchronizing in CCM Figure 48. Plot of Synchronizing in DCM
Figure 49. Plot of Synchronizing in PSM
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l TEXAS INSTRUMENTS CSHQJuF w U1 4';uH vouv wssuIsoco 3.3 v, as A V‘N : 12745V ; BODY PH '99 ' 1 2 L VOUT L 5:3 =::: a m as Rs (:2 R1 4 55/"? ms 7 awaI ‘7'” 5‘ ZuF 2.2uF 332k 5 a s max ; Pwnen T RS f ‘i R4 31.5k T 731k PWRGD ::55 R2 7 R3 18pF R7 56.2k 237k :07 1am aseapr ,L
TPS54060
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
www.ti.com
8.2 Typical Applications
8.2.1 Buck Converter for 3.3-V Output
Figure 50. High Frequency, 3.3V Output Power Supply Design with Adjusted UVLO
8.2.1.1 Design Requirements
This example details the design of a high frequency switching regulator design using ceramic output capacitors.
A few parameters must be known in order to start the design process. These parameters are typically determined
at the system level. For this example, we will start with the following known parameters:
Table 1. Design Parameters
DESIGN PARAMETERS EXAMPLE VALUES
Output Voltage 3.3 V
Transient Response 0 to 0.5-A ΔVout = 4%
load step
Maximum Output Current 0.5 A
Input Voltage 34 V nom. 12 V to 48 V
Output Voltage Ripple 1% of Vout
Start Input Voltage (rising VIN) 8.9 V
Stop Input Voltage (falling VIN) 7.9 V
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Selecting the Switching Frequency
The first step is to decide on a switching frequency for the regulator. Typically, the user will want to choose the
highest switching frequency possible since this will produce the smallest solution size. The high switching
frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that
switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of
the internal power switch, the input voltage and the output voltage and the frequency shift limitation.
Equation 26 and Equation 27 must be used to find the maximum switching frequency for the regulator, choose
the lower value of the two equations. Switching frequencies higher than these values will result in pulse skipping
or the lack of overcurrent protection during a short circuit.
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l TEXAS INSTRUMENTS L \ND 'R IL ( ) *
2
Iripple
IoutILpeak +=
( ) ( ) 2
2OUT OUT
L(rms) O
O SW
V Vinmax - V
1
I I 12 Vinmax L
æ ö
´
= + ´ ç ÷
ç ÷
´ ´
è ø
f
( )
´
=´ ´ f
OUT OUT
RIPPLE
O SW
V Vin max - V
I
Vin m ax L
IND
Vinmax Vout Vout
Lo min = Io K Vinmax ƒsw
-
´
´ ´
TPS54060
www.ti.com
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
The typical minimum on time, tonmin, is 130 ns for the TPS54060. For this example, the output voltage is 3.3 V
and the maximum input voltage is 48 V, which allows for a maximum switch frequency up to 616 kHz when
including the inductor resistance, on resistance and diode voltage in Equation 26. To ensure overcurrent
runaway is not a concern during short circuits in your design use Equation 27 or the solid curve in Figure 45 to
determine the maximum switching frequency. With a maximum input voltage of 48 V, assuming a diode voltage
of 0.5 V, inductor resistance of 130m, switch resistance of 400m, a current limit value of 0.94 A and a short
circuit output voltage of 0.1V. The maximum switching frequency is approximately 923 kHz.
Choosing the lower of the two values and adding some margin a switching frequency of 500kHz is used. To
determine the timing resistance for a given switching frequency, use Equation 2 or the curve in Figure 29.
The switching frequency is set by resistor R3shown in Figure 50.
8.2.1.2.2 Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use Equation 28.
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
The inductor ripple current will be filtered by the output capacitor. Therefore, choosing high inductor ripple
currents will impact the selection of the output capacitor since the output capacitor must have a ripple current
rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion
of the designer; however, the following guidelines may be used.
For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be used.
When using higher ESR output capacitors, KIND = 0.2 yields better results. Since the inductor ripple current is
part of the PWM control system, the inductor ripple current should always be greater than 30 mA for dependable
operation. In a wide input voltage regulator, it is best to choose an inductor ripple current on the larger side. This
allows the inductor to still have a measurable ripple current with the input voltage at its minimum.
For this design example, use KIND = 0.3 and the minimum inductor value is calculated to be 39.7 μH. For this
design, a nearest standard value was chosen: 47μH. For the output filter inductor, it is important that the RMS
current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from
Equation 30 and Equation 31.
For this design, the RMS inductor current is 0.501 A and the peak inductor current is 0.563 A. The chosen
inductor is a MSS1048-473ML. It has a saturation current rating of 1.44 A and an RMS current rating of 1.83A.
As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but
will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of
the regulator but allow for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
(28)
(29)
(30)
(31)
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l TEXAS INSTRUMENTS
2 Iout
Cout >
sw Vout
´ D
¦ ´ D
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8.2.1.2.3 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor will
determine the modulator pole, the output voltage ripple, and how the regulators responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator also will temporarily not be able to
supply sufficient output current if there is a large, fast increase in the current needs of the load such as
transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop
to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output
capacitor must be sized to supply the extra current to the load until the control loop responds to the load change.
The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only
allowing a tolerable amount of droop in the output voltage. Equation 32 shows the minimum output capacitance
necessary to accomplish this.
For this example, the transient load response is specified as a 4% change in Vout for a load step from 0A (no
load) to 0.5 A (full load). For this example, ΔIout = 0.5-0 = 0.5 A and ΔVout = 0.04 × 3.3 = 0.132 V. Using these
numbers gives a minimum capacitance of 15.2μF. This value does not take the ESR of the output capacitor into
account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this
calculation. Aluminum electrolytic and tantalum capacitors have higher ESR that should be taken into account.
The catch diode of the regulator can not sink current so any stored energy in the inductor will produce an output
voltage overshoot when the load current rapidly decreases, see Figure 51. The output capacitor must also be
sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current.
The excess energy that gets stored in the output capacitor will increase the voltage on the capacitor. The
capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 33 is
used to calculate the minimum capacitance to keep the output voltage overshoot to a desired value. For this
example, the worst case load step will be from 0.5 A to 0 A. The output voltage will increase during this load
transition and the stated maximum in our specification is 4% of the output voltage. This will make Vf = 1.04 × 3.3
= 3.432. Vi is the initial capacitor voltage which is the nominal output voltage of 3.3 V. Using these numbers in
Equation 33 yields a minimum capacitance of 13.2 μF.
Equation 34 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, Voripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. Equation 34 yields 1μF.
Equation 35 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 35 indicates the ESR should be less than 248m.
The most stringent criteria for the output capacitor is 15.2μF of capacitance to keep the output voltage in
regulation during an load transient.
Additional capacitance de-ratings for aging, temperature and dc bias should be factored in which will increase
this minimum value. For this example, a 47 μF 10V X5R ceramic capacitor with 5 mof ESR will be used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the Root Mean Square (RMS) value of the maximum ripple current. Equation 36 can be used
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 36 yields
37.7 mA.
where
ΔIout is the change in output current.
ƒsw is the regulators switching frequency.
ΔVout is the allowable change in the output voltage. (32)
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TEXAS INSTRUMENTS Vin max
( )2
´ ´
- ´ ´ Cj ƒsw Vin + Vƒd
(Vin max Vout) Iout Vƒd
Pd = + 2
Vin max
Vout (Vin max Vout)
Icorms = 12 Vin max Lo sw
´ -
´ ´ ´ ¦
ORIPPLE
ESR
RIPPLE
V
R
I
<
1 1
ORIPPLE
RIPPLE
Cout > V
8 sw
I
´
´ ¦
( )
( )
2
2 2
2
Ioh Iol
Cout > Lo
V Vi
-
´
¦ -
TPS54060
www.ti.com
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
where
L is the value of the inductor.
• IOH is the output current under heavy load.
• IOL is the output under light load.
VF is the final peak output voltage.
Vi is the initial capacitor voltage. (33)
(34)
(35)
(36)
8.2.1.2.4 Catch Diode
The TPS54060 requires an external catch diode between the PH pin and GND. The selected diode must have a
reverse voltage rating equal to or greater than Vinmax. The peak current rating of the diode must be greater than
the maximum inductor current. The diode should also have a low forward voltage. Schottky diodes are typically a
good choice for the catch diode due to their low forward voltage. The lower the forward voltage of the diode, the
higher the efficiency of the regulator.
Typically, the higher the voltage and current ratings the diode has, the higher the forward voltage will be. Since
the design example has an input voltage up to 48V, a diode with a minimum of 60V reverse voltage will be
selected.
For the example design, the B160A Schottky diode is selected for its lower forward voltage and it comes in a
larger package size which has good thermal characteristics over small devices. The typical forward voltage of the
B160A is 0.50 volts.
The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by
the forward voltage of the diode which equals the conduction losses of the diode. At higher switch frequencies,
the ac losses of the diode need to be taken into account. The ac losses of the diode are due to the charging and
discharging of the junction capacitance and reverse recovery. Equation 37 is used to calculate the total power
dissipation, conduction losses plus ac losses, of the diode.
The B160A has a junction capacitance of 110pF. Using Equation 37, the selected diode will dissipate 0.297
Watts. This power dissipation, depending on mounting techniques, should produce a 5.9°C temperature rise in
the diode when the input voltage is 48V and the load current is 0.5A.
If the power supply spends a significant amount of time at light load currents or in sleep mode consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
(37)
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l TEXAS INSTRUMENTS
Iout max 0.25
ΔVin =
Cin sw
´
´ ¦
( )
Vin min Vout
Vout
Icirms = Iout
Vin min Vin min
-
´ ´
TPS54060
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
www.ti.com
8.2.1.2.5 Input Capacitor
The TPS54060 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 3 μF of
effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any dc
bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The
capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54060.
The input ripple current can be calculated using Equation 38.
The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the dc bias taken into account. The capacitance value of a capacitor
decreases as the dc bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 60V voltage rating is required to support the
maximum input voltage. Common standard ceramic capacitor voltage ratings include 4V, 6.3V, 10V, 16V, 25V,
50V or 100V so a 100V capacitor should be selected. For this example, two 2.2μF, 100V capacitors in parallel
have been selected. Table 2 shows a selection of high voltage capacitors. The input capacitance value
determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 39.
Using the design example values, Ioutmax = 0.5 A, Cin = 4.4μF, ƒsw = 500 kHz, yields an input voltage ripple of
57 mV and a rms input ripple current of 0.223A.
(38)
(39)
Table 2. Capacitor Types
VENDOR VALUE (μF) EIA Size VOLTAGE DIALECTRIC COMMENTS
1.0 to 2.2 100 V
1210 GRM32 series
1.0 to 4.7 50 V
Murata 1.0 100 V
1206 GRM31 series
1.0 to 2.2 50 V
1.0 10 1.8 50 V
2220
1.0 to 1.2 100 V
Vishay VJ X7R series
1.0 to 3.9 50 V
2225
1.0 to 1.8 100 V X7R
1.0 to 2.2 100 V
1812 C series C4532
1.5 to 6.8 50 V
TDK 1.0. to 2.2 100 V
1210 C series C3225
1.0 to 3.3 50 V
1.0 to 4.7 50 V
1210
1.0 100 V
AVX X7R dielectric series
1.0 to 4.7 50 V
1812
1.0 to 2.2 100 V
8.2.1.2.6 Slow Start Capacitor
The slow start capacitor determines the minimum amount of time it will take for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is large and would require large amounts of current to quickly charge the
capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54060 reach the current limit or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
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TEXAS INSTRUMENTS 2 x n XVoulx Com
Ioutmax
p mod = 2 × × Vout × Cout
¦p
Cout Vout 0.8
tss > Issavg
´ ´
TPS54060
www.ti.com
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output
voltage without drawing excessive current. Equation 40 can be used to find the minimum slow start time, tss,
necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average
slow start current of Issavg. In the example, to charge the 47μF output capacitor up to 3.3V while only allowing
the average input current to be 0.125A would require a 1 ms slow start time.
Once the slow start time is known, the slow start capacitor value can be calculated using Equation 1. For the
example circuit, the slow start time is not too critical since the output capacitor value is 47μF which does not
require much current to charge to 3.3V. The example circuit has the slow start time set to an arbitrary value of
3.2ms which requires a 0.01 μF capacitor.
(40)
8.2.1.2.7 Bootstrap Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10V
or higher voltage rating.
8.2.1.2.8 Undervoltage Lockout (UVLO) Set Point
The UVLO can be adjusted using an external voltage divider on the EN pin of the TPS54060. The UVLO has two
thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the
input voltage is falling. For the example design, the supply should turn on and start switching once the input
voltage increases above 8.9V (enabled). After the regulator starts switching, it should continue to do so until the
input voltage falls below 7.9V (UVLO stop).
The programmable UVLO and enable voltages are set using a resistor divider between Vin and ground to the EN
pin. Equation 18 through Equation 19 can be used to calculate the resistance values necessary. For the example
application, a 332kbetween Vin and EN and a 56.2kbetween EN and ground are required to produce the 8.9
and 7.9 volt start and stop voltages.
8.2.1.2.9 Output Voltage and Feedback Resistors Selection
For the example design, 10.0 kwas selected for R2. Using Equation 17, R1 is calculated as 31.25 k. The
nearest standard 1% resistor is 31.6 k. Due to current leakage of the VSENSE pin, the current flowing through
the feedback network should be greater than 1 μA in order to maintain the output voltage accuracy. This
requirement makes the maximum value of R2 equal to 800 k. Choosing higher resistor values will decrease
quiescent current and improve efficiency at low output currents but may introduce noise immunity problems.
8.2.1.2.10 Compensation
There are several methods used to compensate DC/DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual cross over frequency will usually be lower than the cross over frequency
used in the calculations. This method assume the crossover frequency is between the modulator pole and the
esr zero and the esr zero is at least 10 times greater the modulator pole. Use SwitcherPro software for a more
accurate design.
To get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 41 and
Equation 42. For Cout, use a derated value of 40 μF. Use equations Equation 43 and Equation 44, to estimate a
starting point for the crossover frequency, fco, to design the compensation. For the example design, fpmod is
603 Hz and fzmod is 796 kHz. Equation 43 is the geometric mean of the modulator pole and the esr zero and
Equation 44 is the mean of modulator pole and the switching frequency. Equation 43 yields 21.9 kHz and
Equation 44 gives 12.3 kHz. Use the lower value of Equation 43 or Equation 44 for an initial crossover frequency.
For this example, fco is 12.3kHz. Next, the compensation components are calculated. A resistor in series with a
capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the
compensating pole.
(41)
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l TEXAS INSTRUMENTS Vin
Ptot = Pcon + Psw + Pgd + Pq
6
Pq = 116 10 Vin
-
´ ´
9
Pgd = Vin 3 10 sw
-
´ ´ ´ ¦
2 9
Psw = Vin sw lo 0.25 10-
´ ¦ ´ ´ ´
2
DS(on)
Vout
Pcon = Io R Vin
´ ´
1
sw
fp
=
´ ´
C8
R4
Re´
=o
C sr
C8
R4
1
2fp
=
´ ´ ´ p
C7 R4 m od
2f
gmps gmea
pæ ö
æ ö
´ ´ ´
= ´ç ÷
ç ÷ ´
è ø è ø
co out out
ref
C V
R4
V
2
sw
p
f
f f= ´
co mod
p z
f f f= ´
co mod mod
1
z mod =
2 Resr × Cout
¦´ p ´
TPS54060
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
www.ti.com
(42)
(43)
(44)
To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance,
gmps, is 1.9A/V. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, gmea, are
3.3V, 0.8V and 97μS, respectively. R4 is calculated to be 72.6 k, use the nearest standard value of 73.2k.
Use Equation 46 to set the compensation zero to the modulator pole frequency. Equation 46 yields 3600pF for
compensating capacitor C7, a 3300pF is used on the board.
(45)
(46)
Use the larger value of Equation 47 and Equation 48 to calculate the C8, to set the compensation pole.
Equation 48 yields 8.7pF so the nearest standard of 10pF is used.
(47)
(48)
8.2.1.2.11 Discontinuous Mode and Eco Mode Boundary
With an input voltage of 34V, the power supply enters discontinuous mode when the output current is less than
60mA. The power supply enters EcoMode when the output current is lower than 38mA.
The input current draw at no load is 228μA.
8.2.1.2.12 Power Dissipation Estimate
The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM)
operation. These equations should not be used if the device is working in discontinuous conduction mode (DCM).
The power dissipation of the IC includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd) and
supply current (Pq).
(49)
(50)
(51)
(52)
Where:
Io is the output current (A).
RDS(on) is the on-resistance of the high-side MOSFET ().
VOUT is the output voltage (V).
VIN is the input voltage (V).
fsw is the switching frequency (Hz).
So
(53)
36 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: TPS54060
‘5‘ TEXAS INSTRUMENTS Tune : 5 mS/dlv ‘ WW ”WWW JMMMLMMJMJM Tune : '1 us/dw Tune : 5 us/dw
V = 10 mV/div (AC Coupled)
OUT
PH = 20 V/div
Time = 1 s/divμ
PH = 20 V/div
Time = 5 s/divμ
V = 10 mV/div (AC Coupled)
OUT
Inductor Current = 100 mA/div
I = 200 mA/div (0.125 to 0.375 A Step)
OUT
V = 20 V/div (AC Coupled)
IN
Time = 5 ms/div
V = 1 V/div
OUT
V = 20 V/div
IN
Time = 2 ms/div
TAmax = TJmax Rth Ptot- ´
TJ = TA + Rth Ptot´
TPS54060
www.ti.com
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
For given TA,
(54)
For given TJMAX = 150°C
(55)
Where:
Ptot is the total device power dissipation (W).
TAis the ambient temperature (°C).
TJis the junction temperature (°C).
Rth is the thermal resistance junction to ambient for a given PCB layout (°C/W).
TJMAX is maximum junction temperature (°C).
TAMAX is maximum ambient temperature (°C).
There will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode
and trace resistance that will impact the overall efficiency of the regulator.
8.2.1.3 Application Curves
Figure 51. Load Transient Figure 52. Start-Up With VIN
Figure 53. Output Ripple CCM Figure 54. Output Ripple, DCM
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 37
Product Folder Links: TPS54060
l TEXAS INSTRUMENTS FLLLLJFL Tune : éo us/dlv n n L Tune : '1 us/dw W JMWMMW m MWWMNWAMMM‘ Tune : s us/dw um 100
100 1k
–60
–40
0
20
40
60
–150
–100
–50
0
50
100
150
Frequency (Hz)
Gain (dB)
Phase ( )
o
10k 100k 1M
–20
Phase
Gain
C030
0
10
20
40
50
60
70
80
90
100
0 0.02 0.04 0.06 0.08
Output Current (A)
Efficiency (%)
0.10
30
V = 24 V
IN
V = 42 V
IN
V = 12 V
IN
V = 34 V
IN
V = 18 V
IN
C029
0
10
20
30
40
50
60
70
80
100
0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
Output Current (A)
Efficiency (%)
0.45 0.50
V = 24 V
IN
V = 42 V
IN
V = 12 V
IN
V = 34 V
IN
V = 18 V
IN
90
C028
Time = 5 s/divμ
V = 20 V/div (AC Coupled)
IN
PH = 20 V/div
Inductor Current = 100 mA/div
PH = 20 V/div
Time = 50 s/divμ
V = 10 mV/div (AC Coupled)
OUT
PH = 20 V/div
Time = 1 s/divμ
V = 20 mV/div (AC Coupled)
IN
TPS54060
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
www.ti.com
Figure 55. Output Ripple, PSM Figure 56. Input Ripple CCM
Figure 57. Input Ripple DCM Figure 58. Efficiency vs Load Current
Figure 59. Light Load Efficiency Figure 60. Overall Loop Frequency Response
38 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: TPS54060
PH
VIN
GND
BOOT
VSENSE
COMP
TPS54060
EN
RT/CLK
SS/TR
Cpole
Czero
Rcomp
RT
Css
Co
Lo
Cboot
Cin
R1
R2
Cd
VIN
VOUT
+
+
GND
–0.1
–0.08
–0.06
0
0.04
0.06
0.1
0.00 0.25 0.1 0.2 0.25 0.3 0.4 0.45 0.5
Load Current (A)
Regulation (%)
0.15 0.35
–0.02
–0.04
0.02
0.08
C031
–0.1
–0.08
–0.06
–0.04
–0.02
0
0.02
10 45 60
Regulation (%)
Input Voltage (V)
0.1
0.08
0.06
0.04
403530252015 55
50
C032
TPS54060
www.ti.com
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
Figure 62. Regulation vs Input Voltage
Figure 61. Regulation vs Load Current
8.2.2 Inverting Power Supply
Figure 63. Inverting Power Supply from the SLVA317 Application Note
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 39
Product Folder Links: TPS54060
AW \
PH
VIN
GND
BOOT
VSENSE
COMP
TPS54060
EN
RT/CLK
SS/TR
Cpole
Czero
Rcomp
RT
Css
Coneg
Lo
Cboot
Cin
R1
R2
Cd
VIN
VONEG
+
+
GND
VOPOS
Copos
+
TPS54060
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
www.ti.com
8.2.3 Split Rail Power Supply
Figure 64. Split Rail Power Supply Based on the SLVA369 Application Note
9 Power Supply Recommendations
The design of the device is for operation from an power supply range between 3.5 V and 60 V. It is essential that
the power supply voltage remains within this range. If the power supply is more distant than a few inches from
the TPS54060 converter, the circuit may require additional bulk capacitance besides the ceramic bypass
capacitors. An electrolytic capacitor with a value of 100 µF is a typical choice.
40 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: TPS54060
‘5‘ TEXAS INSTRUMENTS
BOOT
VIN
EN
SS/TR
RT/CLK
PH
GND
COMP
VSENSE
PWRGD
Input
Bypass
Capacitor
UVLO
Adjust
Resistors
SlowStart
Capacitor Frequency
SetResistor
Compensation
Network Resistor
Divider
Output
Inductor
Output
Capacitor
Vout
Vin
Topside
Ground
Area Catch
Diode
RouteBootCapacitor
Traceonanotherlayerto
providewidepathfor
topsideground
ThermalVIA
SignalVIA
TPS54060
www.ti.com
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signals paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed
to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to
minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch
diode. See Figure 65 for a PCB layout example. The GND pin should be tied directly to the power pad under the
IC and the power pad.
The power pad should be connected to any internal PCB ground planes using multiple vias directly under the IC.
The PH pin should be routed to the cathode of the catch diode and to the output inductor. Since the PH
connection is the switching node, the catch diode and output inductor should be located close to the PH pins,
and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated
load, the top side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise
so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The
additional external components can be placed approximately as shown. It may be possible to obtain acceptable
performance with alternate PCB layouts, however this layout has been shown to produce good results and is
meant as a guideline.
10.1.1 Estimated Circuit Area
The estimated printed circuit board area for the components used in the design of Figure 50 is 0.55 in2. This area
does not include test points or connectors.
10.2 Layout Example
Figure 65. PCB Layout Example
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 41
Product Folder Links: TPS54060
l TEXAS INSTRUMENTS
TPS54060
SLVS919C –JANUARY 2009REVISED SEPTEMBER 2015
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
For the TPS54060 and TPS54060A family Excel design tool, see SLVC432.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
TPS54060EVM-457 0.5-A, SWIFT(TM) Regulator EVM, SLVU299
Create an Inverting Power Supply From a Step-Down Regulator, SLVA317
Level Shifting Control for an Inverting Buck-boost , SLVA540
Creating a Split-Rail Power Supply With a Wide Input Voltage Buck Regulator, SLVA369
TPS54060EVM-590 100mA, Split Rail SWIFT™ Regulator Evaluation Module, SLVU374
Improved Load Current Capability for Cap-Drop Off-Line Power Supply for E-Meter, SLVA491
11.3 Trademarks
Eco-Mode, PowerPAD, WEBENCH, SwitcherPro are trademarks of Texas Instruments.
Excel is a registered trademark of Microsoft Corporation.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
42 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: TPS54060
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS54060DGQ ACTIVE HVSSOP DGQ 10 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 150 54060
TPS54060DGQR ACTIVE HVSSOP DGQ 10 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 150 54060
TPS54060DRCR ACTIVE VSON DRC 10 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 150 54060
TPS54060DRCT ACTIVE VSON DRC 10 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 150 54060
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS54060 :
Enhanced Product: TPS54060-EP
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
I TEXAS INSTRUMENTS ‘3‘ V.'
PACKAGE MATERIALS INFORMATION
www.ti.com 28-Nov-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS54060DGQR HVSSOP DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS54060DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 28-Nov-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54060DGQR HVSSOP DGQ 10 2500 364.0 364.0 27.0
TPS54060DRCR VSON DRC 10 3000 346.0 346.0 35.0
Pack Materials-Page 2
I TEXAS INSTRUMENTS __________________ ‘(I(I“""""""""
PACKAGE MATERIALS INFORMATION
www.ti.com 28-Nov-2022
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPS54060DGQ DGQ HVSSOP 10 80 330 6.55 500 2.88
Pack Materials-Page 3
www.ti.com
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
HVSSOP - 1.1 mm max height
TM
PowerPADDGQ 10
PLASTIC SMALL OUTLINE
3 x 3, 0.5 mm pitch
4224775/A
www.ti.com
PACKAGE OUTLINE
C
5.05
4.75 TYP
1.1 MAX
8X 0.5
10X 0.27
0.17
2X
2
0.23
0.13 TYP
0 - 8
0.15
0.05
1.83
1.63
1.89
1.69
0.25
GAGE PLANE
0.7
0.4
A
3.1
2.9
NOTE 3
B3.1
2.9
4218842/A 01/2019
PowerPAD - 1.1 mm max heightDGQ0010D
PLASTIC SMALL OUTLINE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA-T.
PowerPAD is a trademark of Texas Instruments.
TM
110
0.08 C A B
6
5
PIN 1 ID
AREA
NOTE 4
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 3.700
EXPOSED
THERMAL PAD
4
1
5
8
www.ti.com
EXAMPLE BOARD LAYOUT
(4.4)
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
10X (1.45)
10X (0.3)
8X (0.5)
(2.2)
NOTE 9
(3.1)
NOTE 9
(1.83)
(1.89)
SOLDER MASK
OPENING
( 0.2) TYP
VIA
(1.3) TYP
(1.3)
TYP
(R0.05) TYP
4218842/A 01/2019
PowerPAD - 1.1 mm max heightDGQ0010D
PLASTIC SMALL OUTLINE
SYMM
SYMM
SEE DETAILS
LAND PATTERN EXAMPLE
SCALE:15X
1
56
10
SOLDER MASK
OPENING
METAL COVERED
BY SOLDER MASK
SOLDER MASK
DEFINED PAD
TM
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
10X (1.45)
10X (0.3)
8X (0.5)
(4.4)
(1.83)
(1.89)
BASED ON
0.125 THICK
STENCIL
(R0.05) TYP
4218842/A 01/2019
PowerPAD - 1.1 mm max heightDGQ0010D
PLASTIC SMALL OUTLINE
1.55 X 1.600.175
1.67 X 1.730.150
1.83 X 1.89 (SHOWN)0.125
2.05 X 2.110.1
SOLDER STENCIL
OPENING
STENCIL
THICKNESS
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
TM
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X
SYMM
SYMM
1
56
10
BASED ON
0.125 THICK
STENCIL
BY SOLDER MASK
METAL COVERED
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
www.ti.com
GENERIC PACKAGE VIEW
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
VSON - 1 mm max heightDRC 10
PLASTIC SMALL OUTLINE - NO LEAD
3 x 3, 0.5 mm pitch
4226193/A
--I vfi g C C C C C r1 C I WW‘iTiqu C A 33933
www.ti.com
PACKAGE OUTLINE
C
10X 0.30
0.18
2.4 0.1
2X
2
1.65 0.1
8X 0.5
1.0
0.8
10X 0.5
0.3
0.05
0.00
A3.1
2.9 B
3.1
2.9
(0.2) TYP
4X (0.25)
2X (0.5)
VSON - 1 mm max heightDRC0010J
PLASTIC SMALL OUTLINE - NO LEAD
4218878/B 07/2018
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
56
10
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
SYMM
SYMM
11
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
10X (0.24)
(2.4)
(2.8)
8X (0.5)
(1.65)
( 0.2) VIA
TYP
(0.575)
(0.95)
10X (0.6)
(R0.05) TYP
(3.4)
(0.25)
(0.5)
VSON - 1 mm max heightDRC0010J
PLASTIC SMALL OUTLINE - NO LEAD
4218878/B 07/2018
SYMM
1
56
10
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
11
SYMM
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(R0.05) TYP
10X (0.24)
10X (0.6)
2X (1.5)
2X
(1.06)
(2.8)
(0.63)
8X (0.5)
(0.5)
4X (0.34)
4X (0.25)
(1.53)
VSON - 1 mm max heightDRC0010J
PLASTIC SMALL OUTLINE - NO LEAD
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
SYMM
1
56
10
EXPOSED METAL
TYP
11
SYMM
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