PIC12F508/9, PIC16F505 Datasheet by Microchip Technology

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© 2009 Microchip Technology Inc. DS41236E
PIC12F508/509/16F505
Data Sheet
8/14-Pin, 8-Bit Flash Microcontrollers
QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV = ISO/TS 16949:2002 =
DS41236E-page 2 © 2009 Microchip Technology Inc.
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Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
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Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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and manufacture of development systems is ISO 9001:2000 certified.
Q ‘MICROCHIP
© 2009 Microchip Technology Inc. DS41236E-page 3
PIC12F508/509/16F505
Devices Included In This Data Sheet:
High-Performance RISC CPU:
Only 33 Single-Word Instructions to Learn
All Single-Cycle Instructions Except for Program
Branches, which are Two-Cycle
12-Bit Wide Instructions
2-Level Deep Hardware Stack
Direct, Indirect and Relative Addressing modes
for Data and Instructions
8-Bit Wide Data Path
8 Special Function Hardware Registers
Operating Speed:
- DC – 20 MHz clock input (PIC16F505 only)
- DC – 200 ns instruction cycle (PIC16F505
only)
- DC – 4 MHz clock input
- DC – 1000 ns instruction cycle
Special Microcontroller Features:
4 MHz Precision Internal Oscillator:
- Factory calibrated to ±1%
In-Circuit Serial Programming™ (ICSP™)
In-Circuit Debugging (ICD) Support
Power-On Reset (POR)
Device Reset Timer (DRT)
Watchdog Timer (WDT) with Dedicated On-Chip
RC Oscillator for Reliable Operation
Programmable Code Protection
Multiplexed MCLR Input Pin
Internal Weak Pull-Ups on I/O Pins
Power-Saving Sleep mode
Wake-Wp from Sleep on Pin Change
Selectable Oscillator Options:
- INTRC: 4 MHz precision Internal oscillator
- EXTRC: External low-cost RC oscillator
- XT: Standard crystal/resonator
- HS: High-speed crystal/resonator
(PIC16F505 only)
- LP: Power-saving, low-frequency crystal
- EC: High-speed external clock input
(PIC16F505 only)
Low-Power Features/CMOS Technology:
Operating Current:
- < 175 μA @ 2V, 4 MHz, typical
Standby Current:
- 100 nA @ 2V, typical
Low-Power, High-Speed Flash Technology:
- 100,000 Flash endurance
- > 40 year retention
Fully Static Design
Wide Operating Voltage Range: 2.0V to 5.5V
Wide Temperature Range:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Peripheral Features (PIC12F508/509):
6 I/O Pins:
- 5 I/O pins with individual direction control
- 1 input only pin
- High current sink/source for direct LED drive
- Wake-on-change
- Weak pull-ups
8-Bit Real-Time Clock/Counter (TMR0) with 8-Bit
Programmable Prescaler
Peripheral Features (PIC16F505):
12 I/O Pins:
- 11 I/O pins with individual direction control
- 1 input only pin
- High current sink/source for direct LED drive
- Wake-on-change
- Weak pull-ups
8-Bit Real-Time Clock/Counter (TMR0) with 8-Bit
Programmable Prescaler
• PIC12F508 • PIC12F509 • PIC16F505
8/14-Pin, 8-Bit Flash Microcontrollers
PIC12F508/509/16F505
DS41236E-page 4 © 2009 Microchip Technology Inc.
Pin Diagrams
PIC16F505 16-Pin Diagram (QFN)
PDIP, SOIC, TSSOP
VDD
RB5/OSC1/CLKIN
RB4/OSC2/CLKOUT
RB3/MCLR/VPP
1
2
3
4
VSS
RB0/ICSPDAT
14
13
12
11
PIC16F505
5
6
7
10
9
8
RC5/T0CKI
RC4
RC3
RB1/ICSPCLK
RB2
RC0
RC1
RC2
PDIP, SOIC, MSOP
VDD
GP5/OSC1/CLKIN
GP4/OSC2
GP3/MCLR/VPP
1
2
3
4
VSS
GP0/ICSPDAT
8
7
6
5
PIC12F508/509
GP1/ICSPCLK
GP2/T0CKI
DFN
PIC12F508/509
1
2
3
4
8
7
6
5
VSS
GP0/ICSPDAT
GP1/ICSPCLK
GP2/T0CKI
VDD
GP5/OSC1/CLKIN
GP4/OSC2
GP3/MCLR/VPP
1
2
3
49
10
11
12
5
6
7
8
16
15
14
13
PIC16F505
RB5/OSC1/CLKIN
RB4/OSC2/CLKOUT
RB3/MCLR/VPP
RC5/TOCKI
VDD
NC
NC
VSS
RB0/ICSPDAT
RB1/ICSPCLK
RB2
RC0
RC4
RC3
RC2
RC1
© 2009 Microchip Technology Inc. DS41236E-page 5
PIC12F508/509/16F505
Device Program Memory Data Memory I/O Timers
8-bit
Flash (words) SRAM (bytes)
PIC12F508 512 25 6 1
PIC12F509 1024 41 6 1
PIC16F505 1024 72 12 1
PIC12F508/509/16F505
DS41236E-page 6 © 2009 Microchip Technology Inc.
Table of Contents
1.0 General Description...................................................................................................................................................................... 7
2.0 PIC12F508/509/16F505 Device Varieties ................................................................................................................................... 9
3.0 Architectural Overview ............................................................................................................................................................... 11
4.0 Memory Organization ................................................................................................................................................................. 17
5.0 I/O Port....................................................................................................................................................................................... 31
6.0 Timer0 Module and TMR0 Register ........................................................................................................................................... 35
7.0 Special Features Of The CPU.................................................................................................................................................... 41
8.0 Instruction Set Summary............................................................................................................................................................ 57
9.0 Development Support................................................................................................................................................................. 65
10.0 Electrical Characteristics............................................................................................................................................................ 69
11.0 DC and AC Characteristics Graphs and Charts ......................................................................................................................... 81
12.0 Packaging Information................................................................................................................................................................ 91
Index .................................................................................................................................................................................................. 105
The Microchip Web Site..................................................................................................................................................................... 107
Customer Change Notification Service .............................................................................................................................................. 107
Customer Support .............................................................................................................................................................................. 107
Reader Response .............................................................................................................................................................................. 108
Product Identification System............................................................................................................................................................. 109
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© 2009 Microchip Technology Inc. DS41236E-page 7
PIC12F508/509/16F505
1.0 GENERAL DESCRIPTION
The PIC12F508/509/16F505 devices from Microchip
Technology are low-cost, high-performance, 8-bit,
fully-static, Flash-based CMOS microcontrollers. They
employ a RISC architecture with only 33 single-word/
single-cycle instructions. All instructions are single
cycle (200 μs) except for program branches, which
take two cycles. The PIC12F508/509/16F505 devices
deliver performance an order of magnitude higher than
their competitors in the same price category. The 12-bit
wide instructions are highly symmetrical, resulting in a
typical 2:1 code compression over other 8-bit
microcontrollers in its class. The easy to use and easy
to remember instruction set reduces development time
significantly.
The PIC12F508/509/16F505 products are equipped
with special features that reduce system cost and
power requirements. The Power-on Reset (POR) and
Device Reset Timer (DRT) eliminate the need for exter-
nal Reset circuitry. There are four oscillator configura-
tions to choose from (six on the PIC16F505), including
INTRC Internal Oscillator mode and the power-saving
LP (Low-Power) Oscillator mode. Power-Saving Sleep
mode, Watchdog Timer and code protection features
improve system cost, power and reliability.
The PIC12F508/509/16F505 devices are available in
the cost-effective Flash programmable version, which
is suitable for production in any volume. The customer
can take full advantage of Microchip’s price leadership
in Flash programmable microcontrollers, while
benefiting from the Flash programmable flexibility.
The PIC12F508/509/16F505 products are supported
by a full-featured macro assembler, a software simula-
tor, an in-circuit emulator, a ‘C’ compiler, a low-cost
development programmer and a full featured program-
mer. All the tools are supported on IBM® PC and
compatible machines.
1.1 Applications
The PIC12F508/509/16F505 devices fit in applications
ranging from personal care appliances and security
systems to low-power remote transmitters/receivers.
The Flash technology makes customizing application
programs (transmitter codes, appliance settings,
receiver frequencies, etc.) extremely fast and conve-
nient. The small footprint packages, for through hole or
surface mounting, make these microcontrollers perfect
for applications with space limitations. Low cost, low
power, high performance, ease-of-use and I/O flexibil-
ity make the PIC12F508/509/16F505 devices very ver-
satile even in areas where no microcontroller use has
been considered before (e.g., timer functions, logic and
PLDs in larger systems and coprocessor applications).
TABLE 1-1: PIC12F508/509/16F505 DEVICES
PIC12F508 PIC12F509 PIC16F505
Clock Maximum Frequency of Operation (MHz) 4 4 20
Memory Flash Program Memory (words) 512 1024 1024
Data Memory (bytes) 25 41 72
Peripherals Timer Module(s) TMR0 TMR0 TMR0
Wake-up from Sleep on Pin Change Yes Yes Yes
Features I/O Pins 5 5 11
Input Pins 1 1 1
Internal Pull-ups Yes Yes Yes
In-Circuit Serial Programming Yes Yes Yes
Number of Instructions 33 33 33
Packages 8-pin PDIP, SOIC,
MSOP, DFN
8-pin PDIP, SOIC,
MSOP, DFN
14-pin PDIP, SOIC,
TSSOP
The PIC12F508/509/16F505 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current
capability and precision internal oscillator.
The PIC12F508/509/16F505 devices use serial programming with data pin RB0/GP0 and clock pin RB1/GP1.
PIC12F508/509/16F505
DS41236E-page 8 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS41236E-page 9
PIC12F508/509/16F505
2.0 PIC12F508/509/16F505 DEVICE
VARIETIES
A variety of packaging options are available. Depend-
ing on application and production requirements, the
proper device option can be selected using the
information in this section. When placing orders, please
use the PIC12F508/509/16F505 Product Identification
System at the back of this data sheet to specify the
correct part number.
2.1 Quick Turn Programming (QTP)
Devices
Microchip offers a QTP programming service for
factory production orders. This service is made
available for users who choose not to program
medium-to-high quantity units and whose code
patterns have stabilized. The devices are identical to
the Flash devices but with all Flash locations and fuse
options already programmed by the factory. Certain
code and prototype verification procedures do apply
before production shipments are available. Please
contact your local Microchip Technology sales office for
more details.
2.2 Serialized Quick Turn
ProgrammingSM (SQTPSM) Devices
Microchip offers a unique programming service, where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry code,
password or ID number.
PIC12F508/509/16F505
DS41236E-page 10 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS41236E-page 11
PIC12F508/509/16F505
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC12F508/509/16F505
devices can be attributed to a number of architectural
features commonly found in RISC microprocessors.
To begin with, the PIC12F508/509/16F505 devices
use a Harvard architecture in which program and data
are accessed on separate buses. This improves
bandwidth over traditional von Neumann architec-
tures where program and data are fetched on the
same bus. Separating program and data memory fur-
ther allows instructions to be sized differently than the
8-bit wide data word. Instruction opcodes are 12 bits
wide, making it possible to have all single-word
instructions. A 12-bit wide program memory access
bus fetches a 12-bit instruction in a single cycle. A
two-stage pipeline overlaps fetch and execution of
instructions. Consequently, all instructions (33)
execute in a single cycle (200 ns @ 20 MHz, 1 μs @
4 MHz) except for program branches.
Table 3-1 below lists program memory (Flash) and data
memory (RAM) for the PIC12F508/509/16F505
devices.
TABLE 3-1: PIC12F508/509/16F505
MEMORY
The PIC12F508/509/16F505 devices can directly or
indirectly address its register files and data memory. All
Special Function Registers (SFR), including the PC,
are mapped in the data memory. The PIC12F508/509/
16F505 devices have a highly orthogonal (symmetri-
cal) instruction set that makes it possible to carry out
any operation, on any register, using any addressing
mode. This symmetrical nature and lack of “special
optimal situations” make programming with the
PIC12F508/509/16F505 devices simple, yet efficient.
In addition, the learning curve is reduced significantly.
The PIC12F508/509/16F505 devices contain an 8-bit
ALU and working register. The ALU is a general
purpose arithmetic unit. It performs arithmetic and
Boolean functions between data in the working register
and any register file.
The ALU is 8 bits wide and capable of addition, sub-
traction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two’s comple-
ment in nature. In two-operand instructions, one
operand is typically the W (working) register. The other
operand is either a file register or an immediate
constant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC) and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow and digit borrow out bit, respec-
tively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
Simplified block diagrams are shown in Figure 3-1 and
Figure 3-2, with the corresponding pin described in
Table 3-2 and Table 3-3.
Device Memory
Program Data
PIC12F508 512 x 12 25 x 8
PIC12F509 1024 x 12 41 x 8
PIC16F505 1024 x 12 72 x 8
PIC12F508/509/16F505
DS41236E-page 12 © 2009 Microchip Technology Inc.
FIGURE 3-1: PIC12F508/509 BLOCK DIAGRAM
Device Reset
Timer
Power-on
Reset
Watchdog
Timer
Flash
Program
Memory
12 Data Bus 8
12
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr 5
RAM Addr 9
Addr MUX
Indirect
Addr
FSR Reg
Status Reg
MUX
ALU
W Reg
Instruction
Decode and
Control
Timing
Generation
OSC1/CLKIN
OSC2
MCLR
VDD, VSS
Timer0
GPIO
8
8
GP4/OSC2
GP3/MCLR/VPP
GP2/T0CKI
GP1/ISCPCLK
GP0/ISCPDAT
5-7
3
GP5/OSC1/CLKIN
Stack 1
Stack 2
512 x 12 or
25 x 8 or
1024 x 12
41 x 8
Internal RC
OSC
© 2009 Microchip Technology Inc. DS41236E-page 13
PIC12F508/509/16F505
TABLE 3-2: PIC12F508/509 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
GP0/ICSPDAT GP0 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal
weak pull-up and wake-up from Sleep on pin change.
ICSPDAT ST CMOS In-Circuit Serial Programming™ data pin.
GP1/ICSPCLK GP1 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal
weak pull-up and wake-up from Sleep on pin change.
ICSPCLK ST CMOS In-Circuit Serial Programming clock pin.
GP2/T0CKI GP2 TTL CMOS Bidirectional I/O pin.
T0CKI ST Clock input to TMR0.
GP3/MCLR/VPP GP3 TTL Input pin. Can be software programmed for internal weak
pull-up and wake-up from Sleep on pin change.
MCLR ST Master Clear (Reset). When configured as MCLR, this pin is
an active-low Reset to the device. Voltage on MCLR/VPP must
not exceed VDD during normal device operation or the device
will enter Programming mode. Weak pull-up always on if
configured as MCLR.
VPP HV Programming voltage input.
GP4/OSC2 GP4 TTL CMOS Bidirectional I/O pin.
OSC2 XTAL Oscillator crystal output. Connections to crystal or resonator in
Crystal Oscillator mode (XT and LP modes only, GPIO in other
modes).
GP5/OSC1/CLKIN GP5 TTL CMOS Bidirectional I/O pin.
OSC1 XTAL Oscillator crystal input.
CLKIN ST External clock source input.
VDD VDD P Positive supply for logic and I/O pins.
VSS VSS P Ground reference for logic and I/O pins.
Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,
ST = Schmitt Trigger input, HV = High Voltage
PIC12F508/509/16F505
DS41236E-page 14 © 2009 Microchip Technology Inc.
FIGURE 3-2: PIC16F505 BLOCK DIAGRAM
Device Reset
Timer
Power-on
Reset
Watchdog
Timer
Flash
Program
Memory
12 Data Bus 8
12
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr 5
RAM Addr 9
Addr MUX
Indirect
Addr
FSR Reg
Status Reg
MUX
ALU
W Reg
Instruction
Decode and
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR
VDD, VSS
Timer0
PORTB
8
8
RB4/OSC2/CLKOUT
RB3/MCLR/VPP
RB2
RB1/ICSPDAT
RB0/ICSPCLK
5-7
3
RB5/OSC1/CLKIN
Stack 1
Stack 2
1K x 12
72 bytes
Internal RC
OSC
PORTC
RC4
RC3
RC2
RC1
RC0
RC5/T0CKI
© 2009 Microchip Technology Inc. DS41236E-page 15
PIC12F508/509/16F505
TABLE 3-3: PIC16F505 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
RB0/ICSPDAT RB0 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal
weak pull-up and wake-up from Sleep on pin change.
ICSPDAT ST CMOS In-Circuit Serial Programming™ data pin.
RB1/ICSPCLK RB1 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal
weak pull-up and wake-up from Sleep on pin change.
ICSPCLK ST CMOS In-Circuit Serial Programming clock pin.
RB2 RB2 TTL CMOS Bidirectional I/O pin.
RB3/MCLR/VPP RB3 TTL Input port. Can be software programmed for internal weak
pull-up and wake-up from Sleep on pin change.
MCLR ST Master Clear (Reset). When configured as MCLR, this pin is
an active-low Reset to the device. Voltage on MCLR/VPP must
not exceed VDD during normal device operation or the device
will enter Programming mode. Weak pull-up always on if
configured as MCLR.
VPP HV Programming voltage input.
RB4/OSC2/CLKOUT RB4 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal
weak pull-up and wake-up from Sleep on pin change.
OSC2 XTAL Oscillator crystal output. Connections to crystal or resonator in
Crystal Oscillator mode (XT, HS and LP modes only).
CLKOUT CMOS In EXTRC and INTRC modes, the pin output can be
configured for CLKOUT, which has 1/4 the frequency of OSC1
and denotes the instruction cycle rate.
RB5/OSC1/CLKIN RB5 TTL CMOS Bidirectional I/O pin.
OSC1 XTAL Crystal input.
CLKIN ST External clock source input.
RC0 RC0 TTL CMOS Bidirectional I/O pin.
RC1 RC1 TTL CMOS Bidirectional I/O pin.
RC2 RC2 TTL CMOS Bidirectional I/O pin.
RC3 RC3 TTL CMOS Bidirectional I/O pin.
RC4 RC4 TTL CMOS Bidirectional I/O pin.
RC5/T0CKI RC5 TTL CMOS Bidirectional I/O pin.
T0CKI ST Clock input to TMR0.
VDD VDD P Positive supply for logic and I/O pins.
VSS VSS P Ground reference for logic and I/O pins.
Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,
ST = Schmitt Trigger input, HV = High Voltage
PIC12F508/509/16F505
DS41236E-page 16 © 2009 Microchip Technology Inc.
3.1 Clocking Scheme/Instruction
Cycle
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC
is incremented every Q1 and the instruction is fetched
from program memory and latched into the instruction
register in Q4. It is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-3 and Example 3-1.
3.2 Instruction Flow/Pipelining
An instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the PC to change (e.g., GOTO), then two cycles
are required to complete the instruction (Example 3-1).
A fetch cycle begins with the PC incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-3: CLOCK/INSTRUCTION CYCLE
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC PC PC + 1 PC + 2
Fetch INST (PC)
Execute INST (PC – 1) Fetch INST (PC + 1)
Execute INST (PC) Fetch INST (PC + 2)
Execute INST (PC + 1)
Internal
phase
clock
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
1. MOVLW 03H Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. CALL SUB_1 Fetch 3 Execute 3
4. BSF PORTB, BIT1 Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
© 2009 Microchip Technology Inc. DS41236E-page 17
PIC12F508/509/16F505
4.0 MEMORY ORGANIZATION
The PIC12F508/509/16F505 memories are organized
into program memory and data memory. For devices
with more than 512 bytes of program memory, a paging
scheme is used. Program memory pages are accessed
using one STATUS register bit. For the PIC12F509 and
PIC16F505, with data memory register files of more
than 32 registers, a banking scheme is used. Data
memory banks are accessed using the File Select
Register (FSR).
4.1 Program Memory Organization for
the PIC12F508/509
The PIC12F508 device has a 10-bit Program Counter
(PC) and PIC12F509 has a 11-bit Program Counter
(PC) capable of addressing a 2K x 12 program memory
space.
Only the first 512 x 12 (0000h-01FFh) for the
PIC12F508, and 1K x 12 (0000h-03FFh) for the
PIC12F509 are physically implemented (see
Figure 4-1). Accessing a location above these
boundaries will cause a wrap-around within the first
512 x 12 space (PIC12F508) or 1K x 12 space
(PIC12F509). The effective Reset vector is a 0000h
(see Figure 4-1). Location 01FFh (PIC12F508) and
location 03FFh (PIC12F509) contain the internal
clock oscillator calibration value. This value should
never be overwritten.
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F508/509
CALL, RETLW
PC<11:0>
Stack Level 1
Stack Level 2
User Memory
Space
12
0000h
7FFh
01FFh
0200h
On-chip Program
Memory
Reset Vector(1)
Note 1: Address 0000h becomes the
effective Reset vector. Location
01FFh, 03FFh (PIC12F508,
PIC12F509) contains the MOVLW XX
internal oscillator calibration value.
512 Word
1024 Word 03FFh
0400h
On-chip Program
Memory
PIC12F508/509/16F505
DS41236E-page 18 © 2009 Microchip Technology Inc.
4.2 Program Memory Organization
For The PIC16F505
The PIC16F505 device has a 11-bit Program Counter
(PC) capable of addressing a 2K x 12 program memory
space.
The 1K x 12 (0000h-03FFh) for the PIC16F505 are
physically implemented. Refer to Figure 4-2.
Accessing a location above this boundary will cause a
wrap-around within the first 1K x 12 space. The
effective Reset vector is at 0000h (see Figure 4-2).
Location 03FFh contains the internal oscillator
calibration value. This value should never be
overwritten.
FIGURE 4-2: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F505
4.3 Data Memory Organization
Data memory is composed of registers or bytes of
RAM. Therefore, data memory for a device is specified
by its register file. The register file is divided into two
functional groups: Special Function Registers (SFR)
and General Purpose Registers (GPR).
The Special Function Registers include the TMR0
register, the Program Counter (PCL), the STATUS
register, the I/O registers (ports) and the File Select
Register (FSR). In addition, Special Function Registers
are used to control the I/O port configuration and
prescaler options.
The General Purpose Registers are used for data and
control information under command of the instructions.
For the PIC12F508/509, the register file is composed of
7 Special Function Registers, 9 General Purpose
Registers and 16 or 32 General Purpose Registers
accessed by banking (see Figure 4-3 and Figure 4-4).
For the PIC16F505, the register file is composed of 8
Special Function Registers, 8 General Purpose
Registers and 64 General Purpose Registers accessed
by banking (Figure 4-5).
4.3.1 GENERAL PURPOSE REGISTER
FILE
The General Purpose Register file is accessed, either
directly or indirectly, through the File Select Register
(FSR). See Section 4.9 “Indirect Data Addressing:
INDF and FSR Registers”.
CALL, RETLW
PC<11:0>
Stack Level 1
Stack Level 2
User Memory
Space
12
0000h
7FFh
01FFh
0200h
Reset Vector(1)
Note 1: Address 0000h becomes the
effective Reset vector. Location
03FFh contains the MOVLW XX
internal oscillator calibration value.
1024 Words 03FFh
0400h
On-chip Program
Memory
© 2009 Microchip Technology Inc. DS41236E-page 19
PIC12F508/509/16F505
FIGURE 4-3: PIC12F508 REGISTER
FILE MAP FIGURE 4-4: PIC12F509 REGISTER
FILE MAP
FIGURE 4-5: PIC16F505 REGISTER FILE MAP
File Address
00h
01h
02h
03h
04h
05h
06h
07h
1Fh
INDF(1)
TMR0
PCL
STATUS
FSR
OSCCAL
GPIO
General
Purpose
Registers
Note 1: Not a physical register. See Section 4.9
“Indirect Data Addressing: INDF and
FSR Registers”.
File Address
00h
01h
02h
03h
04h
05h
06h
07h
1Fh
INDF(1)
TMR0
PCL
STATUS
FSR
OSCCAL
GPIO
0Fh
10h
Bank 0 Bank 1
3Fh
30h
20h
2Fh
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
Addresses map
back to
addresses
in Bank 0.
Note 1: Not a physical register. See Section 4.9
“Indirect Data Addressing: INDF and FSR
Registers”.
FSR<5> 0 1
File Address
00h
01h
02h
03h
04h
05h
06h
07h
1Fh
INDF(1)
TMR0
PCL
STATUS
FSR
OSCCAL
PORTB
0Fh
10h
Bank 0 Bank 1
3Fh
30h
20h
2Fh
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
Addresses map back to
addresses in Bank 0.
Note 1: Not a physical register. See Section 4.9 “Indirect Data Addressing: INDF and FSR Registers”.
FSR<6:5> 00 01
Bank 3
7Fh
70h
60h
6Fh
General
Purpose
Registers
11
Bank 2
5Fh
50h
40h
4Fh
General
Purpose
Registers
10
08h
PORTC
PIC12F508/509/16F505
DS41236E-page 20 © 2009 Microchip Technology Inc.
4.3.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral functions to control the
operation of the device (Table 4-1).
The Special Function Registers can be classified into
two sets. The Special Function Registers associated
with the “core” functions are described in this section.
Those related to the operation of the peripheral
features are described in the section for each
peripheral feature.
TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC12F508/509)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
Power-On
Reset(2) Page #
00h INDF Uses Contents of FSR to Address Data Memory (not a physical
register)
xxxx xxxx 28
01h TMR0 8-bit Real-Time Clock/Counter xxxx xxxx 35
02h(1) PCL Low-order 8 bits of PC 1111 1111 27
03h STATUS GPWUF —PA0
(5) TO PD ZDCC0-01 1xxx(3) 22
04h FSR Indirect Data Memory Address Pointer 111x xxxx 28
04h(4) FSR Indirect Data Memory Address Pointer 110x xxxx 28
05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 1111 111- 26
06h GPIO GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx 31
N/A TRISGPIO I/O Control Register --11 1111 31
N/A OPTION GPWU GPPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 24
Legend: – = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = value depends on condition.
Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.7 “Program Counter
for an explanation of how to access these bits.
2: Other (non Power-up) Resets include external Reset through MCLR, Watchdog Timer and wake-up on pin
change Reset.
3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
4: PIC12F509 only.
5: This bit is used on the PIC12F509. For code compatibility do not use this bit on the PIC12F508.
© 2009 Microchip Technology Inc. DS41236E-page 21
PIC12F508/509/16F505
TABLE 4-2: SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC16F505)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
Power-On
Reset(2) Page #
00h INDF Uses Contents of FSR to Address Data Memory (not a physical
register)
xxxx xxxx 28
01h TMR0 8-bit Real-Time Clock/Counter xxxx xxxx 35
02h(1) PCL Low-order 8 bits of PC 1111 1111 27
03h STATUS RBWUF —PA0TO PD ZDCC0-01 1xxx 22
04h FSR Indirect Data Memory Address Pointer 100x xxxx 28
05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 1111 111- 26
06h PORTB RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx 31
07h PORTC RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx 31
N/A TRISB I/O Control Register --11 1111 31
N/A TRISC I/O Control Register --11 1111 31
N/A OPTION RBWU RBPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 25
Legend: – = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = value depends on condition.
Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
2: Other (non Power-up) Resets include external reset through MCLR, Watchdog Timer and wake-up on pin
change Reset.
ADZWF , sump, ADZWF, suawr RRF or RLF
PIC12F508/509/16F505
DS41236E-page 22 © 2009 Microchip Technology Inc.
4.4 STATUS Register
This register contains the arithmetic status of the ALU,
the Reset status and the page preselect bit.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
Therefore, it is recommended that only BCF, BSF and
MOVWF instructions be used to alter the STATUS regis-
ter. These instructions do not affect the Z, DC or C bits
from the STATUS register. For other instructions which
do affect Status bits, see Section 8.0 “Instruction Set
Summary”.
REGISTER 4-1: STATUS REGISTER (ADDRESS: 03h) (PIC12F508/509)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
GPWUF —PA0TOPD ZDCC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GPWUF: GPIO Reset bit
1 = Reset due to wake-up from Sleep on pin change
0 = After power-up or other Reset
bit 6 Reserved: Do not use
bit 5 PA0: Program Page Preselect bits(1)
1 = Page 1 (200h-3FFh)
0 = Page 0 (000h-1FFh)
Each page is 512 bytes.
Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is
not recommended, since this may affect upward compatibility with future products.
bit 4 TO: Time-Out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit (for ADDWF and SUBWF instructions)
ADDWF:
1 = A carry from the 4th low-order bit of the result occurred
0 = A carry from the 4th low-order bit of the result did not occur
SUBWF:
1 = A borrow from the 4th low-order bit of the result did not occur
0 = A borrow from the 4th low-order bit of the result occurred
bit 0 C: Carry/Borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)
ADDWF: SUBWF: RRF or RLF:
1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively
0 = A carry did not occur 0 = A borrow occurred
Note 1: This bit is used on the PIC12F509. For code compatibility do not use this bit on the PIC12F508.
ADDWF: SUBWF ADDWF. SUBWF. RRF or RLF.
© 2009 Microchip Technology Inc. DS41236E-page 23
PIC12F508/509/16F505
REGISTER 4-2: STATUS REGISTER (ADDRESS: 03h) (PIC16F505)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
RBWUF —PA0TOPD ZDCC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RBWUF: PORTB Reset bit
1 = Reset due to wake-up from Sleep on pin change
0 = After power-up or other Reset
bit 6 Reserved: Do not use
bit 5 PA0: Program Page Preselect bits
1 = Page 1 (200h-3FFh)
0 = Page 0 (000h-1FFh)
Each page is 512 bytes.
Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page
preselect is not recommended, since this may affect upward compatibility with future products.
bit 4 TO: Time-Out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit (for ADDWF and SUBWF instructions)
ADDWF:
1 = A carry from the 4th low-order bit of the result occurred
0 = A carry from the 4th low-order bit of the result did not occur
SUBWF:
1 = A borrow from the 4th low-order bit of the result did not occur
0 = A borrow from the 4th low-order bit of the result occurred
bit 0 C: Carry/Borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)
ADDWF:SUBWF:RRF or RLF:
1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively
0 = A carry did not occur 0 = A borrow occurred
PIC12F508/509/16F505
DS41236E-page 24 © 2009 Microchip Technology Inc.
4.5 OPTION Register
The OPTION register is a 8-bit wide, write-only register,
which contains various control bits to configure the
Timer0/WDT prescaler and Timer0.
By executing the OPTION instruction, the contents of
the W register will be transferred to the OPTION regis-
ter. A Reset sets the OPTION<7:0> bits.
Note: If TRIS bit is set to ‘0’, the wake-up on
change and pull-up functions are disabled
for that pin (i.e., note that TRIS overrides
Option control of GPPU/RBPU and
GPWU/RBWU).
Note: If the T0CS bit is set to ‘1’, it will override
the TRIS function on the T0CKI pin.
REGISTER 4-3: OPTION REGISTER (PIC12F508/509)
W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1
GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GPWU: Enable Wake-up on Pin Change bit (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
bit 6 GPPU: Enable Weak Pull-ups bit (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin)
0 = Transition on internal instruction cycle clock, FOSC/4
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on the T0CKI pin
0 = Increment on low-to-high transition on the T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0 PS<2:0>: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value Timer0 Rate WDT Rate
© 2009 Microchip Technology Inc. DS41236E-page 25
PIC12F508/509/16F505
REGISTER 4-4: OPTION REGISTER (PIC16F505)
W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1
RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RBWU: Enable Wake-up on Pin Change bit (RB0, RB1, RB3, RB4)
1 = Disabled
0 = Enabled
bit 6 RBPU: Enable Weak Pull-ups bit (RB0, RB1, RB3, RB4)
1 = Disabled
0 = Enabled
bit 5 T0CS: Timer0 clock Source Select bit
1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin)
0 = Transition on internal instruction cycle clock, FOSC/4
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on the T0CKI pin
0 = Increment on low-to-high transition on the T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0 PS<2:0>: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value Timer0 Rate WDT Rate
PIC12F508/509/16F505
DS41236E-page 26 © 2009 Microchip Technology Inc.
4.6 OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used to
calibrate the internal precision 4 MHz oscillator. It
contains seven bits for calibration.
After you move in the calibration constant, do not
change the value. See Section 7.2.5 “Internal 4 MHz
RC Oscillator”.
Note: Erasing the device will also erase the pre-
programmed internal calibration value for
the internal oscillator. The calibration
value must be read prior to erasing the
part so it can be reprogrammed correctly
later.
REGISTER 4-5: OSCCAL REGISTER (ADDRESS: 05h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0
CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 CAL<6:0>: Oscillator Calibration bits
0111111 = Maximum frequency
0000001
0000000 = Center frequency
1111111
1000000 = Minimum frequency
bit 0 Unimplemented: Read as ‘0
© 2009 Microchip Technology Inc. DS41236E-page 27
PIC12F508/509/16F505
4.7 Program Counter
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
For a GOTO instruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The Program Counter
(PCL) is mapped to PC<7:0>. Bit 5 of the STATUS
register provides page information to bit 9 of the PC
(Figure 4-6).
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are
provided by the instruction word. However, PC<8>
does not come from the instruction word, but is always
cleared (Figure 4-6).
Instructions where the PCL is the destination, or modify
PCL instructions, include MOVWF PC, ADDWF PC and
BSF PC,5.
FIGURE 4-6: LOADING OF PC
BRANCH INSTRUCTIONS
4.7.1 EFFECTS OF RESET
The PC is set upon a Reset, which means that the PC
addresses the last location in the last page (i.e., the
oscillator calibration instruction). After executing
MOVLW XX, the PC will roll over to location 00h and
begin executing user code.
The STATUS register page preselect bits are cleared
upon a Reset, which means that page 0 is pre-selected.
Therefore, upon a Reset, a GOTO instruction will
automatically cause the program to jump to page 0 until
the value of the page bits is altered.
4.8 Stack
The PIC12F508/509/16F505 devices have a 2-deep,
12-bit wide hardware PUSH/POP stack.
A CALL instruction will PUSH the current value of Stack
1 into Stack 2 and then PUSH the current PC value,
incremented by one, into Stack Level 1. If more than two
sequential CALLs are executed, only the most recent two
return addresses are stored.
A RETLW instruction will POP the contents of Stack
Level 1 into the PC and then copy Stack Level 2
contents into Stack Level 1. If more than two sequential
RETLWs are executed, the stack will be filled with the
address previously stored in Stack Level 2. Note that
the W register will be loaded with the literal value
specified in the instruction. This is particularly useful for
the implementation of data look-up tables within the
program memory.
Note: Because PC<8> is cleared in the CALL
instruction or any modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any
program memory page (512 words long).
PA0
Status
PC 87 0
PCL
910
Instruction Word
70
GOTO Instruction
CALL or Modify PCL Instruction
11
PA0
Status
PC 87 0
PCL
910
Instruction Word
70
11
Reset to ‘0
Note 1: There are no Status bits to indicate stack
overflows or stack underflow conditions.
2: There are no instruction mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL
and RETLW instructions.
4E
PIC12F508/509/16F505
DS41236E-page 28 © 2009 Microchip Technology Inc.
4.9 Indirect Data Addressing: INDF
and FSR Registers
The INDF register is not a physical register.
Addressing INDF actually addresses the register
whose address is contained in the FSR register (FSR
is a pointer). This is indirect addressing.
4.9.1 INDIRECT ADDRESSING
Register file 07 contains the value 10h
Register file 08 contains the value 0Ah
Load the value 07 into the FSR register
A read of the INDF register will return the value
of 10h
Increment the value of the FSR register by one
(FSR = 08)
A read of the INDR register now will return the
value of 0Ah.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no operation (although Status bits may be affected).
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-1.
EXAMPLE 4-1: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
The FSR is a 5-bit wide register. It is used in conjunction
with the INDF register to indirectly address the data
memory area.
The FSR<4:0> bits are used to select data memory
addresses 00h to 1Fh.
FIGURE 4-7: DIRECT/INDIRECT ADDRESSING (PIC12F508/509)
PIC12F508 Does not use banking. FSR <7:5> are
unimplemented and read as 1’s.
PIC12F509 – Uses FSR<5>. Selects between bank 0
and bank 1. FSR<7:6> are unimplemented, read as
1’.
PIC16F505 – Uses FSR<6:5>. Selects from bank 0 to
bank 3. FSR<7> is unimplemented, read as ‘1’.
MOVLW 0x10 ;initialize pointer
MOVWF FSR ;to RAM
NEXT CLRF INDF ;clear INDF
;register
INCF FSR,F ;inc pointer
BTFSC FSR,4 ;all done?
GOTO NEXT ;NO, clear next
CONTINUE
: ;YES, continue
:
Note 1: For register map detail, see Section 4.3 “Data Memory Organization”.
2: PIC12F509.
Bank Location Select
Location Select
Bank Select
Indirect Addressing
Direct Addressing
Data
Memory(1) 0Fh
10h
Bank 0 Bank 1(2)
0
4
5
6(FSR)
00 01
00h
1Fh 3Fh
(opcode) 04
5
6
(FSR)
Addresses
map back to
addresses
in Bank 0.
© 2009 Microchip Technology Inc. DS41236E-page 29
PIC12F508/509/16F505
FIGURE 4-8: DIRECT/INDIRECT ADDRESSING (PIC16F505)
Note 1: For register map detail, see Section 4.3 “Data Memory Organization”.
Direct Addressing
(FSR)
6 5 4 (opcode) 0
Bank Select Location Select
00 01 10 11
00h
0Fh
10h
Data
Memory(1)
1Fh 3Fh 5Fh 7Fh
Bank 0 Bank 1 Bank 2 Bank 3
Indirect Addressing
6 5 4 (FSR) 0
Bank Location Select
Addresses
map back to
addresses
in Bank 0.
PIC12F508/509/16F505
DS41236E-page 30 © 2009 Microchip Technology Inc.
NOTES:
F, ,fi
© 2009 Microchip Technology Inc. DS41236E-page 31
PIC12F508/509/16F505
5.0 I/O PORT
As with any other register, the I/O register(s) can be
written and read under program control. However, read
instructions (e.g., MOVF PORTB,W) always read the I/O
pins independent of the pin’s Input/Output modes. On
Reset, all I/O ports are defined as input (inputs are at
high-impedance) since the I/O control registers are all
set.
5.1 PORTB/GPIO
PORTB/GPIO is an 8-bit I/O register. Only the low-
order 6 bits are used (RB/GP<5:0>). Bits 7 and 6 are
unimplemented and read as ‘0’s. Please note that RB3/
GP3 is an input only pin. The Configuration Word can
set several I/O’s to alternate functions. When acting as
alternate functions, the pins will read as ‘0’ during a port
read. Pins RB0/GP0, RB1/GP1, RB3/GP3 and RB4
can be configured with weak pull-ups and also for
wake-up on change. The wake-up on change and weak
pull-up functions are not pin selectable. If RB3/GP3/
MCLR is configured as MCLR, weak pull-up is always
on and wake-up on change for this pin is not enabled.
5.2 PORTC (PIC16F505 Only)
PORTC is an 8-bit I/O register. Only the low-order 6 bits
are used (RC<5:0>). Bits 7 and 6 are unimplemented
and read as ‘0’s.
5.3 TRIS Registers
The Output Driver Control register is loaded with the
contents of the W register by executing the TRIS f
instruction. A ‘1’ from a TRIS register bit puts the corre-
sponding output driver in a High-Impedance mode. A
0’ puts the contents of the output data latch on the
selected pins, enabling the output buffer. The excep-
tions are RB3/GP3, which is input only and the T0CKI
pin, which may be controlled by the OPTION register.
See Register 4-3 and Register 4-4.
The TRIS registers are “write-only” and are set (output
drivers disabled) upon Reset.
5.4 I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 5-2. All port pins, except RB3/GP3 which is
input only, may be used for both input and output oper-
ations. For input operations, these ports are non-latch-
ing. Any input must be present until read by an input
instruction (e.g., MOVF PORTB, W). The outputs are
latched and remain unchanged until the output latch is
rewritten. To use a port pin as output, the correspond-
ing direction control bit in TRIS must be cleared (= 0).
For use as an input, the corresponding TRIS bit must
be set. Any I/O pin (except RB3/GP3) can be
programmed individually as input or output.
FIGURE 5-1: PIC12F508/509/16F505
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Note: On the PIC12F508/509, I/O PORTB is ref-
erenced as GPIO. On the PIC16F505, I/O
PORTB is referenced as PORTB.
Note: On power-up, TOCKI functionality is
enabled in the OPTION register and must
be disabled to allow RC5 to be used as
general purpose I/O.
Note: A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
Data
Bus
Q
D
Q
CK
Q
D
Q
CK P
N
WR
Port
TRIS ‘f’
Data
TRIS
RD Port
VSS
VDD
I/O
pin
W
Reg
Latch
Latch
Reset
Note 1: See Table 3-3 for buffer type.
VSS
VDD
(1)
PIC12F508/509/16F505
DS41236E-page 32 © 2009 Microchip Technology Inc.
TABLE 5-1: SUMMARY OF PORT REGISTERS
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
Power-On
Reset
Value on
All Other
Resets
N/A TRISGPIO(1) I/O Control Register --11 1111 --11 1111
N/A TRISB(2) I/O Control Register --11 1111 --11 1111
N/A TRISC(2) I/O Control Register --11 1111 --11 1111
N/A OPTION(1) GPWU GPPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 1111 1111
N/A OPTION(2) RBWU RBPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 1111 1111
03h STATUS(1) GPWUF PAO TO PD ZDC C0-01 1xxx q00q quuu(3)
03h STATUS(2) RBWUF PAO TO PD ZDC C0-01 1xxx q00q quuu(3)
06h GPIO(1) GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu
06h PORTB(2) RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx --uu uuuu
07h PORTC(2) RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --uu uuuu
Legend: Shaded cells are not used by Port registers, read as ‘0’. – = unimplemented, read as ‘0’, x = unknown, u = unchanged,
q = depends on condition.
Note 1: PIC12F508/509 only.
2: PIC16F505 only.
3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
© 2009 Microchip Technology Inc. DS41236E-page 33
PIC12F508/509/16F505
5.5 I/O Programming Considerations
5.5.1 BIDIRECTIONAL I/O PORTS
Some instructions operate internally as read followed
by write operations. The BCF and BSF instructions, for
example, read the entire port into the CPU, execute the
bit operation and re-write the result. Caution must be
used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSF operation on bit 5 of PORTB/GPIO will
cause all eight bits of PORTB/GPIO to be read into the
CPU, bit 5 to be set and the PORTB/GPIO value to be
written to the output latches. If another bit of PORTB/
GPIO is used as a bidirectional I/O pin (say bit 0) and it
is defined as an input at this time, the input signal pres-
ent on the pin itself would be read into the CPU and
rewritten to the data latch of this particular pin, overwrit-
ing the previous content. As long as the pin stays in the
Input mode, no problem occurs. However, if bit 0 is
switched into Output mode later on, the content of the
data latch may now be unknown.
Example 5-1 shows the effect of two sequential
Read-Modify-Write instructions (e.g., BCF, BSF, etc.)
on an I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired OR”, “wired
AND”). The resulting high output currents may damage
the chip.
EXAMPLE 5-1: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT(e.g., PIC16F505)
5.5.2 SUCCESSIVE OPERATIONS ON
I/O PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle (Figure 5-2).
Therefore, care must be exercised if a write followed by
a read operation is carried out on the same I/O port. The
sequence of instructions should allow the pin voltage to
stabilize (load dependent) before the next instruction
causes that file to be read into the CPU. Otherwise, the
previous state of that pin may be read into the CPU rather
than the new state. When in doubt, it is better to separate
these instructions with a NOP or another instruction not
accessing this I/O port.
FIGURE 5-2: SUCCESSIVE I/O OPERATION (PIC16F505 Shown)
;Initial PORTB Settings
;PORTB<5:3> Inputs
;PORTB<2:0> Outputs
;
; PORTB latch PORTB pins
; ---------- ----------
BCF PORTB, 5 ;--01 -ppp --11 pppp
BCF PORTB, 4 ;--10 -ppp --11 pppp
MOVLW 007h;
TRIS PORTB ;--10 -ppp --11 pppp
;
Note 1: The user may have expected the pin values to
be ‘--00 pppp’. The 2nd BCF caused RB5 to
be latched as the pin value (High).
PC PC + 1 PC + 2 PC + 3
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetched
RB<5:0>
MOVWF PORTB NOP
Port pin
sampled here
NOPMOVF PORTB, W
Instruction
Executed MOVWF PORTB
(Write to PORTB) NOPMOVF PORTB,W
This example shows a write to PORTB
followed by a read from PORTB.
Data setup time = (0.25 TCY – TPD)
where: TCY = instruction cycle
TPD = propagation delay
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
(Read PORTB)
Port pin
written here
PIC12F508/509/16F505
DS41236E-page 34 © 2009 Microchip Technology Inc.
NOTES:
\ngw < x="" x="" 1x‘x="" b="">
© 2009 Microchip Technology Inc. DS41236E-page 35
PIC12F508/509/16F505
6.0 TIMER0 MODULE AND TMR0
REGISTER
The Timer0 module has the following features:
8-bit timer/counter register, TMR0
Readable and writable
8-bit software programmable prescaler
Internal or external clock select:
- Edge select for external clock
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 6-2 and Figure 6-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
T0SE bit (OPTION<4>) determines the source edge.
Clearing the T0SE bit selects the rising edge. Restric-
tions on the external clock input are discussed in detail
in Section6.1Using Timer0 with an External
Clock”.
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit, PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4,...,
1:256 are selectable. Section 6.2 “Prescaler” details
the operation of the prescaler.
A summary of registers associated with the Timer0
module is found in Table 6-1.
FIGURE 6-1: TIMER0 BLOCK DIAGRAM
FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-5).
0
1
1
0
T0CS(1)
FOSC/4
Programmable
Prescaler(2)
Sync with
Internal
Clocks TMR0 Reg
PSOUT
(2 TCY delay)
PSOUT
Data Bus
8
PSA(1)
PS2, PS1, PS0(1)
3
Sync
T0SE
(GP2/RC5)/T0CKI
Pin
PC – 1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetch
Timer0
PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 6
T0 T0 + 1 T0 + 2 NT0 NT0 + 1 NT0 + 2
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Write TMR0
executed Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 + 1 Read TMR0
reads NT0 + 2
Instruction
Executed
PC + 5
PC
(Program
Counter)
PIC12F508/509/16F505
DS41236E-page 36 © 2009 Microchip Technology Inc.
FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
Power-On
Reset
Value on
All Other
Resets
01h TMR0 Timer0 – 8-bit Real-Time Clock/Counter xxxx xxxx uuuu uuuu
N/A OPTION(1) GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
N/A OPTION(2) RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
N/A TRISGPIO(1), (3) I/O Control Register --11 1111 --11 1111
N/A TRISC(2), (3) RC5 RC4 RC3 RC2 RC1 RC0 --11 1111 --11 1111
Legend: Shaded cells are not used by Timer0. – = unimplemented, x = unknown, u = unchanged.
Note 1: PIC12F508/509 only.
2: PIC16F505 only.
3: The TRIS of the T0CKI pin is overridden when T0CS = 1.
PC – 1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetch
Timer0
PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 6
T0 T0 + 1 NT0 NT0 + 1
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Write TMR0
executed Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 + 1 Read TMR0
reads NT0 + 2
Instruction
Executed
PC + 5
PC
(Program
Counter)
© 2009 Microchip Technology Inc. DS41236E-page 37
PIC12F508/509/16F505
6.1 Using Timer0 with an External
Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock require-
ment is due to internal phase clock (TOSC) synchroni-
zation. Also, there is a delay in the actual incrementing
of Timer0 after synchronization.
6.1.1 EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 6-4).
Therefore, it is necessary for T0CKI to be high for at
least 2 TOSC (and a small RC delay of 2 Tt0H) and low
for at least 2 TOSC (and a small RC delay of 2 Tt0H).
Refer to the electrical specification of the desired
device.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler, so that the prescaler output is symmetrical.
For the external clock to meet the sampling require-
ment, the ripple counter must be taken into account.
Therefore, it is necessary for T0CKI to have a period of
at least 4 TOSC (and a small RC delay of 4 Tt0H)
divided by the prescaler value. The only requirement
on T0CKI high and low time is that they do not violate
the minimum pulse width requirement of Tt0H. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device.
6.1.2 TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-4 shows the
delay from the external clock edge to the timer
incrementing.
FIGURE 6-4: TIMER0 TIMING WITH EXTERNAL CLOCK
Increment Timer0 (Q4)
External Clock Input or
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Timer0 T0 T0 + 1 T0 + 2
Small pulse
misses sampling
External Clock/Prescaler
Output After Sampling (3)
Prescaler Output (2)
(1)
Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC). Therefore, the error
in measuring the interval between two edges on Timer0 input = ±4 TOSC max.
2: External clock if no prescaler selected; prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
PIC12F508/509/16F505
DS41236E-page 38 © 2009 Microchip Technology Inc.
6.2 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer (WDT), respectively (see Section 7.6 “Watch-
dog Timer (WDT)”). For simplicity, this counter is
being referred to as “prescaler” throughout this data
sheet.
The PSA and PS<2:0> bits (OPTION<3:0>) determine
prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1, x, etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the WDT. The prescaler is neither readable
nor writable. On a Reset, the prescaler contains all0’s.
6.2.1 SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software control
(i.e., it can be changed “on-the-fly” during program
execution). To avoid an unintended device Reset, the
following instruction sequence (Example 6-1) must be
executed when changing the prescaler assignment
from Timer0 to the WDT.
EXAMPLE 6-1: CHANGING PRESCALER
(TIMER0 WDT)
To change the prescaler from the WDT to the Timer0
module, use the sequence shown in Example 6-2. This
sequence must be used even if the WDT is disabled. A
CLRWDT instruction should be executed before
switching the prescaler.
EXAMPLE 6-2: CHANGING PRESCALER
(WDT TIMER0)
Note: The prescaler may be used by either the
Timer0 module or the WDT, but not both.
Thus, a prescaler assignment for the
Timer0 module means that there is no
prescaler for the WDT and vice versa.
CLRWDT ;Clear WDT
CLRF TMR0 ;Clear TMR0 & Prescaler
MOVLW ‘00xx1111’b ;These 3 lines (5, 6, 7)
OPTION ;are required only if
;desired
CLRWDT ;PS<2:0> are 000 or 001
MOVLW ‘00xx1xxx’b ;Set Postscaler to
OPTION ;desired WDT rate
CLRWDT ;Clear WDT and
;prescaler
MOVLW ‘xxxx0xxx’ ;Select TMR0, new
;prescale value and
;clock source
OPTION
© 2009 Microchip Technology Inc. DS41236E-page 39
PIC12F508/509/16F505
FIGURE 6-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER(1), (2)
TCY (= FOSC/4)
Sync
2
Cycles TMR0 Reg
8-bit Prescaler
8-to-1 MUX
M
MUX
Watchdog
Timer
PSA
01
0
1
WDT
Time-out
PS<2:0>
8
PSA
WDT Enable bit
0
1
0
1
Data Bus
8
PSA
T0CS
M
U
XM
U
X
U
X
T0SE
(GP2/RC5)/T0CKI
pin
Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
2: T0CKI is shared with pin RC5 on the PIC16F505 and pin GP2 on the PIC12F508/509.
PIC12F508/509/16F505
DS41236E-page 40 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS41236E-page 41
PIC12F508/509/16F505
7.0 SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other
processors are special circuits that deal with the needs
of real-time applications. The PIC12F508/509/16F505
microcontrollers have a host of such features intended
to maximize system reliability, minimize cost through
elimination of external components, provide power-
saving operating modes and offer code protection.
These features are:
Oscillator Selection
• Reset:
- Power-on Reset (POR)
- Device Reset Timer (DRT)
- Wake-up from Sleep on Pin Change
Watchdog Timer (WDT)
• Sleep
Code Protection
ID Locations
In-Circuit Serial Programming™
•Clock Out
The PIC12F508/509/16F505 devices have a Watchdog
Timer, which can be shut off only through Configuration
bit WDTE. It runs off of its own RC oscillator for added
reliability. If using HS (PIC16F505), XT or LP selectable
oscillator options, there is always an 18 ms (nominal)
delay provided by the Device Reset Timer (DRT),
intended to keep the chip in Reset until the crystal
oscillator is stable. If using INTRC or EXTRC, there is
an 18 ms delay only on VDD power-up. With this timer
on-chip, most applications need no external Reset
circuitry.
The Sleep mode is designed to offer a very low-current
Power-Down mode. The user can wake-up from Sleep
through a change on input pins or through a Watchdog
Timer time-out. Several oscillator options are also
made available to allow the part to fit the application,
including an internal 4 MHz oscillator. The EXTRC
oscillator option saves system cost while the LP crystal
option saves power. A set of Configuration bits are
used to select various options.
7.1 Configuration Bits
The PIC12F508/509/16F505 Configuration Words
consist of 12 bits. Configuration bits can be
programmed to select various device configurations.
Three bits are for the selection of the oscillator type;
(two bits on the PIC12F508/509), one bit is the
Watchdog Timer enable bit, one bit is the MCLR enable
bit and one bit is for code protection (Register 7-1,
Register 7-2).
PIC12F508/509/16F505
DS41236E-page 42 © 2009 Microchip Technology Inc.
REGISTER 7-1: CONFIGURATION WORD FOR PIC12F508/509(1)
— — MCLRE CP WDTE FOSC1 FOSC0
bit 11 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared x = Bit is unknown
bit 11-5 Unimplemented: Read as ‘0
bit 4 MCLRE: GP3/MCLR Pin Function Select bit
1 = GP3/MCLR pin function is MCLR
0 = GP3/MCLR pin function is digital input, MCLR internally tied to VDD
bit 3 CP: Code Protection bit
1 = Code protection off
0 = Code protection on
bit 2 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0 FOSC<1:0>: Oscillator Selection bits
11 = EXTRC = external RC oscillator
10 = INTRC = internal RC oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Refer to the “PIC12F508/509 Memory Programming Specifications” (DS41227) to determine how to
access the Configuration Word. The Configuration Word is not user addressable during device operation.
© 2009 Microchip Technology Inc. DS41236E-page 43
PIC12F508/509/16F505
REGISTER 7-2: CONFIGURATION WORD FOR PIC16F505(1)
MCLRE CP WDTE FOSC2 FOSC1 FOSC0
bit 11 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 11-6 Unimplemented: Read as ‘0
bit 5 MCLRE: RB3/MCLR Pin Function Select bit
1 = RB3/MCLR pin function is MCLR
0 = RB3/MCLR pin function is digital input, MCLR internally tied to VDD
bit 4 CP: Code Protection bit
1 = Code protection off
0 = Code protection on
bit 3 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0 FOSC<1:0>: Oscillator Selection bits
111 = External RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin
110 = External RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin
101 = Internal RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin
100 = Internal RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin
011 = EC oscillator/RB4 function on RB4/OSC2/CLKOUT pin
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
Note 1: Refer to the “PIC16F505 Memory Programming Specifications” (DS41226) to determine how to access
the Configuration Word. The Configuration Word is not user addressable during device operation.
PIC12F508/509/16F505
DS41236E-page 44 © 2009 Microchip Technology Inc.
7.2 Oscillator Configurations
7.2.1 OSCILLATOR TYPES
The PIC12F508/509/16F505 devices can be operated
in up to six different oscillator modes. The user can
program up to three Configuration bits (FOSC<1:0>
[PIC12F508/509], FOSC<2:0> [PIC16F505]). To select
one of these modes:
LP: Low-Power Crystal
• XT: Crystal/Resonator
HS: High-Speed Crystal/Resonator
(PIC16F505 only)
INTRC: Internal 4 MHz Oscillator
EXTRC: External Resistor/Capacitor
EC: External High-Speed Clock Input
(PIC16F505 only)
7.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In HS (PIC16F505), XT or LP modes, a crystal or
ceramic resonator is connected to the (GP5/RB5)/
OSC1/(CLKIN) and (GP4/RB4)/OSC2/(CLKOUT) pins
to establish oscillation (Figure 7-1). The PIC12F508/
509/16F505 oscillator designs require the use of a
parallel cut crystal. Use of a series cut crystal may give
a frequency out of the crystal manufacturers
specifications. When in HS (PIC16F505), XT or LP
modes, the device can have an external clock source
drive the (GP5/RB5)/OSC1/CLKIN pin (Figure 7-2).
When the part is used in this fashion, the output drive
levels on the OSC2 pin are very weak. This pin should
be left open and unloaded. Also, when using this mode,
the external clock should observe the frequency limits
for the clock mode chosen (HS, XT or LP).
FIGURE 7-1: CRYSTAL OPERATION
(OR CERAMIC
RESONATOR)
(HS, XT OR LP OSC
CONFIGURATION)
FIGURE 7-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
CONFIGURATION)
TABLE 7-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS –
PIC12F508/509/16F505(1)
Note 1: This device has been designed to per-
form to the parameters of its data sheet.
It has been tested to an electrical
specification designed to determine its
conformance with these parameters.
Due to process differences in the
manufacture of this device, this device
may have different performance charac-
teristics than its earlier version. These
differences may cause this device to
perform differently in your application
than the earlier version of this device.
2: The user should verify that the device
oscillator starts and performs as
expected. Adjusting the loading capacitor
values and/or the Oscillator mode may
be required.
Osc
Type Resonator
Freq. Cap. Range
C1 Cap. Range
C2
XT 4.0 MHz 30 pF 30 pF
HS(2) 16 MHz 10-47 pF 10-47 pF
Note 1: These values are for design guidance
only. Since each resonator has its own
characteristics, the user should consult
the resonator manufacturer for
appropriate values of external
components.
2: PIC16F505 only.
Note 1: See Capacitor Selection tables for
recommended values of C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF approx. value = 10 MΩ.
C1(1)
C2(1)
XTAL
OSC2
OSC1
RF(3)
Sleep
To internal
logic
RS(2)
PIC12F508/509
PIC16F505
Clock from
ext. system
OSC1
OSC2 PIC16F505
Open
PIC12F508/509
EEE
© 2009 Microchip Technology Inc. DS41236E-page 45
PIC12F508/509/16F505
TABLE 7-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR –
PIC12F508/509/16F505(2)
7.2.3 EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external
crystal oscillator circuit. Prepackaged oscillators
provide a wide operating range and better stability. A
well-designed crystal oscillator will provide good perfor-
mance with TTL gates. Two types of crystal oscillator
circuits can be used: one with parallel resonance, or
one with series resonance.
Figure 7-3 shows implementation of a parallel resonant
oscillator circuit. The circuit is designed to use the fun-
damental frequency of the crystal. The 74AS04 inverter
performs the 180-degree phase shift that a parallel
oscillator requires. The 4.7 kΩ resistor provides the
negative feedback for stability. The 10 kΩ potentiome-
ters bias the 74AS04 in the linear region. This circuit
could be used for external oscillator designs.
FIGURE 7-3: EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
Figure 7-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180-
degree phase shift in a series resonant oscillator
circuit. The 330 Ω resistors provide the negative
feedback to bias the inverters in their linear region.
FIGURE 7-4: EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
7.2.4 EXTERNAL RC OSCILLATOR
For timing insensitive applications, the RC device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (REXT) and capacitor (CEXT) values, and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit-to-unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C
components used.
Figure 7-5 shows how the R/C combination is
connected to the PIC12F508/509/16F505 devices. For
REXT values below 3.0 kΩ, the oscillator operation may
become unstable, or stop completely. For very high
REXT values (e.g., 1 MΩ), the oscillator becomes
sensitive to noise, humidity and leakage. Thus, we
recommend keeping REXT between 5.0 kΩ and
100 kΩ.
Osc
Type Resonator
Freq. Cap. Range
C1 Cap. Range
C2
LP 32 kHz(1) 15 pF 15 pF
XT 200 kHz
1 MHz
4 MHz
47-68 pF
15 pF
15 pF
47-68 pF
15 pF
15 pF
HS(3) 20 MHz 15-47 pF 15-47 pF
Note 1: For VDD > 4.5V, C1 = C2 30 pF is
recommended.
2: These values are for design guidance
only. Rs may be required to avoid over-
driving crystals with low drive level specifi-
cation. Since each crystal has its own
characteristics, the user should consult
the crystal manufacturer for appropriate
values of external components.
3: PIC16F505 only.
20 pF
+5V
20 pF
10k
4.7k
10k
74AS04
XTAL
10k
74AS04
PIC16F505
CLKIN
To O ther
Devices
PIC12F508
PIC12F509
330
74AS04 74AS04
PIC16F505
CLKIN
To Other
Devices
XTAL
330
74AS04
0.1 mF
PIC12F508
PIC12F509
‘H—Hiw
PIC12F508/509/16F505
DS41236E-page 46 © 2009 Microchip Technology Inc.
Although the oscillator will operate with no external
capacitor (CEXT = 0pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
Section 10.0 “Electrical Characteristics” shows RC
frequency variation from part-to-part due to normal
process variation. The variation is larger for larger val-
ues of R (since leakage current variation will affect RC
frequency more for large R) and for smaller values of C
(since variation of input capacitance will affect RC
frequency more).
Also, see the Electrical Specifications section for
variation of oscillator frequency due to VDD for given
REXT/CEXT values, as well as frequency variation due
to operating temperature for given R, C and VDD
values.
FIGURE 7-5: EXTERNAL RC
OSCILLATOR MODE
7.2.5 INTERNAL 4 MHz RC OSCILLATOR
The internal RC oscillator provides a fixed 4 MHz
(nominal) system clock at VDD = 5V and 25°C, (see
Section 10.0 “Electrical Characteristics” for
information on variation over voltage and temperature).
In addition, a calibration instruction is programmed into
the last address of memory, which contains the
calibration value for the internal RC oscillator. This
location is always uncode protected, regardless of the
code-protect settings. This value is programmed as a
MOVLW XX instruction where XX is the calibration value,
and is placed at the Reset vector. This will load the W
register with the calibration value upon Reset and the
PC will then roll over to the users program at address
0x000. The user then has the option of writing the value
to the OSCCAL Register (05h) or ignoring it.
OSCCAL, when written to with the calibration value, will
“trim” the internal oscillator to remove process variation
from the oscillator frequency.
For the PIC12F508/509/16F505 devices, only bits
<7:1> of OSCCAL are implemented. Bits CAL6-CAL0
are used for calibration. Adjusting CAL6-CAL0 from
0000000’ to ‘1111111’ changes the clock speed. See
Register 4-5 for more information.
VDD
REXT
CEXT
VSS
OSC1 Internal
clock
PIC16F505
N
FOSC/4 OSC2/CLKOUT
PIC12F508
PIC12F509
Note: Erasing the device will also erase the pre-
programmed internal calibration value for
the internal oscillator. The calibration
value must be read prior to erasing the
part so it can be reprogrammed correctly
later.
Note: The 0 bit of OSCCAL is unimplemented
and should be written as ‘0’ when
modifying OSCCAL for compatibility with
future devices.
© 2009 Microchip Technology Inc. DS41236E-page 47
PIC12F508/509/16F505
7.3 Reset
The device differentiates between various kinds of
Reset:
Power-on Reset (POR)
•MCLR
Reset during normal operation
•MCLR
Reset during Sleep
WDT time-out Reset during normal operation
WDT time-out Reset during Sleep
Wake-up from Sleep on pin change
Some registers are not reset in any way, they are
unknown on POR and unchanged in any other Reset.
Most other registers are reset to “Reset state” on
Power-on Reset (POR), MCLR, WDT or Wake-up on
pin change Reset during normal operation. They are
not affected by a WDT Reset during Sleep or MCLR
Reset during Sleep, since these Resets are viewed as
resumption of normal operation. The exceptions to this
are TO, PD and RBWUF/GPWUF bits. They are set or
cleared differently in different Reset situations. These
bits are used in software to determine the nature of
Reset. See Table 7-4 for a full description of Reset
states of all registers.
TABLE 7-3: RESET CONDITIONS FOR REGISTERS – PIC12F508/509
Register Address Power-on Reset MCLR Reset, WDT Time-out,
Wake-up On Pin Change
W—qqqq qqqu(1) qqqq qqqu(1)
INDF 00h xxxx xxxx uuuu uuuu
TMR0 01h xxxx xxxx uuuu uuuu
PC 02h 1111 1111 1111 1111
STATUS 03h 0001 1xxx q00q quuu(2), (3)
FSR(4) 04h 110x xxxx 11uu uuuu
FSR(5) 04h 111x xxxx 111u uuuu
OSCCAL 05h 1111 111- uuuu uuu-
GPIO 06h --xx xxxx --uu uuuu
OPTION 1111 1111 1111 1111
TRIS --11 1111 --11 1111
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of
memory.
2: See Table 7-5 for Reset value for specific conditions.
3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
4: PIC12F509 only.
5: PIC12F508 only.
PIC12F508/509/16F505
DS41236E-page 48 © 2009 Microchip Technology Inc.
TABLE 7-4: RESET CONDITIONS FOR REGISTERS – PIC16F505
TABLE 7-5: RESET CONDITION FOR SPECIAL REGISTERS
Register Address Power-on Reset MCLR Reset, WDT Time-out,
Wake-up On Pin Change
W—qqqq qqqu(1) qqqq qqqu(1)
INDF 00h xxxx xxxx uuuu uuuu
TMR0 01h xxxx xxxx uuuu uuuu
PC 02h 1111 1111 1111 1111
STATUS 03h 0001 1xxx q00q quuu(2), (3)
FSR 04h 100x xxxx 1uuu uuuu
OSCCAL 05h 1111 111- uuuu uuu-
PORTB 06h --xx xxxx --uu uuuu
PORTC 07h --xx xxxx --uu uuuu
OPTION 1111 1111 1111 1111
TRISB --11 1111 --11 1111
TRISC --11 1111 --11 1111
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of
memory.
2: See Table 7-5 for Reset value for specific conditions.
3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
STATUS Addr: 03h PCL Addr: 02h
Power-on Reset 0001 1xxx 1111 1111
MCLR Reset during normal operation 000u uuuu 1111 1111
MCLR Reset during Sleep 0001 0uuu 1111 1111
WDT Reset during Sleep 0000 0uuu 1111 1111
WDT Reset normal operation 0000 uuuu 1111 1111
Wake-up from Sleep on pin change 1001 0uuu 1111 1111
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’.
© 2009 Microchip Technology Inc. DS41236E-page 49
PIC12F508/509/16F505
7.3.1 MCLR ENABLE
This Configuration bit, when unprogrammed (left in the
1’ state), enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
VDD and the pin is assigned to be an input only. See
Figure 7-6.
FIGURE 7-6: MCLR SELECT
7.4 Power-on Reset (POR)
The PIC12F508/509/16F505 devices incorporate an
on-chip Power-on Reset (POR) circuitry, which
provides an internal chip Reset for most power-up
situations.
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper
operation. To take advantage of the internal POR,
program the (GP3/RB3)/MCLR/VPP pin as MCLR and
tie through a resistor to VDD, or program the pin as
(GP3/RB3). An internal weak pull-up resistor is
implemented using a transistor (refer to Table 10-2 for
the pull-up resistor ranges). This will eliminate external
RC components usually needed to create a Power-on
Reset. A maximum rise time for VDD is specified. See
Section 10.0 “Electrical Characteristics” for details.
When the devices start normal operation (exit the
Reset condition), device operating parameters
(voltage, frequency, temperature,...) must be met to
ensure operation. If these conditions are not met, the
devices must be held in Reset until the operating
parameters are met.
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 7-7.
The Power-on Reset circuit and the Device Reset
Timer (see Section 7.5 “Device Reset Timer (DRT)”)
circuit are closely related. On power-up, the Reset latch
is set and the DRT is reset. The DRT timer begins
counting once it detects MCLR to be high. After the
time-out period, which is typically 18 ms, it will reset the
Reset latch and thus end the on-chip Reset signal.
A power-up example where MCLR is held low is shown
in Figure 7-8. VDD is allowed to rise and stabilize before
bringing MCLR high. The chip will actually come out of
Reset TDRT msec after MCLR goes high.
In Figure 7-9, the on-chip Power-on Reset feature is
being used (MCLR and VDD are tied together or the pin
is programmed to be (GP3/RB3). The VDD is stable
before the start-up timer times out and there is no prob-
lem in getting a proper Reset. However, Figure 7-10
depicts a problem situation where VDD rises too slowly.
The time between when the DRT senses that MCLR is
high and when MCLR and VDD actually reach their full
value, is too long. In this situation, when the start-up
timer times out, VDD has not reached the VDD (min)
value and the chip may not function correctly. For such
situations, we recommend that external RC circuits be
used to achieve longer POR delay times (Figure 7-9).
For additional information, refer to Application Notes
AN522 “Power-Up Considerations” (DS00522) and
AN607 “Power-up Trouble Shooting (DS00607).
(GP3/RB3)/MCLR/VPP
MCLRE Internal MCLR
GPWU/RBWU
Note: When the devices start normal operation
(exit the Reset condition), device operat-
ing parameters (voltage, frequency, tem-
perature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.
PIC12F508/509/16F505
DS41236E-page 50 © 2009 Microchip Technology Inc.
FIGURE 7-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
FIGURE 7-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
FIGURE 7-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE
TIME
SQ
RQ
VDD
(GP3/RB3)/MCLR/VPP
Power-up
Detect POR (Power-on Reset)
WDT Reset CHIP Reset
MCLRE
Wake-up on pin Change Reset
Start-up Timer
(10 μs or 18 ms)
WDT Time-out
Pin Change
Sleep
MCLR Reset
VDD
MCLR
Internal POR
DRT Time-out
Internal Reset
TDRT
VDD
MCLR
Internal POR
DRT Time-out
Internal Reset
TDRT
© 2009 Microchip Technology Inc. DS41236E-page 51
PIC12F508/509/16F505
FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE
TIME
VDD
MCLR
Internal POR
DRT Time-out
Internal Reset
TDRT
V1
Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final
value. In this example, the chip will reset properly if, and only if, V1 VDD min.
PIC12F508/509/16F505
DS41236E-page 52 © 2009 Microchip Technology Inc.
7.5 Device Reset Timer (DRT)
On the PIC12F508/509/16F505 devices, the DRT runs
any time the device is powered up. DRT runs from
Reset and varies based on oscillator selection and
Reset type (see Table 7-6).
The DRT operates on an internal RC oscillator. The
processor is kept in Reset as long as the DRT is active.
The DRT delay allows VDD to rise above VDD min. and
for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic resona-
tors require a certain time after power-up to establish a
stable oscillation. The on-chip DRT keeps the devices in
a Reset condition for approximately 18 ms after MCLR
has reached a logic high (VIH MCLR) level.
Programming (GP3/RB3)/MCLR/VPP as MCLR and
using an external RC network connected to the MCLR
input is not required in most cases. This allows savings
in cost-sensitive and/or space restricted applications, as
well as allowing the use of the (GP3/RB3)/MCLR/VPP
pin as a general purpose input.
The Device Reset Time delays will vary from chip-to-
chip due to VDD, temperature and process variation.
See AC parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out from Sleep. This is particularly important for
applications using the WDT to wake from Sleep mode
automatically.
Reset sources are POR, MCLR, WDT time-out and
wake-up on pin change. See Section 7.9.2 “Wake-up
from Sleep”, Notes 1, 2 and 3.
7.6 Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator, which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the (GP5/RB5)/OSC1/CLKIN
pin and the internal 4 MHz oscillator. This means that
the WDT will run even if the main processor clock has
been stopped, for example, by execution of a SLEEP
instruction. During normal operation or Sleep, a WDT
Reset or wake-up Reset, generates a device Reset.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer Reset.
The WDT can be permanently disabled by
programming the configuration WDTE as a ‘0’ (see
Section 7.1 “Configuration Bits). Refer to the
PIC12F508/509/16F505 Programming Specifications
to determine how to access the Configuration Word.
TABLE 7-6: DRT (DEVICE RESET TIMER
PERIOD)
7.6.1 WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by
writing to the OPTION register. Thus, a time-out period
of a nominal 2.3 seconds can be realized. These
periods vary with temperature, VDD and part-to-part
process variations (see DC specs).
Under worst case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
7.6.2 WDT PROGRAMMING
CONSIDERATIONS
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device Reset.
The SLEEP instruction resets the WDT and the post-
scaler, if assigned to the WDT. This gives the maximum
Sleep time before a WDT wake-up Reset.
Oscillator
Configuration POR Reset Subsequent
Resets
INTOSC, EXTRC 18 ms (typical) 10 μs (typical)
HS(1), XT, LP 18 ms (typical) 18 ms (typical)
EC(1) 18 ms (typical) 10 μs (typical)
Note 1: PIC16F505 only.
© 2009 Microchip Technology Inc. DS41236E-page 53
PIC12F508/509/16F505
FIGURE 7-11: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 7-7: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
Power-On
Reset
Value on
All Other
Resets
N/A OPTION(1) GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
N/A OPTION(2) RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer. – = unimplemented, read as ‘0’, u = unchanged.
Note 1: PIC12F508/509 only.
2: PIC16F505 only.
(Figure 6-5)
Postscaler
Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
WDT Time-out
Watchdog
Time
From Timer0 Clock Source
WDT Enable
Configuration
Bit
PSA
Postscaler
8-to-1 MUX PS<2:0>
(Figure 6-4)
To Timer0
0
1M
U
X
1
0
PSA
MUX
PIC12F508/509/16F505
DS41236E-page 54 © 2009 Microchip Technology Inc.
7.7 Time-out Sequence, Power-down
and Wake-up from Sleep Status
Bits (TO, PD, GPWUF/RBWUF)
The TO, PD and (GPWUF/RBWUF) bits in the
STATUS register can be tested to determine if a Reset
condition has been caused by a Power-up condition, a
MCLR or Watchdog Timer (WDT) Reset.
TABLE 7-8: TO/PD/(GPWUF/RBWUF)
STATUS AFTER RESET
7.8 Reset on Brown-out
A brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and then
recovers. The device should be reset in the event of a
brown-out.
To reset PIC12F508/509/16F505 devices when a
brown-out occurs, external brown-out protection
circuits may be built, as shown in Figure 7-12 and
Figure 7-13.
FIGURE 7-12: BROWN-OUT
PROTECTION CIRCUIT 1
FIGURE 7-13: BROWN-OUT
PROTECTION CIRCUIT 2
FIGURE 7-14: BROWN-OUT
PROTECTION CIRCUIT 3
GPWUF/
RBWUF TO PD Reset Caused By
000WDT wake-up from Sleep
00uWDT time-out (not from
Sleep)
010MCLR wake-up from Sleep
011Power-up
0uuMCLR not during Sleep
110Wake-up from Sleep on pin
change
Legend: u = unchanged
Note 1: The TO, PD and GPWUF/RBWUF bits
maintain their status (u) until a Reset
occurs. A low-pulse on the MCLR input
does not change the TO, PD and
GPWUF/RBWUF Status bits.
Note 1: This circuit will activate Reset when VDD goes
below Vz + 0.7V (where Vz = Zener voltage).
2: Pin must be confirmed as MCLR.
33k
10k
40k(1)
VDD
MCLR(2)
PIC16F505
VDD
Q1
PIC12F508
PIC12F509
Note 1: This brown-out circuit is less expensive,
although less accurate. Transistor Q1 turns
off when VDD is below a certain level such
that:
2: Pin must be confirmed as MCLR.
VDD R1
R1 + R2 = 0.7V
R2 40k(1)
VDD
MCLR(2)
PIC16F505
R1
Q1
VDD
PIC12F508
PIC12F509
Note: This brown-out protection circuit employs
Microchip Technology’s MCP809 micro-
controller supervisor. There are 7 different
trip point selections to accommodate 5V to
3V systems.
MCLR
PIC16F505
VDD
VDD
VSS
RST
MCP809
VDD
Bypass
Capacitor
PIC12F508
PIC12F509
© 2009 Microchip Technology Inc. DS41236E-page 55
PIC12F508/509/16F505
7.9 Power-down Mode (Sleep)
A device may be powered down (Sleep) and later
powered up (wake-up from Sleep).
7.9.1 SLEEP
The Power-Down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low or high-impedance).
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the
(GP3/RB3)/MCLR/VPP pin must be at a logic high
level if MCLR is enabled.
7.9.2 WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of
the following events:
1. An external Reset input on (GP3/RB3)/MCLR/
VPP pin, when configured as MCLR.
2. A Watchdog Timer time-out Reset (if WDT was
enabled).
3. A change on input pin GP0/RB0, GP1/RB1,
GP3/RB3 or RB4 when wake-up on change is
enabled.
These events cause a device Reset. The TO, PD and
GPWUF/RBWUF bits can be used to determine the
cause of device Reset. The TO bit is cleared if a WDT
time-out occurred (and caused wake-up). The PD bit,
which is set on power-up, is cleared when SLEEP is
invoked. The GPWUF/RBWUF bit indicates a change
in state while in Sleep at pins GP0/RB0, GP1/RB1,
GP3/RB3 or RB4 (since the last file or bit operation on
GP/RB port).
The WDT is cleared when the device wakes from
Sleep, regardless of the wake-up source.
7.10 Program Verification/Code
Protection
If the code protection bit has not been programmed, the
on-chip program memory can be read out for
verification purposes.
The first 64 locations and the last location (OSCCAL)
can be read, regardless of the code protection bit
setting.
The last memory location can be read regardless of the
code protection bit setting on the PIC12F508/509/
16F505 devices.
7.11 ID Locations
Four memory locations are designated as ID locations
where the user can store checksum or other code
identification numbers. These locations are not
accessible during normal execution, but are readable
and writable during Program/Verify.
Use only the lower 4 bits of the ID locations and always
program the upper 8 bits as ‘0’s.
7.12 In-Circuit Serial Programming™
The PIC12F508/509/16F505 microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock and data,
and three other lines for power, ground and the
programming voltage. This allows customers to manu-
facture boards with unprogrammed devices and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware, or
a custom firmware, to be programmed.
The devices are placed into a Program/Verify mode by
holding the GP1/RB1 and GP0/RB0 pins low while
raising the MCLR (VPP) pin from VIL to VIHH (see
programming specification). GP1/RB1 becomes the
programming clock and GP0/RB0 becomes the
programming data. Both GP1/RB1 and GP0/RB0 are
Schmitt Trigger inputs in this mode.
After Reset, a 6-bit command is then supplied to the
device. Depending on the command, 14 bits of program
data are then supplied to or from the device, depending
if the command was a Load or a Read. For complete
details of serial programming, please refer to the
PIC12F508/509/16F505 Programming Specifications.
A typical In-Circuit Serial Programming connection is
shown in Figure 7-15.
Note: A Reset generated by a WDT time-out
does not drive the MCLR pin low.
Note: Caution: Right before entering Sleep,
read the input pins. When in Sleep, wake-
up occurs when the values at the pins
change from the state they were in at the
last reading. If a wake-up on change
occurs and the pins are not read before re-
entering Sleep, a wake-up will occur
immediately even if no pins change while
in Sleep mode.
PIC12F508/509/16F505
DS41236E-page 56 © 2009 Microchip Technology Inc.
FIGURE 7-15: TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
External
Connector
Signals
To Normal
Connections
To Normal
Connections
PIC16F505
VDD
VSS
MCLR/VPP
GP1/RB1
GP0/RB0
+5V
0V
VPP
CLK
Data I/O
VDD
PIC12F508
PIC12F509
© 2009 Microchip Technology Inc. DS41236E-page 57
PIC12F508/509/16F505
8.0 INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is
comprised of three basic categories.
Byte-oriented operations
Bit-oriented operations
Literal and control operations
Each PIC16 instruction is a 12-bit word divided into an
opcode, which specifies the instruction type, and one
or more operands which further specify the operation
of the instruction. The formats for each of the catego-
ries is presented in Figure 8-1, while the various
opcode fields are summarized in Table 8-1.
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is1’, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ‘f’ represents the number of the
file in which the bit is located.
For literal and control operations, ‘k’ represents an
8 or 9-bit constant or literal value.
TABLE 8-1: OPCODE FIELD
DESCRIPTIONS
All instructions are executed within a single instruction
cycle, unless a conditional test is true or the program
counter is changed as a result of an instruction. In this
case, the execution takes two instruction cycles. One
instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 μs. If a conditional test is
true or the program counter is changed as a result of an
instruction, the instruction execution time is 2 μs.
Figure 8-1 shows the three general formats that the
instructions can have. All examples in the figure use
the following format to represent a hexadecimal
number:
0xhhh
where ‘h’ signifies a hexadecimal digit.
FIGURE 8-1: GENERAL FORMAT FOR
INSTRUCTIONS
Field Description
f Register file address (0x00 to 0x7F)
W Working register (accumulator)
b Bit address within an 8-bit file register
k Literal field, constant data or label
x Don’t care location (= 0 or 1)
The assembler will generate code with x = 0. It is
the recommended form of use for compatibility with
all Microchip software tools.
d Destination select;
d = 0 (store result in W)
d = 1 (store result in file register ‘f’)
Default is d = 1
label Label name
TOS Top-of-Stack
PC Program Counter
WDT Watchdog Timer counter
TO Time-out bit
PD Power-down bit
dest Destination, either the W register or the specified
register file location
[ ] Options
( ) Contents
Assigned to
< > Register bit field
In the set of
italics User defined term (font is courier)
Byte-oriented file register operations
11 6 5 4 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 5-bit file register address
Bit-oriented file register operations
11 8 7 5 4 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address
f = 5-bit file register address
Literal and control operations (except GOTO)
11 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
Literal and control operationsGOTO instruction
11 9 8 0
OPCODE k (literal)
k = 9-bit immediate value
PIC12F508/509/16F505
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TABLE 8-2: INSTRUCTION SET SUMMARY
Mnemonic,
Operands Description Cycles 12-Bit Opcode Status
Affected Notes
MSb LSb
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
0001
0001
0000
0000
0010
0000
0010
0010
0011
0001
0010
0000
0000
0011
0011
0000
0011
0001
11df
01df
011f
0100
01df
11df
11df
10df
11df
00df
00df
001f
0000
01df
00df
10df
10df
10df
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C, DC, Z
Z
Z
Z
Z
Z
None
Z
None
Z
Z
None
None
C
C
C, DC, Z
None
Z
1, 2, 4
2, 4
4
2, 4
2, 4
2, 4
2, 4
2, 4
2, 4
1, 4
2, 4
2, 4
1, 2, 4
2, 4
2, 4
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1(2)
1(2)
0100
0101
0110
0111
bbbf
bbbf
bbbf
bbbf
ffff
ffff
ffff
ffff
None
None
None
None
2, 4
2, 4
LITERAL AND CONTROL OPERATIONS
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
XORLW
k
k
k
k
k
k
f
k
AND literal with W
Call Subroutine
Clear Watchdog Timer
Unconditional branch
Inclusive OR literal with W
Move literal to W
Load OPTION register
Return, place literal in W
Go into Standby mode
Load TRIS register
Exclusive OR literal to W
1
2
1
2
1
1
1
2
1
1
1
1110
1001
0000
101k
1101
1100
0000
1000
0000
0000
1111
kkkk
kkkk
0000
kkkk
kkkk
kkkk
0000
kkkk
0000
0000
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
0010
kkkk
0011
0fff
kkkk
Z
None
TO, PD
None
Z
None
None
None
TO, PD
None
Z
1
3
Note 1: The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for
GOTO. See Section 4.7 “Program Counter”.
2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and
is driven low by an external device, the data will be written back with a ‘0’.
3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state
latches of PORTB. A ‘1 forces the pin to a high-impedance state and disables the output buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared (if assigned to TMR0).
© 2009 Microchip Technology Inc. DS41236E-page 59
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ADDWF Add W and f
Syntax: [ label ] ADDWF f,d
Operands: 0 f 31
d ∈ [0,1]
Operation: (W) + (f) (dest)
Status Affected: C, DC, Z
Description: Add the contents of the W register
and register ‘f’. If ‘d’ is’0’, the result
is stored in the W register. If ‘d’ is
1’, the result is stored back in
register ‘f’.
ANDLW AND literal with W
Syntax: [ label ] ANDLW k
Operands: 0 k 255
Operation: (W).AND. (k) (W)
Status Affected: Z
Description: The contents of the W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0 f 31
d [0,1]
Operation: (W) .AND. (f) (dest)
Status Affected: Z
Description: The contents of the W register are
AND’ed with register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W register.
If ‘d’ is1’, the result is stored back
in register ‘f’.
BCF Bit Clear f
Syntax: [ label ] BCF f,b
Operands: 0 f 31
0 b 7
Operation: 0 (f<b>)
Status Affected: None
Description: Bit ‘b’ in register ‘f’ is cleared.
BSF Bit Set f
Syntax: [ label ] BSF f,b
Operands: 0 f 31
0 b 7
Operation: 1 (f<b>)
Status Affected: None
Description: Bit ‘b’ in register ‘f’ is set.
BTFSC Bit Test f, Skip if Clear
Syntax: [ label ] BTFSC f,b
Operands: 0 f 31
0 b 7
Operation: skip if (f<b>) = 0
Status Affected: None
Description: If bit ‘b’ in register ‘f’ is ‘0’, then the
next instruction is skipped.
If bit ‘b’ is ‘0’, then the next instruc-
tion fetched during the current
instruction execution is discarded,
and a NOP is executed instead,
making this a two-cycle instruction.
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DS41236E-page 60 © 2009 Microchip Technology Inc.
BTFSS Bit Test f, Skip if Set
Syntax: [ label ] BTFSS f,b
Operands: 0 f 31
0 b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Description: If bit ‘b’ in register ‘f’ is ‘1’, then the
next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a NOP is executed instead,
making this a two-cycle instruction.
CALL Subroutine Call
Syntax: [ label ] CALL k
Operands: 0 k 255
Operation: (PC) + 1 Top-of-Stack;
k PC<7:0>;
(STATUS<6:5>) PC<10:9>;
0 PC<8>
Status Affected: None
Description: Subroutine call. First, return
address (PC + 1) is PUSHed onto
the stack. The eight-bit immediate
address is loaded into PC
bits <7:0>. The upper bits
PC<10:9> are loaded from
STATUS<6:5>, PC<8> is cleared.
CALL is a two-cycle instruction.
CLRF Clear f
Syntax: [ label ] CLRF f
Operands: 0 f 31
Operation: 00h (f);
1 Z
Status Affected: Z
Description: The contents of register ‘f’ are
cleared and the Z bit is set.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h (W);
1 Z
Status Affected: Z
Description: The W register is cleared. Zero bit
(Z) is set.
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h WDT;
0 WDT prescaler (if assigned);
1 TO;
1 PD
Status Affected: TO, PD
Description: The CLRWDT instruction resets the
WDT. It also resets the prescaler, if
the prescaler is assigned to the
WDT and not Timer0. Status bits
TO and PD are set.
COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 f 31
d [0,1]
Operation: (f) (dest)
Status Affected: Z
Description: The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back in
register ‘f’.
© 2009 Microchip Technology Inc. DS41236E-page 61
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DECF Decrement f
Syntax: [ label ] DECF f,d
Operands: 0 f 31
d [0,1]
Operation: (f) – 1 (dest)
Status Affected: Z
Description: Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is1’, the result is
stored back in register ‘f’.
DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0 f 31
d [0,1]
Operation: (f) – 1 d; skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
1’, the result is placed back in
register ‘f’.
If the result is ‘0, the next instruc-
tion, which is already fetched, is
discarded and a NOP is executed
instead making it a two-cycle
instruction.
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 k 511
Operation: k PC<8:0>;
STATUS<6:5> PC<10:9>
Status Affected: None
Description: GOTO is an unconditional branch.
The 9-bit immediate value is
loaded into PC bits <8:0>. The
upper bits of PC are loaded from
STATUS<6:5>. GOTO is a two-
cycle instruction.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0 f 31
d [0,1]
Operation: (f) + 1 (dest)
Status Affected: Z
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
1’, the result is placed back in
register ‘f’.
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0 f 31
d [0,1]
Operation: (f) + 1 (dest), skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
1’, the result is placed back in
register ‘f’.
If the result is ‘0’, then the next
instruction, which is already
fetched, is discarded and a NOP is
executed instead making it a
two-cycle instruction.
IORLW Inclusive OR literal with W
Syntax: [ label ] IORLW k
Operands: 0 k 255
Operation: (W) .OR. (k) (W)
Status Affected: Z
Description: The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the
W register.
PIC12F508/509/16F505
DS41236E-page 62 © 2009 Microchip Technology Inc.
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0 f 31
d [0,1]
Operation: (W).OR. (f) (dest)
Status Affected: Z
Description: Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’,
the result is placed back in register
‘f’.
MOVF Move f
Syntax: [ label ] MOVF f,d
Operands: 0 f 31
d [0,1]
Operation: (f) (dest)
Status Affected: Z
Description: The contents of register ‘f’ are
moved to destination ‘d’. If ‘d’ is ‘0’,
destination is the W register. If ‘d
is ‘1’, the destination is file
register ‘f’. ‘d’ = 1 is useful as a
test of a file register, since status
flag Z is affected.
MOVLW Move Literal to W
Syntax: [ label ] MOVLW k
Operands: 0 k 255
Operation: k (W)
Status Affected: None
Description: The eight-bit literal ‘k’ is loaded
into the W register. The “don’t
cares” will assembled as ‘0’s.
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Operands: 0 f 31
Operation: (W) (f)
Status Affected: None
Description: Move data from the W register to
register ‘f’.
NOP No Operation
Syntax: [ label ] NOP
Operands: None
Operation: No operation
Status Affected: None
Description: No operation.
OPTION Load OPTION Register
Syntax: [ label ] OPTION
Operands: None
Operation: (W) OPTION
Status Affected: None
Description: The content of the W register is
loaded into the OPTION register.
Q
© 2009 Microchip Technology Inc. DS41236E-page 63
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RETLW Return with Literal in W
Syntax: [ label ] RETLW k
Operands: 0 k 255
Operation: k (W);
TOS PC
Status Affected: None
Description: The W register is loaded with the
eight-bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address). This
is a two-cycle instruction.
RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 f 31
d [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
1’, the result is stored back in
register ‘f’.
RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 f 31
d [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are
rotated one bit to the right through
the Carry flag. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
1’, the result is placed back in
register ‘f’.
Cregister ‘f’
Cregister ‘f’
SLEEP Enter SLEEP Mode
Syntax: [label ]SLEEP
Operands: None
Operation: 00h WDT;
0 WDT prescaler;
1 TO;
0 PD
Status Affected: TO, PD, RBWUF
Description: Time-out Status bit (TO) is set. The
Power-down Status bit (PD) is
cleared.
RBWUF is unaffected.
The WDT and its prescaler are
cleared.
The processor is put into Sleep
mode with the oscillator stopped.
See Section 7.9 “Power-down
Mode (Sleep)” on Sleep for more
details.
SUBWF Subtract W from f
Syntax: [label ] SUBWF f,d
Operands: 0 f 31
d [0,1]
Operation: (f) – (W) → (dest)
Status Affected: C, DC, Z
Description: Subtract (2’s complement method)
the W register from register ‘f’. If ‘d’
is ‘0’, the result is stored in the W
register. If ‘d’ is1’, the result is
stored back in register ‘f’.
SWAPF Swap Nibbles in f
Syntax: [ label ] SWAPF f,d
Operands: 0 f 31
d [0,1]
Operation: (f<3:0>) (dest<7:4>);
(f<7:4>) (dest<3:0>)
Status Affected: None
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
0’, the result is placed in W
register. If ‘d’ is1’, the result is
placed in register ‘f’.
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DS41236E-page 64 © 2009 Microchip Technology Inc.
TRIS Load TRIS Register
Syntax: [ label ] TRIS f
Operands: f = 6
Operation: (W) TRIS register f
Status Affected: None
Description: TRIS register ‘f’ (f = 6 or 7) is
loaded with the contents of the W
register
XORLW Exclusive OR literal with W
Syntax: [label ]XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k → (W)
Status Affected: Z
Description: The contents of the W register are
XOR’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
XORWF Exclusive OR W with f
Syntax: [ label ] XORWF f,d
Operands: 0 f 31
d [0,1]
Operation: (W) .XOR. (f) → (dest)
Status Affected: Z
Description: Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
0’, the result is stored in the W
register. If ‘d’ is1’, the result is
stored back in register ‘f’.
© 2009 Microchip Technology Inc. DS41236E-page 65
PIC12F508/509/16F505
9.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C18 and MPLAB C30 C Compilers
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
•Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB REAL ICE™ In-Circuit Emulator
In-Circuit Debugger
- MPLAB ICD 2
Device Programmers
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
Low-Cost Demonstration and Development
Boards and Evaluation Kits
9.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
A full-featured editor with color-coded context
A multiple project manager
Customizable data windows with direct edit of
contents
High-level source code debugging
Visual device initializer for easy register
initialization
Mouse over variable inspection
Drag and drop variables from source to watch
windows
Extensive on-line help
Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
The MPLAB IDE allows you to:
Edit your source files (either assembly or C)
One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
PIC12F508/509/16F505
DS41236E-page 66 © 2009 Microchip Technology Inc.
9.2 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
Integration into MPLAB IDE projects
User-defined macros to streamline
assembly code
Conditional assembly for multi-purpose
source files
Directives that allow complete control over the
assembly process
9.3 MPLAB C18 and MPLAB C30
C Compilers
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI C compilers for
Microchip’s PIC18 and PIC24 families of microcon-
trollers and the dsPIC30 and dsPIC33 family of digital
signal controllers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
9.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
Efficient linking of single libraries instead of many
smaller files
Enhanced code maintainability by grouping
related modules together
Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
9.5 MPLAB ASM30 Assembler, Linker
and Librarian
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
Support for the entire dsPIC30F instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
9.6 MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by
simulating the PIC MCUs and dsPIC® DSCs on an
instruction level. On any given instruction, the data
areas can be examined or modified and stimuli can be
applied from a comprehensive stimulus controller.
Registers can be logged to files for further run-time
analysis. The trace buffer and logic analyzer display
extend the power of the simulator to record and track
program execution, actions on I/O, most peripherals
and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
© 2009 Microchip Technology Inc. DS41236E-page 67
PIC12F508/509/16F505
9.7 MPLAB ICE 2000
High-Performance
In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC
microcontrollers. Software control of the MPLAB ICE
2000 In-Circuit Emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitor-
ing features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
9.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be supported,
and new features will be added, such as software break-
points and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
9.9 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers cost-
effective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by setting breakpoints, single step-
ping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
9.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
PIC12F508/509/16F505
DS41236E-page 68 © 2009 Microchip Technology Inc.
9.11 PICSTART Plus Development
Programmer
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
9.12 PICkit 2 Development Programmer
The PICkit™ 2 Development Programmer is a low-cost
programmer and selected Flash device debugger with
an easy-to-use interface for programming many of
Microchip’s baseline, mid-range and PIC18F families
of Flash memory microcontrollers. The PICkit 2 Starter
Kit includes a prototyping development board, twelve
sequential lessons, software and HI-TECH’s PICC™
Lite C compiler, and is designed to help get up to speed
quickly using PIC® microcontrollers. The kit provides
everything needed to program, evaluate and develop
applications using Microchip’s powerful, mid-range
Flash memory family of microcontrollers.
9.13 Demonstration, Development and
Evaluation Boards
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and
demonstration software for analog filter design,
KEELOQ® security ICs, CAN, IrDA®, PowerSmart
battery management, SEEVAL® evaluation system,
Sigma-Delta ADC, flow rate sensing, plus many more.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
© 2009 Microchip Technology Inc. DS41236E-page 69
PIC12F508/509/16F505
10.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
Ambient temperature under bias..........................................................................................................-40°C to +125°C
Storage temperature ............................................................................................................................-65°C to +150°C
Voltage on VDD with respect to VSS ...............................................................................................................0 to +6.5V
Voltage on MCLR with respect to VSS..........................................................................................................0 to +13.5V
Voltage on all other pins with respect to VSS ............................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ..................................................................................................................................800 mW
Max. current out of VSS pin ................................................................................................................................200 mA
Max. current into VDD pin ...................................................................................................................................150 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)...........................................................................................................±20 mA
Max. output current sunk by any I/O pin ..............................................................................................................25 mA
Max. output current sourced by any I/O pin .........................................................................................................25 mA
Max. output current sourced by I/O port ..............................................................................................................75 mA
Max. output current sunk by I/O port ...................................................................................................................75 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD IOH} + {(VDD – VOH) x IOH} + (VOL x IOL)
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
50 S S 40”
PIC12F508/509/16F505
DS41236E-page 70 © 2009 Microchip Technology Inc.
FIGURE 10-1: PIC12F508/509/16F505 VOLTAGE-FREQUENCY GRAPH, -40°C TA +125°C
FIGURE 10-2: MAXIMUM OSCILLATOR FREQUENCY TABLE
6.0
2.5
4.0
3.0
0
3.5
4.5
5.0
5.5
410
Frequency (MHz)
VDD
20
(Volts)
25
2.0
8
(PIC16F505 only)
0200 kHz 4 MHz 20 MHz
Frequency (MHz)
HS(1)
EXTRC
XT
LP
Oscillator Mode
EC(1)
INTOSC
Note 1: For PIC16F505 only.
© 2009 Microchip Technology Inc. DS41236E-page 71
PIC12F508/509/16F505
10.1 DC Characteristics: PIC12F508/509/16F505 (Industrial)
DC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C TA +85°C (industrial)
Param
No. Sym. Characteristic Min. Typ(1) Max. Units Conditions
D001 VDD Supply Voltage 2.0 5.5 V See Figure 10-1
D002 VDR RAM Data Retention Voltage(2) 1.5* V Device in Sleep mode
D003 VPOR VDD Start Voltage to ensure
Power-on Reset Vss V See Section 7.4 "Power-on
Reset (POR)" for details
D004 SVDD VDD Rise Rate to ensure
Power-on Reset 0.05* V/ms See Section 7.4 "Power-on
Reset (POR)" for details
D010 IDD Supply Current(3,4)
175
0.625 275
1.1
μA
mA FOSC = 4 MHz, VDD = 2.0V
FOSC = 4 MHz, VDD = 5.0V
500
1.5 650
2.2
μA
mA FOSC = 10 MHz, VDD = 3.0V
FOSC = 20 MHz, VDD = 5.0V
(PIC16F505 only)
11
38 20
54
μA
μAFOSC = 32 kHz, VDD = 2.0V
FOSC = 32 kHz, VDD = 5.0V
D020 IPD Power-down Current(5)
0.1
0.35 1.2
2.4
μA
μAVDD = 2.0V
VDD = 5.0V
D022 IWDT WDT Current(5)
1.0
7.0 3.0
16.0
μA
μAVDD = 2.0V
VDD = 5.0V
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design
guidance only and is not tested.
2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
4: The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR =
VDD; WDT enabled/disabled as specified.
5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep
mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep.
PIC12F508/509/16F505
DS41236E-page 72 © 2009 Microchip Technology Inc.
10.2 DC Characteristics: PIC12F508/509/16F505 (Extended)
DC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C TA +125°C (extended)
Param
No. Sym. Characteristic Min. Typ(1) Max. Units Conditions
D001 VDD Supply Voltage 2.0 5.5 V See Figure 10-1
D002 VDR RAM Data Retention Voltage(2) 1.5* V Device in Sleep mode
D003 VPOR VDD Start Voltage to ensure
Power-on Reset —Vss VSee Section 7.4 "Power-on
Reset (POR)" for details
D004 SVDD VDD Rise Rate to ensure
Power-on Reset 0.05* V/ms See Section 7.4 "Power-on
Reset (POR)" for details
D010 IDD Supply Current(3,4)
175
0.625 275
1.1
μA
mA FOSC = 4 MHz, VDD = 2.0V
FOSC = 4 MHz, VDD = 5.0V
500
1.5 650
2.2
μA
mA FOSC = 10 MHz, VDD = 3.0V
FOSC = 20 MHz, VDD = 5.0V
(PIC16F515 only)
11
38 26
110
μA
μAFOSC = 32 kHz, VDD = 2.0V
FOSC = 32 kHz, VDD = 5.0V
D020 IPD Power-down Current(5)
0.1
0.35 9.0
15.0
μA
μAVDD = 2.0V
VDD = 5.0V
D022 IWDT WDT Current(5)
1.0
7.0 18
22
μA
μAVDD = 2.0V
VDD = 5.0V
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design
guidance only and is not tested.
2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
4: The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR =
VDD; WDT enabled/disabled as specified.
5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep
mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep.
Ema‘ cm anon agp rug on G 3 Wm a
© 2009 Microchip Technology Inc. DS41236E-page 73
PIC12F508/509/16F505
TABLE 10-1: DC CHARACTERISTICS: PIC12F508/509/16F505 (Industrial, Extended)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating temperature -40°C TA +85°C (industrial)
-40°C TA +125°C (extended)
Operating voltage VDD range as described in DC specification
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
VIL Input Low Voltage
I/O ports:
D030 with TTL buffer Vss 0.8V V For all 4.5 VDD 5.5V
D030A Vss 0.15 VDD V Otherwise
D031 with Schmitt Trigger buffer Vss 0.15 VDD V
D032 MCLR, T0CKI Vss 0.15 VDD V
D033 OSC1 (in EXTRC) Vss 0.15 VDD V(Note1)
D033 OSC1 (in HS) Vss 0.3 VDD V(Note1)
D033 OSC1 (in XT and LP) Vss 0.3 V (Note1)
VIH Input High Voltage
I/O ports:
D040 with TTL buffer 2.0 VDD V4.5 VDD 5.5V
D040A 0.25 VDD
+ 0.8 —V
DD V Otherwise
D041 with Schmitt Trigger buffer 0.85 VDD —VDD V For entire VDD range
D042 MCLR, T0CKI 0.85 VDD —VDD V
D043 OSC1 (in EXTRC) 0.85 VDD —VDD V(Note1)
D043 OSC1 (in HS) 0.7 VDD —VDD V(Note1)
D043 OSC1 (in XT and LP) 1.6 VDD V
D070 IPUR GPIO/PORTB weak pull-up
current(4) 50 250 400 μAVDD = 5V, VPIN = VSS
IIL Input Leakage Current(2), (3)
D060 I/O ports ± 1 μAVss VPIN VDD, Pin at high-impedance
D061 GP3/RB3/MCLRI(5) —± 0.7± 5 μAVss VPIN VDD
D063 OSC1 ± 5 μAVss VPIN VDD, XT, HS and LP oscillator
configuration
Output Low Voltage
D080 I/O ports/CLKOUT 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C
D080A 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40°C to +125°C
D083 OSC2 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40°C to +85°C
D083A 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40°C to +125°C
Output High Voltage
D090 I/O ports/CLKOUT(3) VDD – 0.7 V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C
D090A VDD0.7 V IOH = -2.5 mA, VDD = 4.5V, -40°C to +125°C
D092 OSC2 VDD – 0.7 V IOH = -1.3 mA, VDD = 4.5V, -40°C to +85°C
D092A VDD0.7 V IOH = -1.0 mA, VDD = 4.5V, -40°C to +125°C
Capacitive Loading Specs on
Output Pins
D100 OSC2 pin 15 pF In XT, HS and LP modes when external clock is
used to drive OSC1.
D101 All I/O pins and OSC2 50 pF
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12F508/509/
16F505 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating
conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: The specification applies to all weak pull-up devices, including the weak pull-up on GP3/MCLR. The current listed will be the same
whether GP3/MCLR is configured as GP3 with a weak pull-up or enabled as MCLR.
5: This specification applies when GP3/RB3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit
is higher than the standard I/O logic.
PIC12F508/509/16F505
DS41236E-page 74 © 2009 Microchip Technology Inc.
TABLE 10-2: PULL-UP RESISTOR RANGES – PIC12F508/509/16F505
VDD (Volts) Temperature (°C) Min. Typ. Max.
GP0(RBO)/GP1(RB1)
2.0 –40 73K 105K 186K
25 73K 113K 187K
85 82K 123K 190K
125 86K 132k 190K
5.5 –40 15K 21K 33K
25 15K 22K 34K
85 19K 26k 35K
125 23K 29K 35K
GP3(RB3)
2.0 –40 63K 81K 96K
25 77K 93K 116K
85 82K 96k 116K
125 86K 100K 119K
5.5 –40 16K 20k 22K
25 16K 21K 23K
85 24K 25k 28K
125 26K 27K 29K
* These parameters are characterized but not tested.
rnwxflz‘ ¢-‘- +‘+¢
© 2009 Microchip Technology Inc. DS41236E-page 75
PIC12F508/509/16F505
10.3 Timing Parameter Symbology and Load Conditions – PIC12F508/509/16F505
The timing parameter symbols have been created following one of the following formats:
FIGURE 10-3: LOAD CONDITIONS – PIC12F508/509/16F505
FIGURE 10-4: EXTERNAL CLOCK TIMING – PIC12F508/509/16F505
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase subscripts (pp) and their meanings:
pp
2to mcMCLR
ck CLKOUT osc Oscillator
cy Cycle time os OSC1
drt Device Reset Timer t0 T0CKI
io I/O port wdt Watchdog Timer
Uppercase letters and their meanings:
S
FFall PPeriod
HHigh RRise
I Invalid (high-impedance) V Valid
L Low Z High-impedance
CL
VSS
pin
Legend:
CL = 50 pF for all pins except OSC2
15 pF for OSC2 in XT, HS or LP
modes when external clock
is used to drive OSC1
OSC1
Q4 Q1 Q2 Q3 Q4 Q1
133
44
2
PIC12F508/509/16F505
DS41236E-page 76 © 2009 Microchip Technology Inc.
TABLE 10-3: EXTERNAL CLOCK TIMING REQUIREMENTS – PIC12F508/509/16F505
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C TA +85°C (industrial),
-40°C TA +125°C (extended)
Operating Voltage VDD range is described in Section 10.1 "Power-
on Reset (POR)"
Param
No. Sym. Characteristic Min. Typ(1) Max. Units Conditions
1A FOSC External CLKIN Frequency(2) DC 4 MHz XT Oscillator mode
DC 20 MHz EC, HS Oscillator mode
(PIC16F505 only)
DC 200 kHz LP Oscillator mode
Oscillator Frequency(2) 4 MHz EXTRC Oscillator mode
0.1 4 MHz XT Oscillator mode
4 20 MHz HS Oscillator mode (PIC16F505
only)
200 kHz LP Oscillat