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MCP23017, MCP23S17 Datasheet by Microchip Technology

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6‘ MICROCHIP 0000000 #559333 f 0000000 0000000 ¢¢¢¢¢¢¢ ft‘ff 0000000
2005-2016 Microchip Technology Inc. DS20001952C-page 1
MCP23017/MCP23S17
Features
16-Bit Remote Bidirectional I/O Port:
- I/O pins default to input
High-Speed I2C Interface (MCP23017):
-100kHz
-400kHz
-1.7MHz
High-Speed SPI Interface (MCP23S17):
- 10 MHz (maximum)
Three Hardware Address Pins to Allow Up to
Eight Devices On the Bus
Configurable Interrupt Output Pins:
- Configurable as active-high, active-low or
open-drain
INTA and INTB Can Be Configured to Operate
Independently or Together
Configurable Interrupt Source:
- Interrupt-on-change from configured register
defaults or pin changes
Polarity Inversion Register to Configure the
Polarity of the Input Port Data
External Reset Input
Low Standby Current: 1 µA (max.)
Operating Voltage:
- 1.8V to 5.5V @ -40°C to +85°C
- 2.7V to 5.5V @ -40°C to +85°C
- 4.5V to 5.5V @ -40°C to +125°C
Packages
28-pin QFN, 6 x 6 mm Body
28-pin SOIC, Wide, 7.50 mm Body
28-pin SPDIP, 300 mil Body
28-pin SSOP, 5.30 mm Body
Package Types
2
3
4
5
6
1
7
V
SS
NC 15
16
17
18
19
20
21 GPA4
GPA3
GPA2
GPA1
GPA0
V
DD
INTB
SCK
SDA
NC
A0
A1
A2
RESET
232425262728 22
GPB3
GPB2
GPB1
GPB0
GPA7
GPA6
GPA5
10118 9 121314
GPB5
GPB6
GPB7
GPB4
INTA
GPB0
GPB1
GPB2
GPB3
INTA
GPB4
NC
NC
GPB5
GPB6
GPB7
SCK
GPA7
GPA6
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0
V
DD
V
SS
A2
A1
A0
SDA
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INTB
RESET
EP
29 *
SPDIP
SSOP
SOIC
QFN
* Includes Exposed Thermal Pad; see Table 2-1.
2
3
4
5
6
1
7
VSS
CS 15
16
17
18
19
20
21 GPA4
GPA3
GPA2
GPA1
GPA0
VDD
INTB
SI
SO
A0
A1
A2
RESET
232425262728 22
GPB3
GPB2
GPB1
GPB0
GPA7
GPA6
GPA5
10118 9 121314
GPB5
GPB6
GPB7
GPB4
INTA
SCK
EP
29 *
GPB0
GPB1
GPB2
GPB3
INTA
GPB4
SO
CS
GPB5
GPB6
GPB7
SCK
GPA7
GPA6
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0
VDD
VSS
A2
A1
A0
SI
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INTB
RESET
MCP23S17
MCP23017
16-Bit I/O Expander with Serial Interface
MCP23017/MCP23S17
DS20001952C-page 2 2005-2016 Microchip Technology Inc.
Functional Block Diagram
GPB7
GPB6
GPB5
GPB4
GPB3
GPB2
GPB1
GPB0
I2C
Control
GPIO
SCL
SDA
RESET
INTA 16
Configuration/
8
A2:A0 3
Control
Registers
SPI
SI
SO
SCK
CS MCP23S17
MCP23017
GPA7
GPA6
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0
INTB Interrupt
GPIO
Serializer/
Deserializer
Logic
Decode
2005-2016 Microchip Technology Inc. DS20001952C-page 3
MCP23017/MCP23S17
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature ...............................................................................................................................-65°C to +150°C
Voltage on VDD with respect to VSS ..........................................................................................................-0.3V to +5.5V
Voltage on all other pins with respect to VSS (except VDD).............................................................-0.6V to (VDD + 0.6V)
Total power dissipation.........................................................................................................................................700 mW
Maximum current out of VSS pin ...........................................................................................................................150 mA
Maximum current into VDD pin ..............................................................................................................................125 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20 mA
Maximum output current sunk by any output pin ....................................................................................................25 mA
Maximum output current sourced by any output pin ...............................................................................................25 mA
ESD protection on all pins (HBM:MM) ..............................................................................................................4 kV:400V
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
DD DD LO Vss VPIN VDD VDD VDD Clo
MCP23017/MCP23S17
DS20001952C-page 4 2005-2016 Microchip Technology Inc.
1.1 DC Characteristics
TABLE 1-1: DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C
Param.
No. Characteristic Sym. Min. Typ.(1)Max. Units Conditions
D001 Supply Voltage VDD 1.8 — 5.5 V
D002 VDD Start Voltage to
ensure Power-on Reset VPOR —V
SS —V
D003 VDD Rise Rate to ensure
Power-on Reset SVDD 0.05 V/ms Design guidance only.
Not tested.
D004 Supply Current IDD 1 mA SCL/SCK = 1 MHz
D005 Standby current IDDS8 ——1µA-40°C TA +85°C
——3µA4.5V VDD 5.5V
+85°C TA +125C
(Note 1)
Input Low Voltage
D030 A0, A1, A2 (TTL buffer) VIL VSS —0.15V
DD V
D031 CS, GPIO, SCL/SCK,
SDA, RESET
(Schmitt Trigger)
VIL VSS —0.2V
DD V
Input High Voltage
D040 A0, A1, A2 (TTL buffer) VIH 0.25 VDD + 0.8 VDD V
D041 CS, GPIO, SCL/SCK,
SDA, RESET
(Schmitt Trigger)
VIH 0.8 VDD —V
DD V For entire VDD range
Input Leakage Current
D060 I/O port pins IIL ——±1µAV
SS VPIN VDD
Output Leakage Current
D065 I/O port pins ILO ——±1µAV
SS VPIN VDD
D070 GPIO weak pull-up
current IPU 40 75 115 µA VDD = 5V
GP pins = VSS
Output Low-Voltage
D080 GPIO VOL ——0.6VI
OL = 8.0 mA
VDD = 4.5V
INT VOL ——0.6VI
OL = 1.6 mA
VDD = 4.5V
SO, SDA VOL ——0.6VI
OL = 3.0 mA
VDD = 1.8V
SDA VOL ——0.8VI
OL = 3.0 mA
VDD = 4.5V
Output High-Voltage
D090 GPIO, INT, SO VOH VDD – 0.7 V IOH = -3.0 mA
VDD = 4.5V
VDD – 0.7 IOH = -400 µA
VDD = 1.8V
Capacitive Loading Specs on Output Pins
D101 GPIO, SO, INT CIO ——50pF
D102 SDA CB 400 pF
Note 1: This parameter is characterized, not 100% tested.
2005-2016 Microchip Technology Inc. DS20001952C-page 5
MCP23017/MCP23S17
1.2 AC Characteristics
FIGURE 1-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
FIGURE 1-2: RESET AND DEVICE RESET TIMER TIMING
TABLE 1-2: DEVICE RESET SPECIFICATIONS
AC Characteristics: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C
Param.
No. Characteristic Sym. Min. Typ. (1)Max. Units Conditions
30 RESET Pulse Width
(Low)
TRSTL 1—µs
32 Device Active After Reset
high
THLD —0nsV
DD = 5.0V
34 Output High-Impedance
From RESET Low
TIOZ ——1µs
Note 1: This parameter is characterized, not 100% tested.
135 pF
1k
VDD
SCL and
SDA pin
MCP23017
50 pF
Pin
VDD
RESET
Internal
RESET
34
Output pin
32
30
MCP23017/MCP23S17
DS20001952C-page 6 2005-2016 Microchip Technology Inc.
FIGURE 1-3: I2C BUS START/STOP BITS TIMING
FIGURE 1-4: I2C BUS DATA TIMING
TABLE 1-3: I2C BUS DATA REQUIREMENTS
I2C Interface AC Characteristics: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C, RPU (SCL,
SDA) = 1 k, CL (SCL, SDA) = 135 pF
Param.
No. Characteristic Sym. Min. Typ. Max. Units Conditions
100 Clock High Time: THIGH
100 kHz mode 4.0 µs 1.8V – 5.5V
400 kHz mode 0.6 µs 2.7V – 5.5V
1.7 MHz mode 0.12 µs 4.5V – 5.5V
101 Clock Low Time: TLOW
100 kHz mode 4.7 µs 1.8V – 5.5V
400 kHz mode 1.3 µs 2.7V – 5.5V
1.7 MHz mode 0.32 µs 4.5V – 5.5V
102 SDA and SCL Rise Time: TR (1)
100 kHz mode 1000 ns 1.8V – 5.5V
400 kHz mode 20 + 0.1 CB (2) 300 ns 2.7V – 5.5V
1.7 MHz mode 20 160 ns 4.5V – 5.5V
103 SDA and SCL Fall Time: TF (1)
100 kHz mode 300 ns 1.8V – 5.5V
400 kHz mode 20 + 0.1 CB (2) 300 ns 2.7V – 5.5V
1.7 MHz mode 20 80 ns 4.5V – 5.5V
Note 1: This parameter is characterized, not 100% tested.
2: CB is specified to be from 10 to 400 pF.
91 93
SCL
SDA
Start
Condition Stop
Condition
90 92
90 91 92
100 101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
2005-2016 Microchip Technology Inc. DS20001952C-page 7
MCP23017/MCP23S17
90 START Condition Setup Time: TSU:STA
100 kHz mode 4.7 µs 1.8V – 5.5V
400 kHz mode 0.6 µs 2.7V – 5.5V
1.7 MHz mode 0.16 µs 4.5V – 5.5V
91 START Condition Hold Time: THD:STA
100 kHz mode 4.0 µs 1.8V – 5.5V
400 kHz mode 0.6 µs 2.7V – 5.5V
1.7 MHz mode 0.16 µs 4.5V – 5.5V
106 Data Input Hold Time: THD:DAT
100 kHz mode 0 3.45 µs 1.8V – 5.5V
400 kHz mode 0 0.9 µs 2.7V – 5.5V
1.7 MHz mode 0 0.15 µs 4.5V – 5.5V
107 Data Input Setup Time: TSU:DAT
100 kHz mode 250 ns 1.8V – 5.5V
400 kHz mode 100 ns 2.7V – 5.5V
1.7 MHz mode 0.01 µs 4.5V – 5.5V
92 Stop Condition Setup Time: TSU:STO
100 kHz mode 4.0 µs 1.8V – 5.5V
400 kHz mode 0.6 µs 2.7V – 5.5V
1.7 MHz mode 0.16 µs 4.5V–5.5V
109 Output Valid From Clock: TAA
100 kHz mode 3.45 µs 1.8V – 5.5V
400 kHz mode 0.9 µs 2.7V – 5.5V
1.7 MHz mode 0.18 µs 4.5V – 5.5V
110 Bus Free Time: TBUF
100 kHz mode 4.7 µs 1.8V – 5.5V
400 kHz mode 1.3 µs 2.7V – 5.5V
1.7 MHz mode N/A N/A µs 4.5V – 5.5V
111 Bus Capacitive Loading: CB
100 kHz and 400 kHz 400 pF Note 1
1.7 MHz 100 pF Note 1
112 Input Filter Spike Suppression
(SDA and SCL): TSP
100 kHz and 400 kHz 50 ns
1.7 MHz 10 ns Spike suppression off
TABLE 1-3: I2C BUS DATA REQUIREMENTS (CONTINUED)
I2C Interface AC Characteristics: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C, RPU (SCL,
SDA) = 1 k, CL (SCL, SDA) = 135 pF
Param.
No. Characteristic Sym. Min. Typ. Max. Units Conditions
Note 1: This parameter is characterized, not 100% tested.
2: CB is specified to be from 10 to 400 pF.
MCP23017/MCP23S17
DS20001952C-page 8 2005-2016 Microchip Technology Inc.
FIGURE 1-5: SPI INPUT TIMING
FIGURE 1-6: SPI OUTPUT TIMING
TABLE 1-4: SPI INTERFACE REQUIREMENTS
SPI Interface AC Characteristics: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C
Param.
No. Characteristic Sym. Min. Typ. Max. Units Conditions
Clock Frequency FCLK 5 MHz 1.8V – 5.5V
10 MHz 2.7V – 5.5V
10 MHz 4.5V – 5.5V
1CS
Setup Time TCSS 50 — ns
2CS
Hold Time TCSH 100 ns 1.8V – 5.5V
50 ns 2.7V – 5.5V
3CS
Disable Time TCSD 100 ns 1.8V – 5.5V
50 ns 2.7V – 5.5V
4 Data Setup Time TSU 20 ns 1.8V – 5.5V
10 ns 2.7V – 5.5V
Note 1: This parameter is characterized, not 100% tested.
SCK
SI
SO
1
5
4
7
6
3
10
2
LSB in
MSB in
High-Impedance
11
Mode 1,1
Mode 0,0
Note 1: When using SPI Mode 1,1 the CS pin needs to be toggled once before the first communication after
power-up.
CS (1)
CS
SCK
SO
8
13
MSB out LSB out
2
14
Don’t Care
SI
Mode 1,1
Mode 0,0
9
12
2005-2016 Microchip Technology Inc. DS20001952C-page 9
MCP23017/MCP23S17
FIGURE 1-7: GPIO AND INT TIMING
5Data Hold Time T
HD 20 ns 1.8V – 5.5V
10 ns 2.7V – 5.5V
6CLK Rise Time T
R—— 2 µsNote 1
7CLK Fall Time T
F—— 2 µsNote 1
8Clock High Time T
HI 90 ns 1.8V – 5.5V
45 ns 2.7V – 5.5V
9 Clock Low Time TLO 90 ns 1.8V – 5.5V
45 ns 2.7V – 5.5V
10 Clock Delay Time TCLD 50 — ns
11 Clock Enable Time TCLE 50 — ns
12 Output Valid from Clock Low TV 90 ns 1.8V – 5.5V
45 ns 2.7V – 5.5V
13 Output Hold Time THO 0—ns
14 Output Disable Time TDIS — 100 ns
TABLE 1-4: SPI INTERFACE REQUIREMENTS (CONTINUED)
SPI Interface AC Characteristics: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C
Param.
No. Characteristic Sym. Min. Typ. Max. Units Conditions
Note 1: This parameter is characterized, not 100% tested.
50
SCL/SCK
SDA/SI
In
GPn
Pin
D0
D1
LSb of data byte zero
during a write or read
INT
Pin INT Pin Active
51
command, depending
on parameter
Output
GPn
Pin
Input
Inactive
53
52
Register
Loaded
MCP23017/MCP23S17
DS20001952C-page 10 2005-2016 Microchip Technology Inc.
TABLE 1-5: GP AND INT PINS REQUIREMENTS
GP and INT Pins AC Characteristics: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C
Param.
No. Characteristic Sym. Min. Typ. Max. Units Conditions
50 Serial Data to Output Valid TGPOV ——500ns
51 Interrupt Pin Disable Time TINTD ——600ns
52 GP Input Change to
Register Valid TGPIV ——450ns
53 IOC Event to INT Active TGPINT ——600ns
Glitch Filter on GP Pins TGLITCH ——150nsNote 1
Note 1: This parameter is characterized, not 100% tested.
2005-2016 Microchip Technology Inc. DS20001952C-page 11
MCP23017/MCP23S17
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PINOUT DESCRIPTION
Pin
Name QFN SOIC
SPDIP
SSOP
Pin
Type Function
GPB0 25 1 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB1 26 2 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB2 27 3 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB3 28 4 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB4 1 5 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB5 2 6 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB6 3 7 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB7 4 8 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
VDD 5 9 P Power
VSS 6 10 P Ground
NC/CS 7 11 I NC (MCP23017)/Chip Select (MCP23S17)
SCK 8 12 I Serial clock input
SDA/SI 9 13 I/O Serial data I/O (MCP23017)/Serial data input (MCP23S17)
NC/SO 10 14 O NC (MCP23017)/Serial data out (MCP23S17)
A0 11 15 I Hardware address pin. Must be externally biased.
A1 12 16 I Hardware address pin. Must be externally biased.
A2 13 17 I Hardware address pin. Must be externally biased.
RESET 14 18 I Hardware reset. Must be externally biased.
INTB 15 19 O Interrupt output for PORTB. Can be configured as active-high, active-low or open-drain.
INTA 16 20 O Interrupt output for PORTA. Can be configured as active-high, active-low or open-drain.
GPA0 17 21 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA1 18 22 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA2 19 23 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA3 20 24 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA4 21 25 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA5 22 26 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA6 23 27 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA7 24 28 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
EP 29 Exposed Thermal Pad. Either connect to VSS, or leave unconnected.
MCP23017/MCP23S17
DS20001952C-page 12 2005-2016 Microchip Technology Inc.
3.0 DEVICE OVERVIEW
The MCP23017/MCP23S17 (MCP23X17) device
family provides 16-bit, general purpose parallel I/O
expansion for I2C bus or SPI applications. The two
devices differ only in the serial interface:
MCP23017 – I2C interface
MCP23S17 – SPI interface
The MCP23X17 consists of multiple 8-bit configuration
registers for input, output and polarity selection. The
system master can enable the I/Os as either inputs or
outputs by writing the I/O configuration bits (IODIRA/B).
The data for each input or output is kept in the
corresponding input or output register. The polarity of
the Input Port register can be inverted with the Polarity
Inversion register. All registers can be read by the
system master.
The 16-bit I/O port functionally consists of two 8-bit
ports (PORTA and PORTB). The MCP23X17 can be
configured to operate in the 8-bit or 16-bit modes via
IOCON.BANK.
There are two interrupt pins, INTA and INTB, that can
be associated with their respective ports, or can be
logically OR’ed together so that both pins will activate if
either port causes an interrupt.
The interrupt output can be configured to activate
under two conditions (mutually exclusive):
1. When any input state differs from its
corresponding Input Port register state. This is
used to indicate to the system master that an
input state has changed.
2. When an input state differs from a preconfigured
register value (DEFVAL register).
The Interrupt Capture register captures port values at
the time of the interrupt, thereby saving the condition
that caused the interrupt.
The Power-on Reset (POR) sets the registers to their
default values and initializes the device state machine.
The hardware address pins are used to determine the
device address.
3.1 Power-on Reset (POR)
The on-chip POR circuit holds the device in reset until
VDD has reached a high enough voltage to deactivate
the POR circuit (i.e., release the device from reset).
The maximum VDD rise time is specified in Section 1.0
“Electrical Characteristics”.
When the device exits the POR condition (releases
reset), device operating parameters (i.e., voltage,
temperature, serial bus frequency, etc.) must be met to
ensure proper operation.
3.2 Serial Interface
This block handles the functionality of the I2C
(MCP23017) or SPI (MCP23S17) interface protocol.
The MCP23X17 contains 22 individual registers (11
register pairs) that can be addressed through the Serial
Interface block, as shown in Table 3-1.
TABLE 3-1: REGISTER ADDRESSES
Address
IOCON.BANK = 1Address
IOCON.BANK = 0Access to:
00h 00h IODIRA
10h 01h IODIRB
01h 02h IPOLA
11h 03h IPOLB
02h 04h GPINTENA
12h 05h GPINTENB
03h 06h DEFVALA
13h 07h DEFVALB
04h 08h INTCONA
14h 09h INTCONB
05h 0Ah IOCON
15h 0Bh IOCON
06h 0Ch GPPUA
16h 0Dh GPPUB
07h 0Eh INTFA
17h 0Fh INTFB
08h 10h INTCAPA
18h 11h INTCAPB
09h 12h GPIOA
19h 13h GPIOB
0Ah 14h OLATA
1Ah 15h OLATB
|:|:|:|:|—>|:|—>|:l |:I:I:|:|4>|:l |:|—>|:|
2005-2016 Microchip Technology Inc. DS20001952C-page 13
MCP23017/MCP23S17
3.2.1 BYTE MODE AND SEQUENTIAL
MODE
The MCP23X17 family has the ability to operate in Byte
mode or Sequential mode (IOCON.SEQOP).
Byte mode disables automatic Address Pointer
incrementing. When operating in Byte mode, the
MCP23X17 family does not increment its internal
address counter after each byte during the data
transfer. This gives the ability to continually access the
same address by providing extra clocks (without
additional control bytes). This is useful for polling the
GPIO register for data changes or for continually
writing to the output latches.
A special mode (Byte mode with IOCON.BANK = 0)
causes the address pointer to toggle between
associated A/B register pairs. For example, if the BANK
bit is cleared and the Address Pointer is initially set to
address 12h (GPIOA) or 13h (GPIOB), the pointer will
toggle between GPIOA and GPIOB. Note that the
Address Pointer can initially point to either address in
the register pair.
Sequential mode enables automatic address pointer
incrementing. When operating in Sequential mode, the
MCP23X17 family increments its address counter after
each byte during the data transfer. The Address Pointer
automatically rolls over to address 00h after accessing
the last register.
These two modes are not to be confused with single
writes/reads and continuous writes/reads that are
serial protocol sequences. For example, the device
may be configured for Byte mode and the master may
perform a continuous read. In this case, the
MCP23X17 would not increment the Address Pointer
and would repeatedly drive data from the same
location.
3.2.2 I2C INTERFACE
3.2.2.1 I2C Write Operation
The I2C write operation includes the control byte and
register address sequence, as shown in Figure 3-1.
This sequence is followed by eight bits of data from the
master and an Acknowledge (ACK) from the
MCP23017. The operation is ended with a Stop (P) or
Restart (SR) condition being generated by the master.
Data is written to the MCP23017 after every byte
transfer. If a Stop or Restart condition is generated
during a data transfer, the data will not be written to the
MCP23017.
Both “byte writes” and “sequential writes” are
supported by the MCP23017. If Sequential mode is
enabled (IOCON, SEQOP = 0) (default), the
MCP23017 increments its address counter after each
ACK during the data transfer.
FIGURE 3-1: BYTE AND SEQUENTIAL WRITE
S PWOP ADDR DIN DIN
....
S WOP ADDR DIN P
Byte
Sequential
S
P
SR
W
R
OP
ADDR
DIN
- Start
- Restart
- Stop
- Write
- Read
- Device opcode
- Device register address
- Data out from MCP23017
- Data in to MCP23017
DOUT
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MCP23017/MCP23S17
DS20001952C-page 14 2005-2016 Microchip Technology Inc.
3.2.2.2 I2C Read Operation
I2C Read operations include the control byte sequence,
as shown in Figure 3-2. This sequence is followed by
another control byte (including the Start condition and
ACK) with the R/W bit set (R/W = 1). The MCP23017
then transmits the data contained in the addressed
register. The sequence is ended with the master
generating a Stop or Restart condition.
FIGURE 3-2: BYTE AND SEQUENTIAL READ
3.2.2.3 I2C Sequential Write/Read
For sequential operations (Write or Read), instead of
transmitting a Stop or Restart condition after the data
transfer, the master clocks the next byte pointed to by
the address pointer (see Section 3.2.1 “Byte Mode
and Sequential Mode” for details regarding sequential
operation control).
The sequence ends with the master sending a Stop or
Restart condition.
The MCP23017 Address Pointer will roll over to
address zero after reaching the last register address.
Refer to Figure 3-3.
FIGURE 3-3: MCP23017 I2C DEVICE PROTOCOL
SR ROP DOUT DOUT
.... P
SW
OP SR
R
OP
DOUT
P
Byte
Sequential SW
OP
S P
SR
W
R
OP ADDR DIN DIN
....
P
W
OP
ADDR
D
OUT DOUT.... P
SR WOP
D
IN DIN.... P
P
SR R
DOUT DOUT
....
P
OP .... P
SR OP DIN
.... P
DIN
DOUT DOUT
S ROP
T
2005-2016 Microchip Technology Inc. DS20001952C-page 15
MCP23017/MCP23S17
3.2.3 SPI INTERFACE
3.2.3.1 SPI Write Operation
The SPI write operation is started by lowering CS. The
Write command (slave address with R/W bit cleared) is
then clocked into the device. The opcode is followed by
an address and at least one data byte.
3.2.3.2 SPI Read Operation
The SPI read operation is started by lowering CS. The
SPI read command (slave address with R/W bit set) is
then clocked into the device. The opcode is followed by
an address, with at least one data byte being clocked
out of the device.
3.2.3.3 SPI Sequential Write/Read
For sequential operations, instead of deselecting the
device by raising CS, the master clocks the next byte
pointed to by the Address Pointer. (see Section 3.2.1
“Byte Mode and Sequential Mode” for details
regarding sequential operation control).
The sequence ends by the raising of CS.
The MCP23S17 Address Pointer will roll over to
address zero after reaching the last register address.
3.3 Hardware Address Decoder
The hardware address pins are used to determine the
device address. To address a device, the correspond-
ing address bits in the control byte must match the pin
state. The pins must be biased externally.
3.3.1 ADDRESSING I2C DEVICES
(MCP23017)
The MCP23017 is a slave I2C interface device that
supports 7-bit slave addressing, with the read/write bit
filling out the control byte. The slave address contains
four fixed bits and three user-defined hardware
address bits (pins A2, A1 and A0). Figure 3-4 shows
the control byte format.
3.3.2 ADDRESSING SPI DEVICES
(MCP23S17)
The MCP23S17 is a slave SPI device. The slave
address contains four fixed bits and three user-defined
hardware address bits (if enabled via IOCON.HAEN)
(pins A2, A1 and A0) with the read/write bit filling out
the control byte. Figure 3-5 shows the control byte
format. The address pins should be externally biased
even if disabled (IOCON.HAEN = 0).
FIGURE 3-4: I2C CONTROL BYTE
FORMAT
FIGURE 3-5: SPI CONTROL BYTE
FORMAT
FIGURE 3-6: I2C ADDRESSING REGISTERS
S 0 1 0 0 A2A1A0R/WACK
Start
bit
Slave Address
R/W bit
ACK bit
Control Byte
R/W = 0 = write
R/W = 1 = read
0 1 0 0 A2 A1 A0 R/W
Slave Address
R/W bit
Control Byte
R/W = 0 = write
R/W = 1 = read
CS
S0100A2A1A00ACK *A7 A6 A5 A4 A3 A2 A1 A0
ACK
*
Device Opcode Register Address
R/W = 0
*The ACKs are provided by the MCP23017.
MCP23017/MCP23S17
DS20001952C-page 16 2005-2016 Microchip Technology Inc.
FIGURE 3-7: SPI ADDRESSING REGISTERS
3.4 GPIO Port
The GPIO module is a general purpose, 16-bit wide,
bidirectional port that is functionally split into two
8-bit wide ports.
The GPIO module contains the data ports (GPIOn),
internal pull-up resistors and the output latches
(OLATn).
Reading the GPIOn register reads the value on the
port. Reading the OLATn register only reads the
latches, not the actual value on the port.
Writing to the GPIOn register actually causes a write to
the latches (OLATn). Writing to the OLATn register
forces the associated output drivers to drive to the level
in OLATn. Pins configured as inputs turn off the
associated output driver and put it in high-impedance.
0100A2 * A1 * A0 * R/W A7 A6 A5 A4 A3 A2 A1 A0
Device Opcode Register Address
CS
* Address pins are enabled/disabled via IOCON.HAEN.
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 1)
Register
Name Address
(hex) bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
POR/RST
value
IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111
IPOLA 01IP7IP6IP5IP4IP3IP2IP1IP00000 0000
GPINTENA 02 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
GPPUA 06 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000
GPIOA 09 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000
OLATA 0A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000
IODIRB 10 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111
IPOLB 11 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000
GPINTENB 12 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
GPPUB 16 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000
GPIOB 19 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000
OLATB 1A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000
TABLE 3-3: SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 0)
Register
Name Address
(hex) bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
POR/RST
value
IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111
IODIRB 01 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111
IPOLA 02IP7IP6IP5IP4IP3IP2IP1IP00000 0000
IPOLB 03 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000
GPINTENA 04 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
GPINTENB 05 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
GPPUA 0C PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000
GPPUB 0D PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000
GPIOA 12 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000
GPIOB 13 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000
OLATA 14 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000
OLATB 15 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000
2005-2016 Microchip Technology Inc. DS20001952C-page 17
MCP23017/MCP23S17
3.5 Configuration and Control
Registers
There are 21 registers associated with the MCP23X17,
as shown in Tables 3-4 and3-5. The two tables show
the register mapping with the two BANK bit values. Ten
registers are associated with PORTA and ten are
associated with PORTB. One register (IOCON) is
shared between the two ports. The PORTA registers
are identical to the PORTB registers, therefore, they
will be referred to without differentiating between the
port designation (i.e., they will not have the “A” or “B”
designator assigned) in the register tables.
TABLE 3-4: CONTROL REGISTER SUMMARY (IOCON.BANK = 1)
Register
Name Address
(hex) bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
POR/RST
value
IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111
IPOLA 01IP7IP6IP5IP4IP3IP2IP1IP00000 0000
GPINTENA 02 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
DEFVALA 03 DEF7DEF6DEF5DEF4DEF3DEF2DEF1DEF00000 0000
INTCONA 04 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000
IOCON 05 BANK MIRROR SEQOP DISSLW HAEN ODR INTPOL 0000 0000
GPPUA 06 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000
INTFA 07 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000
INTCAPA 08 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000
GPIOA 09 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000
OLATA 0A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000
IODIRB 10 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111
IPOLB 11 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000
GPINTENB 12 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
DEFVALB 13 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 0000 0000
INTCONB 14 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000
IOCON 15 BANK MIRROR SEQOP DISSLW HAEN ODR INTPOL 0000 0000
GPPUB 16 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000
INTFB 17 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000
INTCAPB 18 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000
GPIOB 19 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000
OLATB 1A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000
TABLE 3-5: CONTROL REGISTER SUMMARY (IOCON.BANK = 0)
Register
Name Address
(hex) bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
POR/RST
value
IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111
IODIRB 01 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111
IPOLA 02IP7IP6IP5IP4IP3IP2IP1IP00000 0000
IPOLB 03 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000
GPINTENA 04 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
GPINTENB 05 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
DEFVALA 06 DEF7DEF6DEF5DEF4DEF3DEF2DEF1DEF00000 0000
DEFVALB 07 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 0000 0000
INTCONA 08 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000
INTCONB 09 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000
IOCON 0A BANK MIRROR SEQOP DISSLW HAEN ODR INTPOL 0000 0000
IOCON 0B BANK MIRROR SEQOP DISSLW HAEN ODR INTPOL 0000 0000
GPPUA 0C PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000
GPPUB 0D PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000
MCP23017/MCP23S17
DS20001952C-page 18 2005-2016 Microchip Technology Inc.
3.5.1 I/O DIRECTION REGISTER
Controls the direction of the data I/O.
When a bit is set, the corresponding pin becomes an
input. When a bit is clear, the corresponding pin
becomes an output.
3.5.2 INPUT POLARITY REGISTER
This register allows the user to configure the polarity on
the corresponding GPIO port bits.
If a bit is set, the corresponding GPIO register bit will
reflect the inverted value on the pin.
INTFA 0E INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000
INTFB 0F INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000
INTCAPA 10 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000
INTCAPB 11 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000
GPIOA 12 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000
GPIOB 13 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000
OLATA 14 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000
OLATB 15 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000
TABLE 3-5: CONTROL REGISTER SUMMARY (IOCON.BANK = 0) (CONTINUED)
Register
Name Address
(hex) bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
POR/RST
value
REGISTER 3-1: IODIR: I/O DIRECTION REGISTER (ADDR 0x00)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 IO<7:0>: Controls the direction of data I/O <7:0>
1 = Pin is configured as an input.
0 = Pin is configured as an output.
REGISTER 3-2: IPOL: INPUT POLARITY PORT REGISTER (ADDR 0x01)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 IP<7:0>: Controls the polarity inversion of the input pins <7:0>
1 = GPIO register bit reflects the opposite logic state of the input pin.
0 = GPIO register bit reflects the same logic state of the input pin.
2005-2016 Microchip Technology Inc. DS20001952C-page 19
MCP23017/MCP23S17
3.5.3 INTERRUPT-ON-CHANGE
CONTROL REGISTER
The GPINTEN register controls the
interrupt-on-change feature for each pin.
If a bit is set, the corresponding pin is enabled for
interrupt-on-change. The DEFVAL and INTCON
registers must also be configured if any pins are
enabled for interrupt-on-change.
3.5.4 DEFAULT COMPARE REGISTER
FOR INTERRUPT-ON-CHANGE
The default comparison value is configured in the
DEFVAL register. If enabled (via GPINTEN and
INTCON) to compare against the DEFVAL register, an
opposite value on the associated pin will cause an
interrupt to occur.
REGISTER 3-3: GPINTEN: INTERRUPT-ON-CHANGE PINS (ADDR 0x02) (Note 1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 GPINT<7:0>: General purpose I/O interrupt-on-change bits <7:0>
1 = Enables GPIO input pin for interrupt-on-change event.
0 = Disables GPIO input pin for interrupt-on-change event.
Note 1: Refer to INTCON.
REGISTER 3-4: DEFVAL: DEFAULT VALUE REGISTER (ADDR 0x03)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 DEF<7:0>: Sets the compare value for pins configured for interrupt-on-change from defaults <7:0>
(Note 1)
If the associated pin level is the opposite from the register bit, an interrupt occurs. (Note 2)
Note 1: Refer to INTCON.
2: Refer to INTCON and GPINTEN.
MCP23017/MCP23S17
DS20001952C-page 20 2005-2016 Microchip Technology Inc.
3.5.5 INTERRUPT CONTROL REGISTER
The INTCON register controls how the associated pin
value is compared for the interrupt-on-change feature.
If a bit is set, the corresponding I/O pin is compared
against the associated bit in the DEFVAL register. If a
bit value is clear, the corresponding I/O pin is compared
against the previous value.
3.5.6 CONFIGURATION REGISTER
The IOCON register contains several bits for
configuring the device:
The BANK bit changes how the registers are mapped
(see Tables 3-4 and3-5 for more details).
If BANK = 1, the registers associated with each
port are segregated. Registers associated with
PORTA are mapped from address 00h - 0Ah and
registers associated with PORTB are mapped
from 10h - 1Ah.
If BANK = 0, the A/B registers are paired. For
example, IODIRA is mapped to address 00h and
IODIRB is mapped to the next address (address
01h). The mapping for all registers is from 00h
-15h.
It is important to take care when changing the BANK bit
as the address mapping changes after the byte is
clocked into the device. The address pointer may point
to an invalid location after the bit is modified.
For example, if the device is configured to
automatically increment its internal Address Pointer,
the following scenario would occur:
BANK = 0
Write 80h to address 0Ah (IOCON) to set the
BANK bit
Once the write completes, the internal address
now points to 0Bh which is an invalid address
when the BANK bit is set.
For this reason, when changing the BANK bit, it is
advised to only perform byte writes to this register.
The MIRROR bit controls how the INTA and INTB pins
function with respect to each other.
When MIRROR = 1, the INTn pins are functionally
OR’ed so that an interrupt on either port will cause
both pins to activate.
When MIRROR = 0, the INT pins are separated.
Interrupt conditions on a port will cause its
respective INT pin to activate.
The Sequential Operation (SEQOP) controls the
incrementing function of the Address Pointer. If the
address pointer is disabled, the Address Pointer does
not automatically increment after each byte is clocked
during a serial transfer. This feature is useful when it is
desired to continuously poll (read) or modify (write) a
register.
The Slew Rate (DISSLW) bit controls the slew rate
function on the SDA pin. If enabled, the SDA slew rate
will be controlled when driving from a high to low.
The Hardware Address Enable (HAEN) bit
enables/disables hardware addressing on the
MCP23S17 only. The address pins (A2, A1 and A0)
must be externally biased, regardless of the HAEN bit
value.
If enabled (HAEN = 1), the device’s hardware address
matches the address pins.
If disabled (HAEN = 0), the device’s hardware address
is A2 = A1 = A0 = 0.
REGISTER 3-5: INTCON: INTERRUPT-ON-CHANGE CONTROL REGISTER (ADDR 0x04) (Note 1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 IOC<7:0>: Controls how the associated pin value is compared for interrupt-on-change <7:0>
1 = Pin value is compared against the associated bit in the DEFVAL register.
0 = Pin value is compared against the previous pin value.
Note 1: Refer to INTCON and GPINTEN.
2005-2016 Microchip Technology Inc. DS20001952C-page 21
MCP23017/MCP23S17
The Open-Drain (ODR) control bit enables/disables the
INT pin for open-drain configuration. Setting this bit
overrides the INTPOL bit.
The Interrupt Polarity (INTPOL) sets the polarity of the
INT pin. This bit is functional only when the ODR bit is
cleared, configuring the INT pin as active push-pull.
REGISTER 3-6: IOCON: I/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
BANK MIRROR SEQOP DISSLW HAEN ODR INTPOL
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 BANK: Controls how the registers are addressed
1 = The registers associated with each port are separated into different banks.
0 = The registers are in the same bank (addresses are sequential).
bit 6 MIRROR: INT Pins Mirror bit
1 = The INT pins are internally connected
0 = The INT pins are not connected. INTA is associated with PORTA and INTB is associated with
PORTB
bit 5 SEQOP: Sequential Operation mode bit
1 = Sequential operation disabled, address pointer does not increment.
0 = Sequential operation enabled, address pointer increments.
bit 4 DISSLW: Slew Rate control bit for SDA output
1 = Slew rate disabled
0 = Slew rate enabled
bit 3 HAEN: Hardware Address Enable bit (MCP23S17 only) (Note 1)
1 = Enables the MCP23S17 address pins.
0 = Disables the MCP23S17 address pins.
bit 2 ODR: Configures the INT pin as an open-drain output
1 = Open-drain output (overrides the INTPOL bit.)
0 = Active driver output (INTPOL bit sets the polarity.)
bit 1 INTPOL: This bit sets the polarity of the INT output pin
1 = Active-high
0 =Active-low
bit 0 Unimplemented: Read as ‘0
Note 1: Address pins are always enabled on the MCP23017.
MCP23017/MCP23S17
DS20001952C-page 22 2005-2016 Microchip Technology Inc.
3.5.7 PULL-UP RESISTOR
CONFIGURATION REGISTER
The GPPU register controls the pull-up resistors for the
port pins. If a bit is set and the corresponding pin is
configured as an input, the corresponding port pin is
internally pulled up with a 100 k resistor.
3.5.8 INTERRUPT FLAG REGISTER
The INTF register reflects the interrupt condition on the
port pins of any pin that is enabled for interrupts via the
GPINTEN register. A set bit indicates that the
associated pin caused the interrupt.
This register is read-only. Writes to this register will be
ignored.
REGISTER 3-7: GPPU: GPIO PULL-UP RESISTOR REGISTER (ADDR 0x06)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PU<7:0> Controls the weak pull-up resistors on each pin (when configured as an input)
1 = Pull-up enabled
0 = Pull-up disabled
REGISTER 3-8: INTF: INTERRUPT FLAG REGISTER (ADDR 0x07)
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 INT<7:0>: Reflects the interrupt condition on the port. It reflects the change only if interrupts are
enabled per GPINTEN<7:0>.
1 = Pin caused interrupt.
0 = Interrupt not pending
2005-2016 Microchip Technology Inc. DS20001952C-page 23
MCP23017/MCP23S17
3.5.9 INTERRUPT CAPTURED REGISTER
The INTCAP register captures the GPIO port value at
the time the interrupt occurred. The register is
read-only and is updated only when an interrupt
occurs. The register remains unchanged until the
interrupt is cleared via a read of INTCAP or GPIO.
3.5.10 PORT REGISTER
The GPIO register reflects the value on the port.
Reading from this register reads the port. Writing to this
register modifies the Output Latch (OLAT) register.
REGISTER 3-9: INTCAP: INTERRUPT CAPTURED VALUE FOR PORT REGISTER (ADDR 0x08)
R-x R-x R-x R-x R-x R-x R-x R-x
ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ICP<7:0>: Reflects the logic level on the port pins at the time of interrupt due to pin change <7:0>
1 = Logic-high
0 = Logic-low
REGISTER 3-10: GPIO: GENERAL PURPOSE I/O PORT REGISTER (ADDR 0x09)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 GP<7:0>: Reflects the logic level on the pins <7:0>
1 = Logic-high
0 = Logic-low
MCP23017/MCP23S17
DS20001952C-page 24 2005-2016 Microchip Technology Inc.
3.5.11 OUTPUT LATCH REGISTER (OLAT)
The OLAT register provides access to the output
latches. A read from this register results in a read of the
OLAT and not the port itself. A write to this register
modifies the output latches that modifies the pins
configured as outputs.
3.6 Interrupt Logic
If enabled, the MCP23X17 activates the INTn interrupt
output when one of the port pins changes state or when
a pin does not match the preconfigured default. Each
pin is individually configurable as follows:
Enable/disable interrupt via GPINTEN
Can interrupt on either pin change or change from
default as configured in DEFVAL
Both conditions are referred to as Interrupt-on-Change
(IOC).
The interrupt control module uses the following
registers/bits:
IOCON.MIRROR – controls if the two interrupt
pins mirror each other
GPINTEN – Interrupt enable register
INTCON – controls the source for the IOC
DEFVAL – contains the register default for IOC
operation
3.6.1 INTA AND INTB
There are two interrupt pins: INTA and INTB. By
default, INTA is associated with GPAn pins (PORTA)
and INTB is associated with GPBn pins (PORTB).
Each port has an independent signal which is cleared if
its associated GPIO or INTCAP register is read.
3.6.1.1 Mirroring the INT pins
Additionally, the INTn pins can be configured to mirror
each other so that any interrupt will cause both pins to
go active. This is controlled via IOCON.MIRROR.
If IOCON.MIRROR = 0, the internal signals are routed
independently to the INTA and INTB pads.
If IOCON.MIRROR = 1, the internal signals are OR’ed
together and routed to the INTn pads. In this case, the
interrupt will only be cleared if the associated GPIO or
INTCAP is read (see Table 3-6).
3.6.2 IOC FROM PIN CHANGE
If enabled, the MCP23X17 generates an interrupt if a
mismatch condition exists between the current port
value and the previous port value. Only IOC-enabled
pins will be compared. Refer to Registers 3-3 and 3-5.
3.6.3 IOC FROM REGISTER DEFAULT
If enabled, the MCP23X17 generates an interrupt if a
mismatch occurs between the DEFVAL register and
the port. Only IOC enabled pins are compared. Refer to
Registers 3-3, 3-4 and 3-5.
REGISTER 3-11: OLAT: OUTPUT LATCH REGISTER 0 (ADDR 0x0A)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 OL<7:0>: Reflects the logic level on the output latch <7:0>
1 = Logic-high
0 = Logic-low
TABLE 3-6: INTERRUPT OPERATION
(IOCON.MIRROR = 1)
Interrupt
Condition Read PORTn (1)Interrupt
Result
GPIOA PORTA Clear
PORTB Unchanged
GPIOB PORTA Unchanged
PORTB Clear
GPIOA and
GPIOB
PORTA Unchanged
PORTB Unchanged
Both PORTA and
PORTB Clear
Note 1: PORTn = GPIOn or INTCAPn
2005-2016 Microchip Technology Inc. DS20001952C-page 25
MCP23017/MCP23S17
3.6.4 INTERRUPT OPERATION
The INTn interrupt output can be configured as
active-low, active-high or open-drain via the IOCON
register.
Only those pins that are configured as an input (IODIR
register) with Interrupt-On-Change (IOC) enabled
(IOINTEN register) can cause an interrupt. Pins
defined as an output have no effect on the interrupt
output pin.
Input change activity on a port input pin that is enabled
for IOC generates an internal device interrupt and the
device captures the value of the port and copies it into
INTCAP. The interrupt remains active until the INTCAP
or GPIO register is read. Writing to these registers does
not affect the interrupt. The interrupt condition is
cleared after the LSb of the data is clocked out during
a read command of GPIO or INTCAP.
The first interrupt event causes the port contents to be
copied into the INTCAP register. Subsequent interrupt
conditions on the port will not cause an interrupt to
occur as long as the interrupt is not cleared by a read
of INTCAP or GPIO.
3.6.5 INTERRUPT CONDITIONS
There are two possible configurations that cause
interrupts (configured via INTCON):
1. Pins configured for interrupt-on-pin change
will cause an interrupt to occur if a pin changes
to the opposite state. The default state is reset
after an interrupt occurs and after clearing the
interrupt condition (i.e., after reading GPIO or
INTCAP). For example, an interrupt occurs by
an input changing from ‘1’ to0’. The new initial
state for the pin is a logic ‘0’ after the interrupt is
cleared.
2. Pins configured for interrupt-on-change from
register value will cause an interrupt to occur if
the corresponding input pin differs from the
register bit. The interrupt condition will remain as
long as the condition exists, regardless if the
INTCAP or GPIO is read.
See Figures 3-8 and 3-9 for more information on
interrupt operations.
FIGURE 3-8: INTERRUPT-ON-PIN
CHANGE
FIGURE 3-9: INTERRUPT-ON-CHANGE
FROM REGISTER
DEFAULT
Note: The value in INTCAP can be lost if GPIO
is read before INTCAP while another IOC
is pending. After reading GPIO, the
interrupt will clear and then set due to the
pending IOC, causing the INTCAP
register to update.
GPx
INT ACTIVE ACTIVE
Port value
is captured
into INTCAP
Read GPIO
or INTCAP Port value
is captured
into INTCAP
INT
Port value
is captured
into INTCAP
Read GPIO
or INTCAP
DEFVAL REGISTER
X X X X X 0 X X
GP2
76543210
GPx<7:0>
ACTIVE
ACTIVE
(INT clears only if interrupt
condition does not exist.)
Pin
Pin
' ’3‘ xxxxxxx xxxxxxx YYWWNNN HHHEJHH[HHHHHH XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX ea C) SQ YHNWNNN 'UUHLJHULHUUHUH' fl K/Q HHHHHHHHHHHHHH C) S? HUHHHHUHUHUUUH HHHHHHHHHHHHHH om UUUUUUUUUUUUUU HHHHHHHHHHHHHH () SQ UUUHUHUUHHUUUU NNN
MCP23017/MCP23S17
DS20001952C-page 26 2005-2016 Microchip Technology Inc.
4.0 PACKAGING INFORMATION
4.1 Package Marking Information
MCP23017-E/SO
3
e
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
28-Lead SOIC Example:
28-Lead SSOP
YYWWNNN
XXXXXXXXXXXX
XXXXXXXXXXXX
Example:
28-Lead QFN Example:
28-Lead SPDIP Example:
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNN
MCP23017-E/SP
1628256
3
e
MCP23017
E/SS
3
e
1628256
23017
E/ML
1628256
3
e
1628256
28-Lead Plastic Quad Flat, No Lead Package (ML) - 6x6 mm Body [QFN] With 0.55 mm Terminal Length Note: For me mosx currem package drawings. please see me Microcmp Packagmg Specxficaxion localed al http'//www mmrochlp Dom/packaging NOTE1 ///// 1 W/;// 2 // (DATUMA)—/ /// I: <—iei—>>-fl (DATUM B) 7 2x Q 0.15 c 2X 5 0-15 C TOP VIEW — A ‘ // 010 c SEATING E ’4I:D—D—D—D—D—D—D—I 11" 7 7* PLANE J 23X A3 7 A1 E 0.08 SIDE VIEW <1} o.10®="" z:="" a="" b="" 52="" 7="" 28x="" k="" m="" .="" 7="" i="" n="" 25x="" i.="" )l="" l="" 28x="" b="" 010®="" c="" aibi="" ‘9="" 0.05®="" c="" bottom="" view="" microcmp="" technoiogy="" drawmg="" comosc="" sheeh="" 0'2="">
2005-2016 Microchip Technology Inc. DS20001952C-page 27
MCP23017/MCP23S17
28-Lead Plastic Quad Flat, No Lead Package (ML) - 6x6 mm Body [QFN] With 0.55 mm Terminal Length Note: For me mosl current package drawings. please see me Microchip Packaging Specificaiicn iccaied at http [/www microchip com/packaging Uniis MiLLIMETERS Dimensio Limits MIN | NOM \ MAX Number of Pins N 25 Pitch e 0.55 ass Overail Height A o 00 o 90 i 00 Stands" A1 0 00 0.02 0.05 Terminai Thickness A3 0 2o REF Overaii Widlh E 5.00 ass Exposed Pad Widm E2 3 65 i 3.70 | 4.20 Overaii Lenglh D s 00 asc Exposed Pad Lengiii 02 3 65 3.70 4.20 Terrrrirrai wium n o 23 o 30 0 35 Terminai Length L o 50 0.55 0.70 TerminairtorExposed Pad K o 20 . , Moles: 1. Pin 1 visuai index feamre may vary. cm mus‘ be \Dcaled Wllhlri the hamhed area. 2 Package is saw singulaled 3. Dimensrening arid Iolerancing per ASME Y14.5M. BSC Basic Dlmensiun Theurehcaliy exam value shown wlmoufi mierances REF' Relerence Dimension, usualiy without (oierance, Vor inlormation purposes oniy Micmchip Tecnncicgy Drawing 004-1050 Sheet 2 of 2
MCP23017/MCP23S17
DS20001952C-page 28 2005-2016 Microchip Technology Inc.
l T é m WHEDDUDE la 02 |:| |:| t f G U |:| |:| —i m m i 7 7 7 }|:| |:| |:| |:| |:| |: Y1 X1 ,1 E ? SILK SCREEN RECOMMENDED LAND PATTERN Links MiLLIMETERS Dimension LimiKs MIN \ NOM \ MAX Coniaci Pm E o 65 BSC Ophonal Center Fad Width W2 A 25 Optional Cenler Fad Length T2 4 25 Contacl Pad Spacmg c1 5.70 Contad Pad Spacing 02 5.70 Contact Pad Width (x23) x1 0.37 Contact Pad Length (x25) Y1 1.00 Distance Between Pads G U 20 Notes: 1 Dimensionmg and toierancmg per ASME v14 SM 380. BaSic Dimensian. Theorehcafly exad vame Shawn without tolerances Microchip Technoiogy Drawing No {20472105A
2005-2016 Microchip Technology Inc. DS20001952C-page 29
MCP23017/MCP23S17
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MCP23017/MCP23S17
DS20001952C-page 30 2005-2016 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
28-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC] 4X17 Umls MILLIMETERS Dimension leils MIN | NOM | MAX Number of Pins N 25 Pltcl’l e 1.27 850 Overall Helght A - - 2 65 Molded Package Thlckness A2 2 05 , , Slandorf § A1 010 - o 30 Overall Wldlh E 10 30 asc Molded Package Width E1 7 50 BSC Overall Length D 17 so 550 Chamfer (Optlonal) n o 25 - 0 75 Foot Length L o 40 , 1 27 Footprlnl L1 1 40 REF Lead Angle e 0” , , Foot Angle 10 0’ - a" Lead Thlckness c 018 , o 33 Lead Width b o 31 , o 51 Mold Draft Angle Top 01 5° , 15" Mold Draft Angle Bottom 1‘? 5" , 15" Notes: 1 2. 3. Plrl 1 vlsual lrldex leature may vary‘ but must be located wlthln the hatched area §slgnl1lcanl Characterlsllc Dlmension D does not lnclude mold flash‘ protrusmns or gale burrs, which shall not exceed 0 15 mm per end. Dlmensmn E1 does nal include lnlerlead llash or prolruslon‘ wnlcn snall nnl exceed 0 25 mm per srde Dlmensionlng and Iolerancing per ASME Y14.5M 550 523le Dlmenslon Theoretlcally exact value shown wlttlout tolerances REF. Relerence DimenSlon usually wllllout tolerance, for lnformatlon purposes only Datums A Sr B to be determlned at Datum H Microchlp Technology Drawing c047052c Sheet 2 on
2005-2016 Microchip Technology Inc. DS20001952C-page 31
MCP23017/MCP23S17
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
28-Lead Plastic Small Out‘ine (SO) - Wide, 7.50 mm Body [SOIC] —>| ‘—— Gx 4*74HHHDHDHUDDDHDH S‘LK / SCREEN ‘ 0 ‘ v :HWWDDDHDDDDDDDEE, E 4 le »| L x RECOMMENDED LAND PATTERN UNIS MILLIMETERS Dxmension mew|s MW \ NOM \ MAX Contact Pwtch E 1 27 BSC Comact Pad Spacing c 9.40 Contact Pad wmh (x23) x n so Comact Fad Length (X28) Y 2.00 Distance Bewveen Pads Gx o 67 Dlslance Between Pads S 7.40 Notes 1 Dwmensiomng and to‘erancmg perASME v14 5M BSC: Bash: Dimenswon Theoreucany exact va‘ue shown wuhom ko‘erances chrochip Technology Drawmg No. 00472052}:
MCP23017/MCP23S17
DS20001952C-page 32 2005-2016 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2005-2016 Microchip Technology Inc. DS20001952C-page 33
MCP23017/MCP23S17
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MCP23017/MCP23S17
DS20001952C-page 34 2005-2016 Microchip Technology Inc.
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2005-2016 Microchip Technology Inc. DS20001952C-page 35
MCP23017/MCP23S17
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP23017/MCP23S17
DS20001952C-page 36 2005-2016 Microchip Technology Inc.
NOTES:
2005-2016 Microchip Technology Inc. DS20001952C-page 37
MCP23017/MCP23S17
APPENDIX A: REVISION HISTORY
Revision C (July 2016)
The following is the list of modifications:
1. Added ESD data to Section 1.0, Electrical
Characteristics.
2. Updated Table 2-1.
3. Updated package outline drawings.
4. Minor typographical errors
Revision B (February 2007)
1. Changed Byte and Sequential Read in
Figure 1-1 from “R” to “W”.
2. Table 2-4, Param No. 51 and 53: Changed from
450 to 600 and 500 to 600, respecively.
3. Added disclaimers to package outline drawings.
4. Updated package outline drawings.
Revision A (June 2005)
Original release of this document.
MCP23017/MCP23S17
DS20001952C-page 38 2005-2016 Microchip Technology Inc.
NOTES:
PART N0. 2 x 4' 41x
2005-2016 Microchip Technology Inc. DS20001952C-page 39
MCP23017/MCP23S17
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP23017: 16-Bit I/O Expander with I2C Interface
MCP23S17: 16-Bit I/O Expander with SPI Interface
Temperature
Range: E=-40C to +125C (Extended)
Package: ML = Plastic Quad Flat, No Lead Package, 6x6 mm
Body, QFN, 28-lead
SO = Plastic Small Outline, Wide, 7.50 mm Body, SOIC,
28-Lead
SP = Skinny Plastic Dual In-Line, 300 mil Body, SPDIP,
28-Lead
SS = Plastic Shrink Small Outline, 5.30 mm Body,
SSOP, 28-Lead
Tape and Reel
Option: T = Tape and Reel (1)
Blank = Tube
PART NO. X/XX
PackageTemperature
Range
Device
Examples:
a) MCP23017-E/ML: Extended temperature,
28LD QFN package
b) MCP23017T-E/ML: Extended temperature,
28LD QFN package,
Tape and Reel
c) MCP23017-E/SP: Extended temperature ,
28LD SPDIP package
d) MCP23017-E/SO: Extended temperature,
28LD SOIC package
e) MCP23017T-E/SO: Extended temperature,
28LD SOIC package,
Tape and Reel
f) MCP23017-E/SS: Extended temperature,
28LD SSOP package
g) MCP23017T-E/SS: Extended temperature,
28LD SSOP package,
Tape and Reel
a) MCP23S17-E/ML: Extended temperature,
28LD QFN package
b) MCP23S17T-E/ML: Extended temperature,
28LD QFN package,
Tape and Reel
c) MCP23S17-E/SP: Extended temperature,
28LD SPDIP package
d) MCP23S17-E/SO: Extended temperature,
28LD SOIC package
e) MCP23S17T-E/SO: Extended temperature,
28LD SOIC package,
Tape and Reel
f) MCP23S17-E/SS: Extended temperature,
28LD SSOP package
g) MCP23S17T-E/SS: Extended temperature,
28LD SSOP package
Tape and Reel
X (1)
Tape and Reel
Option
Note 1: Tape and Reel identifier only appears in the
catalog part number description. This identifier
is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
MCP23017/MCP23S17
DS20001952C-page 40 2005-2016 Microchip Technology Inc.
NOTES:
YSTEM
2005-2016 Microchip Technology Inc. DS20001952C-page 41
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2005-2016, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0755-3
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
6‘ ‘MICRDCHIP
DS20001952C-page 42 2005-2016 Microchip Technology Inc.
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06/23/16

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