MCP6001/1R/1U/2/4 Datasheet by Microchip Technology

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‘MICRQICHIP MCP6001I1RI1UI2I4 #9 “g WWW E M HWWWWWF‘ \EHEEHEEHQHE
2002-2020 Microchip Technology Inc. DS20001733L-page 1
MCP6001/1R/1U/2/4
Features
Available in 5-Lead SC-70 and 5-Lead SOT-23
Packages
Gain Bandwidth Product: 1 MHz (typical)
Rail-to-Rail Input/Output
Supply Voltage: 1.8V to 6.0V
Supply Current: IQ = 100 µA (typical)
Phase Margin: 90° (typical)
Temperature Range:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Available in Single, Dual and Quad Packages
Applications
• Automotive
Portable Equipment
Photodiode Amplifier
Analog Filters
Notebooks and PDAs
Battery-Powered Systems
Design Aids
SPICE Macro Models
•FilterLab
® Software
Mindi™ Circuit Designer and Analog Simulator
Microchip Advanced Part Selector (MAPS)
Analog Demonstration and Evaluation Boards
Application Notes
Typical Application
Description
The Microchip Technology Inc. MCP6001/2/4 family of
operational amplifiers (op amps) is specifically
designed for general purpose applications. This family
has a 1 MHz Gain Bandwidth Product (GBWP) and 90°
phase margin (typical). It also maintains a 45° phase
margin (typical) with a 500 pF capacitive load. This
family operates from a single-supply voltage as low as
1.8V, while drawing 100 µA (typical) quiescent current.
Additionally, the MCP6001/2/4 supports rail-to-rail input
and output swing, with a Common-mode input voltage
range of VDD + 300 mV to VSS 300 mV. This family of
op amps is designed with Microchip’s advanced CMOS
process.
The MCP6001/2/4 family is available in the industrial
and extended temperature ranges, with a power supply
range of 1.8V to 6.0V.
Package Types
R1
VOUT
R2
VIN
VDD
+
Gain 1
R1
R2
------+=
Noninverting Amplifier
MCP6001
VREF
VSS
4
5
4
5
4
MCP6001
1
2
3
5VDD
VIN-
VOUT
VSS
VIN+
5-Lead SC70, SOT-23
MCP6002
8-Lead PDIP, SOIC, MSOP
MCP6004
VINA+
VINA-
VSS
1
2
3
4
14
13
12
11
VOUTA
+
+
VDD
VOUTD
VIND-
VIND+
10
9
8
5
6
7
VOUTB
VINB-
VINB+V
INC+
VINC-
VOUTC
++
14-Lead PDIP, SOIC, TSSOP
VINA+
VINA-
VSS
1
2
3
4
8
7
6
5
VOUTA
+
VDD
VOUTB
VINB-
VINB+
MCP6001R
5-Lead SOT-23
1
2
3
VSS
VIN-
VOUT
VDD
VIN+
MCP6001U
5-Lead SOT-23
1
2
3
VDD
VOUT
VIN+
VSS
VIN-
MCP6002
VINA+
VINA-
VSS
VOUTB
VINB-
1
2
3
4
8
7
6
5VINB+
VOUTA
EP
9
VDD
8-Lead 2x3 DFN*
*Includes Exposed Thermal Pad (EP); see Table 3-1.
+
+
+
+
1 MHz, Low-Power Op Amp
MCP6001/1R/1U/2/4
DS20001733L-page 2 2002-2020 Microchip Technology Inc.
NOTES:
2002-2020 Microchip Technology Inc. DS20001733L-page 3
MCP6001/1R/1U/2/4
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings
VDD –V
SS ........................................................................7.0V
Current at Analog Input Pins (VIN+, VIN-)......................±2 mA
Analog Inputs (VIN+, VIN-)††.......... VSS –1.0VtoV
DD +1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD +0.3V
Difference Input Voltage ...................................... |VDD –V
SS|
Output Short-Circuit Current ................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ....................................-65°C to +150°C
Maximum Junction Temperature (TJ)......................... .+150°C
ESD Protection On All Pins (HBM; MM)   4 kV; 200V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and func-
tional operation of the device at those or any other
conditions above those indicated in the operational
listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods
may affect device reliability.
†† See Section 4.1.2 “Input Voltage and Current
Limits”.
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VL = VDD/2,
RL = 10 kto VL and VOUT VDD/2 (refer to Figure 1-1).
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage VOS -4.5 +4.5 mV VCM = VSS (Note 1)
Input Offset Drift with Temperature VOS/TA—±2.0µV/°CT
A= -40°C to +125°C,
VCM = VSS
Power Supply Rejection Ratio PSRR 86 dB VCM = VSS
Input Bias Current and Impedance
Input Bias Current: IB— ±1.0 pA
Industrial Temperature IB—19pAT
A = +85°C
Extended Temperature IB 1100 pA TA = +125°C
Input Offset Current IOS — ±1.0 pA
Common-Mode Input Impedance ZCM —10
13||6 ||pF
Differential Input Impedance ZDIFF —10
13||3 ||pF
Common-Mode
Common-Mode Input Range VCMR VSS 0.3 — VDD + 0.3 V
Common-Mode Rejection Ratio CMRR 60 76 dB VCM = -0.3V to 5.3V, VDD = 5V
Open-Loop Gain
DC Open-Loop Gain (Large Signal) AOL 88 112 dB VOUT = 0.3V to VDD0.3V,
VCM =V
SS
Output
Maximum Output Voltage Swing VOL, VOH VSS + 25 — VDD25 mV VDD = 5.5V,
0.5V input overdrive
Output Short-Circuit Current ISC —±6—mAV
DD = 1.8V
—±23mAV
DD = 5.5V
Power Supply
Supply Voltage VDD 1.8 6.0 V Note 2
Quiescent Current per Amplifier IQ50 100 170 µA IO = 0, VDD = 5.5V, VCM = 5V
Note 1: MCP6001/1R/1U/2/4 parts with date codes prior to December 2004 (week code 49) were tested to ±7 mV
minimum/maximum limits.
2: All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However, the
other minimum and maximum specifications are measured at 1.8V and 5.5V.
MCP6001/1R/1U/2/4
DS20001733L-page 4 2002-2020 Microchip Technology Inc.
AC ELECTRICAL SPECIFICATIONS
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8 to 5.5V, VSS = GND, VCM = VDD/2,
VL = VDD/2, VOUT VDD/2, RL = 10 k to VL and CL = 60 pF (refer to Figure 1-1).
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP 1.0 MHz
Phase Margin PM 90 ° G = +1 V/V
Slew Rate SR 0.6 V/µs
Noise
Input Noise Voltage Eni 6.1 µVp-p f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni —28nV/Hz f = 1 kHz
Input Noise Current Density ini —0.6fA/Hz f = 1 kHz
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Industrial Temperature Range TA-40 +85 °C
Extended Temperature Range TA-40 — +125 °C
Operating Temperature Range TA-40 +125 °C Note 1
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5-Lead SC70 JA 331 — °C/W
Thermal Resistance, 5-Lead SOT-23 JA 256 — °C/W
Thermal Resistance, 8-Lead PDIP JA —85—°C/W
Thermal Resistance, 8-Lead SOIC (150 mil) JA 163 — °C/W
Thermal Resistance, 8-Lead MSOP JA 206 — °C/W
Thermal Resistance, 8-Lead DFN (2x3) JA —68—°C/W
Thermal Resistance, 14-Lead PDIP JA —70—°C/W
Thermal Resistance, 14-Lead SOIC JA 120 — °C/W
Thermal Resistance, 14-Lead TSSOP JA 100 — °C/W
Note 1: The industrial temperature devices operate over this extended temperature range, but with reduced
performance. In any case, the internal Junction Temperature (TJ) must not exceed the Absolute Maximum
specification of +150°C.
gfl—U‘ $7474 i l FIGURE 1-1: AC and DC Test Circuit for
2002-2020 Microchip Technology Inc. DS20001733L-page 5
MCP6001/1R/1U/2/4
1.1 Test Circuits
The circuit used for most DC and AC tests is shown in
Figure 1-1. This circuit can independently set VCM and
VOUT
; see Equation 1-1. Note that VCM is not the
circuit’s Common-mode voltage ((VP + VM)/2) and that
VOST includes VOS plus the effects (on the input offset
error, VOST) of temperature, CMRR, PSRR and AOL.
EQUATION 1-1:
FIGURE 1-1: AC and DC Test Circuit for
Most Specifications.
GDM RFRG
=
VCM VPVDD 2
+2
=
VOUT VDD 2
VPVM
VOST 1G
DM
+++=
Where:
GDM = Differential-Mode Gain (V/V)
VCM = Op Amp’s Common-Mode
Input Voltage
(V)
VOST = Op Amp’s Total Input Offset
Voltage
(mV)
VOST VIN– VIN+
=
VDD
RGRF
VOUT
VM
CB2
CL
RL
VL
CB1
100 k100 k
RGRF
VDD/2
VP
100 k100 k
60 pF10 k
F100 nF
VIN-
VIN+
CF
6.8 pF
CF
6.8 pF
MCP600X +
MCP6001/1R/1U/2/4
DS20001733L-page 6 2002-2020 Microchip Technology Inc.
NOTES:
FIGURE 2-1: lnput Offset Voltage. FIGURE 2-4: lnput Offset Voltage vs. FIGURE 2-2: Input Offset Voltage Dn'l‘t, FIGURE 2-5: lnput Offset Voltage vs. FIGURE 2-3: lnput Offset Quadratic FIGURE 2-6: lnput Offset Voltage vs.
2002-2020 Microchip Technology Inc. DS20001733L-page 7
MCP6001/1R/1U/2/4
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 10 kto VL and CL = 60 pF.
FIGURE 2-1: Input Offset Voltage.
FIGURE 2-2: Input Offset Voltage Drift.
FIGURE 2-3: Input Offset Quadratic
Temp. C o.
FIGURE 2-4: Input Offset Voltage vs.
Common-Mode Input Voltage at VDD = 1.8V.
FIGURE 2-5: Input Offset Voltage vs.
Common-Mode Input Voltage at VDD = 5.5V.
FIGURE 2-6: Input Offset Voltage vs.
Output Voltage.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
5-4-3-2-1012345
Input Offset Voltage (mV)
Percentage of Occurrences
64,695 Samples
VCM = VSS
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
-12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12
Input Offset Voltage Drift;
TC1 (µV/°C)
Percentage of Occurrences
2453 Samples
TA = -40°C to +125°C
VCM = VSS
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
-0.02
-0.01
0.00
0.01
0.02
0.03
0.04
0.05
0.06
0.07
Input Offset Quadratic Temp. Co.;
TC2 (µV/°C2)
Percentage of Occurrences
2453 Samples
TA = -40°C to +125°C
VCM = VSS
-700
-600
-500
-400
-300
-200
-100
0
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 1.8V
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
-700
-600
-500
-400
-300
-200
-100
0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 5.5V
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
-200
-150
-100
-50
0
50
100
150
200
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Input Offset Voltage (µV)
VDD = 1.8V
VCM = VSS
VDD = 5.5V
uenc FIGURE 2-8: Input 3135 Current at
MCP6001/1R/1U/2/4
DS20001733L-page 8 2002-2020 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 10 kto VL and CL = 60 pF.
FIGURE 2-7: Input Bias Current at +85°C.
FIGURE 2-8: Input Bias Current at
+125°C.
FIGURE 2-9: CMRR, PSRR vs. Ambient
Temperature.
FIGURE 2-10: PSRR, CMRR vs.
Frequency.
FIGURE 2-11: Open-Loop Gain, Phase vs.
Frequency.
FIGURE 2-12: Input Noise Voltage Density
vs. Frequency.
0%
2%
4%
6%
8%
10%
12%
14%
0 3 6 9 12 15 18 21 24 27 30
Input Bias Current (pA)
Percentage of Occurrences
1230 Samples
VDD = 5.5V
VCM = VDD
TA = +85°C
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
55%
0
150
300
450
600
750
900
1050
1200
1350
1500
Input Bias Current (pA)
Percentage of Occurrences
605 Samples
VDD = 5.5V
VCM = VDD
TA = +125°C
70
75
80
85
90
95
100
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
PSRR, CMRR (dB)
PSRR (VCM = VSS)
CMRR (VCM = -0.3V to +5.3V)
VDD = 5.0V
20
30
40
50
60
70
80
90
100
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
Frequency (Hz)
PSRR, CMRR (dB)
PSRR+
CMRR
PSRR–
VCM = VSS
10 100 1k 10k 100k
-20
0
20
40
60
80
100
120
1.E-
01
1.E+
00
1.E+
01
1.E+
02
1.E+
03
1.E+
04
1.E+
05
1.E+
06
1.E+
07
Frequency (Hz)
Open-Loop Gain (dB)
-210
-180
-150
-120
-90
-60
-30
0
Open-Loop Phase (°)
0.1 1 10 100 10k 100k 1M 10M
Phase
Gain
1k
VCM = VSS
10
100
1,000
1.E-01 1.E+0
0
1.E+0
1
1.E+0
2
1.E+0
3
1.E+0
4
1.E+0
5Frequency (Hz)
Input Noise Voltage Density
(nV/Hz)
0.1 101 100 10k1k 100k
FIGURE 2-13: Output Short-Circuit Current FIGURE 2-16: Small-Signal, Noninvert/‘ng FIGURE 2-14: Output Voltage Headmom FIGURE 2-17: Large-Signal, Noninvening FIGURE 2-15: Quiescent Current vs.
2002-2020 Microchip Technology Inc. DS20001733L-page 9
MCP6001/1R/1U/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 10 kto VL and CL = 60 pF.
FIGURE 2-13: Output Short-Circuit Current
vs. Power Supply Voltage.
FIGURE 2-14: Output Voltage Headroom
vs. Output Current Magnitude.
FIGURE 2-15: Quiescent Current vs.
Power Supply Voltage.
FIGURE 2-16: Small-Signal, Noninverting
Pulse Response.
FIGURE 2-17: Large-Signal, Noninverting
Pulse Response.
FIGURE 2-18: Slew Rate vs. Ambient
Temperature.
0
5
10
15
20
25
30
0.00.51.01.52.02.53.03.54.04.55.05.5
Power Supply Voltage (V)
Short Circuit Current
Magnitude (mA)
TA
= -40°C
TA
= +25°C
TA
= +85°C
TA
= +125°C
1
10
100
1,000
1.E-05 1.E-04 1.E-03 1.E-02
Output Current Magnitude (A)
Output Voltage Headroom
(mV)
VDD – VOH
10µ 10m1m100µ
VOL – VSS
0
20
40
60
80
100
120
140
160
180
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Quiescent Current
per amplifier (µA)
VCM = VDD - 0.5V
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.E+00 1.E- 06 2.E-0 6 3.E-06 4.E-06 5. E-06 6 .E-06 7. E-06 8.E -06 9. E-06 1.E -05
Time (1 µs/div)
Output Voltage (20 mV/div)
G = +1 V/V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.E+00 1.E- 05 2.E-05 3 .E-05 4.E -05 5.E- 05 6.E-05 7. E-05 8.E -05 9.E- 05 1.E-04
Time (10 µs/div)
Output Voltage (V)
G = +1 V/V
VDD = 5.0V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Slew Rate (V/µs)
VDD = 5.5V
VDD = 1.8V
Rising Edge
Falling Edge
FIGURE 2-19: Output Voltage Swing vs. FIGURE 2-21: The MCP6001/2/4 Show No FIGURE 2-20: Measured Input Current vs.
MCP6001/1R/1U/2/4
DS20001733L-page 10 2002-2020 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 10 kto VL and CL = 60 pF.
FIGURE 2-19: Output Voltage Swing vs.
Frequency.
FIGURE 2-20: Measured Input Current vs.
Input Voltage (below VSS).
FIGURE 2-21: The MCP6001/2/4 Show No
Phase Reversal.
0.1
1
10
1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
Output Voltage Swing (V P-P)
VDD = 5.5V
1k 10k 100k 1M
VDD = 1.8V
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Input Current Magnitude (A)
+125°C
+85°C
+25°C
-40°C
10m
1m
100µ
10µ
100n
10n
1n
100p
10p
1p
-1
0
1
2
3
4
5
6
0.E+00 1.E- 05 2.E-05 3.E -05 4.E-05 5. E-05 6.E-05 7. E-05 8. E-05 9.E-05 1. E-04
Time (10 µs/div)
Input, Output Voltages (V)
VDD = 5.0V
G = +2 V/V
VIN
VOUT
2002-2020 Microchip Technology Inc. DS20001733L-page 11
MCP6001/1R/1U/2/4
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Analog Outputs
The output pins are low-impedance voltage sources.
3.2 Analog Inputs
The noninverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
3.3 Power Supply Pins
The positive power supply (VDD) is 1.8V to 6.0V higher
than the negative power supply (VSS). For normal
operation, the other pins are at voltages between VSS
and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
3.4 Exposed Thermal Pad (EP)
There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the VSS pin; they must
be connected to the same potential on the Printed
Circuit Board (PCB).
MCP6001 MCP6001R MCP6001U MCP6002 MCP6004
Symbol Description
5-Lead
SC70,
SOT-23
5-Lead
SOT-23
5-Lead
SOT-23
8-Lead
MSOP,
PDIP, SOIC
8-Lead
2x3
DFN
8-Lead
PDIP, SOIC,
TSSOP
1 1 4 111V
OUT
, VOUTA Analog Output (Op Amp A)
4 4 3 222V
IN-, VINA- Inverting Input (Op Amp A)
3 3 1 333V
IN+, VINA+ Noninverting Input (Op Amp A)
5 2 5 884 V
DD Positive Power Supply
— — 555 V
INB+ Noninverting Input (Op Amp B)
— — 666 V
INB- Inverting Input (Op Amp B)
777 V
OUTB Analog Output (Op Amp B)
—— — 8V
OUTC Analog Output (Op Amp C)
—— 9 V
INC- Inverting Input (Op Amp C)
—— — 10V
INC+ Noninverting Input (Op Amp C)
25 2 4411V
SS Negative Power Supply
—— — 12V
IND+ Noninverting Input (Op Amp D)
—— — 13V
IND- Inverting Input (Op Amp D)
—— — 14V
OUTD Analog Output (Op Amp D)
9 EP Exposed Thermal Pad (EP);
must be connected to VSS.
MCP6001/1R/1U/2/4
DS20001733L-page 12 2002-2020 Microchip Technology Inc.
NOTES:
O—VW MCFGOOX 7 O—Ww / FIGURE 4-2: Protecting the Analog FIGURE 4-1: Simplified Analog Input ESD
2002-2020 Microchip Technology Inc. DS20001733L-page 13
MCP6001/1R/1U/2/4
4.0 APPLICATION INFORMATION
The MCP6001/2/4 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process and
is specifically designed for low-cost, low-power and
general purpose applications. The low supply voltage,
low quiescent current and wide bandwidth makes the
MCP6001/2/4 ideal for battery-powered applications.
These devices have high phase margin, which makes
them stable for larger capacitive load applications.
4.1 Rail-to-Rail Inputs
4.1.1 PHASE REVERSAL
The MCP6001/1R/1U/2/4 op amp is designed to
prevent phase reversal when the input pins exceed the
supply voltages. Figure 2-21 shows the input voltage
exceeding the supply voltage without any phase
reversal.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors and to minimize Input Bias
(IB) current. The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation and low enough to bypass quick
ESD events within the specified limits.
FIGURE 4-1: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must limit the
currents and voltages at the VIN+ and VIN- pins (see
Absolute Maximum Ratings† at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-2
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN-) from going too far below ground, and
the resistors, R1 and R2, limit the possible current
drawn out of the input pins. Diodes, D1 and D2, prevent
the input pins (VIN+ and VIN-) from going too far above
VDD, and dump any currents onto VDD. When
implemented as shown, resistors, R1 and R2, also limit
the current through D1 and D2.
FIGURE 4-2: Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of
resistors, R1 and R2. In this case, current through the
diodes, D1 and D2, needs to be limited by some other
mechanism. The resistors then serve as inrush current
limiters; the DC current into the input pins (VIN+ and
VIN-) should be very small.
A significant amount of current can flow out of the
inputs when the Common-Mode Voltage (VCM) is below
ground (VSS); see Figure 2-20. Applications that are
high-impedance may need to limit the usable voltage
range.
4.1.3 NORMAL OPERATION
The input stage of the MCP6001/1R/1U/2/4 op amps
use two differential CMOS input stages in parallel. One
operates at low Common-mode input voltage (VCM),
while the other operates at high VCM. With this
topology, the device operates with VCM up to 0.3V
above VDD and 0.3V below VSS.
The transition between the two input stages occurs
when VCM = VDD – 1.1V. For the best distortion and
gain linearity, with noninverting gains, avoid this region
of operation.
4.2 Rail-to-Rail Output
The output voltage range of the MCP6001/2/4 op amps
is VDD – 25 mV (minimum), and VSS + 25 mV
(maximum) when RL = 10 k is connected to VDD/2
and VDD = 5.5V. Refer to Figure 2-14 for more
information.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage
Bond
Pad VIN-
V1
MCP600X
R1
VDD
D1
R1>VSS – (minimum expected V1)
2mA
R2>VSS – (minimum expected V2)
2mA
V2
R2
D2
R3
+
FIGURE 4-3: Output Resistor, R , Li, L FIGURE 4-5: Unused Op Amps. zed Loa (arms FIGURE 4-4: Recommended R Values
MCP6001/1R/1U/2/4
DS20001733L-page 14 2002-2020 Microchip Technology Inc.
4.3 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. While a unity gain buffer (G = +1) is the most
sensitive to capacitive loads, all gains show the same
general behavior.
When driving large capacitive loads with these
op amps (e.g., >100 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitance load.
FIGURE 4-3: Output Resistor, RISO,
Stabilizes Large Capacitive Loads.
Figure 4-4 gives recommended RISO values for different
capacitive loads and gains. The x-axis is the normalized
load capacitance (CL/GN), where GN is the circuit’s noise
gain. For noninverting gains, GN and the signal gain are
equal. For inverting gains, GN is 1+|Signal Gain| (e.g.,
-1 V/V gives GN = +2 V/V).
FIGURE 4-4: Recommended RISO Values
for Capacitive Loads.
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISOs value until the
response is reasonable. Bench evaluation and
simulations with the MCP6001/1R/1U/2/4 SPICE
macro model are very helpful.
4.4 Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with nearby analog parts.
4.5 Unused Op Amps
An unused op amp in a quad package (MCP6004)
should be configured as shown in Figure 4-5. These
circuits prevent the output from toggling and causing
crosstalk. Circuit A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
FIGURE 4-5: Unused Op Amps.
VIN
RISO
VOUT
MCP600X
CL
+
10
100
1000
1.E-11 1.E-10 1.E-09 1.E-08
Normalized Load Capacitance; CL/GN (F)
Recommended RISO (Ω)
GN = 1
GN 2
10p 10n
100p
VDD = 5.0V
RL = 100 k
1n
VDD
VDD
¼ MCP6004 (A) ¼ MCP6004 (B)
R1
R2
VDD
VREF
VREF VDD
R2
R1R2
+
------------------=
+
+
FIGURE 4-6: Example Guard Ring Layout FIGURE 4-8: Active Second-Order
2002-2020 Microchip Technology Inc. DS20001733L-page 15
MCP6001/1R/1U/2/4
4.6 PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6001/1R/1U/2/4 family’s bias current at +25°C
(typically 1 pA).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-6.
FIGURE 4-6: Example Guard Ring Layout
for Inverting Gain.
1. Noninverting Gain and Unity Gain Buffer:
a. Connect the noninverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b. Connect the guard ring to the inverting input
pin (VIN-). This biases the guard ring to the
Common-mode input voltage.
2. Inverting Gain and Transimpedance Gain
Amplifiers (convert current to voltage, such as
photo detectors):
a. Connect the guard ring to the noninverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the
op amp (e.g., VDD/2 or ground).
b. Connect the inverting pin (VIN-) to the input
with a wire that does not touch the PCB
surface.
4.7 Application Circuits
4.7.1 UNITY GAIN BUFFER
The rail-to-rail input and output capability of the
MCP6001/2/4 op amp is ideal for unity gain buffer
applications. The low quiescent current and wide
bandwidth makes the device suitable for a buffer
configuration in an instrumentation amplifier circuit, as
shown in Figure 4-7.
FIGURE 4-7: Instrumentation Amplifier
with Unity Gain Buffer Inputs.
4.7.2 ACTIVE LOW-PASS FILTER
The MCP6001/2/4 op amp’s low input bias current
makes it possible for the designer to use larger resis-
tors and smaller capacitors for active low-pass filter
applications. However, as the resistance increases, the
noise generated also increases. Parasitic capacitances
and the large value resistors could also modify the
frequency response. These trade-offs need to be
considered when selecting circuit elements.
Usually, the op amp bandwidth is 100x the filter cutoff
frequency (or higher) for good performance. It is
possible to have the op amp bandwidth 10x higher than
the cutoff frequency, thus having a design that is more
sensitive to component tolerances.
Figure 4-8 shows a second-order Butterworth filter with
100 kHz cutoff frequency and a gain of +1 V/V; the
op amp bandwidth is only 10x higher than the cutoff
frequency. The component values were selected using
Microchip’s FilterLab® software.
FIGURE 4-8: Active Second-Order
Low-Pass Filter.
Guard Ring
VSS
VIN-V
IN+
VIN1
R2
MCP6002
VIN2
R2
MCP6002
VREF
MCP6001 VOUT
R1
R1
1/2
1/2
VOUT VIN2VIN1

R1
R2
------VREF
+=
R1 = 20 k
R2 = 10 k
+
+
+
14.3 k
MCP6002
VOUT
53.6 k
100 pF
VIN
33 pF
+
FIGURE 4-9: Peak Detector with Clear and Sample CMOS Analog Switches.
MCP6001/1R/1U/2/4
DS20001733L-page 16 2002-2020 Microchip Technology Inc.
4.7.3 PEAK DETECTOR
The MCP6001/2/4 op amp has a high input impedance,
rail-to-rail input/output and low input bias current, which
makes this device suitable for peak detector applica-
tions. Figure 4-9 shows a peak detector circuit with
clear and sample switches. The peak detection cycle
uses a clock (CLK), as shown in Figure 4-9.
At the rising edge of the CLK, the sample switch closes
to begin sampling. The peak voltage stored on C1 is
sampled to C2 for a sample time defined by tSAMP. At the
end of the sample time (falling edge of sample signal),
the clear signal goes high and closes the clear switch.
When the clear switch closes, C1 discharges through R1
for a time defined by tCLEAR. At the end of the clear time
(falling edge of the clear signal), Op Amp A begins to
store the peak value of VIN on C1 for a time defined by
tDETECT
.
In order to define tSAMP and tCLEAR, it is necessary to
determine the capacitor charging and discharging
period. The capacitor charging time is limited by the
amplifier source current, while the discharging time ()
is defined using R1 ( = R1C1). tDETECT is the time that
the input signal is sampled on C1 and is dependent on
the input voltage change frequency.
The op amp output current limit, and the size of the
storage capacitors (both C1 and C2), could create
slewing limitations as the Input Voltage (VIN) increases.
Current through a capacitor is dependent on the size of
the capacitor and the rate of voltage change. From this
relationship, the rate of voltage change or the slew rate
can be determined. For example, with an op amp
short-circuit current of ISC = 25 mA and a load capacitor
of C1 = 0.1 µF, then:
EQUATION 4-1:
This voltage rate of change is less than the
MCP6001/2/4 slew rate of 0.6 V/µs. When the input
voltage swings below the voltage across C1, D1
becomes reverse-biased. This opens the feedback
loop and rails the amplifier. When the input voltage
increases, the amplifier recovers at its slew rate. Based
on the rate of voltage change shown in the above equa-
tion, it takes an extended period of time to charge a
0.1 µF capacitor. The capacitors need to be selected so
that the circuit is not limited by the amplifier slew rate.
Therefore, the capacitors should be less than 40 µF
and a stabilizing resistor (RISO) needs to be properly
selected. (Refer to Section 4.3 “Capacitive Loads”.)
FIGURE 4-9: Peak Detector with Clear and Sample CMOS Analog Switches.
dVC1
dt
-------------
ISC
C1
--------=
25mA
0.1F
---------------=
dVC1
dt
-------------250mV s=
ISC C1
dVC1
dt
-------------=
VIN
MCP6002
VC1
MCP6002
D1
Op Amp A
Op Amp B
VOUT
MCP6001
Op Amp C
C2
Sample Signal
Clear Signal
Clear
RISO
Sample
CLK
tSAMP
tCLEAR
tDETECT
Switch
Switch
1/2
1/2
R1
RISO VC2
C1
+
+
+
2002-2020 Microchip Technology Inc. DS20001733L-page 17
MCP6001/1R/1U/2/4
5.0 DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP6001/1R/1U/2/4 family of op amps.
5.1 SPICE Macro Model
The latest SPICE macro model for the
MCP6001/1R/1U/2/4 op amps is available on the
Microchip website at www.microchip.com. The model
was written and tested in official OrCAD™ (Cadence®)
owned PSpice®. For the other simulators, it may
require translation.
The model covers a wide aspect of the op amp’s
electrical specifications. Not only does the model cover
voltage, current and resistance of the op amp, but it
also covers the temperature and noise effects on the
behavior of the op amp. The model has not been
verified outside of the specification range listed in the
op amp data sheet. The model behaviors under these
conditions can not be ensured that it will match the
actual op amp performance.
Moreover, the model is intended to be an initial design
tool. Bench testing is a very important part of any
design and cannot be replaced with simulations. Also,
simulation results using this macro model need to be
validated by comparing them to the data sheet
specifications and characteristic curves.
5.2 FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip website at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
5.3 Mindi™ Circuit Designer and
Analog Simulator
Microchip’s Mindi™ Circuit Designer and Analog Simula-
tor aids in the design of various circuits useful for active
filter, amplifier and power management applications. It is
a free online circuit designer and simulator available from
the Microchip website at www.microchip.com/mindi. This
interactive circuit designer and analog simulator enables
designers to quickly generate circuit diagrams and
simulate circuits. Circuits developed using the Mindi Cir-
cuit Designer and Analog Simulator can be downloaded
to a personal computer or workstation.
5.4 Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip website at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparison
reports. Helpful links are also provided for Data Sheets,
Purchase and Sampling of Microchip parts.
5.5 Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are designed
to help you achieve faster time to market. For a complete
listing of these boards and their corresponding user’s
guides and technical information, visit the Microchip
website at www.microchip.com/analogtools.
Some boards that are especially useful are:
MCP6XXX Amplifier Evaluation Board 1
MCP6XXX Amplifier Evaluation Board 2
MCP6XXX Amplifier Evaluation Board 3
MCP6XXX Amplifier Evaluation Board 4
Active Filter Demo Board Kit
5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2
8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
14-Pin SOIC/TSSOP/DIP Evaluation Board,
P/N SOIC14EV
MCP6001/1R/1U/2/4
DS20001733L-page 18 2002-2020 Microchip Technology Inc.
5.6 Application Notes
The following Microchip Analog Design Note and
Application Notes are available on the Microchip
website at www.microchip.com/appnotes and are
recommended as supplemental reference resources.
ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits” (DS21821)
AN722: “Operational Amplifier Topologies and DC
Specifications” (DS00722)
AN723: “Operational Amplifier AC Specifications
and Applications” (DS00723)
AN884: “Driving Capacitive Loads With Op Amps”
(DS00884)
AN990: “Analog Sensor Conditioning Circuits –
An Overview” (DS00990)
AN1177: “Op Amp Precision Design: DC Errors”
(DS01177)
AN1228: “Op Amp Precision Design: Random
Noise” (DS01228)
AN1297: “Microchip’s Op Amp SPICE Macro
Models (DS01297)
These application notes and others are listed in the
design guide:
“Signal Chain Design Guide” (DS21825)
HHH H H HHH UUU HH‘Wfi‘Wfl LALuJLuJLJ H H HHH H H HHH H H UUU mflmfl HHHHHH MCP 0% 0’9 mama mmwm NNN
2002-2020 Microchip Technology Inc. DS20001733L-page 19
MCP6001/1R/1U/2/4
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
MCP6002
I/P256
0432
5-Lead SC-70 (MCP6001) Example: (I-Temp)
123
54
5-Lead SOT-23 (MCP6001/1R/1U) Example: (E-Temp)
XXNN
123
54
CD25
XXN (Front)
YWW (Back)
AA7 (Front)
432 (Back)
Device I-Temp
Code
E-Temp
Code
MCP6001 AANN CDNN
MCP6001R ADNN CENN
MCP6001U AFNN CFNN
Note: Applies to 5-Lead SOT-23.
Device I-Temp
Code
E-Temp
Code
MCP6001 AAN CDN
Note: Applies to 5-Lead SC-70.
OR OR
XXNN AA74
Device I-Temp
Code
E-Temp
Code
MCP6001 AANN CDNN
Note: Applies to 5-Lead SC-70.
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
MCP6002
I/P^^256
0746
OR
3
e
8-Lead DFN (2 x 3)
XXX
YWW
NN
Example:
ABY
944
25
HHHH HHHH HHHH QQ 0‘52 0&2 UUUU UUUU UUUU XXXXXX 6002| ofi‘ 0% W W 03‘ 00 W W FF‘WFF‘WH‘WH‘WH‘WH‘WH‘W 03‘ W HHHHHHH HHHHHHH HHHHHHH 0‘3 0% 08‘ UUUUUUU UUUUUUU UUUUUUU HHWHW WHWW WWWH Q ’3‘ ‘3‘ O O O UUUUUUU UUUUUUU UUUUUUU
MCP6001/1R/1U/2/4
DS20001733L-page 20 2002-2020 Microchip Technology Inc.
Package Marking Information (Continued)
8-Lead SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
MCP6002I
SN0432
256
OR
OR
OR
OR
MCP6002I
SN^^0746
256
3
e
3
e
3
e
XXXXXX
8-Lead MSOP
YWWNNN
6002I
Example:
432256
XXXXXXXXXXXXXX
14-Lead PDIP (300 mil) (MCP6004)
XXXXXXXXXXXXXX
YYWWNNN
MCP6004
Example:
I/P
0432256
3
e
MCP6004
E/P
0746256
XXXXXXXXXX
14-Lead SOIC (150 mil) (MCP6004)
XXXXXXXXXX
YYWWNNN
MCP6004ISL
Example:
0432256
MCP6004
E/SL
0746256
XXXXXX
14-Lead TSSOP
(MCP6004)
YYWW
NNN
6004ST
Example:
0432
256
6004STE
0432
256
\ \ \ -—-—- 2x \ \ \\ @015 c x \ 4H ' 2x Eons c TOP VIEW 7 4 ¢ W t PLANE T f SIDE VIEW Microcmp Tech
2002-2020 Microchip Technology Inc. DS20001733L-page 21
MCP6001/1R/1U/2/4
0.15 C
0.15 C
0.10 C A B
C
SEATING
PLANE
13
4
2X
TOP VIEW
SIDE VIEW
Microchip Technology Drawing C04-061-LT Rev E Sheet 1 of 2
2X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
5-Lead Plastic Small Outline Transistor (LT) [SC70]
D
EE1
e
e
5X b
0.30 C
5X TIPS
END VIEW
B
A
N
A
A1
A2
L
c
NOTE 1
MCP6001/1R/1U/2/4
DS20001733L-page 22 2002-2020 Microchip Technology Inc.
Microchip Technology Drawing C04-061-LT Rev E Sheet 2 of 2
Number of Pins
Overall Height
Terminal Width
Overall Width
Terminal Length
Molded Package Width
Molded Package Thickness
Pitch
Standoff
Units
Dimension Limits
A1
A
b
E1
A2
e
L
E
N
0.65 BSC
0.10
0.15
0.80
0.00
-
0.20
1.25 BSC
-
-
2.10 BSC
MILLIMETERS
MIN NOM
5
0.46
0.40
1.10
0.10
MAX
c-0.08 0.26
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Lead Thickness
5-Lead Plastic Small Outline Transistor (LT) [SC70]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Overall Length D 2.00 BSC
0.80 - 1.00
1.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
2002-2020 Microchip Technology Inc. DS20001733L-page 23
MCP6001/1R/1U/2/4
RECOMMENDED LAND PATTERN
Microchip Technology Drawing No. C04-2061-LT Rev E
5-Lead Plastic Small Outline Transistor (LT) [SC70]
12
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M1.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Dimension Limits
Units
CContact Pad Spacing
Contact Pad Width
Contact Pitch
X
MILLIMETERS
0.65 BSC
MIN
E
MAX
Distance Between Pads
Contact Pad Length
G
Y0.95
GxDistance Between Pads 0.20
NOM
0.45
2.20
1.25
X
Y
E
C
Gx
G
3
45
SILK SCREEN
ECU —E— | | ! + ! g N i i | | K1 E3 70/507 7 \; m / /// /‘ / // I Q0.15CD i 2X NOTE1 1 i 2 ‘ i——E|—* IA <—n>
MCP6001/1R/1U/2/4
DS20001733L-page 24 2002-2020 Microchip Technology Inc.
0.15 C D
2X
NOTE 1 12
N
TOP VIEW
SIDE VIEW
Microchip Technology Drawing C04-091-OT Rev F Sheet 1 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
0.20 C
C
SEATING PLANE
AA2
A1
e
NX bB
0.20 CA-B D
e1
D
E1
E1/2
E/2
E
D
A
0.20 C2X
(DATUM D)
(DATUM A-B)
A
A
SEE SHEET 2
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
2002-2020 Microchip Technology Inc. DS20001733L-page 25
MCP6001/1R/1U/2/4
Microchip Technology Drawing C04-091-OT Rev F Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
c
L
L1
T
VIEW A-A
SHEET 1
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
protrusions shall not exceed 0.25mm per side.
1.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2.
Foot Angle
Number of Pins
Pitch
Outside lead pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
Footprint
Lead Thickness
Lead Width
Notes:
L1
I
b
c
Dimension Limits
E
E1
D
L
e1
A
A2
A1
Units
N
e
0.08
0.20 -
-
-
10°
0.26
0.51
MILLIMETERS
0.95 BSC
1.90 BSC
0.30
0.90
0.89
-
0.60 REF
2.90 BSC
-
2.80 BSC
1.60 BSC
-
-
-
MIN
5
NOM
1.45
1.30
0.15
0.60
MAX
REF: Reference Dimension, usually without tolerance, for information purposes only.
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
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MCP6001/1R/1U/2/4
DS20001733L-page 26 2002-2020 Microchip Technology Inc.
RECOMMENDED LAND PATTERN
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
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Dimension Limits
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Overall Width
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Contact Pad Width (X5)
Contact Pitch
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2002-2020 Microchip Technology Inc. DS20001733L-page 27
MCP6001/1R/1U/2/4
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8-Lead P‘astic Dual Flat, No Lead Package (MC) - 2x3x0.9mm Body [DFN] _V * TDD‘ S‘LK SCREEN RECOMMENDED LAND PATTERN Unus MILLIMETERS Dwmenswon meus MW | NOM \ MAX Comact Push E o 50 BSC Op‘lcna‘ Center Pad wmm W2 1 45 Opnonaw Center Pad Lengm T2 1 75 Cement Fad Spacing c1 2 90 Comm Fad Wwdth (X8) x1 0 so Corned Fad Length (xa) v1 0 75 Instance EeMeen Pads 6 o 20 Notes 1 D‘mens‘oning and lolerancing per ASME V14 5M BSC Easwc D‘mensmn Theore‘lca‘ly exam Va‘ue shown wllhout to‘erances Microchip Technology Drawmg No. C04721238
MCP6001/1R/1U/2/4
DS20001733L-page 28 2002-2020 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2002-2020 Microchip Technology Inc. DS20001733L-page 29
MCP6001/1R/1U/2/4
B
A
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
eB
E
A
A1
A2
L
8X b
8X b1
E1
c
C
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.010 C
12
N
D
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END VIEWSIDE VIEW
e
MCP6001/1R/1U/2/4
DS20001733L-page 30 2002-2020 Microchip Technology Inc.
Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e.100 BSC
Top to Seating Plane A - - .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c.008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b.014 .018 .022
Overall Row Spacing eB --.430
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
3.
1.
protrusions shall not exceed .010" per side.
2.
4.
Notes:
§
--
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
Pin 1 visual index feature may vary, but must be located within the hatched area.
§ Significant Characteristic
Dimensioning and tolerancing per ASME Y14.5M
e
DATUM A DATUM A
e
b
e
2
b
e
2
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\ \\\ \ )3 444444 _ ___ _ / /////j \ U i 1 J U NOTE1 1‘ 2‘ +‘ El Le +‘ ‘« NM .4 «MOTH I-I-I TOP VIEW ¢ A A2 SEATING __ ,,,,,,,, PLANE T 8X A1 — SIDE VIEW big 75 SEE V‘EW CJ—J VIEW A— A chrochip Techno‘ogy Drawmg N
2002-2020 Microchip Technology Inc. DS20001733L-page 31
MCP6001/1R/1U/2/4
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C
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0.10 C
0.10 C
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2
8X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
12
N
h
h
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A2
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A
B
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E
E
2
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D
MCP6001/1R/1U/2/4
DS20001733L-page 32 2002-2020 Microchip Technology Inc.
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Foot Angle 0° - 8°
15°-
Mold Draft Angle Bottom
15°-
Mold Draft Angle Top
0.51-0.31
b
Lead Width
0.25-0.17
c
Lead Thickness
1.27-0.40LFoot Length
0.50-0.25hChamfer (Optional)
4.90 BSCDOverall Length
3.90 BSCE1Molded Package Width
6.00 BSCEOverall Width
0.25-0.10
A1
Standoff
--1.25A2Molded Package Thickness
1.75--AOverall Height
1.27 BSC
e
Pitch
8NNumber of Pins
MAXNOMMINDimension Limits
MILLIMETERSUnits
protrusions shall not exceed 0.15mm per side.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
4. Dimensioning and tolerancing per ASME Y14.5M
Notes:
§
Footprint L1 1.04 REF
5. Datums A & B to be determined at Datum H.
T1 D M D k.) m m M ’H\
2002-2020 Microchip Technology Inc. DS20001733L-page 33
MCP6001/1R/1U/2/4
RECOMMENDED LAND PATTERN
Microchip Technology Drawing C04-2057-SN Rev E
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M1.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Dimension Limits
Units
CContact Pad Spacing
Contact Pitch
MILLIMETERS
1.27 BSC
MIN
E
MAX
5.40
Contact Pad Length (X8)
Contact Pad Width (X8)
Y1
X1
1.55
0.60
NOM
E
X1
C
Y1
SILK SCREEN
8-Lead Plastic Micro Small Outline Package (MS) [MSOP] E 2x a W ? _ SEATING PLANE SIDE VIEW A1 7 fl/ SEE DETAIL C _I % 7 J END VIEW Mmmcmp Technology Drawmg C047111C sheet 1 ol 2
MCP6001/1R/1U/2/4
DS20001733L-page 34 2002-2020 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
8-Lead Plastic Micro Small Outline Package (MS) [MSOP] _ _GAUGE PLANE SEATING PLANE . 77 (L1) DETAIL c UNIS MILLIMETERS Dimenslon leils MlN NOM MAX Number el F'lns N l e l Pllch e O 65 BSC Overall Heigm A , , 1 10 Molded Package Thlckness AZ 0.75 0.85 0.95 Standofi A1 0.00 . 0.l5 Overall Wldth E 4 90 BSC Molded Package Width El 3 no asc Overall Length D 3 00 BSC Foot Lenglh l. 0.40 l 0.50 l 0.50 Footprint L1 0 95 REF Foot Angle w 0" . a- Lead Thlckness C D 08 , 0 23 Lead Wldm b [7.22 - 0.40 Notes: 1. Pin 1 visual lndex lealure may vary, but must be located Wllhlh the hatched area 2. Dimenslens D and El :10 ml lnclude mold flash or protrusions. Mold llash or protruswhs shall ngl exceed 0 15mm per slde 3. Dimehslonlng and tolerahcihg per ASME Y14.5M 550. Sam Dlmehsmn. Theorellcally exacl value shown Wllhoul Iolerances. REF' Relevenee Dlmenslon. usually Wlthout tolerance, [or lnformallon puvpcses only Mlcrocllip Technology Drawing 004711“: Sheet 2 ol2
2002-2020 Microchip Technology Inc. DS20001733L-page 35
MCP6001/1R/1U/2/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
8-Lead Plastic Micro SmaH Outlme Package (MS) [MSOP] imr ’* ’ ' ' \ SILK . SCREEN ML- RECOMMENDED LAND PATTERN Unws M‘LLIMETERS Dxmensxon mewls MW | NOM | MAX Contact PiKch E 0.55 550 Contact Pad Spacing c A 40 Overs“ Wldlh Z 5 B5 Conlam Pad wmm (x3) x1 0.45 Conlact Pad Length (x5) w 1.45 DisKance Between Pads :31 2.95 Dismnce Between Pads ex 0.20 Notes: 1 Dimensiomng and lo‘erancmg per ASME V14 5M ESC. Baslc Dlmenslun. Theoreflca‘ly exam va‘ue shown wllhom Io‘erances. Microchip Techno‘ogy Drawmg No 50472111A
MCP6001/1R/1U/2/4
DS20001733L-page 36 2002-2020 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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2002-2020 Microchip Technology Inc. DS20001733L-page 37
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MCP6001/1R/1U/2/4
DS20001733L-page 38 2002-2020 Microchip Technology Inc.
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 1 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
0.20 C
0.25 CA–B D
12
N
2X N/2 TIPS
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SIDE VIEW
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A
e
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E
D
E
2
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E1
E2
2
NX b
A1
A2
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C
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c
h
h
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(L1)
L
R0.13
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0.10 C
NOTE 5
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2X
2X
2002-2020 Microchip Technology Inc. DS20001733L-page 39
MCP6001/1R/1U/2/4
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 2 of 2
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Foot Angle 0° - 8°
15°-
Mold Draft Angle Bottom
15°-
Mold Draft Angle Top
0.51-0.31bLead Width
0.25-0.10
c
Lead Thickness
1.04 REFL1Footprint
0.50-0.25hChamfer (Optional)
8.65 BSCDOverall Length
3.90 BSCE1Molded Package Width
6.00 BSCEOverall Width
0.25-0.10
A1
Standoff
--1.25A2Molded Package Thickness
1.75--AOverall Height
1.27 BSC
e
Pitch
14NNumber of Pins
MAXNOMMINDimension Limits
MILLIMETERSUnits
Foot Length L 0.40 - 1.27
§
or protrusion, which shall not exceed 0.25 mm per side.
3.
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
4.
Notes:
Dimension D does not include mold flash, protrusions or gate burrs, which shall
Pin 1 visual index feature may vary, but must be located within the hatched area.
§ Significant Characteristic
Dimensioning and tolerancing per ASME Y14.5M
not exceed 0.15 mm per end. Dimension E1 does not include interlead flash
5. Datums A & B to be determined at Datum H.
Lead Angle 0° - -
*flUDDDUU / \ L ' ++ .fl a m m D UJUL 54—4
MCP6001/1R/1U/2/4
DS20001733L-page 40 2002-2020 Microchip Technology Inc.
RECOMMENDED LAND PATTERN
Dimension Limits
Units
Contact Pitch
MILLIMETERS
1.27 BSC
MIN
E
MAX
Contact Pad Length (X14)
Contact Pad Width (X14)
Y
X
1.55
0.60
NOM
CContact Pad Spacing 5.40
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M1.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
E
X
Y
C
SILK SCREEN
Microchip Technology Drawing No. C04-2065-SL Rev D
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
12
14
———»>—D HHHWHHH i \ —'—_ \\ x M \ \ \ ‘ \ \ \ \ \ \ \\ \\ \ \\\‘1 HHWHHH *‘EP— TOPVIEW l 7 SEAT‘NG -j_____ri 7 7 _ _ _ _l 1 PLANE ‘ 1 7 J SIDEVIEW I/"\\( \\\-/// VIEW A—A Microcmp Technology Draw
2002-2020 Microchip Technology Inc. DS20001733L-page 41
MCP6001/1R/1U/2/4
TOP VIEW
VIEW A–A
SIDE VIEW
Sheet 1 of 2
Note:
http://www.microchip.com/packaging
For the most current package drawings, please see the Microchip Packaging Specification located at
14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP]
Microchip Technology Drawing C04-087 Rev D
AB
C
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PLANE
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2X 7 TIPS
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14X
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A
A
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D
E
E
2
E1
E1
2
e
A
A2
A1
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MCP6001/1R/1U/2/4
DS20001733L-page 42 2002-2020 Microchip Technology Inc.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1.
2.
Pin 1 visual index feature may vary, but must be located within the hatched area.
Dimensioning and tolerancing per ASME Y14.5M
Sheet 2 of 2
H
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c
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L
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R2
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Molded Package Thickness
Pitch
Standoff
Units
Dimension Limits
A1
A
b
E1
A2
e
L
E
N
0.65 BSC
1.00
0.45
0.19
0.05
0.60
MILLIMETERS
MIN NOM
14
0.75
0.30
1.20
0.15
MAX
L1 1.00 REFFootprint
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Terminal Thickness c0.09–0.20
R1
R2
ș1
0.09 –Lead Bend Radius
0.09 –Lead Bend Radius
0° 8°Foot Angle
ș212° REFMold Draft Angle
0.80 1.05
ș312° REFMold Draft Angle
6.40 BSC
4.40
4.30 4.50
4.90 5.10
14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP]
Microchip Technology Drawing C04-087 Rev D
WI“ *%]DUUUDU \ 4 wwwg D: 45L
2002-2020 Microchip Technology Inc. DS20001733L-page 43
MCP6001/1R/1U/2/4
RECOMMENDED LAND PATTERN
Dimension Limits
Units
Contact Pitch
MILLIMETERS
0.65 BSC
MIN
E
MAX
Contact Pad Length (Xnn)
Contact Pad Width (Xnn)
Y
X
1.45
0.45
NOM
CContact Pad Spacing 5.90
Contact Pad to Contact Pad (Xnn) G 0.20
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M1.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
C
X
Y
G
E
SILK SCREEN
14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP]
Microchip Technology Drawing C04-2087 Rev D
MCP6001/1R/1U/2/4
DS20001733L-page 44 2002-2020 Microchip Technology Inc.
NOTES:
2002-2020 Microchip Technology Inc. DS20001733L-page 45
MCP6001/1R/1U/2/4
APPENDIX A: REVISION HISTORY
Revision L (March 2020)
The following is the list of modifications:
1. Updated package drawings for the 5-Lead
SC-70 and 14-Lead TSSOP packages in
Section 6.0 “Packaging Information”.
Revision K (November 2019)
The following is the list of modifications:
1. Updated Section 6.0 “Packaging
Information”.
Revision J (November 2009)
The following is the list of modifications:
1. Added new 2x3 DFN 8-Lead package on
page 1.
2. Updated the Temperature Specifications table
with 2x3 DFN thermal resistance information.
3. Updated Section 1.1 “Test Circuits”.
4. Updated Figure 2-15.
5. Added the 2x3 DFN column to Table 3-1.
6. Added new Section 3.4 “Exposed Thermal
Pad (EP)”.
7. Updated Section 5.1 “SPICE Macro Model”.
8. Updated Section 5.5 “Analog Demonstration
and Evaluation Boards”.
9. Updated Section 5.6 “Application Notes”.
10. Updated Section 6.1 “Package Marking
Information” with the new 2x3 DFN package
marking information.
11. Updated the package drawings.
12. Updated the Product Identification System
section with new 2x3 DFN package information.
Revision H (May 2008)
The following is the list of modifications:
1. Section 5.0 “Design Aids”: Name change for
Mindi™ Simulation Tool.
2. Package Types: Correct device labeling error.
3. Section 1.0 “Electrical Characteristics”, DC
Electrical Specifications: Changed “Maximum
Output Voltage Swing” condition from 0.9V Input
Overdrive to 0.5V Input Overdrive.
4. Section 1.0 “Electrical Characteristics”, AC
Electrical Specifications: Changed Phase
Margin condition from G = +1 to G= +1 V/V.
5. Section 5.0 “Design Aids: Name change for
Mindi Simulation Tool.
Revision G (November 2007)
The following is the list of modifications:
1. Updated notes to Section 1.0 “Electrical
Characteristics.
2. Increased Absolute Maximum Voltage range at
input pins.
3. Increased maximum operating supply voltage
(VDD).
4. Added test circuits.
5. Added Figure 2-3 and Figure 2-20.
6. Added Section 4.1.1 “Phase Reversal”,
Section 4.1.2 “Input Voltage and Current
Limits”, Section 4.1.3 “Normal Operation
and Section 4.5 “Unused Op Amps.
7. Updated Section 5.0 “Design Aids”,
8. Updated Section 6.0 “Packaging
Information”.
9. Updated Package Outline Drawings.
Revision F (March 2005)
The following is the list of modifications:
1. Updated Section 6.0 “Packaging
Information” to include old and new packaging
examples.
Revision E (December 2004)
The following is the list of modifications:
1. VOS specification reduced to ±4.5 mV from
±7.0 mV for parts starting with date code
YYWW = 0449
2. Corrected package markings in Section 6.0
“Packaging Information”.
3. Added Appendix A: Revision History.
Revision D (May 2003)
Undocumented changes.
Revision C (December 2002)
Undocumented changes.
Revision B (October 2002)
Undocumented changes.
Revision A (June 2002)
Original data sheet release.
2002-2020 Microchip Technology Inc. DS20001733L-page 46
MCP6001/1R/1U/2/4
NOTES:
PART No. Ixx
2002-2020 Microchip Technology Inc. DS20001733L-page 47
MCP6001/1R/1U/2/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP6001T: Single Op Amp (Tape and Reel)
(SC-70, SOT-23)
MCP6001RT: Single Op Amp (Tape and Reel) (SOT-23)
MCP6001UT: Single Op Amp (Tape and Reel) (SOT-23)
MCP6002: Dual Op Amp
MCP6002T: Dual Op Amp (Tape and Reel)
(SOIC, MSOP)
MCP6004: Quad Op Amp
MCP6004T: Quad Op Amp (Tape and Reel)
(SOIC, MSOP)
Temperature Range: I = -40°C to +85°C
E = -40°C to +125°C
Package: LT = Plastic Small Outline Transistor (SC-70), 5-Lead
(MCP6001 only)
OT = Plastic Small Outline Transistor (SOT-23), 5-Lead
(MCP6001, MCP6001R, MCP6001U)
MS = Plastic MSOP, 8-Lead
MC = Plastic Dual Flat, 2x3x0.9 mm (DFN), 8-Lead
P = Plastic DIP, 300 mil Body (PDIP), 8-Lead, 14-Lead
SN = Plastic SOIC (3.90 mm body), 8-Lead
SL = Plastic SOIC (3.90 body), 14-Lead
ST = Plastic TSSOP (4.4 mm body), 14-Lead
PART NO. X/XX
PackageTemperature
Range
Device
Examples:
a) MCP6001T-I/LT: Tape and Reel,
Industrial Temperature,
5-Lead SC-70 Package.
b) MCP6001T-I/OT: Tape and Reel,
Industrial Temperature,
5-Lead SOT-23 Package.
c) MCP6001RT-I/OT: Tape and Reel,
Industrial Temperature,
5-Lead SOT-23 Package.
d) MCP6001UT-E/OT: Tape and Reel,
Extended Temperature,
5-Lead SOT-23 Package.
a) MCP6002-I/MS: Industrial Temperature,
8-Lead MSOP Package.
b) MCP6002-I/P: Industrial Temperature,
8-Lead PDIP Package.
c) MCP6002-E/P: Extended Temperature,
8-Lead PDIP Package.
d) MCP6002-E/MC: Extended Temperature,
8-Lead DFN Package.
e) MCP6002-I/SN: Industrial Temperature,
8-Lead SOIC Package.
f) MCP6002T-I/MS: Tape and Reel,
Industrial Temperature,
8-Lead MSOP Package.
g) MCP6002T-E/MC: Tape and Reel,
Extended Temperature,
8-Lead DFN Package.
a) MCP6004-I/P: Industrial Temperature,
14-Lead PDIP Package.
b) MCP6004-I/SL: Industrial Temperature,
14-Lead SOIC Package.
c) MCP6004-E/SL: Extended Temperature,
14-Lead SOIC Package.
d) MCP6004-I/ST: Industrial Temperature,
14-Lead TSSOP Package.
e) MCP6004T-I/SL: Tape and Reel,
Industrial Temperature,
14-Lead SOIC Package.
f) MCP6004T-I/ST: Tape and Reel,
Industrial Temperature,
14-Lead TSSOP Package.
MCP6001/1R/1U/2/4
DS20001733L-page 48 2002-2020 Microchip Technology Inc.
NOTES:
2002-2020 Microchip Technology Inc. DS20001733L-page 49
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2002-2020, Microchip Technology Incorporated, All Rights
Reserved.
ISBN: 978-1-5224-5717-6
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
6‘ MICROCHIP AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
DS20001733L-page 50 2002-2020 Microchip Technology Inc.
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