Virtex-4 FPGA User Guide Datasheet by Xilinx Inc.

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Virtex-4 FPGA
User Guide
UG070 (v2.6) December 1, 2008
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Virtex-4 FPGA User Guide www.xilinx.com UG070 (v2.6) December 1, 2008
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Revision History
The following table shows the revision history for this document.
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Date Version Revision
08/02/04 1.0 Initial Xilinx release. Printed Handbook version.
09/10/04 1.1 In Chapter 1, “Clock Resources”:
Removed Table 1-6: "BUFGMUX_VIRTEX4 Attributes". Updated Table 1-1, Table 1-2,
Table 1-5, the new Table 1-6. Revised Figure 1-2, Figure 1-5, Figure 1-6, Figure 1-7,
Figure 1-9, Figure 1-10, Figure 1-13, Figure 1-14, and Figure 1-16. Associated text around
these tables and figures were revised.
In Chapter 2, “Digital Clock Managers (DCMs)”, changes to “FACTORY_JF Attribute” and
in Table 2-6.
In Chapter 9, “System Monitor”:
Changed in Figure 9-4, Figure 9-5, Figure 9-7, Figure 9-8, Figure 9-9, Figure 9-10, Figure 9-21,
Figure 9-25, Figure 9-26, and Figure 9-27. Changes to the equation in the Temperature Sensor
section. The following tables had changes: Table 9-3, Table 9-5, Table 9-6, Table 9-9, Table 9-
11, Table 9-12, Table 9-14, and Table 9-15. Changes to the entire System Monitor Calibration,
System Monitor VHDL and Verilog Design Example sections.
02/01/05 1.2 In Chapter 1, “Clock Resources”, revised “Global Clock Buffers”, “Clock Regions”, and
“Clock Capable I/O” sections.
In Chapter 4, “Block RAM,” revised “Reset,” page 151 description and Table 4-13.
In Chapter 6, “SelectIO Resources,” removed the device configuration section. The Virtex-4
Configuration Guide describes this information in detail. Edited “SSTL (Stub-Series
Terminated Logic),” page 281. Replaced LVDS_25_DCI with LVDCI_25 in “Compatible
example:,” page 302. Added rule “7” to DCI in Virtex-4 FPGA Hardware, page 241. Added
“Simultaneous Switching Output Limits,” page 306.
Removed Chapter 9: System Monitor.
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UG070 (v2.6) December 1, 2008 www.xilinx.com Virtex-4 FPGA User Guide
04/11/05 1.3 Chapter 1: Revised Table 1-1, page 26, Figure 1-14, and “BUFR Attributes and Modes”
section including Figure 1-21, page 43.
Chapter 2: Revised FACTORY_JF value in Table 2-6, page 65. Added “Phase-Shift Overflow”
section. Clarified global clock discussion in “Global Clock Buffers”, “Clock Regions”, and
“Clock Capable I/O”.
Chapter 4: Added “Built-in Block RAM Error Correction Code” section. Revised Figure 4-6
and Figure 4-8, page 123.
Chapter 5: Revised Table 5-1 and Table 5-2, page 184.
Chapter 6: Revised Table 6-29, page 290.
Chapter 7: Revised “REFCLK - Reference Clock” and added Table 7-10, page 326.
Chapter 8: Added “ISERDES Latencies,” page 379 and “OSERDES Latencies,” page 394.
Revised “Guidelines for Using the Bitslip Submodule” section.
09/12/05 1.4 Chapter 2: Revised FACTORY_JF value in Table 2-6, page 65. The LOCKED signal
description is updated in Figure 2-20 and Figure 2-21.
Chapter 6: Revised the “Simultaneous Switching Output Limits” section.
Chapter 8: Added more information to “Clock Enable Inputs – CE1 and CE2,” page 369.
03/21/06 1.5 Chapter 1: Updated description under Table 1-1. Updated Figure 1-21, page 43.
Chapter 4: Changed Table 4-8, page 144 and added a note. Updated the discussions in
NO_CHANGE Mode and Cascadable Block RAM sections. Removed synchronous FIFO
application example.
Chapter 5: Revised slice label in Figure 5-30, page 224.
Chapter 6: Added to the “Xilinx DCI” section. Added IBUF to the
“PULLUP/PULLDOWN/KEEPER for IBUF, OBUFT, and IOBUF” discussion. Added VCCO
numbers in the +1.5V column in Table 6-5, page 258. Corrected Figure 6-70, page 292. Added
notes 4 and 5 to Table 6-38, page 299. Updated 3.3V I/O Design Guidelines “Summary,”
page 306. Added “HSLVDCI (High-Speed Low Voltage Digitally Controlled Impedance),”
page 259 section. Added 1.2V to Table 6-40, page 308, and added link to SSO calculator to
text above table. Added HSLVDCI to Table 6-42, page 310. Revised Virtex-4 (SX Family)
FF668 in Table 6-43.
Chapter 8: Revised “Clock Enable Inputs – CE1 and CE2”.
Chapter 9, “Temperature Sensing Diode”: Added the Virtex-4 temperature-sensing diode.
10/06/06 1.6 Chapter 7, “SelectIO Logic Resources”: Modified text in section “REFCLK - Reference
Clock” and deleted former Table 7-10.
Date Version Revision
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Virtex-4 FPGA User Guide www.xilinx.com UG070 (v2.6) December 1, 2008
01/04/07 2.0 Chapter 1, “Clock Resources”:
“I/O Clock Buffer - BUFIO”: Added “in the same region” to BUFIO ability to drive
BUFRs.
“BUFG VHDL and Verilog Templates”: Corrected typo in VHDL template.
“Regional Clocks and I/O Clocks”: Added reference to the PACE tool for identifying
clock regions.
Chapter 2, “Digital Clock Managers (DCMs)”:
“Status Flags”: Corrected descriptions for Clock Events 2, 3, and 4.
“Input Clock Requirements”: Clarified when DCM output clocks are deskewed.
“Reset Input — RST”: Updated RST hold time to 200 ms after clock stabilization.
“Frequency Synthesizer Characteristics”: Added reference and link to a macro for
monitoring LOCKED.
Chapter 4, “Block RAM”:
“Data Flow”: Added paragraph clarifying ADDR setup/hold requirements.
Table 4-11: Corrected typo to ALMOST FULL.
“RAMB16 Port Mapping Design Rules”: Corrected logic level tie for unused
ADDR[A|B] pins to High.
“Synchronous Clocking”: Clarified synchronous write/read timing.
Deleted SIM_COLLISION_CHECK statements from all templates.
Chapter 6, “SelectIO Resources”:
Figure 6-53: Corrected internal termination resistor designation.
Table 6-1: Updated LVTTL DC voltage specifications.
Table 6-31 and following: Globally corrected OBUFGDS to OBUFTDS.
“Differential Termination Attribute”: Corrected paragraph describing use of
DIFF_TERM attribute.
“Xilinx DCI”: Added reference to section “Driver with Termination to VCCO/2 (Split
Termination).”
Figure 6-64: Corrected I/O standard name to DIFF_SSTL2_II.
Table 6-38: Corrected I/O standard name to DIFF_HSTL_II_18_DCI.
Chapter 7, “SelectIO Logic Resources”:
“IDELAYCTRL Locations”: Reworded description of IDELAYCTRL locations in clock
regions.
Table 7-6: Added “when in Variable mode” to function descriptions of C, INC, and CE
ports.
Table 7-9: Added Note (1) to TIDELAYRESOLUTION.
Added requirement to wait 8 clock cycles after increment or decrement before
sampling IDELAY.
Figure 7-12: Modified to show 8 clock cycle wait time.
Modified timing description to match new Figure 7-12.
“IDELAY VHDL and Verilog Instantiation Template”: Changed port map for C, CE,
INC, and RST from open to zero (both Verilog and VHDL).
Deleted synthesis translate_off/synthesis translate_on statements
from all IDELAY instantiation templates.
Date Version Revision
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01/04/07
(cont’d)
2.0
(cont’d)
Chapter 8, “Advanced SelectIO Logic Resources”:
Table 8-1: REV: Added instruction to connect to GND.
Table 8-2: Corrected BITSLIP_ENABLE value from “String” to “Boolean”.
“Registered Outputs – Q1 to Q6”: Added clarification on bit in/out sequence.
“High-Speed Clock for Strobe-Based Memory Interfaces – OCLK”: Added instruction
to ground OCLK when INTERFACE_TYPE is NETWORKING.
“BITSLIP_ENABLE Attribute”: Specified setting according to setting of
INTERFACE_TYPE.
“INTERFACE_TYPE Attribute”: Added recommendation to use MIG when ISERDES
is in Memory Mode. Added Figure 8-6 to illustrate ISERDES internal connections in
Memory Mode.
Added section “ISERDES Clocking Methods.”
“ISERDES Width Expansion”: Added explanatory paragraph regarding master/slave
ISERDES use with differential/single-ended inputs.
“Guidelines for Expanding the Serial-to-Parallel Converter Bit Width”: Corrected a
number of master/slave and input/output reversals.
“Verilog Instantiation Template to use Width Expansion Feature”: Corrected a number
of errors in the template.
“ISERDES Latencies”: Deleted former Table 8-4 and most of the text in this section and
replaced with statement relating latency to INTERFACE_TYPE.
Deleted synthesis translate_off/synthesis translate_on statements
from all ISERDES instantiation templates.
“Data Parallel-to-Serial Converter”: Added recommendation to apply a reset to
OSERDES prior to use.
“OSERDES Width Expansion”: Added explanatory paragraph regarding master/slave
OSERDES use with differential/single-ended outputs.
“OSERDES VHDL Template” in Chapter 8: Removed erroneous semicolon following
TRISTATE_WIDTH.
03/15/07 2.1 “ILOGIC Resources”: Added sentence clarifying SR and REV sharing between
ILOGIC/ISERDES and OLOGIC/OSERDES.
Figure 7-1: Removed OFB/TFB inputs and associated MUXes.
Figure 8-2: Removed OFB/TFB inputs.
“DIFF_SSTL2_II_DCI, DIFF_SSTL18_II_DCI Usage”: Removed incorrect bidirectional
link requirements and reference to on-chip differential termination.
DCI in Virtex-4 FPGA Hardware: Modified point 3 detailing when VRP/VRN reference
resistors are not required.
“PULLUP/PULLDOWN/KEEPER for IBUF, OBUFT, and IOBUF”: Added a paragraph
recommending against using these circuits to drive a logic level on a board-level trace.
“Frequency Synthesizer Characteristics”: Updated information regarding the setting of
AUTOCALIBRATE and CONFIG STEPPING.
Added new section “FIFO16 Error Condition and Work-Arounds” in Chapter 4,
including VHDL/Verilog source files in UG070.zip.
Table 6-41: Added SSO data for FF676 device/package combinations.
Date Version Revision
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Virtex-4 FPGA User Guide www.xilinx.com UG070 (v2.6) December 1, 2008
04/10/07 2.2 Added section “Cascading DCMs” in Chapter 2.
Table 7-9: Deleted Note (1).
Figure 7-12: Added assumption that IOBDELAY_VALUE = 0 to text.
Section “IDELAY Timing”: Revised descriptions of Clock Events 1, 2, and 3 in Figure 7-12.
Added new section “Note on Instability after an Increment/Decrement Operation”.
Table 7-12: Revised description of CE port.
Chapter 8, “Advanced SelectIO Logic Resources”: ISERDES and OSERDES sections
extensively revised and expanded with many new figures and tables.
08/10/07 2.3 Figure 2-5 and associated text: Updated.
Figure 2-20: Corrected reset requirement from 3 periods to 200 ns.
Figure 2-22, associated text: Corrected number of clock cycles in Clock Event 4.
“Frequency Synthesizer Characteristics” in Chapter 2: Added note to indicate no need for
the LOCKED monitoring macro on recent step devices.
“SelectIO Resources Introduction” in Chapter 6: Added note that differential and
VREF-dependent inputs are powered by VCCAUX.
“DCI in Virtex-4 FPGA Hardware” in Chapter 6: Removed erroneous reference to SSTL3
standard.
“Lower Capacitance I/O Attributes” in Chapter 6: Added RSDS_25 to list of standards
that do not have differential driver circuits.
Added Note (1) to Table 6-40.
Table 6-43: Included FX family devices and added note (3) for Banks 9 and 10.
“Temperature Sensor Examples” in Chapter 9: Added information on Texas Instruments
temperature sensor.
04/10/08 2.4 Table 2-6, page 65: Added CLK_FEEDBACK and DCM_AUTOCALIBRATION attribute
rows. Added descriptions to CLKFX_DIVIDE and CLKFX_MULTIPLY rows.
“DCM_AUTOCALIBRATION Attribute,” page 68: New section.
Figure 2-9, page 84 and Figure 2-11, page 85: Removed element from Q output.
Under Figure 3-5, page 104: Clarified bullet regarding RST must be Low before REL has
an effect.
Figure 4-11, page 142: Removed REGCEN.
Table 6-40, page 308: Added LVCMOS15_16_fast, LVDCI_DV2_18, and LVTTL24_fast.
“REFCLK - Reference Clock,” page 342: Changed IDELAYCTRL_REF_PRECISION units
to MHz.
Figure 7-21, page 355: Corrected OFFDDRB labeling.
06/17/08 2.5 Figure 2-4, page 73: Revised the contents of the DCM block.
“System-Synchronous Setting (Default),” page 73: Added text to the end of the section
describing cases when the DESKEW_ADJUST parameter has no effect.
12/01/08 2.6 “Asynchronous Clocking,” page 119: Added the results of performing a read and write
operation.
Figure 6-6, page 238: Moved VREF to be inside the FPGA.
“DCI in Virtex-4 FPGA Hardware,” page 241: Added SSTL18_I_DCI to the list of DCI
outputs that do not require reference resistors on VRP/VRN.
Figure 7-10, page 330: Updated figure title.
Date Version Revision
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UG070 (v2.6) December 1, 2008
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Chapter 1: Clock Resources
Global and Regional Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Global Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Regional Clocks and I/O Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Global Clocking Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Global Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Global Clock Input Buffer Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power Savings by Disabling Global Clock Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Global Clock Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Global Clock Buffer Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Additional Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Clock Tree and Nets - GCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Clock Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Regional Clocking Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Clock Capable I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
I/O Clock Buffer - BUFIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
BUFIO Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
BUFIO Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Regional Clock Buffer - BUFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
BUFR Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
BUFR Attributes and Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
BUFR Use Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Regional Clock Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
BUFGCTRL VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
VHDL Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Verilog Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Declaring Constraints in UCF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
BUFG VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
VHDL Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Verilog Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Declaring Constraints in UCF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
BUFGCE and BUFGCE_1 VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . 48
VHDL Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Verilog Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table of Contents
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Declaring Constraints in UCF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
BUFGMUX and BUFGMUX_1 VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . 49
VHDL Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Verilog Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Declaring Constraints in UCF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
BUFGMUX_VIRTEX4 VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . 50
VHDL Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Verilog Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Declaring Constraints in UCF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
BUFIO VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
VHDL Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Verilog Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Declaring Constraints in UCF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
BUFR VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
VHDL Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Verilog Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Declaring Constraints in UCF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Chapter 2: Digital Clock Managers (DCMs)
DCM Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
DCM Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DCM_BASE Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DCM_PS Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DCM_ADV Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DCM Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Clock Input Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Source Clock Input — CLKIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Feedback Clock Input — CLKFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Phase-Shift Clock Input — PSCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Dynamic Reconfiguration Clock Input — DCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Control and Data Input Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Reset Input — RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Phase-Shift Increment/Decrement Input — PSINCDEC . . . . . . . . . . . . . . . . . . . . . . . . 61
Phase-Shift Enable Input — PSEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Dynamic Reconfiguration Data Input — DI[15:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Dynamic Reconfiguration Address Input — DADDR[6:0] . . . . . . . . . . . . . . . . . . . . . . . 61
Dynamic Reconfiguration Write Enable Input — DWE . . . . . . . . . . . . . . . . . . . . . . . . . 62
Dynamic Reconfiguration Enable Input — DEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Clock Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
1x Output Clock — CLK0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
1x Output Clock, 90° Phase Shift — CLK90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
1x Output Clock, 180° Phase Shift — CLK180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
1x Output Clock, 270° Phase Shift — CLK270 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2x Output Clock — CLK2X. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2x Output Clock, 180° Phase Shift — CLK2X180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Frequency Divide Output Clock — CLKDV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Frequency-Synthesis Output Clock — CLKFX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Frequency-Synthesis Output Clock, 180° — CLKFX180 . . . . . . . . . . . . . . . . . . . . . . . . . 63
Status and Data Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Locked Output — LOCKED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Phase-Shift Done Output — PSDONE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Status or Dynamic Reconfiguration Data Output — DO[15:0] . . . . . . . . . . . . . . . . . . . . 64
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Dynamic Reconfiguration Ready Output — DRDY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
DCM Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
CLK_FEEDBACK Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
CLKDV_DIVIDE Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
CLKFX_MULTIPLY and CLKFX_DIVIDE Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . 67
CLKIN_DIVIDE_BY_2 Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
CLKIN_PERIOD Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
CLKOUT_PHASE_SHIFT Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
DCM_AUTOCALIBRATION Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
DCM_PERFORMANCE_MODE Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
DESKEW_ADJUST Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
DFS_FREQUENCY_MODE Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
DLL_FREQUENCY_MODE Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
DUTY_CYCLE_CORRECTION Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
FACTORY_JF Attribute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PHASE_SHIFT Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
STARTUP_WAIT Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DCM Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Clock Deskew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Clock Deskew Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Input Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Input Clock Changes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Output Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DCM During Configuration and Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Deskew Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Characteristics of the Deskew Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Cascading DCMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Frequency Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Frequency Synthesis Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Frequency Synthesizer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Phase Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Phase-Shifting Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Interaction of PSEN, PSINCDEC, PSCLK, and PSDONE . . . . . . . . . . . . . . . . . . . . . . . . 79
Phase-Shift Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Phase-Shift Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Dynamic Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Connecting DCMs to Other Clock Resources in Virtex-4 Devices. . . . . . . . . . . . . 82
IBUFG to DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
DCM to BUFGCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
BUFGCTRL to DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
DCM to and from PMCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Standard Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Board-Level Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Board Deskew with Internal Deskew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Clock Switching Between Two DCMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
VHDL and Verilog Templates, and the Clocking Wizard. . . . . . . . . . . . . . . . . . . . . 89
DCM Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Reset/Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Fixed-Phase Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Variable-Phase Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
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Legacy Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Chapter 3: Phase-Matched Clock Dividers (PMCDs)
PMCD Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
PMCD Primitives, Ports, and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
PMCD Usage and Design Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Phase-Matched Divided Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Matched Clock Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Reset (RST) and Release (REL) Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Connecting PMCD to other Clock Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
IBUFG to PMCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
DCM to PMCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
BUFGCTRL to PMCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
PMCD to BUFGCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
PMCD to PMCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
DCM and a Single PMCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
DCM and Parallel PMCDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
IBUFG, BUFG, and PMCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
PMCD for Further Division of Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
VHDL and Verilog Templates, and the Clocking Wizard. . . . . . . . . . . . . . . . . . . . 109
VHDL Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Verilog Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Chapter 4: Block RAM
Block RAM Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Block RAM Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Synchronous Dual-Port and Single-Port RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
WRITE_FIRST or Transparent Mode (Default). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
READ_FIRST or READ-BEFORE-WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
NO_CHANGE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Conflict Avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Asynchronous Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Synchronous Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Additional Block RAM Features in Virtex-4 Devices . . . . . . . . . . . . . . . . . . . . . . . . 120
Optional Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Independent Read and Write Port Width Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Cascadable Block RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
FIFO Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Byte-Wide Write Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Block RAM Library Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Block RAM Port Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Clock - CLK[A|B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Enable - EN[A|B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Write Enable - WE[A|B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Register Enable - REGCE[A|B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
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Set/Reset - SSR[A|B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Address Bus - ADDR[A|B]<14:#> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Data-In Buses - DI[A|B]<#:0> & DIP[A|B]<#:0> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Data-Out Buses - DO[A|B]<#:0> and DOP[A|B]<#:0> . . . . . . . . . . . . . . . . . . . . . . . . 126
Cascade - CASCADEIN[A|B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Cascade - CASCADEOUT[A|B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Inverting Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
GSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Block RAM Address Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Block RAM Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Content Initialization - INIT_xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Content Initialization - INITP_xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Output Latches Initialization - INIT (INIT_A & INIT_B) . . . . . . . . . . . . . . . . . . . . . . 128
Output Latches Synchronous Set/Reset - SRVAL (SRVAL_A & SRVAL_B) . . . . . . 128
Optional Output Register On/Off Switch - DO[A|B]_REG . . . . . . . . . . . . . . . . . . . . 129
Clock Inversion at Output Register Switch - INVERT_CLK_DO[A|B]_REG . . . . . 129
Extended Mode Address Determinant - RAM_EXTENSION_[A|B] . . . . . . . . . . . . 129
Read Width - READ_WIDTH_[A|B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Write Width - WRITE_WIDTH_[A|B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Write Mode - WRITE_MODE_[A|B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Block RAM Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Block RAM Initialization in VHDL or Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . 130
Block RAM VHDL and Verilog Templates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
RAMB16 VHDL Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
RAMB16 Verilog Template. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Additional RAMB16 Primitive Design Considerations . . . . . . . . . . . . . . . . . . . . . . 139
Data Parity Buses - DIP[A/B] and DOP[A/B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Optional Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Independent Read and Write Port Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
RAMB16 Port Mapping Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Cascadable Block RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Byte-Write Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Additional Block RAM Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Instantiation of Additional Block RAM Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Block RAM Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Creating Larger RAM Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Block RAM Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Block RAM Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Block RAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Clock Event 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Clock Event 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Clock Event 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Clock Event 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Block RAM Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Built-in FIFO Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
EMPTY Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Top-Level View of FIFO Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
FIFO Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
FIFO Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
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FIFO Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Standard Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
First Word Fall Through (FWFT) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Empty Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
ALMOSTEMPTY Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Read Error Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Full Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Write Error Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
ALMOSTFULL Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
FIFO Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
FIFO ALMOSTEMPTY / ALMOSTFULL Flag Offset Range . . . . . . . . . . . . . . . . . . . 153
FIFO VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
FIFO VHDL Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
FIFO Verilog Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
FIFO Timing Models and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
FIFO Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Case 1: Writing to an Empty FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Case 2: Writing to a Full or Almost Full FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Case 3: Reading From a Full FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Case 4: Reading From an Empty or Almost Empty FIFO . . . . . . . . . . . . . . . . . . . . . . . 162
Case 5: Resetting All Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
FIFO Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Cascading FIFOs to Increase Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Cascading FIFOs to Increase Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
FIFO16 Error Condition and Work-Arounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
FIFO16 Error Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Solution 1: Synchronous/Asynchronous Clock Work-Arounds . . . . . . . . . . . . . . . . 165
Synchronous Clock Work-Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Asynchronous Clock Work-Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
WRCLK Faster than RDCLK Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
RDCLK Faster than WRCLK Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
User-Programmable Flag Settings in the Composite FIFO . . . . . . . . . . . . . . . . . . . . . . 167
Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Performance Expressed in Maximum Read and/or Write Clock Frequency . . . . . . . . 168
CORE Generator Tool Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Software Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Software IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Solution 2: Work-Around Using a Third Fast Clock . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Notes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Design Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Solution 3: FIFO Flag Generator Using Gray Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Notes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
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Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Design Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Solution Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Built-in Block RAM Error Correction Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Top-Level View of the Block RAM ECC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 178
Block RAM ECC Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Block RAM ECC Port Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Error Status Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Block RAM ECC Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Block RAM ECC VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Block RAM ECC VHDL Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Block RAM ECC Verilog Template. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Chapter 5: Configurable Logic Blocks (CLBs)
CLB Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Slice Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
CLB/Slice Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Look-Up Table (LUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Storage Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Distributed RAM and Memory (Available in SLICEM only) . . . . . . . . . . . . . . . . . . . . 188
Read Only Memory (ROM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Shift Registers (Available in SLICEM only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Shift Register Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Designing Large Multiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Fast Lookahead Carry Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Arithmetic Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
CLB / Slice Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
General Slice Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Slice Distributed RAM Timing Model and Parameters
(Available in SLICEM only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Distributed RAM Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Distributed RAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Slice SRL Timing Model and Parameters (Available in SLICEM only) . . . . . . . . . . . 211
Slice SRL Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Slice SRL Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Slice Carry-Chain Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Slice Carry-Chain Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Slice Carry-Chain Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
CLB Primitives and Verilog/VHDL Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Distributed RAM Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
VHDL and Verilog Instantiations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Clock - WCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Enable - WE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Address - A0, A1, A2, A3 (A4, A5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Data In - D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Data Out - O, SPO, and DPO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Inverting Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Global Set/Reset - GSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
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Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Content Initialization - INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Initialization in VHDL or Verilog Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Creating Larger RAM Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Shift Registers (SRLs) Primitives and Verilog/VHDL Example . . . . . . . . . . . . . . 221
SRL Primitives and Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Initialization in VHDL or Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Clock - CLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Data In - D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Clock Enable - CE (optional). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Address - A0, A1, A2, A3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Data Out - Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Data Out - Q15 (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Inverting Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Global Set/Reset - GSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Content Initialization - INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Fully Synchronous Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Static-Length Shift Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Multiplexer Primitives and Verilog/VHDL Examples . . . . . . . . . . . . . . . . . . . . . . . 227
Multiplexer Primitives and Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Data In - DATA_I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Control In - SELECT_I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Data Out - DATA_O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Multiplexer Verilog/VHDL Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
VHDL and Verilog Instantiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
VHDL and Verilog Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Chapter 6: SelectIO Resources
I/O Tile Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
SelectIO Resources Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
SelectIO Technology Resources General Guidelines . . . . . . . . . . . . . . . . . . . . . . . . 234
Virtex-4 FPGA I/O Bank Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
3.3V I/O Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Reference Voltage (VREF) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Output Drive Source Voltage (VCCO) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Virtex-4 FPGA Digitally Controlled Impedance (DCI) . . . . . . . . . . . . . . . . . . . . . . . . 236
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Xilinx DCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Controlled Impedance Driver (Source Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Controlled Impedance Driver with Half Impedance (Source Termination) . . . . . . . . . 237
Input Termination to VCCO (Single Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Input Termination to VCCO/2 (Split Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Driver with Termination to VCCO (Single Termination) . . . . . . . . . . . . . . . . . . . . . . . . 240
Driver with Termination to VCCO/2 (Split Termination) . . . . . . . . . . . . . . . . . . . . . . . 241
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DCI in Virtex-4 FPGA Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
DCI Usage Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Virtex-4 FPGA SelectIO Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
IBUF and IBUFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
OBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
OBUFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
IOBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
IBUFDS and IBUFGDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
OBUFDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
OBUFTDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
IOBUFDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Virtex-4 FPGA SelectIO Attributes/Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
IOStandard Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Output Slew Rate Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Output Drive Strength Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Lower Capacitance I/O Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
PULLUP/PULLDOWN/KEEPER for IBUF, OBUFT, and IOBUF . . . . . . . . . . . . . . . . 251
Differential Termination Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Virtex-4 FPGA I/O Resource VHDL/Verilog Examples . . . . . . . . . . . . . . . . . . . . . . . 251
VHDL Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Verilog Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Specific Guidelines for Virtex-4 FPGA I/O Supported Standards. . . . . . . . . . . . 253
LVTTL (Low Voltage Transistor-Transistor Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
LVCMOS (Low Voltage Complementary Metal Oxide Semiconductor). . . . . . . . . . 255
LVDCI (Low Voltage Digitally Controlled Impedance) . . . . . . . . . . . . . . . . . . . . . . . . 257
LVDCI_DV2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
HSLVDCI (High-Speed Low Voltage Digitally Controlled Impedance). . . . . . . . . . . . 259
PCIX, PCI33, PCI66 (Peripheral Component Interface) . . . . . . . . . . . . . . . . . . . . . . . . 260
GTL (Gunning Transceiver Logic). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
GTL_DCI Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
GTLP (Gunning Transceiver Logic Plus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
GTLP_DCI Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
HSTL (High-Speed Transceiver Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
HSTL_ I, HSTL_ III, HSTL_ I_18, HSTL_ III_18 Usage . . . . . . . . . . . . . . . . . . . . . . . . . 263
HSTL_ I_DCI, HSTL_ III_DCI, HSTL_ I_DCI_18, HSTL_ III_DCI_18 Usage . . . . . . . . 263
HSTL_ II, HSTL_ IV, HSTL_ II_18, HSTL_ IV_18 Usage. . . . . . . . . . . . . . . . . . . . . . . . 264
HSTL_ II_DCI, HSTL_ IV_DCI, HSTL_ II_DCI_18, HSTL_ IV_DCI_18 Usage . . . . . . . 264
DIFF_HSTL_ II, DIFF_HSTL_II_18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
DIFF_HSTL_II_DCI, DIFF_HSTL_II_DCI_18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
HSTL Class I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
HSTL Class II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Complementary Single-Ended (CSE) Differential HSTL Class II . . . . . . . . . . . . . . . . 268
HSTL Class III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
HSTL Class IV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
HSTL Class I (1.8V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
HSTL Class II (1.8V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Complementary Single-Ended (CSE) Differential HSTL Class II (1.8V) . . . . . . . . . . 276
HSTL Class III (1.8V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
HSTL Class IV (1.8V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
SSTL (Stub-Series Terminated Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
SSTL2_I, SSTL18_I Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
SSTL2_I_DCI, SSTL18_I_DCI Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
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SSTL2_II, SSTL18_II Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
SSTL2_II_DCI, SSTL18_II_DCI Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
DIFF_SSTL2_II, DIFF_SSTL18_II Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
DIFF_SSTL2_II_DCI, DIFF_SSTL18_II_DCI Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
SSTL2 Class I (2.5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
SSTL2 Class II (2.5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Complementary Single-Ended (CSE) Differential SSTL2 Class II (2.5V) . . . . . . . . . . 285
SSTL18 Class I (1.8V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
SSTL18 Class II (1.8V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Complementary Single-Ended (CSE) Differential SSTL Class II (1.8V) . . . . . . . . . . . 291
Differential Termination: DIFF_TERM Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
LVDS and Extended LVDS (Low Voltage Differential Signaling) . . . . . . . . . . . . . . . 294
Transmitter Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Receiver Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
HyperTransport Protocol (LDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
BLVDS (Bus LVDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
CSE Differential LVPECL (Low-Voltage Positive Emitter-Coupled Logic) . . . . . . . 297
LVPECL Transceiver Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
I/O Standards Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
I/O Standards Special Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Rules for Combining I/O Standards in the Same Bank . . . . . . . . . . . . . . . . . . . . . . . . 302
3.3V I/O Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
I/O Standard Design Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Mixing Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Simultaneous Switching Output Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Sparse-Chevron Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Nominal PCB Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
PCB Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Signal Return Current Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Load Traces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Power Distribution System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Nominal SSO Limit Table: Sparse Chevron . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Equivalent VCCO/GND Pairs: Sparse Chevron . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Nominal SSO Limit Tables: Non-Sparse Chevron . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Equivalent VCCO/GND Pairs: Non-Sparse Chevron . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Actual SSO Limits versus Nominal SSO Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Electrical Basis of SSO Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Parasitic Factors Derating Method (PFDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Weighted Average Calculation of SSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Calculation of Full Device SSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Full Device SSO Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Full Device SSO Calculator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Other SSO Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
LVDCI and HSLVDCI Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Bank 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Chapter 7: SelectIO Logic Resources
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
ILOGIC Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Combinatorial Input Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Input DDR Overview (IDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
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OPPOSITE_EDGE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
SAME_EDGE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
SAME_EDGE_PIPELINED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Input DDR Primitive (IDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
IDDR VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
IDDR VHDL Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
IDDR Verilog Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
ILOGIC Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
ILOGIC Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
ILOGIC Timing Characteristics, DDR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Input Delay Element (IDELAY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
IDELAY Primitive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
IDELAY Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
IDELAY Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
IDELAY Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Note on Instability after an Increment/Decrement Operation . . . . . . . . . . . . . . . . . . . 335
IDELAY VHDL and Verilog Instantiation Template . . . . . . . . . . . . . . . . . . . . . . . . . . 336
IDELAYCTRL Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
IDELAYCTRL Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
IDELAYCTRL Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
IDELAYCTRL Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
IDELAYCTRL Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
IDELAYCTRL Usage and Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
OLOGIC Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Combinatorial Output Data and 3-State Control Path . . . . . . . . . . . . . . . . . . . . . . . . . 354
Output DDR Overview (ODDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
OPPOSITE_EDGE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
SAME_EDGE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Clock Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Output DDR Primitive (ODDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
ODDR VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
ODDR VHDL Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
ODDR Verilog Template. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
OLOGIC Timing Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Chapter 8: Advanced SelectIO Logic Resources
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Input Serial-to-Parallel Logic Resources (ISERDES). . . . . . . . . . . . . . . . . . . . . . . . . 365
ISERDES Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
ISERDES Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Combinatorial Output – O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Registered Outputs – Q1 to Q6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Bitslip Operation – BITSLIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Clock Enable Inputs – CE1 and CE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
High-Speed Clock Input – CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Divided Clock Input – CLKDIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Serial Input Data from IOB – D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
High-Speed Clock for Strobe-Based Memory Interfaces – OCLK . . . . . . . . . . . . . . . . . 370
Reset Input – SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
ISERDES Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
BITSLIP_ENABLE Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
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DATA_RATE Attribute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
DATA_WIDTH Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
INTERFACE_TYPE Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
IOBDELAY Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
NUM_CE Attribute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
SERDES_MODE Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
ISERDES Clocking Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
ISERDES Width Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Guidelines for Expanding the Serial-to-Parallel Converter Bit Width . . . . . . . . . . . . . 376
Verilog Instantiation Template to use Width Expansion Feature . . . . . . . . . . . . . . . . . 376
ISERDES Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
ISERDES Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
ISERDES VHDL and Verilog Instantiation Template. . . . . . . . . . . . . . . . . . . . . . . . . . 380
ISERDES VHDL Instantiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
ISERDES Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
BITSLIP Submodule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Bitslip Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Bitslip Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Output Parallel-to-Serial Logic Resources (OSERDES) . . . . . . . . . . . . . . . . . . . . . . 386
Data Parallel-to-Serial Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
3-State Parallel-to-Serial Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
OSERDES Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
OSERDES Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
Data Path Output – OQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
3-state Control Output – TQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
High-Speed Clock Input – CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Divided Clock Input – CLKDIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Parallel Data Inputs – D1 to D6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Output Data Clock Enable – OCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Parallel 3-State Inputs – T1 to T4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
3-State Signal Clock Enable – TCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Reset Input – SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
OSERDES Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
DATA_RATE_OQ Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
DATA_RATE_TQ Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
DATA_WIDTH Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
SERDES_MODE Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
TRISTATE_WIDTH Attribute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
OSERDES Width Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Guidelines for Expanding the Parallel-to-Serial Converter Bit Width . . . . . . . . . . . . . 393
OSERDES Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
OSERDES Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Timing Characteristics of 2:1 SDR Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Timing Characteristics of 8:1 DDR Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Timing Characteristics of 4:1 DDR 3-State Controller Serialization . . . . . . . . . . . . . . . 396
OSERDES VHDL and Verilog Instantiation Templates . . . . . . . . . . . . . . . . . . . . . . . . 398
OSERDES VHDL Template. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
OSERDES Verilog Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Chapter 9: Temperature Sensing Diode
Temperature-Sensing Diode (TDP/TDN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Temperature Sensor Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
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Maxim Remote/Local Temperature Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Texas Instruments Remote/Local Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . 402
National Semiconductor (LM83 or LM86) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
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Preface
About This Guide
This document describes the Virtex®-4 FPGA architecture. Complete and up-to-date
documentation of the Virtex-4 family of FPGAs is available on the Xilinx® website at
http://www.xilinx.com/virtex4.
Guide Contents
Chapter 1, “Clock Resources”
Chapter 2, “Digital Clock Managers (DCMs)”
Chapter 3, “Phase-Matched Clock Dividers (PMCDs)”
Chapter 4, “Block RAM”
Chapter 5, “Configurable Logic Blocks (CLBs)”
Chapter 6, “SelectIO Resources”
Chapter 7, “SelectIO Logic Resources”
Chapter 8, “Advanced SelectIO Logic Resources”
Chapter 9, “Temperature Sensing Diode”
Additional Documentation
The following documents are also available for download at
http://www.xilinx.com/virtex4.
DS112, Virtex-4 Family Overview
The features and product selection of the Virtex-4 family are outlined in this overview.
DS302, Virtex-4 Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-4 family.
UG073, XtremeDSP for Virtex-4 FPGAs User Guide
This guide describes the XtremeDSP™ slice and includes reference designs for using
DSP48 math functions and various FIR filters.
UG071, Virtex-4 Configuration Guide
This all-encompassing configuration guide includes chapters on configuration
interfaces (serial and SelectMAP), bitstream encryption, Boundary-Scan and JTAG
configuration, reconfiguration techniques, and readback through the SelectMAP and
JTAG interfaces.
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UG072, Virtex-4 PCB Designers Guide
This guide describes PCB guidelines for the Virtex-4 family. It covers SelectIO™
signaling, RocketIO™ signaling, power distribution systems, PCB breakout, and parts
placement.
UG075, Virtex-4 Packaging and Pinout Specification
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
UG076, Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide
This guide describes the RocketIO Multi-Gigabit Transceivers available in the
Virtex-4 FX family.
UG074, Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC User Guide
This guide describes the Tri-mode Ethernet Media Access Controller available in the
Virtex-4 FX family.
UG018, PowerPC 405 Processor Block Reference Guide
This guide describes the IBM PowerPC® 405 processor block available in the
Virtex-4 FX family.
Additional Support Resources
To search the database of silicon and software questions and answers, or to create a
technical support case in WebCase, see the Xilinx website at:
http://www.xilinx.com/support.
Conventions
This document uses the following conventions. An example illustrates each convention.
Typographical
The following typographical conventions are used in this document:
Convention Meaning or Use Example
Courier font
Messages, prompts, and
program files that the system
displays
speed grade: - 100
Courier bold Literal commands that you enter
in a syntactical statement ngdbuild design_name
Helvetica bold
Commands that you select from
a menu File Open
Keyboard shortcuts Ctrl+C
§IXILINXm Blue, underlined text httE:/ / WWw.xilm><.com www.xilinx.com="">
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Conventions
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Online Document
The following conventions are used in this document:
Italic font
Variables in a syntax statement
for which you must supply
values
ngdbuild design_name
References to other manuals
See the Development System
Reference Guide for more
information.
Emphasis in text
If a wire is drawn so that it
overlaps the pin of a symbol, the
two nets are not connected.
Square brackets [ ]
An optional entry or parameter.
However, in bus specifications,
such as bus[7:0], they are
required.
ngdbuild [option_name]
design_name
Braces { } A list of items from which you
must choose one or more lowpwr ={on|off}
Vertical bar | Separates items in a list of
choices lowpwr ={on|off}
Vertical ellipsis
.
.
.
Repetitive material that has
been omitted
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.
Horizontal ellipsis . . . Repetitive material that has
been omitted
allow block block_name loc1
loc2 ... locn;
Convention Meaning or Use Example
Convention Meaning or Use Example
Blue text Cross-reference link to a location
in the current document
See the section “Additional
Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
Red text Cross-reference link to a location
in another document
See Figure 5 in the Virtex-II
Platform FPGA User Guide.
Blue, underlined text Hyperlink to a website (URL) Go to http://www.xilinx.com
for the latest speed files.
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Chapter 1
Clock Resources
Global and Regional Clocks
For clocking purposes, each Virtex®-4 device is divided into regions. The number of
regions varies with device size, eight regions in the smallest device to 24 regions in the
largest one.
Global Clocks
Each Virtex-4 device has 32 matched-skew global clock lines that can clock all sequential
resources on the whole device (CLB, block RAM, DCMs, and I/O), and also drive logic
signals. Any eight of these 32 global clock lines can be used in any region. Global clock
lines are only driven by a global clock buffer, and can also be used as a clock enable circuit
or a glitch-free multiplexer. It can select between two clock sources, and can also switch
away from a failed clock source, a new feature in the Virtex-4 architecture.
A global clock buffer is often driven by a Digital Clock Manager (DCM) to eliminate the
clock distribution delay, or to adjust its delay relative to another clock. There are more
global clocks than DCMs, but a DCM often drives more than one global clock.
Regional Clocks and I/O Clocks
Each region has two “clock capable” regional clock inputs. Each input can differentially or
single-endedly drive regional clocks and I/O clocks in the same region, and also in the
region above or below (i.e., in up to three adjacent regions).
The regional clock buffer can be programmed to divide the incoming clock rate by any
integer number from 1 to 8. This feature, in conjunction with the programmable
serializer/deserializer in the IOB (see Chapter 8, “Advanced SelectIO Logic Resources”)
allows source-synchronous systems to cross clock domains without using additional logic
resources.
A third type of clocking resource, I/O clocks, are very fast and serve localized I/O
serializer/deserializer circuits (see Chapter 8, “Advanced SelectIO Logic Resources”).
For more detail on how to identify clock regions and the associated components, please use
the PACE tool.
Global Clocking Resources
Global clocks are a dedicated network of interconnect specifically designed to reach all
clock inputs to the various resources in an FPGA. These networks are designed to have low
skew and low duty cycle distortion, low power, and increased jitter tolerance. They are
also designed to support very high frequency signals.
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Understanding the signal path for a global clock expands the understanding of the various
global clock resources. The global clocking resources and network consist of the following
paths and components:
Global Clock Inputs
Global Clock Buffers
Clock Tree and Nets - GCLK
Clock Regions
Global Clock Inputs
Virtex-4 FPGAs contain specialized global clock input locations for use as regular user
I/Os if not used as clock inputs. The number of clock inputs varies with the device size.
Smaller devices contain 16 clock inputs, while larger devices have 32 clock inputs.
Table 1-1 summarizes the number of clock inputs available for different Virtex-4 devices.
Clock inputs can be configured for any I/O standard, including differential I/O standards.
Each clock input can be either single-ended or differential. All 16 or 32 clock inputs can be
differential if desired. When used as outputs, global clock input pins can be configured for
any output standard except LVDS and HT output differential standards. Each global clock
input pin supports any single-ended output standard or any CSE output differential
standard.
Global Clock Input Buffer Primitives
The primitives in Table 1-2 are different configurations of the input clock I/O input buffer.
These two primitives work in conjunction with the Virtex-4 FPGA I/O resource by setting
the IOSTANDARD attribute to the desired standard. Refer to Chapter 6, “I/O
Compatibility” Table 6-38 for a complete list of possible I/O standards.
Table 1-1: Number of Clock I/O Inputs by Device
Device Number of Clock I/O Inputs
XC4VLX15, XC4VLX25
XC4VSX25, XC4VSX35
XC4VFX12, XC4VFX20, XC4VFX40, XC4VFX60
16
XC4VLX40(1), XC4VLX60(1), XC4VLX80, XC4VLX100,
XC4VLX160, XC4VLX200
XC4VSX55
XC4VFX100(2), XC4VFX140
32
Notes:
1. The XC4VLX40 and XC4VLX60 in the FF668 package only have 16 clock input pins.
2. The XC4VFX100 in the FF1152 package only has 16 clock input pins.
Table 1-2: Clock Buffer Primitives
Primitive Input Output Description
IBUFG I O Input clock buffer for single-ended I/O
IBUFGDS I, IB O Input clock buffer for differential I/O
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Power Savings by Disabling Global Clock Buffer
The Virtex-4 FPGA clock architecture provides a straightforward means of implementing
clock gating for the purposes of powering down portions of a design.
Most designs contain several unused BUFGMUX resources. A clock can drive multiple
BUFGMUX inputs, and the BUFGMUX outputs, which will be synchronous with each
other, can be used to drive distinct regions of logic. For example, if all the logic required to
be always operating can be constrained to a few clocking regions, then one of the
BUFGMUX outputs can be used to drive those regions. Toggling the enable of the other
BUFGMUX then provides a simple means of stopping all dynamic power consumption in
those regions of logic available for power savings.
The XPower tool can be used to estimate the power savings from such an approach. The
difference can be calculated either by toggling the BUFGMUX enable or by setting the
frequency on the corresponding clock net to 0 MHz.
Global Clock Buffers
There are 32 global clock buffers in every Virtex-4 device. Each half of the die (top/bottom)
contains 16 global clock buffers. A global clock input can directly connect from the P-side
of the differential input pin pair to any global clock buffer input in the same half, either top
or bottom, of the device. Each differential global clock pin pair can connect to either a
differential or single-ended clock on the PCB. If using a single-ended clock, then the P-side
of the pin pair must be used because a direct connection only exists on this pin. For pin
naming conventions, refer to the Virtex-4 Packaging and Pinout Specification. A single-ended
clock connected to the N-side of the differential pair results in a local route and creates
additional delay. If a single-ended clock is connected to a differential pin pair then the
other side (N-side typically) can not be used as another single-ended clock pin. However,
it can be used as a user I/O. A device with 16 global clock pins can be connected to 16
differential or 16 single-ended board clocks. A device with 32 global clock pins can be
connected to 32 clocks under these same conditions.
Global clock buffers allow various clock/signal sources to access the global clock trees and
nets. The possible sources for input to the global clock buffers include:
Global clock inputs
Digital Clock Manager (DCM) outputs
Phase-Matched Clock Divider (PMCD) outputs
Rocket IO Multi-Gigabit Transceivers
Other global clock buffer outputs
General interconnect
The global clock buffers can only be driven by sources in the same half of the die
(top/bottom).
All global clock buffers can drive all clock regions in Virtex-4 devices. The
primary/secondary rules from Virtex-II and Virtex-II Pro FPGAs do not apply. However,
only eight different clocks can be driven in a single clock region. A clock region (16 CLBs)
is a branch of the clock tree consisting of eight CLB rows up and eight CLB rows down. A
clock region only spans halfway across the device.
The clock buffers are designed to be configured as a synchronous or asynchronous “glitch
free” 2:1 multiplexer with two clock inputs. Virtex-4 devices have more control pins to
provide a wider range of functionality and more robust input switching. The following
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subsections detail the various configurations, primitives, and use models of the Virtex-4
FPGA clock buffers.
Global Clock Buffer Primitives
The primitives in Table 1-3 are different configurations of the global clock buffers.
BUFGCTRL
The BUFGCTRL primitive shown in Figure 1-1, can switch between two asynchronous
clocks. All other global clock buffer primitives are derived from certain configurations of
BUFGCTRL. The ISE® software tools manage the configuration of all these primitives.
BUFGCTRL has four select lines, S0, S1, CE0, and CE1. It also has two additional control
lines, IGNORE0 and IGNORE1. These six control lines are used to control the input I0 and
I1.
BUFGCTRL is designed to switch between two clock inputs without the possibility of a
glitch. When the presently selected clock transitions from High to Low after S0 and S1
Table 1-3: Global Clock Buffer Primitives
Primitive Input Output Control
BUFGCTRL I0, I1 O CE0, CE1, IGNORE0, IGNORE1, S0, S1
BUFG I O –
BUFGCE I O CE
BUFGCE_1 I O CE
BUFGMUX I0, I1 O S
BUFGMUX_1 I0, I1 O S
BUFGMUX_VIRTEX4 I0, I1 O S
Notes:
1. All primitives are derived from a software preset of BUFGCTRL.
Figure 1-1: BUFGCTRL Primitive
IGNORE1
IGNORE0
CE1
CE0
S1
S0
I1
I0
O
BUFGCTRL
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change, the output is kept Low until the other (“to-be-selected”) clock has transitioned
from High to Low. Then the new clock starts driving the output.The default configuration
for BUFGCTRL is falling edge sensitive and held at Low prior to the input switching.
BUFGCTRL can also be rising edge sensitive and held at High prior to the input switching.
In some applications the conditions previously described are not desirable. Asserting the
IGNORE pins bypasses the BUFGCTRL from detecting the conditions for switching
between two clock inputs. In other words, asserting IGNORE causes the mux to switch the
inputs at the instant the select pin changes. IGNORE0 causes the output to switch away
from the I0 input immediately when the select pin changes, while IGNORE1 causes the
output to switch away from the I1 input immediately when the select pin changes.
Selection of an input clock requires a “select” pair (S0 and CE0, or S1 and CE1) to be
asserted High. If either S or CE is not asserted High, the desired input is not selected. In
normal operation, both S and CE pairs (all four select lines) are not expected to be asserted
High simultaneously. Typically only one pin of a “select” pair is used as a select line, while
the other pin is tied High. The truth table is shown in Table 1-4.
Although both S and CE are used to select a desired output, each one of these pins behaves
slightly different. When using CE to switch clocks, the change in clock selection can be
faster than when using S. Violation in setup/hold times of the CE pins causes a glitch at the
clock output. On the other hand, using the S pins allows the user to switch between the two
clock inputs without regard to setup/hold times. It does not result in a glitch. See the
discussion of “BUFGMUX_VIRTEX4”. The CE pin is designed to allow backward
compatibility from Virtex-II and Virtex-II Pro FPGAs.
Table 1-4: Truth Table for Clock Resources
CE0S0CE1S1 O
110XI0
11X0I0
0X11I1
X011I1
1111Old Input (1)
Notes:
1. Old input refers to the valid input clock before this state is achieved.
2. For all other states, the output becomes the value of INIT_OUT and does not toggle.
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The timing diagram in Figure 1-2 illustrates various clock switching conditions using the
BUFGCTRL primitives. Exact timing numbers are best found using the speed specification.
Before time event 1, output O uses input I0.
At time TBCCCK_CE, before the rising edge at time event 1, both CE0 and S0 are
deasserted Low. At about the same time, both CE1 and S1 are asserted High.
At time TBCCKO_O, after time event 3, output O uses input I1. This occurs after a High
to Low transition of I0 (event 2) followed by a High to Low transition of I1.
At time event 4, IGNORE1 is asserted.
At time event 5, CE0 and S0 are asserted High while CE1 and S1 are deasserted Low.
At TBCCKO_O, after time event 6, output O has switched from I1 to I0 without
requiring a High to Low transition of I1.
Other capabilities of BUFGCTRL are:
Pre-selection of the I0 and I1 inputs are made after configuration but before device
operation.
The initial output after configuration can be selected as either High or Low.
Clock selection using CE0 and CE1 only (S0 and S1 tied High) can change the clock
selection without waiting for a High to Low transition on the previously selected
clock.
Figure 1-2: BUFGCTRL Timing Diagram
I0
I1
S0
S1
IGNORE0
IGNORE1
O
CE0
CE1
12 3 4 56
TBCCCK_CE
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TBCCKO_O TBCCKO_O TBCCKO_O
at I0 Begin I1 Begin I0
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Table 1-5 summarizes the attributes for the BUFGCTRL primitive.
BUFG
BUFG is simply a clock buffer with one clock input and one clock output. This primitive is
based on BUFGCTRL with some pins connected to logic High or Low. Figure 1-3 illustrates
the relationship of BUFG and BUFGCTRL. A LOC constraint is available for BUFG.
The output follows the input as shown in the timing diagram in Figure 1-4.
BUFGCE and BUFGCE_1
Unlike BUFG, BUFGCE is a clock buffer with one clock input, one clock output and a clock
enable line. This primitive is based on BUFGCTRL with some pins connected to logic High
Table 1-5: BUFGCTRL Attributes
Attribute Name Description Possible Values
INIT_OUT Initializes the BUFGCTRL output to the specified
value after configuration. Sets the positive or
negative edge behavior. Sets the output level when
changing clock selection.
0 (default), 1
PRESELECT_I0 If TRUE, the BUFGCTRL output uses the I0 input
after configuration(1).
FALSE (default),
TRUE
PRESELECT_I1 If TRUE, the BUFGCTRL output uses the I1 input
after configuration(1).
FALSE (default),
TRUE
Notes:
1. Both PRESELECT attributes cannot be TRUE at the same time.
2. The LOC constraint is available.
Figure 1-3: BUFG as BUFGCTRL
Figure 1-4: BUFG Timing Diagram
IGNORE1
IGNORE0
CE1
CE0
S1
S0
I1
I0
O
BUFG
UG070_1_03_031208
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GND
VDD
VDD
VDD
I
O
I
GND
GND
BUFG(I)
BUFG(O)
TBCCKO_O
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or Low. Figure 1-5 illustrates the relationship of BUFGCE and BUFGCTRL. A LOC
constraint is available for BUFGCE and BUFGCE_1.
The switching condition for BUFGCE is similar to BUFGCTRL. If the CE input is Low prior
to the incoming rising clock edge, the following clock pulse does not pass through the
clock buffer, and the output stays Low. Any level change of CE during the incoming clock
High pulse has no effect until the clock transitions Low. The output stays Low when the
clock is disabled. However, when the clock is being disabled it completes the clock High
pulse.
Since the clock enable line uses the CE pin of the BUFGCTRL, the select signal must meet
the setup time requirement. Violating this setup time may result in a glitch. Figure 1-6
illustrates the timing diagram for BUFGCE.
BUFGCE_1 is similar to BUFGCE, with the exception of its switching condition. If the CE
input is Low prior to the incoming falling clock edge, the following clock pulse does not
pass through the clock buffer, and the output stays High. Any level change of CE during
the incoming clock Low pulse has no effect until the clock transitions High. The output
stays High when the clock is disabled. However, when the clock is being disabled it
completes the clock Low pulse.
Figure 1-5: BUFGCE as BUFGCTRL
Figure 1-6: BUFGCE Timing Diagram
IGNORE1
IGNORE0
CE1
CE0
S1
S0
I1
I0
O
BUFGCE
BUFGCE as BUFGCTRL
ug070_1_05_081904
V
DD
GND
V
DD
CE
V
DD
O
I
I
CE
GND
GND
BUFGCE(I)
BUFGCE(CE)
BUFGCE(O)
ug070_1_06_082504
TBCCKO_O
TBCCCK_CE
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Figure 1-7 illustrates the timing diagram for BUFGCE_1.
BUFGMUX and BUFGMUX_1
BUFGMUX is a clock buffer with two clock inputs, one clock output, and a select line. This
primitive is based on BUFGCTRL with some pins connected to logic High or Low.
Figure 1-8 illustrates the relationship of BUFGMUX and BUFGCTRL. A LOC constraint is
available for BUFGMUX and BUFGCTRL.
Since the BUFGMUX uses the CE pins as select pins, when using the select, the setup time
requirement must be met. Violating this setup time may result in a glitch.
Switching conditions for BUFGMUX are the same as the CE pins on BUFGCTRL.
Figure 1-9 illustrates the timing diagram for BUFGMUX.
Figure 1-7: BUFGCE_1 Timing Diagram
Figure 1-8: BUFGMUX as BUFGCTRL
Figure 1-9: BUFGMUX Timing Diagram
BUFGCE_1(I)
BUFGCE_1(CE)
BUFGCE_1(O)
ug070_1_07_081904
TBCCKO_O
TBCCCK_CE
IGNORE1
IGNORE0
CE1S
CE0
S1
S0
I1
I0
O
BUFGMUX
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V
DD
V
DD
O
I1
I0
S
GND
GND
S
I0
I1
O
T
BCCKO_O
T
BCCKO_O
T
BCCCK_CE
begin
ihi i I1
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In Figure 1-9:
The current clock is I0.
S is activated High.
If I0 is currently High, the multiplexer waits for I0 to deassert Low.
Once I0 is Low, the multiplexer output stays Low until I1 transitions High to Low.
When I1 transitions from High to Low, the output switches to I1.
If the setup/hold times are met, no glitches or short pulses can appear on the output.
BUFGMUX_1 is rising edge sensitive and held at High prior to input switch. Figure 1-10
illustrates the timing diagram for BUFGMUX_1. A LOC constraint is available for
BUFGMUX and BUFGMUX_1.
In Figure 1-10:
The current clock is I0.
S is activated High.
If I0 is currently Low, the multiplexer waits for I0 to be asserted High.
Once I0 is High, the multiplexer output stays High until I1 transitions Low to High.
When I1 transitions from Low to High, the output switches to I1.
If the setup/hold times are met, no glitches or short pulses can appear on the output.
Figure 1-10: BUFGMUX_1 Timing Diagram
S
I0
I1
O
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TBCCKO_O
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BUFGMUX_VIRTEX4
BUFGMUX_VIRTEX4 is a clock buffer with two clock inputs, one clock output, and a select
line. This primitive is based on BUFGCTRL with some pins connected to logic High or
Low. Figure 1-11 illustrates the relationship of BUFGMUX_VIRTEX4 and BUFGCTRL.
BUFGMUX_VIRTEX4 uses the S pins as select pins. S can switch anytime without causing
a glitch. The setup/hold times on S determine whether the output will pass an extra pulse
of the previously selected clock before switching to the new clock. If S changes as shown in
Figure 1-12, prior to the setup time TBCCCK_S and before I0 transitions from High to Low,
then the output will not pass an extra pulse of I0. If S changes following the hold time for
S, then the output will pass an extra pulse. If S violates the setup/hold requirements, the
output might pass the extra pulse, but it will not glitch. In any case, the output changes to
the new clock within three clock cycles of the slower clock.
The setup/hold requirements for S0 and S1 are with respect to the falling clock edge
(assuming INIT_OUT = 0), not the rising edge as for CE0 and CE1.
Switching conditions for BUFGMUX_VIRTEX4 are the same as the S pin of BUFGCTRL.
Figure 1-12 illustrates the timing diagram for BUFGMUX_VIRTEX4.
Other capabilities of the BUFGMUX_VIRTEX4 primitive are:
Pre-selection of I0 and I1 input after configuration.
Initial output can be selected as High or Low after configuration.
Figure 1-11: BUFGMUX_VIRTEX4 as BUFGCTRL
Figure 1-12: BUFGMUX_VIRTEX4 Timing Diagram
IGNORE1
IGNORE0
CE1
S
CE0
S1
S0
I1
I0
O
BUFGMUX_VIRTEX4
ug070_1_11_071304
V
DD
V
DD
O
I1
I0
S
GND
GND
S
I0
I1
O
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Additional Use Models
Asynchronous Mux Using BUFGCTRL
In some cases an application requires immediate switching between clock inputs or
bypassing the edge sensitivity of BUFGCTRL. An example is when one of the clock inputs
is no longer switching. If this happens, the clock output would not have the proper
switching conditions because the BUFGCTRL never detected a clock edge. This case uses
the asynchronous mux. Figure 1-13 illustrates an asynchronous mux with BUFGCTRL
design example. Figure 1-14 shows the asynchronous mux timing diagram.
In Figure 1-14:
The current clock is from I0.
S is activated High.
The Clock output immediately switches to I1.
When Ignore signals are asserted High, glitch protection is disabled.
Figure 1-13: Asynchronous Mux with BUFGCTRL Design Example
Figure 1-14: Asynchronous Mux Timing Diagram
IGNORE1
IGNORE0
CE1
S
CE0
S1
S0
I1
I0
S
I1
I0
O
Asynchronous MUX
Design Example
ug070_1_13_082704
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VDD
VDD
VDD
O
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TBCCKO_O TBCCKO_O
I0
I1
S
O
at I0 Begin I1
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BUFGMUX_VIRTEX4 with a Clock Enable
A BUFGMUX_VIRTEX4 with a clock enable BUFGCTRL configuration allows the user to
choose between the incoming clock inputs. If needed, the clock enable is used to disable
the output. Figure 1-15 illustrates the BUFGCTRL usage design example and Figure 1-16
shows the timing diagram.
In Figure 1-16:
At time event 1, output O uses input I0.
Before time event 2, S is asserted High.
At time TBCCKO_O, after time event 2, output O uses input I1. This occurs after a High
to Low transition of I0 followed by a High to Low transition of I1 is completed.
At time TBCCCK_CE, before time event 3, CE is asserted Low. The clock output is
switched Low and kept at Low after a High to Low transition of I1 is completed.
Figure 1-15: BUFGMUX_VIRTEX4 with a CE and BUFGCTRL
IGNORE1
IGNORE0
CE1
S
CE
CE CE0
S1
S0
I1
I0
O
BUFGMUX_VIRTEX4+CE
Design Example
ug070_1_15_071304
O
I1
I0
S
GND
GND
Figure 1-16: BUFGMUX_VIRTEX4 with a CE Timing Diagram
UG070_1_16_082504
TBCCKO_O
TBCCCK_CE
TBCCKO_O
at I0 Clock Off
I0
I1
S
CE
O
Begin I1
12 3
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Clock Tree and Nets - GCLK
Virtex-4 FPGA clock trees are designed for low-skew and low-power operation. Any
unused branch is disconnected. The clock trees also manage the load/fanout when all the
logic resources are used.
All global clock lines and buffers are implemented differentially. This facilitates much
better duty cycles and common-mode noise rejection.
In the Virtex-4 architecture, the pin access of the global clock lines are not limited to the
logic resources clock pins. The global clock lines can access other pins in the CLBs without
using local interconnects. Applications requiring a very fast signal connection and large
load/fanout benefit from this architecture.
Clock Regions
Virtex-4 devices improve the clocking distribution by the use of clock regions. Each clock
region can have up to eight global clock domains. These eight global clocks can be driven
by any combination of the 32 global clock buffers. The restrictions and rules needed in
previous FPGA architectures are no longer applicable. Specifically, a clock region is not
limited to four quadrants regardless of die/device size. Instead, the dimensions of a clock
region are fixed to 16 CLBs tall (32 IOBs) and spanning half of the die (Figure 1-17). By
fixing the dimensions of the clock region, larger Virtex-4 devices can have more clock
regions. As a result, Virtex-4 devices can support many more multiple clock domains than
previous FPGA architectures. Table 1-6 shows the number of clock regions in each Virtex-4
device. The logic resources in the center column (DCMs, IOBs, etc.) are located in the left
clock regions.
The DCMs, if used, utilize the global clocks in the left regions as feedback lines. Up to four
DCMs can be in a specific region. If used in the same region, IDELAYCTRL uses another
global clock in that region. The DCM companion module PMCD, if directly connected to a
global clock, will also utilize the global clocks in the same region.
Figure 1-17: Clock Regions
UG070_1_17_071304
All clock regions
span half the die
All clock regions are 16 CLBs tall
(8 CLBs up and 8 CLBs down)
XC4VLX15 has 8 Clock Regions XC4VLX100 has 24 Clock Regions
Center Column
Logic Resources
8 CLBs
8 CLBs
8 CLBs
8 CLBs
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Regional Clocking Resources
Regional clock networks are a set of clock networks independent of the global clock
network. Unlike global clocks, the span of a regional clock signal is limited to three clock
regions. These networks are especially useful for source-synchronous interface designs.
To understand how regional clocking works, it is important to understand the signal path
of a regional clock signal. The Virtex-4 FPGA regional clocking resources and network
consist of the following paths and components:
Clock Capable I/O
I/O Clock Buffer - BUFIO
Regional Clock Buffer - BUFR
Regional Clock Nets
Table 1-6: Virtex-4 FPGA Clock Regions
Device Number of Clock Regions
LX Family
XC4VLX15 8
XC4VLX25 12
XC4VLX40 16
XC4VLX60 16
XC4VLX80 20
XC4VLX100 24
XC4VLX160 24
XC4VLX200 24
SX Family
XC4VSX25 8
XC4VSX35 12
XC4VSX55 16
FX Family
XC4VFX12 8
XC4VFX20 8
XC4VFX40 12
XC4VFX60 16
XC4VFX100 20
XC4VFX140 24
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Clock Capable I/O
In a typical clock region there are two clock capable I/O pin pairs (there are exceptions in
the center column). Clock capable I/O pairs are regular I/O pairs where the LVDS output
drivers have been removed to reduce the input capacitance. All global clock inputs are
clock capable I/Os (i.e., they do not have LVDS output drivers). There are four dedicated
clock capable I/O sites in every bank. When used as clock inputs, clock-capable pins can
drive BUFIO and BUFR. They can not directly connect to the global clock buffers. When
used as single-ended clock pins, then as described in “Global Clock Buffers”, the P-side of
the pin pair must be used because a direct connection only exists on this pin.
I/O Clock Buffer - BUFIO
The I/O clock buffer (BUFIO) is a new clock buffer available in Virtex-4 devices. The
BUFIO drives a dedicated clock net within the I/O column, independent of the global
clock resources. Thus, BUFIOs are ideally suited for source-synchronous data capture
(forwarded/receiver clock distribution). BUFIOs can only be driven by clock capable I/Os
located in the same clock region. BUFIOs can drive the two adjacent I/O clock nets (for a
total of up to three clock regions) as well as the regional clock buffers (BUFR) in the same
region. BUFIOs cannot drive logic resources (CLB, block RAM, etc.) because the I/O clock
network only reaches the I/O column.
BUFIO Primitive
BUFIO is simply a clock in, clock out buffer. There is a phase delay between input and
output. Figure 1-18 shows the BUFIO. Table 1-7 lists the BUFIO ports. A location constraint
is available for BUFIO.
Figure 1-18: BUFIO Primitive
Table 1-7: BUFIO Port List and Definitions
Port Name Type Width Definition
O Output 1 Clock output port
I Input 1 Clock input port
BUFIO
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BUFIO Use Models
In Figure 1-19, a BUFIO is used to drive the I/O logic using the clock capable I/O. This
implementation is ideal in source-synchronous applications where a forwarded clock is
used to capture incoming data.
Regional Clock Buffer - BUFR
The regional clock buffer (BUFR) is another new clock buffer available in Virtex-4 devices.
BUFRs drive clock signals to a dedicated clock net within a clock region, independent from
the global clock tree. Each BUFR can drive the two regional clock nets in the region it is
located, and the two clock nets in the adjacent clock regions (up to three clock regions).
Figure 1-19: BUFIO Driving I/O Logic In a Single Clock Region
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
BUFIO BUFR
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To Fabric
To Adjacent
Region
To Adjacent
Region
Clock Capable I/O
Clock Capable I/O
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Unlike BUFIOs, BUFRs can drive the I/O logic and logic resources (CLB, block RAM, etc.)
in the existing and adjacent clock regions. BUFRs can be driven by either the output from
BUFIOs or local interconnect. In addition, BUFR is capable of generating divided clock
outputs with respect to the clock input. The divide values are an integer between one and
eight. BUFRs are ideal for source-synchronous applications requiring clock domain
crossing or serial-to-parallel conversion. There are two BUFRs in a typical clock region
(two regional clock networks). The center column does not have BUFRs.
BUFR Primitive
BUFR is a clock-in/clock-out buffer with the capability to divide the input clock frequency.
Additional Notes on the CE Pin
When CE is asserted/deasserted, the output clock signal turns on/off four input clock
cycles later. When global set/reset (GSR) signal is High, BUFR does not toggle, even if CE
is held High. The BUFR output toggles four clock cycles after the GSR signal is deasserted.
BUFR Attributes and Modes
Clock division in the BUFR is controlled in software through the BUFR_DIVIDE attribute.
Table 1-9 lists the possible values when using the BUFR_DIVIDE attribute.
Figure 1-20: BUFR Primitive
Table 1-8: BUFR Port List and Definitions
Port Name Type Width Definition
O Output 1 Clock output port
CE Input 1 Clock enable port. Cannot be used in
BYPASS mode.
CLR Input 1 Asynchronous clear for the divide
logic, and sets the output Low. Cannot
be used in BYPASS mode.
I Input 1 Clock input port
CLR
CE
IO
ug070_1_20_071204
Table 1-9: BUFR_DIVIDE Attribute
Attribute Name Description Possible Values
BUFR_DIVIDE Defines whether the output clock is a divided
version of the input clock.
1, 2, 3, 4, 5, 6, 7, 8
BYPASS (default)
Notes:
1. Location constraint is available for BUFR.
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The propagation delay through BUFR is different for BUFR_DIVIDE = 1 and
BUFR_DIVIDE = BYPASS. When set to 1, the delay is slightly more than BYPASS. All other
divisors have the same delay BUFR_DIVIDE = 1. The phase relationship between the input
clock and the output clock is the same for all possible divisions except BYPASS.
The timing relationship between the inputs and output of BUFR when using the
BUFR_DIVIDE attribute is illustrated in Figure 1-21. In this example, the BUFR_DIVIDE
attribute is set to three. Sometime before this diagram CLR was asserted.
In Figure 1-21:
At time TBRDCK_CE before clock event 1, CE is asserted High.
Four clock cycles and TBRCKO_O after CE is asserted, the output O begins toggling at
the divide by three rate of the input I. TBRCKO_O and other timing numbers are best
found in the speed specification.
Note: The duty cycle is not 50/50 for odd division. The Low pulse is one cycle of I
longer.
At time event 2, CLR is asserted. After TBRDO_CLRO from time event 2, O stops
toggling.
At time event 3, CLR is deasserted.
At time TBRCKO_O after clock event 4, O begins toggling again at the divided by three
rate of I.
BUFR Use Models
BUFRs are ideal for source-synchronous applications requiring clock domain crossing or
serial-to-parallel conversion. Unlike BUFIOs, BUFRs are capable of clocking logic
resources in the FPGAs other than the IOBs. Figure 1-22 is a BUFR design example.
Figure 1-21: BUFR Timing Diagrams with BUFR_DIVIDE Values
UG070_1_21_030806
T
BRCKO_O
T
BRCKO_O
T
BRDO_CLRO
T
BRDCK_CE
I
CE
CLR
O
1 2 34
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Figure 1-22: BUFR Driving Various Logic Resources
UG070_1_22_030708
CLBs
CLBs
CLBs
CLBs
CLBs
CLBs
CLBs
CLBs
CLBs
CLBs
CLBs
CLBs
CLBs
CLBs
CLBs
CLBs
Block
RAM
Block
RAM
Block
RAM
Block
RAM
DSP
Tile
DSP
Tile
BUFR
To Adjacent
Region
To Center
of Die
To Adjacent
Region
DSP
Tile
DSP
Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
BUFIO
Clock
Capable I/O
Clock
Capable I/O
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Regional Clock Nets
In addition to global clock trees and nets, Virtex-4 devices contain regional clock nets.
These clock trees are also designed for low-skew and low-power operation. Unused
branches are disconnected. The clock trees also manage the load/fanout when all the logic
resources are used.
Regional clock nets do not propagate throughout the whole Virtex-4 device. Instead, they
are limited to only one clock region. One clock region contains two independent regional
clock nets.
To access regional clock nets, BUFRs must be instantiated. A BUFR can drive regional
clocks in up to two adjacent clock regions (Figure 1-23). BUFRs in the top or bottom region
can only access one adjacent region; below or above respectively.
VHDL and Verilog Templates
The VHDL and Verilog code follows for all clocking resource primitives.
BUFGCTRL VHDL and Verilog Templates
The following examples illustrate the instantiation of the BUFGCTRL module in VHDL
and Verilog.
VHDL Template
--Example BUFGCTRL declaration
component BUFGCTRL
generic(
INIT_OUT : integer := 0;
Figure 1-23: BUFR Driving Multiple Regions
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BUFRs
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PRESELECT_I0 : boolean := false;
PRESELECT_I1 : boolean := false;
);
port(
O: out std_ulogic;
CE0: in std_ulogic;
CE1: in std_ulogic;
I0: in std_ulogic;
I1 : in std_ulogic;
IGNORE0: in std_ulogic;
IGNORE1: in std_ulogic;
S0: in std_ulogic;
S1: in std_ulogic
);
end component;
--Example BUFGCTRL instantiation
U_BUFGCTRL : BUFGCTRL
Port map (
O => user_o,
CE0 => user_ce0,
CE1 => user_ce1,
I0 => user_i0,
I1 => user_i1,
IGNORE0 => user_ignore0,
IGNORE1 => user_ignore1,
S0 => user_s0,
S1 => user_s1
);
--Declaring constraints in VHDL file
attribute INIT_OUT : integer;
attribute PRESELECT_I0 : boolean;
attribute PRESELECT_I1 : boolean;
attribute LOC : string;
attribute INIT_OUT of U_BUFGCTRL: label is 0;
attribute PRESELECT_I0 of U_BUFGCTRL: label is FALSE;
attribute PRESELECT_I1 of U_BUFGCTRL: label is FALSE;
attribute LOC of U_BUFGCTRL: label is "BUFGCTRL_X#Y#";
--where # is valid integer locations of BUFGCTRL
Verilog Template
//Example BUFGCTRL module declaration
module BUFGCTRL (O, CE0, CE1, I0, I1, IGNORE0, IGNORE1, S0, S1);
output O;
input CE0;
input CE1;
input I0;
input I1;
input IGNORE0;
input IGNORE1;
input S0;
input S1;
parameter INIT_OUT = 0;
parameter PRESELECT_I0 = "FALSE";
parameter PRESELECT_I1 = "FALSE";
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endmodule;
//Example BUFGCTRL instantiation
BUFGCTRL U_BUFGCTRL (
.O(user_o),
.CE0(user_ce0),
.CE1(user_ce1),
.I0(user_i0),
.I1(user_i1),
.IGNORE0(user_ignore0),
.IGNORE1(user_ignore1),
.S0(user_s0),
.S1(user_s1)
);
// Declaring constraints in Verilog
// synthesis attribute INIT_OUT of U_BUFGCTRL is 0;
// synthesis attribute PRESELECT_I0 of U_BUFGCTRL is FALSE;
// synthesis attribute PRESELECT_I1 of U_BUFGCTRL is FALSE;
// synthesis attribute LOC of U_BUFGCTRL is "BUFGCTRL_X#Y#";
// where # is valid integer locations of BUFGCTRL
Declaring Constraints in UCF File
INST "U_BUFGCTRL" INIT_OUT = 0;
INST "U_BUFGCTRL" PRESELECT_I0 = FALSE;
INST "U_BUFGCTRL" PRESELECT_I1 = FALSE;
INST "U_BUFGCTRL" LOC = BUFGCTRL_X#Y#;
where # is valid integer locations of BUFGCTRL
BUFG VHDL and Verilog Templates
The following examples illustrate the instantiation of the BUFG module in VHDL and
Veri log.
VHDL Template
--Example BUFG declaration
component BUFG
port(
O: out std_ulogic;
I: in std_ulogic
);
end component;
--Example BUFG instantiation
U_BUFG : BUFG
Port map (
O => user_o,
I0 => user_i
);
--Declaring constraints in VHDL file
attribute LOC : string;
attribute LOC of U_BUFG: label is "BUFGCTRL_X#Y#";
--where # is valid integer locations of BUFGCTRL
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Verilog Template
//Example BUFG module declaration
module BUFG (O, I);
output O;
input I;
endmodule;
//Example BUFG instantiation
BUFG U_BUFG (
.O(user_o),
.I0(user_i)
);
// Declaring constraints in Verilog
// synthesis attribute LOC of U_BUFG is "BUFGCTRL_X#Y#";
// where # is valid integer locations of BUFGCTRL
Declaring Constraints in UCF File
INST "U_BUFG" LOC = BUFGCTRL_X#Y#;
where # is valid integer locations of BUFGCTRL
BUFGCE and BUFGCE_1 VHDL and Verilog Templates
The following examples illustrate the instantiation of the BUFGCE module in VHDL and
Verilog. The instantiation of BUFGCE_1 is exactly the same as BUFGCE with exception of
the primitive name.
VHDL Template
--Example BUFGCE declaration
component BUFGCE
port(
O: out std_ulogic;
CE: in std_ulogic;
I: in std_ulogic
);
end component;
--Example BUFGCE instantiation
U_BUFGCE : BUFGCE
Port map (
O => user_o,
CE => user_ce,
I => user_i
);
--Declaring constraints in VHDL file
attribute LOC : string;
attribute LOC of U_BUFGCE: label is "BUFGCTRL_X#Y#";
--where # is valid integer locations of BUFGCTRL
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Verilog Template
//Example BUFGCE module declaration
module BUFGCE (O, CE, I);
output O;
input CE;
input I;
endmodule;
//Example BUFGCE instantiation
BUFGCE U_BUFGCE (
.O(user_o),
.CE0(user_ce),
.I0(user_i)
);
// Declaring constraints in Verilog
// synthesis attribute LOC of U_BUFGCE is "BUFGCTRL_X#Y#";
// where # is valid integer locations of BUFGCTRL
Declaring Constraints in UCF File
INST "U_BUFGCE" LOC = BUFGCTRL_X#Y#;
where # is valid integer locations of BUFGCTRL
BUFGMUX and BUFGMUX_1 VHDL and Verilog Templates
The following examples illustrate the instantiation of the BUFGMUX module in VHDL
and Verilog. The instantiation of BUFGMUX_1 is exactly the same as BUFGMUX with
exception of the primitive name.
VHDL Template
--Example BUFGMUX declaration
component BUFGMUX
port(
O: out std_ulogic;
I0: in std_ulogic;
I1 : in std_ulogic;
S: in std_ulogic
);
end component;
--Example BUFGMUX instantiation
U_BUFGMUX : BUFGMUX
Port map (
O => user_o,
I0 => user_i0,
I1 => user_i1,
S => user_s
);
--Declaring constraints in VHDL file
attribute LOC : string;
attribute LOC of U_BUFGMUX: label is "BUFGCTRL_X#Y#";
--where # is valid integer locations of BUFGCTRL
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Verilog Template
//Example BUFGMUX module declaration
module BUFGMUX (O, I0, I1, S);
output O;
input I0;
input I1;
input S;
endmodule;
//Example BUFGMUX instantiation
BUFGMUX U_BUFGMUX (
.O(user_o),
.I0(user_i0),
.I1(user_i1),
.S0(user_s)
);
// Declaring constraints in Verilog
// synthesis attribute LOC of U_BUFGMUX is "BUFGCTRL_X#Y#";
// where # is valid integer locations of BUFGCTRL
Declaring Constraints in UCF File
INST "U_BUFGMUX" LOC = BUFGCTRL_X#Y#;
where # is valid integer locations of BUFGCTRL
BUFGMUX_VIRTEX4 VHDL and Verilog Templates
The following examples illustrate the instantiation of the BUFGMUX_VIRTEX4 module in
VHDL and Verilog.
VHDL Template
--Example BUFGMUX_VIRTEX4 declaration
component BUFGMUX_VIRTEX4
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
--Example BUFGMUX_VIRTEX4 instantiation
U_BUFGMUX_VIRTEX4 : BUFGMUX_VIRTEX4
Port map (
O => user_o,
I0 => user_i0,
I1 => user_i1,
S => user_s
);
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--Declaring constraints in VHDL file
attribute INIT_OUT : integer;
attribute PRESELECT_I0 : boolean;
attribute PRESELECT_I1 : boolean;
attribute LOC : string;
attribute INIT_OUT of U_BUFGMUX_VIRTEX4: label is 0;
attribute PRESELECT_I0 of U_BUFGMUX_VIRTEX4: label is FALSE;
attribute PRESELECT_I1 of U_BUFGMUX_VIRTEX4: label is FALSE;
attribute LOC of U_BUFGMUX_VIRTEX4: label is "BUFGCTRL_X#Y#";
--where # is valid integer locations of BUFGCTRL
Verilog Template
//Example BUFGMUX_VIRTEX4 module declaration
module BUFGMUX_VIRTEX4 (O, I0, I1, S);
output O;
input I0;
input I1;
input S;
parameter INIT_OUT = 1'b0;
parameter PRESELECT_I0 = "TRUE";
parameter PRESELECT_I1 = "FALSE";
endmodule;
//Example BUFGCTRL instantiation
BUFGMUX_VIRTEX4 U_BUFGMUX_VIRTEX4 (
.O(user_o),
.I0(user_i0),
.I1(user_i1),
.S(user_s)
);
// Declaring constraints in Verilog
// synthesis attribute INIT_OUT of U_BUFGMUX_VIRTEX4 is 0;
// synthesis attribute PRESELECT_I0 of U_BUFGMUX_VIRTEX4 is FALSE;
// synthesis attribute PRESELECT_I1 of U_BUFGMUX_VIRTEX4 is FALSE;
// synthesis attribute LOC of U_BUFGMUX_VIRTEX4 is "BUFGCTRL_X#Y#";
// where # is valid integer locations of BUFGCTRL
Declaring Constraints in UCF File
INST "U_BUFGMUX_VIRTEX4" INIT_OUT = 0;
INST "U_BUFGMUX_VIRTEX4" PRESELECT_I0 = FALSE;
INST "U_BUFGMUX_VIRTEX4" PRESELECT_I1 = FALSE;
INST "U_BUFGMUX_VIRTEX4" LOC = BUFGCTRL_X#Y#;
where # is valid integer locations of BUFGCTRL
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BUFIO VHDL and Verilog Templates
The following examples illustrate the instantiation of the BUFIO module in VHDL and
Veri log.
VHDL Template
--Example BUFIO declaration
component BUFIO
port(
O: out std_ulogic;
I: in std_ulogic
);
end component;
--Example BUFIO instantiation
U_BUFIO : BUFIO
Port map (
O => user_o,
I0 => user_i
);
--Declaring constraints in VHDL file
attribute LOC : string;
attribute LOC of U_BUFIO: label is "BUFIO_X#Y#";
--where # is valid integer locations of BUFIO
Verilog Template
//Example BUFIO module declaration
module BUFIO (O, I);
output O;
input I;
endmodule;
//Example BUFIO instantiation
BUFIO U_BUFIO (
.O(user_o),
.I(user_i)
);
// Declaring constraints in Verilog
// synthesis attribute LOC of U_BUFIO is "BUFIO_X#Y#";
// where # is valid integer locations of BUFIO
Declaring Constraints in UCF File
INST "U_BUFIO" LOC = BUFIO_X#Y#;
where # is valid integer locations of BUFIO
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BUFR VHDL and Verilog Templates
The following examples illustrate the instantiation of the BUFR module in VHDL and
Veri log.
VHDL Template
--Example BUFR declaration
component BUFR
generic(
BUFR_DIVIDE : string := "BYPASS";
);
port(
O: out std_ulogic;
CE: in std_ulogic;
CLR: in std_ulogic;
I: in std_ulogic
);
end component;
--Example BUFR instantiation
U_BUFR : BUFR
Port map (
O => user_o,
CE => user_ce,
CLR => user_clr,
I => user_i
);
--Declaring constraints in VHDL file
attribute BUFR_DIVIDE : string;
attribute LOC : string;
attribute INIT_OUT of U_BUFR: label is BYPASS;
attribute LOC of U_BUFR: label is "BUFR_X#Y#";
--where # is valid integer locations of BUFR
Verilog Template
//Example BUFR module declaration
module BUFR (O, CE, CLR, I);
output O;
input CE;
input CLR;
input I;
parameter BUFR_DIVIDE = "BYPASS";
endmodule;
//Example BUFR instantiation
BUFR U_BUFR (
.O(user_o),
.CE(user_ce),
.CLR(user_clr),
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.I(user_i)
);
// Declaring constraints in Verilog
// synthesis attribute BUFR_DIVIDE of U_BUFR is BYPASS;
// synthesis attribute LOC of U_BUFR is "BUFR_X#Y#";
// where # is valid integer locations of BUFR
Declaring Constraints in UCF File
INST "U_BUFR" BUFR_DIVIDE=BYPASS;
INST "U_BUFR" LOC = BUFR_X#Y#;
where # is valid integer locations of BUFR
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Chapter 2
Digital Clock Managers (DCMs)
DCM Summary
The Virtex®-4 FPGA Digital Clock Managers (DCMs) provide a wide range of powerful
clock management features:
Clock Deskew
The DCM contains a delay-locked loop (DLL) to completely eliminate clock
distribution delays, by deskewing the DCM's output clocks with respect to the input
clock. The DLL contains delay elements (individual small buffers) and control logic.
The incoming clock drives a chain of delay elements, thus the output of every delay
element represents a version of the incoming clock delayed at a different point.
The control logic contains a phase detector and a delay-line selector. The phase
detector compares the incoming clock signal (CLKIN) against a feedback input
(CLKFB) and steers the delay line selector, essentially adding delay to the output of
DCM until the CLKIN and CLKFB coincide.
Frequency Synthesis
Separate outputs provide a doubled frequency (CLK2X and CLK2X180). Another
output, CLKDV, provides a frequency that is a specified fraction of the input
frequency.
Two other outputs, CLKFX and CLKFX180, provide an output frequency derived from
the input clock by simultaneous frequency division and multiplication. The user can
specify any integer multiplier (M) and divisor (D) within the range specified in the
DCM Timing Parameters section of the Virtex-4 Data Sheet. An internal calculator
determines the appropriate tap selection, to make the output edge coincide with the
input clock whenever mathematically possible. For example, M = 9 and D = 5,
multiply the frequency by 1.8, and the output rising edge is coincident with the input
rising edge after every fifth input period, or after every ninth output period.
Phase Shifting
The DCM allows coarse and fine-grained phase shifting. The coarse phase shifting
uses the 90°, 180°, and 270° phases of CLK0 to make CLK90, CLK180, and CLK270
clock outputs. The 180° phase of CLK2X and CLKFX provide the respective CLK2X180
and CLKFX180 clock outputs.
There are also four modes of fine-grained phase-shifting; fixed, variable-positive,
variable-center, and direct modes. Fine-grained phase shifting allows all DCM output
clocks to be phase-shifted with respect to CLKIN while maintaining the relationship
between the coarse phase outputs. With fixed mode, a fixed fraction of phase shift can
be defined during configuration and in multiples of the clock period divided by 256.
Using the variable-positive and variable-center modes the phase can be dynamically
and repetitively moved forward and backwards by 1/256 of the clock period. With the
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direct mode the phase can be dynamically and repetitively moved forward and
backwards by the value of one DCM_TAP. See the DCM Timing Parameters section in
the Virtex-4 Data Sheet.
Dynamic Reconfiguration
There is a bus connection to the DCM to change DCM attributes without reconfiguring
the rest of the device. For more information, see the Dynamic Reconfiguration chapter
of the Virtex-4 Configuration Guide.
The DADDR[6:0], DI[15:0], DWE, DEN, DCLK inputs and DO[15:0], and DRDY
outputs are available to dynamically reconfigure select DCM functions. With dynamic
reconfiguration, DCM attributes can be changed to select a different phase shift,
multiply (M) or divide (D) from the currently configured settings.
Figure 2-1 shows a simplified view of the Virtex-4 FPGA center column resources
including all DCM locations. Table 2-1 summarizes the availability of DCMs in each
Virtex-4 device.
Figure 2-1: DCM Location
UG070_2_01_030708
DCMs
(Top Half)
DCMs
(Bottom Half)
PMCDs
(Top Half)
PMCDs
(Bottom Half)
I/Os
I/Os
Virtex-4 FPGA
Center Column
BUFGCTRLs
(Top Half)
BUFGCTRLs
(Bottom Half)
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DCM Primitives
Three DCM primitives are available: DCM_BASE, DCM_PS, and DCM_ADV (see
Figure 2-2).
Table 2-1: Available DCM Resources
Device Available DCMs Site Names
XC4VLX15
XC4VSX25
XC4VFX12, XC4VFX20
4Bottom Half:
DCM_ADV_X0Y0, DCM_ADV_X0Y1
Top Half:
DCM_ADV_X0Y2, DCM_ADV_X0Y3
XC4VLX25, XC4VLX40, XC4VLX60
XC4VSX35, XC4VSX55
XC4VFX40
8Bottom Half:
DCM_ADV_X0Y0, DCM_ADV_X0Y1, DCM_ADV_X0Y2
Top Half:
DCM_ADV_X0Y3, DCM_ADV_X0Y4, DCM_ADV_X0Y5,
DCM_ADV_X0Y6, DCM_ADV_X0Y7
XC4VLX80, XC4VLX100, XC4VLX160,
XC4VLX200
XC4VFX60, XC4VFX100
12 Bottom Half:
DCM_ADV_X0Y0, DCM_ADV_X0Y1, DCM_ADV_X0Y2,
DCM_ADV_X0Y3, DCM_ADV_X0Y4, DCM_ADV_X0Y5
Top Half:
DCM_ADV_X0Y6, DCM_ADV_X0Y7, DCM_ADV_X0Y8,
DCM_ADV_X0Y9, DCM_ADV_X0Y10,
DCM_ADV_X0Y11
XC4VFX140 20 Bottom Half:
DCM_ADV_X0Y0, DCM_ADV_X0Y1, DCM_ADV_X0Y2,
DCM_ADV_X0Y3, DCM_ADV_X0Y4, DCM_ADV_X0Y5,
DCM_ADV_X0Y6, DCM_ADV_X0Y7, DCM_ADV_X0Y8,
DCM_ADV_X0Y9
Top Half:
DCM_ADV_X0Y10, DCM_ADV_X0Y11
DCM_ADV_X0Y12, DCM_ADV_X0Y13
DCM_ADV_X0Y14, DCM_ADV_X0Y15
DCM_ADV_X0Y16, DCM_ADV_X0Y17
DCM_ADV_X0Y18, DCM_ADV_X0Y19
Figure 2-2: DCM Primitives
CLKIN
CLKFB
RST
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
CLKFX180
LOCKED
CLKIN
CLKFB
PSINCDEC
PSEN
PSCLK
RST
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
CLKFX180
LOCKED
PSDONE
DO[15:0]
CLKIN
CLKFB
PSINCDEC
PSEN
PSCLK
DADDR[6:0]
DI[15:0]
DWE
DEN
DCLK
RST
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
CLKFX180
LOCKED
PSDONE
DO[15:0]
DRDY
DCM_PSDCM_ADVDCM_BASE
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DCM_BASE Primitive
The DCM_BASE primitive accesses the basic frequently used DCM features and simplifies
the user-interface ports. The clock deskew, frequency synthesis, and fixed-phase shifting
features are available to use with DCM_BASE. Table 2-2 lists the available ports in the
DCM_BASE primitive.
DCM_PS Primitive
The DCM_PS primitive accesses all DCM features and ports available in DCM_BASE plus
additional ports used by the variable phase shifting feature. DCM_PS also has the
following available DCM features: clock deskew, frequency synthesis, and fixed or
variable phase-shifting. Table 2-3 lists the available ports in the DCM_PS primitive.
DCM_ADV Primitive
The DCM_ADV primitive has access to all DCM features and ports available in DCM_PS
plus additional ports for the dynamic reconfiguration feature. It is a superset of the other
two DCM primitives. DCM_ADV uses all the DCM features including clock deskew,
frequency synthesis, fixed or variable phase shifting, and dynamic reconfiguration.
Table 2-4 lists the available ports in the DCM_ADV primitive.
Table 2-2: DCM_BASE Primitive
Available Ports Port Names
Clock Input CLKIN, CLKFB
Control and Data Input RST
Clock Output CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV,
CLKFX, CLKFX180
Status and Data Output LOCKED
Table 2-3: DCM_PS Primitive
Available Ports Port Names
Clock Input CLKIN, CLKFB, PSCLK
Control and Data Input RST, PSINCDEC, PSEN
Clock Output CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV,
CLKFX, CLKFX180
Status and Data Output LOCKED, PSDONE, DO[15:0]
Table 2-4: DCM_ADV Primitive
Available Ports Port Names
Clock Input CLKIN, CLKFB, PSCLK, DCLK
Control and Data Input RST, PSINCDEC, PSEN, DADDR[6:0], DI[15:0], DWE, DEN
Clock Output CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV,
CLKFX, CLKFX180
Status and Data Output LOCKED, PSDONE, DO[15:0], DRDY
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DCM Ports
There are four types of DCM ports available in the Virtex-4 architecture:
Clock Input Ports
Control and Data Input Ports
Clock Output Ports
Status and Data Output Ports
Clock Input Ports
Source Clock Input — CLKIN
The source clock (CLKIN) input pin provides the source clock to the DCM. The CLKIN
frequency must fall in the ranges specified in the Virtex-4 Data Sheet. The clock input signal
comes from one of the following buffers:
1. IBUFG Global Clock Input Buffer
The DCM compensates for the clock input path when an IBUFG on the same edge (top
or bottom) of the device as the DCM is used.
2. BUFGCTRL Internal Global Clock Buffer
Any BUFGCTRL can drive any DCM in the Virtex-4 device using dedicated global
routing. A BUFGCTRL can drive the DCM CLKIN pin when used to connect two
DCMs in series.
3. IBUF – Input Buffer
When an IBUF drives the CLKIN input, the PAD to DCM input skew is not
compensated.
Feedback Clock Input — CLKFB
The feedback clock (CLKFB) input pin provides a reference or feedback signal to the DCM
to delay-compensate the clock outputs, and align them with the clock input. To provide the
necessary feedback to the DCM, connect only the CLK0 DCM output to the CLKFB pin.
When the CLKFB pin is connected, all clock outputs are deskewed to CLKIN. When the
CLKFB pin is not connected, DCM clock outputs are not deskewed to CLKIN. However,
the relative phase relationship between all output clocks is preserved.
During internal feedback configuration, the CLK0 output of a DCM connects to a global
buffer on the same top or bottom half of the device. The output of the global buffer
connects to the CLKFB input of the same DCM.
During the external feedback configuration, the following rules apply:
1. To forward the clock, the CLK0 of the DCM must directly drive an OBUF or a BUFG-
to-DDR configuration.
2. External to the FPGA, the forwarded clock signal must be connected to the IBUFG
(GCLK pin) or the IBUF driving the CLKFB of the DCM. Both CLK and CLKFB should
have identical I/O buffers.
Figure 2-9 and Figure 2-10, in “Application Examples,” page 82, illustrate clock
forwarding with external feedback configuration.
The feedback clock input signal can be driven by one of the following buffers:
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1. IBUFG Global Clock Input Buffer
This is the preferred source for an external feedback configuration. When an IBUFG
drives a CLKFB pin of a DCM in the same top or bottom half of the device, the pad to
DCM skew is compensated for deskew.
2. BUFGCTRL – Internal Global Clock Buffer
This is an internal feedback configuration.
3. IBUF – Input Buffer
This is an external feedback configuration. When IBUF is used, the PAD to DCM input
skew is not compensated.
Phase-Shift Clock Input — PSCLK
The phase-shift clock (PSCLK) input pin provides the source clock for the DCM phase
shift. The PSCLK can be asynchronous (in phase and frequency) to CLKIN. The phase-shift
clock signal can be driven by any clock source (external or internal), including:
1. IBUF – Input Buffer
2. IBUFG Global Clock Input Buffer
To access the dedicated routing, only the IBUFGs on the same edge of the device (top
or bottom) as the DCM can be used to drive a PSCLK input of the DCM.
3. BUFGCTRL An Internal Global Buffer
4. Internal Clock Any internal clock using general purpose routing.
The frequency range of PSCLK is defined by PSCLK_FREQ_LF/HF (see the Virtex-4 Data
Sheet). This input must be tied to ground when the CLKOUT_PHASE_SHIFT attribute is
set to NONE or FIXED.
Dynamic Reconfiguration Clock Input — DCLK
The dynamic reconfiguration clock (DCLK) input pin provides the source clock for the
DCM's dynamic reconfiguration circuit. The frequency of DCLK can be asynchronous (in
phase and frequency) to CLKIN. The dynamic reconfiguration clock signal is driven by
any clock source (external or internal), including:
1. IBUF – Input Buffer
2. IBUFG Global Clock Input Buffer
Only the IBUFGs on the same edge of the device (top or bottom) as the DCM can be
used to drive a CLKIN input of the DCM.
3. BUFGCTRL An Internal Global Buffer
4. Internal Clock Any internal clock using general purpose routing.
The frequency range of DCLK is described in the Virtex-4 Data Sheet. When dynamic
reconfiguration is not used, this input must be tied to ground. See the dynamic
reconfiguration chapter in the Virtex-4 Configuration Guide for more information.
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Control and Data Input Ports
Reset Input — RST
The reset (RST) input pin resets the DCM circuitry. The RST signal is an active High
asynchronous reset. Asserting the RST signal asynchronously forces all DCM outputs Low
(the LOCKED signal, all status signals, and all output clocks) after some propagation delay.
When the reset is asserted, the last cycle of the clocks can exhibit a short pulse and a
severely distorted duty-cycle, or no longer be deskewed with respect to one another while
deasserting Low. Deasserting the RST signal starts the locking process at the next CLKIN
cycle.
To ensure a proper DCM reset and locking process, the RST signal must be held until the
CLKIN and CLKFB signals are present and stable for at least 200 ms. (The 200 ms
requirement for CLKFB only applies when external feedback is used.)
The time it takes for the DCM to lock after a reset is specified in the Virtex-4 Data Sheet as
LOCK_DLL (for a DLL output) and LOCK_FX (for a DFS output). These are the CLK and
CLKFX outputs described in “Clock Output Ports”. The DCM locks faster at higher
frequencies. The worse-case numbers are specified in the Virtex-4 Data Sheet. In all designs,
the DCM must be held in reset until CLKIN is stable.
Phase-Shift Increment/Decrement Input — PSINCDEC
The phase-shift increment/decrement (PSINCDEC) input signal must be synchronous
with PSCLK. The PSINCDEC input signal is used to increment or decrement the phase-
shift factor when PSEN is activated. As a result, the output clocks are shifted. The
PSINCDEC signal is asserted High for increment or deasserted Low for decrement. This
input must be tied to ground when the CLKOUT_PHASE_SHIFT attribute is set to NONE
or FIXED.
Phase-Shift Enable Input — PSEN
The phase-shift enable (PSEN) input signal must be synchronous with PSCLK. A variable
phase-shift operation is initiated by the PSEN input signal. It must be activated for one
period of PSCLK. After PSEN is initiated, the phase change is gradual with completion
indicated by a High pulse on PSDONE. There are no sporadic changes or glitches on any
output during the phase transition. From the time PSEN is enabled until PSDONE is
flagged, the DCM output clock moves bit-by-bit from its original phase shift to the target
phase shift. The phase shift is complete when PSDONE is flagged. PSEN must be tied to
ground when the CLKOUT_PHASE_SHIFT attribute is set to NONE or FIXED. Figure 2-7
shows the timing for this input.
Dynamic Reconfiguration Data Input — DI[15:0]
The dynamic reconfiguration data (DI) input bus provides reconfiguration data for
dynamic reconfiguration. When not used, all bits must be assigned zeros. See the Dynamic
Reconfiguration chapter of the Virtex-4 Configuration Guide for more information.
Dynamic Reconfiguration Address Input — DADDR[6:0]
The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration
address for the dynamic reconfiguration. When not used, all bits must be assigned zeros.
The DO output bus will reflect the DCM’s status. See the Dynamic Reconfiguration chapter
of the Virtex-4 Configuration Guide for more information.
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Dynamic Reconfiguration Write Enable Input — DWE
The dynamic reconfiguration write enable (DWE) input pin provides the write enable
control signal to write the DI data into the DADDR address. When not used, it must be tied
Low. See the Dynamic Reconfiguration chapter of the Virtex-4 Configuration Guide for more
information.
Dynamic Reconfiguration Enable Input — DEN
The dynamic reconfiguration enable (DEN) input pin provides the enable control signal to
access the dynamic reconfiguration feature. When the dynamic reconfiguration feature is
not used, DEN must be tied Low. When DEN is tied Low, DO reflects the DCM status
signals. See the Dynamic Reconfiguration chapter of the Virtex-4 Configuration Guide for
more information.
Clock Output Ports
A DCM provides nine clock outputs with specific frequency and phase relationships.
When CLKFB is connected, all DCM clock outputs have a fixed phase relationship to
CLKIN. When CLKFB is not connected, the DCM outputs are not phase aligned. However,
the phase relationship between all output clocks is preserved.
1x Output Clock — CLK0
The CLK0 output clock provides a clock with the same frequency as the DCM’s effective
CLKIN frequency. By default, the effective input clock frequency is equal to the CLKIN
frequency. The CLKIN_DIVIDE_BY_2 attribute is set to TRUE to make the effective CLKIN
frequency ½ the actual CLKIN frequency. The CLKIN_DIVIDE_BY_2 Attribute description
provides further information. When CLKFB is connected, CLK0 is phase aligned to
CLKIN.
1x Output Clock, 90° Phase Shift — CLK90
The CLK90 output clock provides a clock with the same frequency as the DCM’s CLK0
only phase-shifted by 90°.
1x Output Clock, 180° Phase Shift — CLK180
The CLK180 output clock provides a clock with the same frequency as the DCM’s CLK0
only phase-shifted by 180°.
1x Output Clock, 270° Phase Shift — CLK270
The CLK270 output clock provides a clock with the same frequency as the DCM’s CLK0
only phase-shifted by 270°.
2x Output Clock — CLK2X
The CLK2X output clock provides a clock that is phase aligned to CLK0, with twice the
CLK0 frequency, and with an automatic 50/50 duty-cycle correction. Until the DCM is
locked, the CLK2X output appears as a 1x version of the input clock with a 25/75 duty
cycle. This behavior allows the DCM to lock on the correct edge with respect to the source
clock.
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2x Output Clock, 180° Phase Shift — CLK2X180
The CLK2X180 output clock provides a clock with the same frequency as the DCM’s
CLK2X only phase-shifted by 180°.
Frequency Divide Output Clock — CLKDV
The CLKDV output clock provides a clock that is phase aligned to CLK0 with a frequency
that is a fraction of the effective CLKIN frequency. The fraction is determined by the
CLKDV_DIVIDE attribute. Refer to the CLKDV_DIVIDE Attribute for more information.
Frequency-Synthesis Output Clock — CLKFX
The CLKFX output clock provides a clock with the following frequency definition:
CLKFX frequency = (M/D) ×effective CLKIN frequency
In this equation, M is the multiplier (numerator) with a value defined by the
CLKFX_MULTIPLY attribute. D is the divisor (denominator) with a value defined by the
CLKFX_DIVIDE attribute. Specifications for M and D, as well as input and output
frequency ranges for the frequency synthesizer, are provided in the Virtex-4 Data Sheet.
The rising edge of CLKFX output is phase aligned to the rising edges of CLK0, CLK2X, and
CLKDV. When M and D to have no common factor, the alignment occurs only once every
D cycles of CLK0.
Frequency-Synthesis Output Clock, 180° — CLKFX180
The CLKFX180 output clock provides a clock with the same frequency as the DCM’s
CLKFX only phase-shifted by 180°.
Status and Data Output Ports
Locked Output — LOCKED
The LOCKED output indicates whether the DCM clock outputs are valid, i.e., the outputs
exhibit the proper frequency and phase. After a reset, the DCM samples several thousand
clock cycles to achieve lock. After the DCM achieves lock, the LOCKED signal is asserted
High. The DCM timing parameters section of the Virtex-4 Data Sheet provides estimates for
locking times.
To guarantee an established system clock at the end of the start-up cycle, the DCM can
delay the completion of the device configuration process until after the DCM is locked. The
STARTUP_WAIT attribute activates this feature. The STARTUP_WAIT Attribute
description provides further information.
Until the LOCKED signal is asserted High, the DCM output clocks are not valid and can
exhibit glitches, spikes, or other spurious movement. In particular, the CLK2X output
appears as a 1x clock with a 25/75 duty cycle.
Phase-Shift Done Output — PSDONE
The phase-shift done (PSDONE) output signal is synchronous to PSCLK. At the
completion of the requested phase shift, PSDONE pulses High for one period of PSCLK.
This signal also indicates a new change to the phase shift can be initiated. The PSDONE
output signal is not valid if the phase-shift feature is not being used or is in fixed mode.
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Status or Dynamic Reconfiguration Data Output — DO[15:0]
The DO output bus provides DCM status or data output when using dynamic
reconfiguration (Table 2-5). Further information on using DO as the data output is
available in the Dynamic Reconfiguration chapter of the Virtex-4 Configuration Guide for
more information.
If the dynamic reconfiguration port is not used, using DCM_BASE or DCM_PS instead of
DCM_ADV is strongly recommended.
When LOCKED is Low (during reset or the locking process), all the status signals deassert
Low.
Dynamic Reconfiguration Ready Output — DRDY
The dynamic reconfiguration ready (DRDY) output pin provides the response to the DEN
signal for the DCM’s dynamic reconfiguration feature. Further information on the DRDY
pin is available in the dynamic reconfiguration section in the Virtex-4 Configuration Guide.
Table 2-5: DCM Status Mapping to DO Bus
DO Bit Status Description
DO[0] Phase-shift overflow Asserted when the DCM is phase-shifted beyond the
allowed phase-shift value or when the absolute delay
range of the phase-shift delay line is exceeded.
DO[1] CLKIN stopped Asserted when the input clock is stopped (CLKIN
remains High or Low for one or more clock cycles).
When CLKIN is stopped, the DO[1] CLKIN stopped
status is asserted within nine CLKIN cycles. When
CLKIN is restarted, CLK0 starts toggling and DO[1] is
deasserted within nine clock cycles.
DO[2] CLKFX stopped Asserted when CLKFX stops. The DO[2] CLKFX
stopped status is asserted within 257 to 260 CLKIN
cycles after CLKFX stopped. CLKFX will not resume,
and DO[2] is not deasserted until the DCM is reset.
DO[3] CLKFB stopped Asserted when the feedback clock is stopped (CLKFB
remains High or Low for one or more clock cycles). The
DO[3] CLKFB stopped status is asserted within six
CLKIN cycles after CLKFB is stopped. CLKFB stopped
is deasserted within six CLKIN cycles when CLKFB
resumes after being stopped momentarily. An
occasionally skipped CLKFB will not affect the DCM
operation. However, stopping CLKFB for a long time
can result in the DCM losing LOCKED. When LOCKED
is lost, the DCM needs to be reset to resume operation.
DO[15:4] Not assigned
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DCM Attributes
A handful of DCM attributes govern the DCM functionality. Table 2-6 summarizes all the
applicable DCM attributes. This section provides a detailed description of each attribute.
For more information on applying these attributes in UCF, VHDL, or Verilog code, refer to
the Constraints Guide at:
http://www.support.xilinx.com/support/software_manuals.htm
Table 2-6: DCM Attributes
DCM Attribute Name Description Values Default Value
CLK_FEEDBACK Determines the type of feedback
applied to CLKFB.
String: “1X” or “NONE” 1X
CLKDV_DIVIDE Controls CLKDV such that the
source clock is divided by N.
This feature provides automatic
duty cycle correction such that the
CLKDV output pin has a 50/50
duty cycle always in low-frequency
mode, as well as for all integer
values of the division factor N in
high-frequency mode.
Real:
1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0,
5.5, 6.0, 6.5, 7.0, 7.5, 8, 9, 10, 11,
12, 13, 14, 15, 16
2.0
CLKFX_DIVIDE Sets the divisor (D) value of CLKFX.
The CLKFX frequency equals the
effective CLKIN frequency
multiplied by M/D.
Integer: 1 to 32 1
CLKFX_MULTIPLY Sets the multiply (M) of CLKFX.
The CLKFX frequency equals the
effective CLKIN frequency
multiplied by M/D.
Integer: 2 to 32 4
CLKIN_DIVIDE_BY_2 Allows for the input clock
frequency to be divided in half
when necessary to meet the DCM
input clock frequency requirements.
Boolean: FALSE or TRUE FALSE
CLKIN_PERIOD Specifies the source clock period to
help the DCM adjust for optimum
CLKFX/CLKFX180 outputs.
Real in ns 0.0
CLKOUT_PHASE_SHIFT Specifies the phase-shift mode. String: “NONE”, “FIXED”,
“VARIABLE_POSITIVE”,
“VARIABLE_CENTER”, or
“DIRECT”
NONE
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CLK_FEEDBACK Attribute
The CLK_FEEDBACK attribute determines the type of feedback applied to the CLKFB.
The possible values are 1X or NONE. The default value is 1X. When this attribute is set to
1X, the CLKFB pin must be driven by CLK0. When this attribute is set to NONE, the
CLKFB pin must be unconnected.
DCM_AUTOCALIBRATION When this attribute is TRUE, the
DCM is protected from the effects
of negative bias temperature
instability (NBTI). This attribute
cannot be set to FALSE unless
CLKIN and CLKFB (if external
feedback is used) are guaranteed
to never stop. The macro can also
be disabled if the user can
guarantee to hold DCM in reset
during clock stoppage. If this
attribute is set to FALSE, the reset
requirement is three clock cycles.
Boolean: TRUE or FALSE TRUE
DCM_PERFORMANCE_MODE Allows selection between
maximum frequency/ minimum
jitter and low frequency/maximum
phase-shift range.
String: “MAX_SPEED” or
“MAX_RANGE”
MAX_SPEED
DESKEW_ADJUST Affects the amount of delay in the
feedback path, and should be used
for source-synchronous interfaces.
String:
“SYSTEM_SYNCHRONOUS”
or
“SOURCE_SYNCHRONOUS”
SYSTEM_
SYNCHRONOUS
DFS_FREQUENCY_MODE Specifies the frequency mode of the
frequency synthesizer.
String: “LOW” or “HIGH” LOW
DLL_FREQUENCY_MODE Specifies the frequency mode of the
DLL.
String: “LOW” or “HIGH” LOW
DUTY_CYCLE_CORRECTION Controls the DCM 1X outputs
(CLK0, CLK90, CLK180, and
CLK270), to exhibit a 50/50 duty
cycle. Leave this attribute set at the
default value.
Boolean: TRUE or FALSE TRUE
FACTORY_JF Controls the DCM tap update rate.
Value depends on
DLL_FREQUENCY_MODE setting.
BIT_VECTOR F0F0
PHASE_SHIFT Specifies the phase-shift numerator.
The value range depends on
CLKOUT_PHASE_SHIFT and
clock frequency.
Integer:
–255 to 255
or
0 to 1023
0
STARTUP_WAIT When this attribute is set to TRUE,
the configuration startup sequence
waits in the specified cycle until the
DCM locks.
Boolean: FALSE or TRUE FALSE
Table 2-6: DCM Attributes (Continued)
DCM Attribute Name Description Values Default Value
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CLKDV_DIVIDE Attribute
The CLKDV_DIVIDE attribute controls the CLKDV frequency. The source clock frequency
is divided by the value of this attribute. The possible values for CLKDV_DIVIDE are: 1.5,
2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, or 16. The default value is 2.
In the low frequency mode, any CLKDV_DIVIDE value produces a CLKDV output with a
50/50 duty-cycle. In the high frequency mode, the CLKDV_DIVIDE value must be set to
an integer value to produce a CLKDV output with a 50/50 duty-cycle. For non-integer
CLKDV_DIVIDE values, the CLKDV output duty cycle is shown in Table 2-7.
CLKFX_MULTIPLY and CLKFX_DIVIDE Attributes
The CLKFX_MULTIPLY attribute sets the multiply value (M) of the CLKFX output. The
CLKFX_DIVIDE attribute sets the divisor (D) value of the CLKFX output. Both control the
CLKFX output making the CLKFX frequency equal the effective CLKIN (source clock)
frequency multiplied by M/D. The possible values for M are any integer from 2 to 32. The
possible values for D are any integer from 1 to 32. The default settings are M = 4 and D = 1.
CLKIN_DIVIDE_BY_2 Attribute
The CLKIN_DIVIDE_BY_2 attribute is used to enable a toggle flip-flop in the input clock
path to the DCM. When set to FALSE, the effective CLKIN frequency of the DCM equals
the source clock frequency driving the CLKIN input. When set to TRUE, the CLKIN
frequency is divided by two before it reaches the rest of the DCM. Thus, the DCM sees half
the frequency applied to the CLKIN input and operates based on this frequency. For
example, if a 100 MHz clock drives CLKIN, and CLKIN_DIVIDE_BY_2 is set to TRUE;
then the effective CLKIN frequency is 50 MHz. Thus, CLK0 output is 50 MHz and CLK2X
output is 100 MHz. The effective CLKIN frequency must be used to evaluate any operation
or specification derived from CLKIN frequency. The possible values for
CLKIN_DIVIDE_BY_2 are TRUE and FALSE. The default value is FALSE.
CLKIN_PERIOD Attribute
The CLKIN_PERIOD attribute specifies the source clock period (in nanoseconds). The
default value is 0.0 ns.
Table 2-7: Non-Integer CLKDV_DIVIDE
CLKDV_DIVIDE Value
CLKDV Duty Cycle in
High Frequency Mode
(High Pulse/Low Pulse Value)
1.5 1/3
2.5 2/5
3.5 3/7
4.5 4/9
5.5 5/11
6.5 6/13
7.5 7/15
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CLKOUT_PHASE_SHIFT Attribute
The CLKOUT_PHASE_SHIFT attribute indicates the mode of the phase shift applied to the
DCM outputs. The possible values are NONE, FIXED, VARIABLE_POSITIVE,
VARIABLE_CENTER, or DIRECT. The default value is NONE.
When set to NONE, a phase shift cannot be performed and a phase-shift value has no effect
on the DCM outputs. When set to FIXED, the DCM outputs are phase-shifted by a fixed
phase from the CLKIN. The phase-shift value is determined by the PHASE_SHIFT
attribute. If the CLKOUT_PHASE_SHIFT attribute is set to FIXED or NONE, then the
PSEN, PSINCDEC, and the PSCLK inputs must be tied to ground.
When set to VARIABLE_POSITIVE, the DCM outputs can be phase-shifted in variable
mode in the positive range with respect to CLKIN. When set to VARIABLE_CENTER, the
DCM outputs can be phase-shifted in variable mode, in the positive and negative range
with respect to CLKIN. If set to VARIABLE_POSITIVE or VARIABLE_CENTER, each
phase-shift increment (or decrement) will increase (or decrease) the phase shift by a period
of 1/256 x CLKIN period.
When set to DIRECT, the DCM output can be phase-shifted in variable mode in the
positive range with respect to CLKIN. Each phase-shift increment/decrement will
increase/decrease the phase shift by one DCM_TAP (see the Virtex-4 Data Sheet).
The starting phase in the VARIABLE_POSITIVE and VARIABLE_CENTER modes is
determined by the phase-shift value. The starting phase in the DIRECT mode is always
zero, regardless of the value specified by the PHASE_SHIFT attribute. Thus, the
PHASE_SHIFT attribute should be set to zero when DIRECT mode is used. A non-zero
phase-shift value for DIRECT mode can be loaded to the DCM using Dynamic
Reconfiguration Ports in the Virtex-4 Configuration Guide.
DCM_AUTOCALIBRATION Attribute
The autocalibration block protects the DCM from the effects of negative bias temperature
instability (NBTI). This attribute cannot be set to FALSE unless the user guarantees that
CLKIN and CLKFB (if external feedback is used) never stop. The macro can also be
disabled if the user can guarantee that DCM is held in reset when the clocks are stopped. If
this attribute is set to FALSE, the reset requirement is three clock cycles.
DCM_PERFORMANCE_MODE Attribute
The DCM_PERFORMANCE_MODE attribute allows the choice of optimizing the DCM
either for high frequency and low jitter or for low frequency and a wide phase-shift range.
The attribute values are MAX_SPEED and MAX_RANGE. The default value is
MAX_SPEED. When set to MAX_SPEED, the DCM is optimized to produce high
frequency clocks with low jitter. However, the phase-shift range is smaller than when
MAX_RANGE is selected. When set to MAX_RANGE, the DCM is optimized to produce
low frequency clocks with a wider phase-shift range. The DCM_PERFORMANCE_MODE
affects the following specifications: DCM input and output frequency range, phase-shift
range, output jitter, DCM_TAP, CLKIN_CLKFB_PHASE, CLKOUT_PHASE, and duty-
cycle precision. The Virtex-4 Data Sheet specifies these values.