M0216SD-162SDAR2-1 Datasheet by Newhaven Display Intl

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Newhaven Disglay Internationall Inc. www.newhavendisglay.com nhtech@newhavendisnlav.com nhsales@newhavendisnlav.com
M0216SD162SDAR2-1
VacuumFluorescentDisplayModule
RoHSCompliant
NewhavenDisplayInternational,Inc.
2511TechnologyDrive,Suite101
ElginIL,60124
Ph:8478448795Fax:8478448796
www.newhavendisplay.com
nhtech@newhavendisplay.com nhsales@newhavendisplay.com
NAL ._ .VFNE. N 592’ny . :SPW
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NAME
2.0 FEATURES
*Since a DC/DC converter is used, only +5Vdc power source is required to operate the module.
*5x8 dot matrix display, DC-DC/AC converter, and controller/driver circuitry.
*High quality display and luminance.
*ASCII and Japanese characters (CG-ROM font).
*The module can be configured for a Motorola M68-type parallel interface, an Intel I80-type parallel
interface, or synchronous serial ainterface.
This specification applies to VFD module (Model NO: M0216SD-162SDAR2-1) .
1.0 SCOPE
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Number ofcharacters (char x line) 16 x 2 Character configuration 5 x 8 dot matrix Character height (mm) 5.34 Character Width (mm) 2.10 Character pitch (mm) 3.30 Line pitch (mm) 6.16 Width 0.34 height 0.58 Width 0.44 height 0.68 Peak wavelength ofillumination Green (505 nm) x : 0.235. y : 0.405 min. 350 / 102 typ. 500 / 146
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3.0 SPECIFICATIONS
3.1 GENERAL SPECIFICATIONS
Number of characters (char x line) 16 x 2
Character configuration 5 x 8 dot matrix
Character height (mm) 5.34
Character width (mm) 2.10
Character pitch (mm) 3.30
Line pitch (mm) 6.16
width 0.34
Dot size (mm) height 0.58
width 0.44
Dot pitch (mm) height 0.68
Peak wavelength of illumination Green (505 nm) x = 0.235, y = 0.405
min. 350 / 102
Luminance (cd/m2 / fL) typ. 500 / 146
VALUE
ITEM
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3.2 MECHANICAL DRAWINGS
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l I ll Item Symbol Min. Max. Unit Comment Operating temperature Topr -40 +85 nC Storage temperature Tstg -50 +95 nC Operating humidity Hopr 20 85 %RH Without condensation Storage humidity Hstg 20 90 %RH Without condensation Total amplitude: 1.5mm Freq: 10 — 55 Hz sine wa Sweep time: 1 min/cycle Duration: 2 bra/axis (X.Y,Z) Dumtion: llms Waveform: half sine wave 3 times/axis (X.Y,Z.—X.—Y,-Z) Item Symbol Min. Max. Unit Supply voltage Vt-c -0. 3 6.5 V Input signal voltage VIN -0. 3 V(‘(-+0.3 V 5?"? N 59351“. . 0'???"
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3.3 SYSTEM BLOCK DIAGRAM
3.4 ENVIRONMENTAL SPECIFICATIONS
ItemSymbolMin.Max.UnitComment
Operating temperatureTopr-40 +85 oC
Storage temperatureTstg-50 +95 oC
Operating humidityHopr 20 85 %RHWithout condensation
Storage humidityHstg 20 90 %RHWithout condensation
Vibration -- -- 4 G
Total amplitude: 1.5mm
Freq: 10 - 55 Hz sine wave
Sweep time: 1 min./cycle
Duration: 2 hrs./axis (X,Y,Z)
Shock -- -- 40 G
Duration: 11ms
Waveform: half sine wave
3 times/axis (X,Y,Z,-X,-Y,-Z)
3.5 ABSOLUTE MAXIMUM SPECIFICATIONS
ItemSymbolMin.Max.Unit
Supply voltage VCC -0.3 6.5 V
Input signal voltage VIN -0.3 VCC+0.3 V
FLUORESCENT
DISPLAY
DOT MATRIX
CONTROLLER
VFD
AND DRIVER
GRID
DRIVER
VACUUM
DC-DC/A C
CONVERTER
NC_RST/_SI/SO
RS_STB
R/W_WR/
E_RD/_SCK
DB0-DB7
Vcc
GND
(IF NEEDED)
(SEE SECTION 2.0)
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High-level input volhage (see Note) (E‘RD/,SCK,RST/) Low-level input Voltage (see Note) (E‘RD/,SCK,RST/) High-level input volhage (see Note) (all inputs except E‘RD/,SCK,RST/) Low-level input Voltage (see Note) (all inputs except E‘RD/,SCK,RST/) High-level output volhage (Ion : -0.1mA) Low—level output voltage (10L : 0.1mA) Input current (see Note) I, -500 - l .0 uA (Sec Figures 1 and 2) Item Symbol Min. Max. Unit Vct- rise time tkvcy - 10 ms Vct- ot'ftjme to” 1 - ms Delay time aflcr power-up reset Imsrn 100 - us Delay time afler extcmal reset [Egg-[D 100 - us RST/ pulse width 10w thTL 500 - 11s Input signal fall time t, - 1 5 11s Input signal iise time tr - 1 5 11s g“. N 592’?!“ .J'f’ff"
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3.6 DC ELECTRICAL SPECIFICATIONS
Item Symbol Min. Typ. Max. Unit
Supply voltage VCC 4.5 5.0 5.5 V
- 170 220
Supply current ICC mA
High-level input voltage (see Note)
(E,RD/,SCK,RST/) VIH1 0.8*VCC -VCC V
Low-level input voltage (see Note)
(E,RD/,SCK,RST/) VIL1 0.0 -0.2*VCC V
High-level input voltage (see Note)
(all inputs except E,RD/,SCK,RST/) VIH2 0.7*VCC -VCC V
Low-level input voltage (see Note)
(all inputs except E,RD/,SCK,RST/) VIL2 0.0 -0.3*VCC V
High-level output voltage
(IOH = -0.1mA) VOH VCC-0.5 - - V
Low-level output voltage
(IOL = 0.1mA) VOL - - 0.5 V
Input current (see Note) II-500 -1.0 uA
Note: A 10K ohm pull-up resistor is provided on each input for TTL compatibility.
3.7 AC ELECTRICAL SPECIFICATIONS
3.7.1 RESET TIMING
(See Figures 1 and 2)
Item Symbol Min. Max. Unit
VCC rise time tRVCC -10 ms
VCC off time tOFF 1-ms
Delay time after power-up reset tIRSTD 100 -us
Delay time after external reset tERSTD 100 -us
RST/ pulse width low tRSTL 500 -ns
Input signal fall time tf-15 ns
Input signal rise time tr-15 ns
Note: All timing is specified using 20% and 80% of V CC as the reference points.
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(Sec Figures 3 and 4) Item Symbol Min. Max. Unit RS. R/W setup time L“ 20 - us RS‘ R/W hold time tA” 10 - us Input signal rise time tr - 1 5 us Input signal fall time t, - 15 us E pulse width high PWE” 230 - us E pulse width low PWEL 230 - us Write data setup time tm 80 - us Write data hold time tn” 10 - us E cycle time tCYCE 500 - us Read data delay time tDD - 160 us Read data hold time tom 5 - us ENE. N 552’?!“ A???“
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Vcc 0.2V
4.5V
tOFF
RS, STB
tIRSTD
tRVCC
Figure 1. Power-up Internal Reset Timing
RST/
tRSTL
RS, STB
tERSTD
tftr
Figure 2. External Reset Timing
3.7.2 MOTOROLA M68-TYPE PARALLEL INTERFACE TIMING
(See Figures 3 and 4)
Item Symbol Min. Max. Unit
RS, R/W setup time tAS 20 -ns
RS, R/W hold time tAH 10 -ns
Input signal rise time tr-15 ns
Input signal fall time tf-15 ns
E pulse width high PWEH 230 -ns
E pulse width low PWEL 230 -ns
Write data setup time tDS 80 -ns
Write data hold time tDH 10 -ns
E cycle time tCYCE 500 -ns
Read data delay time tDD -160 ns
Read data hold time tDHR 5-ns
Note: All timing is specified using 20% and 80% of V CC as the reference points.
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NNNNNNNNNNN
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R/W
E
DB0-DB7
RS
tAHtAS
PW EH
PW EL
tDS tDH
tCYCE
trtf
Figure 3. Motorola M68-Type Parallel Interface Write Cycle Timing
R/W
E
DB0-DB7
RS
tAHtAS
PW EH
PW EL
tDHR
tCYCE
trtf
tDD
Figure 4. Motorola M68-Type Parallel Interface Read Cycle Timing
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(See Figures 5 and 6) Item Symbol Min. Max. Unit RS setup time thg 10 - ns RS hold time [R51] 10 - ns Input signal fall time ti - 15 ns Input signal rise time tr - 1 5 ns WR/ pulse width low IWRL 30 - ns WR/ pulse width high t“ R” 100 - ns Write data setup time tog, 30 - ns Write data hold time to”. 10 - ns WR/ cycle time tcycwn 1 66 - ns RD/ cycle time 1(ch D 1 66 - ns RD/ pulse width low tum. 70 - ns RD/ pulse width high tum; 70 - us Read data delay time top. - 70 us Read data hold time tom, 5 50 ns Note: All timing is specified using 20% and 80% of V (‘r as the reference points. i e a l —. —. ‘— —\F—f;‘l\— l.— _. I: I I
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3.7.3 INTEL I80-TYPE PARALLEL INTERFACE TIMING
(See Figures 5 and 6)
Item Symbol Min. Max. Unit
RS setup time tRSS 10 -ns
RS hold time tRSH 10 -ns
Input signal fall time tf-15 ns
Input signal rise time tr-15 ns
WR/ pulse width low tWRL 30 -ns
WR/ pulse width high tWRH 100 -ns
Write data setup time tDSi 30 -ns
Write data hold time tDHi 10 -ns
WR/ cycle time tCYCWR 166 -ns
RD/ cycle time tCYCRD 166 -ns
RD/ pulse width low tRDL 70 -ns
RD/ pulse width high tRDH 70 -ns
Read data delay time tDDi -70 ns
Read data hold time tDHRi 5 50 ns
Note: All timing is specified using 20% and 80% of V CC as the reference points.
RS
WR/
DB0-DB7
tRSS tRSH
tDSi
tCYCWR
tDHi
tWRL
tWRH
tr
tf
Figure 5. Intel I80-Type Parallel Interface Write Cycle Timing
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(See Figures 7‘ 8 and 12) Item Symbol Mm. Max. Unit STB setup time ls‘rng 100 - us STB hold time tsm” 500 - us Input signal fall time t, - 15 us Input signal rise time tr - 1 5 us STB pulse width high t“ 51.3 500 - us SCK pulse width high {saw 200 - us SCK pulse width low 15cm. 200 - us SI data setup time Cos»- 100 - us SI data held time tum 100 - us SCK cycle time R‘yfgc}; 500 - us SCK wait time between bytes t“ MT 1 - us SO data delay time tum - 150 ns SO data held time [Dum- 5 - us
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RS
RD/
DB0-DB7
tRSS tftRSH
tr
tRDL
tRDH
tDHRi
tCYCRD
tDDi
Figure 6. Intel I80-Type Parallel Interface Read Cycle Timing
3.7.4 SYNCHRONOUS SERIAL INTERFACE TIMING
(See Figures 7, 8 and 12)
Item Symbol Min. Max. Unit
STB setup time tSTBS 100 -ns
STB hold time tSTBH 500 -ns
Input signal fall time tf-15 ns
Input signal rise time tr-15 ns
STB pulse width high tWSTB 500 -ns
SCK pulse width high tSCKH 200 -ns
SCK pulse width low tSCKL 200 -ns
SI data setup time tDSs 100 -ns
SI data hold time tDHs 100 -ns
SCK cycle time tCYCSCK 500 -ns
SCK wait time between bytes tWAIT 1-us
SO data delay time tDDs -150 ns
SO data hold time tDHRs 5-ns
Note: All timing is specified using 20% and 80% of V CC as the reference points.
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NAME
STB
SCK
SI/SO
tDSs
tDHs
tSCKL
tSCKH
tCYCSCK
tSTBS tSTBH
tWSTB
tr
tf
Figure 7. Synchronous Serial Interface Write Cycle Timing
STB
SCK
SI/SO
tDHRs
tSCKL
tSCKH
tCYCSCK
tSTBS tSTBH
tWSTB
tr
tf
tDDs
Figure 8. Synchronous Serial Interface Read Cycle Timing
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4.0 MODES OF OPERATION
The following modes of operation are selectable via jumpers (see section 8.0 Jumper Settings).
4.1 PARALLEL INTERFACE MODES
In the parallel interface mode, 8-bit instructions and data are sent between the host and the modules
using either 4-bit nibbles or 8-bit bytes. Nibbles are transmitted high nibble first on DB4-DB7 (DB0-
DB3 are ignored) whereas bytes are transmitted on DB0-DB7. The Register Select (RS) control signal
is used to identify DB0-DB7 as an instruction (low) or data (high).
4.1.1 MOTOROLA M68-TYPE MODE
This mode uses the Read/Write (R/W) and Enable (E) control signals to transfer information.
Instructions/data are written to the modules on the falling edge of E when R/W is low and are read from
the modules after the rising edge of E when R/W is high.
R/W
E
DB7 IB3IB7 IB7 IB3 BF='0' IB3 DB7 DB3
IB6 IB2 IB6 IB2 IB2IB6 DB6 DB2DB6
IB5 IB1 IB5 IB1 IB1IB5 DB5 DB1DB5
IB4 IB0 IB4 IB0 IB0IB4 DB4 DB0DB4
Write instruction Write instruction Read instruction Write data
RS
Figure 9. Typical 4-Bit Parallel Interface Sequence Using M68-Type Mode
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4.1.2 INTEL I80-TYPE MODE
This mode uses the Read (RD/) and Write (WR/) control signals to transfer information.
Instructions/data are written to the modules on the rising edge of WR/ and are read from the modules
after the falling edge of RD/.
WR/
RD/
DB7 IB7 IB7 BF='0' DB7
IB6 IB6 IB6 DB6DB6
IB0 IB0 IB0 DB0DB0
Write instruction Write instruction Read instruction Write data
RS
Figure 10. Typical 8-Bit Parallel Interface Sequence Using I80-Type Mode
4.2 SYNCHRONOUS SERIAL INTERFACE MODE
In the synchronous serial interface mode, instructions and data are sent between the host and the
modules using 8-bit bytes. Two bytes are required per read/write cycle and are transmitted MSB first.
The start byte contains 5 high bits, the Read/Write (R/W) control bit, the Register Select (RS) control
bit, and a low bit. The following byte contains the instruction/data bits. The R/W bit determines
whether the cycle is a read (high) or a write (low) cycle. The RS bit is used to identify the second byte
as an instruction (low) or data (high).
This mode uses the Strobe (STB) control signal, Serial Clock (SCK) input, and Serial I/O (SI/SO) line
to transfer information. In a write cycle, bits are clocked into the modules on the rising edge of SCK.
In a read cycle, bits in the start byte are clocked into the modules on the rising edge of SCK. After the
minimum wait time, each bit in the instruction/data byte can be read from the modules after each falling
edge of SCK. Each read/write cycle begins on the falling edge of STB and ends on the rising edge. To
be a valid read/write cycle, the STB must go high at the end of the cycle.
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T T HEW jVVVVMXIKXXXXXXXK _| I 2 a 55555 UWWM JVVVVVHKXXXXXXXXX _J ._ MNEWHQ’FR H???“
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STB
SCK
SI/SO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
B0B1B2B3B4B5B6B7'0'RSR/W'1''1''1''1''1'
Start byte Instruction / Data
Figure 11. Typical Synchronous Serial Interface Write Cycle
STB
SCK
SI/SO
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
B0B1B2B3B4B5B6'0'RSR/W'1''1''1''1''1'
Start byte Instruction / Data
tWAIT
B7
Figure 12. Typical Synchronous Serial Interface Read Cycle
4.3 RESET MODES
The modules are reset automatically at power-up by an internal R-C circuit. However, an external reset
mode can also be selected when using one of the parallel interface modes (this option is not available
when using the synchronous serial interface mode). This mode allows the modules to be reset by setting
the Reset (RST/) input low.
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5.0 CHARACTER FONT TABLES
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
CG
RAM
(8)
CG
RAM
(7)
CG
RAM
(6)
CG
RAM
(5)
CG
RAM
(4)
CG
RAM
(3)
CG
RAM
(2)
CG
RAM
(1)
CG
RAM
(8)
CG
RAM
(7)
CG
RAM
(6)
CG
RAM
(5)
CG
RAM
(4)
CG
RAM
(3)
CG
RAM
(2)
CG
RAM
(1)
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
UPPER
NIBBLE
LOWER
NIBBLE
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6.0 FUNCTIONAL DESCRIPTION
6.1 ADDRESS COUNTER (AC)
6.1.1 SINGLE LINE DISPLAYS
The AC stores the address of the data being written to and read from DDRAM or CGRAM. The AC
increments by 1 (overflows from 4FH to 00H) or decrements by 1 (underflows from 00H to 4FH) after
each DDRAM access. The AC increments by 1 (overflows from 3FH to 00H) or decrements by 1
(underflows from 00H to 3FH) after each CGRAM access. When addressing DDRAM, the value in
the AC also represents the cursor position.
6.1.2 MULTIPLE LINE DISPLAYS
The AC stores the address of the data being written to and read from DDRAM or CGRAM. The AC
increments by 1 (overflows from 27H to 40H and from 67H to 00H) or decrements by 1 (underflows
from 40H to 27H and from 00H to 67H) after each DDRAM access. The AC increments by 1
(overflows from 3FH to 00H) or decrements by 1 (underflows from 00H to 3FH) after each CGRAM
access. When addressing DDRAM, the value in the AC also represents the cursor position.
6.2 DISPLAY DATA RAM (DDRAM)
6.2.1 SINGLE LINE DISPLAYS
The DDRAM stores the character code of each character being displayed on the VFD. Valid
DDRAM addresses are 00H to 4FH. DDRAM not being used for display characters can be used as
general purpose RAM. The tables below show the relationship between the DDRAM address and the
character position on the VFD before and after a display shift (with the number of display lines set to 1).
6.2.2 MULTIPLE LINE DISPLAYS
The DDRAM stores the character code of each character being displayed on the VFD. Valid
DDRAM addresses are 00H to 27H and 40H to 67H. DDRAM not being used for display characters
can be used as general purpose RAM. The tables below show the relationship between the DDRAM
address and the character position on the VFD before and after a display shift (with the number of
display lines set to 2).
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00 01 02 03 04 05 06 07 ()8 ()9 0A 0B 00 GD 0E 0F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 01 02 03 04 05 ()6 ()7 ()8 ()9 0A 0B 00 GD 0E 0F 10 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 27 00 01 02 03 04 ()5 ()6 ()7 ()8 ()9 0A 0B 00 GD GE 67 4O 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E
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6.3 DISPLAY SHIFT DETAIL
Relationship before a display shift (non-shifted):
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
100 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
240 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F
Relationship after a display shift to the left:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
101 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
241 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50
Relationship after a display shift to the right:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
127 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
267 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E
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Instmction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Clcar display 0 0 0 0 0 0 0 0 1 Cursor home 0 0 0 0 0 0 0 1 x Entry mode set 0 0 0 0 0 0 0 I/D S Display on/offcontrol 0 0 0 0 0 0 1 D C B Cursor/display shift 0 0 0 0 0 1 S/C R/L x x Function set 0 0 0 0 1 DL N x BR] BRO CGRAM address set 0 0 0 1 CGRAM address DDRAM address set 0 0 1 DDRAM address Address counter read 0 1 BF:0 AC contents DDRAM or CGRAM write 1 0 Write data DDRAM or CGRAM read 1 1 Read data sl mum: mm DOCUMENT NOr
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6.4 CHARACTER GENERATOR RAM (CGRAM)
The CGRAM stores the pixel information (1 = pixel on, 0 = pixel off) for the eight user-
definable 5x8 characters. Valid CGRAM addresses are 00H to 3FH. CGRAM not being used to
define characters can be used as general purpose RAM (lower 5 bits only). Character codes 00H
to 07H (or 08H to 0FH) are assigned to the user-definable characters (see section 5.0 Character
Font Tables). The table below shows the relationship between the character codes, CGRAM
addresses, and CGRAM data for each user-definable character.
D7 D3D4D5D6 D1D2 D0 A3A4A5 A0A1A2 D3D4D5D6D7 D0D1D2
X0000 000 XXX
Character code CGRAM address CGRAM data
00 0000 0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
110
1 1 1
0 00
0 00
0 00 0
0 000
0 000
X0 0 0 0 0 0 1 0
11 11
1
11
1
0
0
0
000
1 0 00
1
1
1
1
0
0
0
0X
0
XX
0
0 0 00 0 0 00
0 0 00 0 00
01X0000 111 1 001 0 0
0
00
0
1
1
1
1
1 1
1 1
X XX0
0
0
0
1
1
1
1
0
0 00
0 00
0 00
0 00
(1)
CGRAM
(2)
CGRAM
(8)
CGRAM
11111
0
0
0
0100
1
1
0
0
111
1
1
1
1
1
10001
1
000
0
0
0
1
0
1
1
1
1
1
0
0 0 0
x = don't care
6.5 INSTRUCTIONS
Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Clear display 0000000001
Cursor home 000000001x
Entry mode set 0 0 0 0 0 0 0 1 I/D S
Display on/off control 0000001DC B
Cursor/display shift 000001S/C R/L x x
Function set 00001DL NxBR1 BR0
CGRAM address set 0001 CGRAM address
DDRAM address set 001 DDRAM address
Address counter read 0 1 BF=0 AC contents
DDRAM or CGRAM write 1 0 Write data
DDRAM or CGRAM read 1 1 Read data
x = don’t care
11
1
1 1
1 1
1 0
11 0
11
11 1
1 1 1 1
111
M0216SD-162SDAR2-1
RS R/W DB7 DB6 DBS DB4 DB3 DB2 DB1 DBO \OIMMOIMOIMMOIW RS R/W DB7 DB6 DBS DB4 DB3 DB2 DB1 DBO \OIMMOIMOIMOMIM RS R/W DB7 DB6 DBS DB4 DB3 DB2 DB1 DBO \0|o\0\0|0\0|0\1\1/D|s\
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6.5.1 CLEAR DISPLAY
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0000000001
This instruction clears the display (without affecting the contents of CGRAM) by performing the
following:
1) Fills all DDRAM locations with character code 20H (character code for a space).
2) Sets the AC to DDRAM address 00H (i.e. sets cursor position to 00H).
3) Returns the display to the non-shifted position.
4) Sets the I/D bit to 1.
6.5.2 CURSOR HOME
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
000000001x
x = don’t care
This instruction returns the cursor to the home position (without affecting the contents of DDRAM or
CGRAM) by performing the following:
1) Sets the AC to DDRAM address 00H (i.e. sets cursor position to 00H).
2) Returns the display to the non-shifted position.
6.5.3 ENTRY MODE SET
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00000001I/D S
This instruction selects whether the AC (cursor position) increments or decrements after each DDRAM
or CGRAM access and determines the direction the information on the display shifts after each
DDRAM write. The instruction also enables or disables display shifts after each DDRAM write
(information on the display does not shift after a DDRAM read or CGRAM access). DDRAM,
CGRAM, and AC contents are not affected by this instruction.
I/D = 0: The AC decrements after each DDRAM or CGRAM access. If S = 1, the information on
the display shifts to the right by one character position after each DDRAM write.
I/D = 1: The AC increments after each DDRAM or CGRAM access. If S = 1, the information on the
display shifts to the left by one character position after each DDRAM write.
S = 0: The display shift function is disabled.
S = 1: The display shift function is enabled.
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RS R/W DB7 DB6 DBS DB4 DB3 DB2 DB1 DBO \MO‘O‘OIO‘OII‘D‘CIB‘ RS R/W DB7 DB6 DBS DB4 DB3 DB2 DB1 DBO \0|o\0\0|0\1|S/C\R/L\x|x\ S/C M AC contents (cursor position) Information on the display 0 0 Decremcnts by one No change 0 1 Increments by one No change 1 0 Decremcnts by one Shifls one character position to the lefi 1 1 Increments by one Shifls one character position to the right
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6.5.4 DISPLAY ON/OFF CONTROL
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0000001DC B
This instruction selects whether the display and cursor are on or off and selects whether or not the
character at the current cursor position blinks. DDRAM, CGRAM, and AC contents are not affected
by this instruction.
D = 0: The display is off (display blank).
D = 1: The display is on (contents of DDRAM displayed).
C = 0: The cursor is off.
C = 1: The cursor is on (8th row of pixels).
B = 0: The blinking character function is disabled.
B = 1: The blinking character function is enabled (a character with all pixels on will alternate with the
character displayed at the current cursor position at about a 1Hz rate with a 50% duty cycle).
6.5.5 CURSOR/DISPLAY SHIFT
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
000001S/C R/L x x
x = don’t care
This instruction increments or decrements the AC (cursor position) and shifts the information on the
display one character position to the left or right without accessing DDRAM or CGRAM. DDRAM
and CGRAM contents are not affected by this instruction. If the AC was addressing CGRAM prior to
this instruction, the AC will be addressing DDRAM after this instruction. However, if the AC was
addressing DDRAM prior to this instruction, the AC will still be addressing DDRAM after this
instruction.
S/C R/L AC contents (cursor position) Information on the display
0 0 Decrements by one No change
0 1 Increments by one No change
1 0 Decrements by one Shifts one character position to the left
1 1 Increments by one Shifts one character position to the right
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RS R/W DB7 DB6 D35 D34 D33 DB2 DB1 DBO ‘OIO‘O‘OII‘DLIN‘X‘BRIIBRO‘ RS R/W DB7 DB6 D35 D34 D33 DB2 D31 D30 \ 0 | o \ 0 \ 1 | CGRAMaddrcss RS R/W DB7 DB6 D35 D34 D33 D32 DB1 D30 \ 0 | o \ 1 \ DDRAMaddrcss
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6.5.6 FUNCTION SET
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00001DL NxBR1 BR0
x = don’t care
This instruction sets the width of the data bus for the parallel interface modes, the number of display
lines, and the luminance level (brightness) of the VFD. It must be the first command sent after any reset.
DDRAM, CGRAM, and AC contents are not affected by this instruction.
DL = 0: Sets the data bus width for the parallel interface modes to 4-bit (DB7-DB4).
DL = 1: Sets the data bus width for the parallel interface modes to 8-bit (DB7-DB0).
N = 0: Sets the number of display lines to 1 (this setting is not recommended for multiple line
displays).
N = 1: Sets the number of display lines to 2 (this setting is not recommended for single line displays).
BR1,BR0 = 0,0: Sets the luminance level to 100%.
0,1: Sets the luminance level to 75% .
1,0: Sets the luminance level to 50%.
1,1: Sets the luminance level to 25%.
6.5.7 CGRAM ADDRESS SET
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 1 CGRAM address
This instruction places the 6-bit CGRAM address specified by DB5-DB0 into the AC (cursor position).
Subsequent data writes (reads) will be to (from) CGRAM. DDRAM and CGRAM contents are not
affected by this instruction.
6.5.8 DDRAM ADDRESS SET
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
001 DDRAM address
This instruction places the 7-bit DDRAM address specified by DB6-DB0 into the AC (cursor position).
Subsequent data writes (reads) will be to (from) DDRAM. DDRAM and CGRAM contents are not
affected by this instruction.
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RS R/W DB7 DB6 DBS DB4 DB3 DB2 DB1 DBO I 0 I 1 IBF:0I AC contents RS R/W DB7 DB6 DBS DB4 DB3 DB2 DB1 DBO I 1 I 0 I Writcdata RS R/W DB7 DB6 DBS DB4 DB3 DB2 DB1 DBO I 1 I 1 I Rcaddata
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6.5.9 ADDRESS COUNTER READ
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 1 BF=0 AC contents
This instruction reads the current 7-bit address from the AC on DB6-DB0 and the busy flag (BF) bit
(always 0) on DB7. DDRAM, CGRAM, and AC contents are not affected by this instruction. Because
the BF is always 0, the host never has to read the BF bit to determine if the modules are busy before
sending data or instructions. Therefore, data and instructions can be sent to the modules continuously
according to the E, WR/, and SCK cycle times specified in section 3.7 AC Timing Specifications. Due
to this feature, the execution times for each instruction are not specified.
6.5.10 DDRAM OR CGRAM WRITE
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 0 Write data
This instruction writes the 8-bit data byte on DB7-DB0 into the DDRAM or CGRAM location
addressed by the AC. The most recent DDRAM or CGRAM Address Set instruction determines
whether the write is to DDRAM or CGRAM. This instruction also increments or decrements the AC
and shifts the display according to the I/D and S bits set by the Entry Mode Set instruction.
6.5.11 DDRAM OR CGRAM READ
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 1 Read data
This instruction reads the 8-bit data byte from the DDRAM or CGRAM location addressed by the AC
on DB7-DB0. The most recent DDRAM or CGRAM Address Set instruction determines whether the
read is from DDRAM or CGRAM. This instruction also increments or decrements the AC and shifts
the display according to the I/D and S bits set by the Entry Mode Set instruction. Before sending this
instruction, a DDRAM or CGRAM Address Set instruction should be executed to set the AC to the
desired DDRAM or CGRAM address to be read.
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6.6 RESET CONDITIONS
After either a power-up reset or an external reset, the modules initialize to the following conditions:
1) All DDRAM locations are set to 20H (character code for a space).
2) The AC is set to DDRAM address 00H (i.e. sets cursor position to 00H).
3) The relationship between DDRAM addresses and character positions on t he VFD is set to the non-
shifted position.
4) Entry Mode Set instruction bits:
I/D = 1: The AC increments after each DDRAM or CGRAM access.
S = 0: The display shift function is disabled.
5) Display On/Off Control instruction bits:
D = 0: The display is off (display blank).
C = 0: The cursor is off.
B = 0: The blinking character function is disabled.
6) Function Set instruction bits:
DL = 1: Sets the data bus width for the parallel interface modes to 8-bit (DB7-DB0).
N = 1(0): Number of display lines set to 2 for multiple line displays (number of display lines
set to 1 for single line displays).
BR1,BR0 = 0,0: Sets the luminance level to 100%.
Note that the function set command must be the first instruction sent to the module after any reset.
6.6.1 INITIALIZATION
The modules can be initialized by using instructions if the modules are not reset according to the reset
timing detailed in Section 3.7.1 (Reset Timing). After any reset, the function set command must be the
first instruction sent to the module.
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NAL ._ .O-FNE. N t‘t‘é’fli . JSPLAY
7.0 CONNECTOR INTERFACE
Pin
NO. Serial Paralle
(Intel)
Parallel
(Motorola)
Pin
NO. Serial Paralle
(Intel)
Parallel
(Motorola)
1 GND GND GND 2 VCC VCC VCC
3 SI/SO NC or RST/ NC or RST/ 4 STB RS RS
5 NC WR/ R/W 6 SCK RD/ E
7 NC DB0 DB0 8 NC DB1 DB1
9 NC DB2 DB2 10 NC DB3 DB3
11 NC DB4 DB4 12 NC DB5 DB5
13 NC DB6 DB6 14 NC DB7 DB7
8.0 Soldering Land Function
Some soldering lands are prepared on the tear side of PCB, to set operating mond of the
Display module. A soldering iron is required to short soldering lands.
1. parallel data transfer mode is selected
J6 J7 J2 J3 FUNCTION
Open Short * Open i80 type
Short Open * Open M68 type MPU type Selection
Open Open Pin #3: No connection
Short Open Pin #3: /RESET
External Reset
Section
2. serial data or parallel data transfer mode set
J5 J3 J2 FUNCTION
Open Open Parallel data Transfer mode
Short Short Open Serial data Transfer mode
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