XC6129 Series Datasheet by Torex Semiconductor Ltd

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Voltage Detector with Delay Time Adjustable
XC6129 Series
GENERAL DESCRIPTION
XC6129 series is an ultra small highly accurate voltage detector with external capacitor type delay function.
The device includes a highly accurate reference voltage source, manufactured using CMOS process and laser trimming
technology, it maintains low power consumption and high accuracy. The device includes the built-in delay circuit. A release
delay time or detect delay time can be set freely by connecting an external delay capacitor to Cd pin.
There are two kinds of the output configuration for the XC6129 such as CMOS or N-channel open drain. The series has a
function to prevent an indefinite operation. Therefore, when the input pin voltage is under minimum operating voltage,
the function controls an output pin voltage in the indefinite operation less than 0.4V (MAX.). Also, the series allows a choice of
an output logic when detection; therefore, it is suitable for various electric devices using Microcontrollers.
Ultra small package USPN-4,USPQ-4B05 and SSOT-24 (standard) are ideally suited for small design of portable devices
and high densely mounting applications.
FEATURES
High Accuracy :±0.8 (Ta=25)
Temperature Characteristic
:±50ppm/ (TYP.)
Hysteresis Width :
V
DF
x5% (TYP.)
Low Power Consumption
:0.42μA TYP. (at Detect, VDF=2.7V)
0.58μA TYP. (at Release, VDF=2.7V)
Detect Voltage Options :1.5V5.5V (0.1V increments)
Operating Voltage Range
:1.3V6.0V
Output Configuration :CMOS or N-channel Open Drain
Output Logic :Active High or Active Low
Release Delay Time :13.9ms (Cd=0.01μF, RP=2M)
Detect Delay Time :17.9ms (Cd=0.01μF, Rn=2M )
Manual Reset Input :When Cd pin is “L” level, detect state
Operating Ambient Temperature
:-40 +85
Packages :USPN-4, SSOT-24, USPQ-4B05
Environmentally Friendly
:EU RoHS Compliant, Pb Free
ETR0222-004
A
PPLICATIONS
Microprocessor
Logic circuit reset circuitry
Battery check
Charge voltage monitors
Memory battery back-up switch circuits
System power on reset
Power failure detection circuits
Delay circuit
TYPICAL APPLICATION CIRCUIT TYPICAL PERFORMANCE
CHARACTERISTICS
XC6129
100
120
140
160
180
200
-50 -25 0 25 50 75 100
Ambient Temperature : Ta ()
Release Delay Time : t
DR
(ms)
V
IN
=V
DF
×0.9V→ V
DF
×1.1V
Cd=0.1μF (t
DR
=139ms)
2/32
XC6129 Series
BLOCK DIAGRAM
1) XC6129C Series (Type A/B/C/D/E/F)
2) XC6129C Series (Type G/J/L)
RESETB
Vref
V
IN
Cd/ MRB
V
SS
M1
M2
M3
M4
Comparator
R
1
R
2
Rp
Rn
DELAY/MR
CONTROL
BLOCK
RESET
Vref
V
IN
Cd/ MRB
V
SS
M1
M2
M3
M4
Comparator
R
1
R
2
Rp
Rn
DELAY/MR
CONTROL
BLOCK
* Diodes inside the circuits are ESD protection diodes and parasitic diodes.
M w: J?“ g H: La
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XC6129
Series
BLOCK DIAGRAM
* Diodes inside the circuits are ESD protection diodes and parasitic diodes.
3) XC6129N Series (Type A/C/E)
4) XC6129N Series (Type G/J/L)
RESETB
Vref
VIN
Cd/ MRB
VSS
M1
M2
M3
Comparator
R
1
R
2
Rp
Rn
DELAY/MR
CONTROL
BLOCK
RESET
Vref
V
IN
Cd/ MRB
V
SS
M1
M2
M3
Comparator
R
1
R
2
Rp
Rn
DELAY/MR
CONTROL
BLOCK
¥ x061291290®® ®
4/32
XC6129 Series
PRODUCT CLASSIFICATION
DESIGNATOR ITEM SYMBOL DESCRIPTION
Output Configuration C CMOS output
N Nch open drain output
②③ Detect Voltage 15~55 e.g. 1.8V =1, =8
Type
A
Refer to Selection Guide
B
C
D
E
F
G
J
L
⑤⑥-⑦ (*1) Packages (Order Unit)
NR-G SSOT-24 (3,000pcs/Reel)
7R-G USPN-4 (5,000pcs/Reel)
9R-G USPQ-4B05 (5,000pcs/Reel)
(*1) The “-G” suffix denotes Halogen and Antimony free as well as being fully EU RoHS compliant.
TYPE RESETB/RESET
OUTPUT
HYSTERESIS
WIDTH
RELEASE
DELAY
DETECT
DELAY
Undefined Operation
Protect
A
Reset Active Low
5% (TYP.)
Yes No No
B Yes (*2)
C No Yes No
D Yes (*2)
E Yes Yes No
F Yes (*2)
G
Reset Active High
Yes No
No
J No Yes
L Yes Yes
(*2) Only supported with CMOS output.
Ordering Information
XC6129①②③④⑤⑥-⑦(*1)
Selection Guide
|:|C| |:||:| TOIi’EX
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XC6129
Series
PIN CONFIGURATION
PIN ASSIGNMENT
PIN NUMBER PIN NAME FUNCTIONS
SSOT-24 USPN-4 USPQ-4B05
1 4 4 VIN Power Input
2 3 3 VSS Ground
3 2 2 Cd/MRB Adjustable Pin for DelayTime
/Manual Reset
4 1 1 RESETB Reset Output (Active Low) (*1)
RESET Reset Output (Active High) (*2)
(*1) Type AF (Refer to the in Ordering Information table)
(*2) Type GM (Refer to the in Ordering Information table)
SSOT-24
(TOP VIEW)
RESETB
RESET
12
34
V
IN
V
SS
Cd/MRB
23
1
4
USPN-4
(BOTTOM VIEW)
V
IN
V
SS
Cd/MRB
RESETB
RESET
USPQ-4B05
(BOTTOM VIEW)
2
3
1
4
V
IN
V
SS
RESETB
RESET
Cd/MRB
*The dissipation pad for the USPQ-4B05 packages should be solder-plated in reference mount pattern and metal masking so as to enhance
mounting strength and heat release. If the pad needs to be connected to other pins, it should be connected to the VSS (No. 3) pin.
6/32
XC6129 Series
FUNCTION
PIN NAME SIGNAL STATUS
Cd/MRB
L Forced Reset
H Release
OPEN Normal Operation
Refer to the table below.
1) Output Logic: Active Low
Function
VIN VCd//MRB Transition of VRESETB Condition
VINVDF+VHYS VCd/MRBVMRL Reset (Low Level) (*1)
VCd/MRBVMRH Release (High Level) (*2)
VINVDF VCd/MRBVMRL Reset (Low Level) (*1)
VCd/MRBVMRH Undefined (*3)
2) Output Logic: Active High
Function
VIN VCd/MRB Transition of VRESET Condition
VINVDF+VHYS VCd/MRBVMRL Reset (High Level) (*2)
VCd/MRBVMRH Release (Low Level) (*1)
VINVDF VCd/MRBVMRL Reset (High Level) (*2)
VCd/MRBVMRH Undefined (*3)
(* 1) CMOS output: VIN × 0.1 or less, N-ch open drain output, pull-up voltage × 0.1 or less.
(* 2) CMOS output: VIN × 0.9 or higher, N-ch open drain output, pull-up voltage × 0.9 or higher.
(* 3) Refer to the OPERATING DESCRIPTION <Manual reset function> below.
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XC6129
Series
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATINGS UNITS
Input Voltage VIN -0.3+6.5 V
Output Current XC6129C (*1) IRBOUT
IROUT
±50 mA
XC6129N (*2) 50
Output Voltage XC6129C (*1) VRESETB
VRESET
VSS-0.3VIN+0.3 or +6.5 (*3) V
XC6129N (*2) VSS-0.3+6.5
Cd/MRB Pin Voltage VCd/MRB VSS-0.3VIN+0.3 V
Cd/MRB Pin Current ICd/MRB ±5 mA
Power Dissipation
SSOT-24
Pd
150
mW USPN-4 100
USPQ-4B05 550
Operating Ambient Temperature Topr -40+85
Storage Temperature Tstg -55+125
* All voltages are described based on the VSS.
(*1) CMOS Output
(*2) N-ch Open Drain Output
(*3) The maximum value should be either VIN+0.3 or +6.5 in the lowest.
Ta= 25
V» a; up VDFXMV 6.0V
8/32
XC6129 Series
ELECTRICAL CHARACTERISTICS
XC6129xxxA~XC6129xxxF Series (Output Logic: Active Low)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNITS
CIRCUIT
Detect Voltage VDF VDF(T) (*1)=1.5V5.5V
V
DF(T)
×0.992
VDF(T)
V
DF(T)
×1.008
V
E-1(*2)
Temperature
Characteristics
V
DF
/
(Topr
V
DF
)
-40Topr85 - ±50 - ppm/
Hysteresis Width VHYS
-
VDF×0.03 VDF×0.05 VDF×0.07 V
Supply Current 1 ISS1 VIN= VDF×0.9V (Detect) E-2 (*2)
μA
Supply Current 2 ISS2 VIN=VDF×1.1V
(Release)
(Type:A,C,E) E-3 (*2)
(Type:B,D,F) E-31 (*2)
Operating Voltage VIN - 1.3 - 6.0 V -
Output Current
IRBOUT1
VIN=1.3V, VRESETB=0.5V (N-ch) 1.7 3.0 -
mA
VIN=2.0V(*3), VRESETB=0.5V (N-ch) 5.2 6.7 -
VIN=3.0V(*4), VRESETB=0.5V (N-ch) 8.6 10.2 -
VIN=4.0V(*5), VRESETB=0.5V (N-ch) 10.6 12.3 -
VIN=5.0V(*6), VRESETB=0.5V (N-ch) 11.7 13.5 -
IRBOUT2 (*7)
VIN=2.0V(*8), VRESETB=VIN-0.5V (P-ch) - -1.9 -0.9
VIN=3.0V(*9), VRESETB=VIN-0.5V (P-ch) - -3.1 -2.1
VIN=4.0V(*10), VRESETB=VIN-0.5V (P-ch) - -4.0 -3.0
VIN=5.0V(*11), VRESETB=VIN-0.5V (P-ch) - -4.7 -3.7
VIN=6.0V, VRESETB=VIN-0.5V (P-ch) - -5.2 -4.2
Leakage
Current
CMOS Output
(P-ch) ILEAK
VIN=VDF×0.9V, VRESETB=0V - -0.01 -
μA
N-ch Open
Drain Output VIN=6.0V, VRESETB=6.0V - 0.01 0.1
Delay Resistance (*12)
Rp VIN=6.0V, VCd/MRB =0V
(Type: A, B, E, F) 1.8 2.0 2.15 M
Rn VIN=VCd/MRB=VDF×0.9V
(Type: C, D, E, F)
Undefined Operation (*13) VUNS VIN<1.3V - - 0.4 V
Release Delay Time tDR0 VIN=VDF×0.9VVDF×1.1V (*14)
Cd: OPEN - 0.05 - ms
Detect Delay Time tDF0 VIN=VDF×1.1VVDF×0.9V (*15)
Cd: OPEN - 0.13 -
ms
Cd Threshold Voltage VTCD
V
IN
=V
DF
×1.1V
6.0V (Release)
VIN×0.44 VIN×0.50 VIN×0.56 V
VIN=VDF×0.9V (Detect)
MRB Low Level Voltage VMRL VIN=VDF×1.1V6.0V 0
-
V
IN×0.17 V
MRB High Level Voltage VMRH VIN=VDF×1.1V6.0V VIN×0.56
-
VIN V
Minimum MRB Pulse Width tMRB VIN=VDF×1.1V
VCd/MRB =VIN0VVIN 5.0 - - μs
Ta= 25
(*1) VDF(T): Nominal detect voltage
(*2) For the detail value, please refer to “Voltage Table”.
(*3) For VDF(T)2.0V only
(*4) For VDF(T)3.0V only
(*5) For VDF(T)4.0V only
(*6) For VDF(T)5.0V only
(*7) For XC6129C (CMOS output) only
(*8) For VDF(T)1.8V only
(*9) For VDF(T)2.7V only
(*10) For VDF(T)3.7V only
(*11) For VDF(T)4.6V only
(*12) Resistance is calculated from voltage applied to Cd/MRB pin and current.
(*13) Types B/D/F of XC6129C series only.
(*14) Time from VIN=VDF + VHYS until VRESETB=VDF × 1.1 × 0.9 when VIN rises. (CMOS output)
Time from VIN=VDF + VHYS until VRESETB=Pull-up voltage × 0.9 when VIN rises. (N-ch open drain output)
(*15) Time from VIN=VDF until VRESETB=VDF × 0.9 × 0.1 when VIN drops. (CMOS output)
Time from VIN=VDF until VRESETB=Pull-up voltage × 0.1 when VIN drops. (N-ch open drain output)
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XC6129
Series
ELECTRICAL CHARACTERISTICS (Continued)
XC6129xxxG~XC6129xxxL Series (Output Logic: Active High)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNITS CIRCUIT
Detect Voltage VDF VDF(T) (*1)=1.5V5.5V
V
DF(T)
×0.992
VDF(T)
V
DF(T)
×1.008
V
E-1 (*2)
Temperature
Characteristics
V
DF
/
(Topr
V
DF
)
-40Topr85 - ±50 - ppm/
Hysteresis Width VHYS
- V
DF
×0.03 V
DF
×0.05 V
DF
×0.07
V
Supply Current 1 ISS1 VIN=VDF×0.9V (Detect) E-2 (*2) μA
Supply Current 2 ISS2 VIN= VDF×1.1V (Release) E-3 (*2)
Operating Voltage VIN
-
1.3 - 6.0 V -
Output Current
IROUT1
VIN=2.0V(*3), VRESET=0.5V (N-ch) 5.2 6.7 -
mA
VIN=3.0V(*4), VRESET=0.5V (N-ch) 8.6 10.2 -
VIN=4.0V(*5), VRESET=0.5V (N-ch) 10.6 12.3 -
VIN=5.0V(*6), VRESET=0.5V (N-ch) 11.7 13.5 -
VIN=6.0V, VRESET=0.5V (N-ch) 12.4 14.3 -
IROUT2 (*7)
VIN=1.3V, VRESET=VIN-0.5V (P-ch) - -0.9 -0.1
VIN=2.0V(*8), VRESET=VIN-0.5V (P-ch) - -1.9 -0.9
VIN=3.0V(*9), VRESET=VIN-0.5V (P-ch) - -3.1 -2.1
VIN=4.0V(*10), VRESET=VIN-0.5V (P-ch) - -4.0 -3.0
VIN=5.0V(*11), VRESET=VIN-0.5V (P-ch) - -4.7 -3.7
Leakage
Current
CMOS Output
(P-ch)
ILEAK
VIN=6.0V, VRESET=0V - -0.01 -
μA
N-ch Open
Drain Output VIN=VDF×0.9V, VRESET=6.0V - 0.01 0.1
Delay Resistance (*12)
Rp VIN=6.0V, VCd/MRB=0V
(Type: G, L) 1.8 2.0 2.15 M
Rn VIN= VCd/MRB=VDF×0.9V
(Type: J,L)
Release Delay Time tDR0 VIN=VDF×0.9VVDF×1.1V (*13)
Cd: OPEN - 0.05 - ms
Detect Delay Time tDF0 VIN=VDF×1.1VVDF×0.9V (*14)
Cd: OPEN - 0.13 - ms
Cd Threshold Voltage VTCD
V
IN
=V
DF
×1.1V
6.0V (Release)
VIN×0.44 VIN×0.50 VIN×0.56 V
VIN=VDF×0.9V (Detect)
MRB Low Level Voltage VMRL V
IN=VDF×1.1V6.0V 0 - VIN×0.17 V
MRB High Level Voltage VMRH V
IN=VDF×1.1V6.0V VIN×0.56 - VIN V
Minimum MRB Pulse Width tMRB VIN=VDF×1.1V
VCd/MRB=VIN0VVIN 5.0 - - μs
Ta= 25
(*1) VDF(T): Nominal detect voltage
(*2) For the detail value, please refer to “Voltage Table”.
(*3) For VDF(T)1.8V only
(*4) For VDF(T)2.7V only
(*5) For VDF(T)3.7V only
(*6) For VDF(T)4.6V only
(*7) For XC6129C (CMOS output) only
(*8) For VDF(T)2.0V only
(*9) For VDF(T)3.0V only
(*10) For VDF(T)4.0V only
(*11) For VDF(T)5.0V only
(*12) Resistance is calculated from voltage applied to Cd/MRB pin and current.
(*13) Time from VIN=VDF + VHYS until VRESETB=VDF × 1.1 × 0.1 when VIN rises. (CMOS output)
Time from VIN=VDF + VHYS until VRESETB=Pull-up voltage × 0.1 when VIN rises. (N-ch open drain output)
(*14) Time from VIN=VDF until VRESETB=VDF × 0.9 × 0.9 when VIN drops. (CMOS output)
Time from VIN=VDF until VRESETB=Pull-up voltage × 0.9 when VIN drops. (N-ch open drain output)
10/32
XC6129 Series
ELECTRICAL CHARACTERISTICS (Continued)
NOMINAL
DETECT
VOLTAGE
E-1 E-2 E-3 E-31
DETECT VOLTAGE (V) Supply Current1
(μA)
Supply Current2
(μA)
VDF(T)
(V)
VDF ISS1 ISS2
MIN. MAX. MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX.
1.5 1.4880 1.5120 - 0.38 1.11 - 0.47 1.39 - 0.63 1.67
1.6 1.5872 1.6128
- 0.42 1.16 - 0.58 1.60 - 0.74 1.88
1.7 1.6864 1.7136
1.8 1.7856 1.8144
1.9 1.8848 1.9152
2.0 1.9840 2.0160
2.1 2.0832 2.1168
2.2 2.1824 2.2176
2.3 2.2816 2.3184
2.4 2.3808 2.4192
2.5 2.4800 2.5200
2.6 2.5792 2.6208
2.7 2.6784 2.7216
2.8 2.7776 2.8224
- 0.47 1.31 - 0.71 1.90 - 0.87 2.18
2.9 2.8768 2.9232
3.0 2.9760 3.0240
3.1 3.0752 3.1248
3.2 3.1744 3.2256
3.3 3.2736 3.3264
3.4 3.3728 3.4272
3.5 3.4720 3.5280
3.6 3.5712 3.6288
3.7 3.6704 3.7296
3.8 3.7696 3.8304
3.9 3.8688 3.9312
4.0 3.9680 4.0320
4.1 4.0672 4.1328
4.2 4.1664 4.2336
- 0.52 1.41 - 0.83 2.17 - 0.99 2.45
4.3 4.2656 4.3344
4.4 4.3648 4.4352
4.5 4.4640 4.5360
4.6 4.5632 4.6368
4.7 4.6624 4.7376
4.8 4.7616 4.8384
4.9 4.8608 4.9392
5.0 4.9600 5.0400
5.1 5.0592 5.1408
5.2 5.1584 5.2416
5.3 5.2576 5.3424
5.4 5.3568 5.4432
5.5 5.4560 5.5440
Voltage Table Ta= 25
loud? (Unused my the CMOS anew products] RESETE RESET VIN (WW5 RESETE ,1 RESET Vss VIN 7 RESETB 7g Cd/MRB RESET 6 VlN RESETB Cd/MRB RESET a Vss TOIi’EX
11/32
XC6129
Series
TEST CIRCUITS
CIRCUIT
CIRCUIT
CIRCUIT
CIRCUIT
look {2 (mm «w m cm): mm madman) ® Cd/MRE 3,5555? 100m (Unuizd (arm: was mam mums) RESETE CWRE RESET mum Vw {Unused «mm CMOS mum umducts) RESETE Cd/MRB RESET Vss VIN RESETE
12/32
XC6129 Series
TEST CIRCUITS (Continued)
CIRCUIT
CIRCUIT
CIRCUIT
CIRCUIT
(3) (7; LE?) (3) (3) (T; 4‘, (6) (2) TOIi’EX
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XC6129
Series
OPERATIONAL DESCRIPTION
Fig. 1: Typical circuit (Active Low product)
Fig. 2: Timing chart of Fig. 1
(1) In the initial state, a voltage sufficiently high in relation to the release voltage is applied to the VIN power input pin, and the
Cd/MRB delay capacitance pin is charged to the power input pin voltage.
The power input pin voltage starts to drop, and during the interval until it reaches the detect voltage (VIN>VDF), the output pin
voltage VRESETB is at High level.
(2) The power input pin voltage continues to drop, and when it reaches the detect voltage (VIN=VDF), the Nch transistor for delay
capacitance discharge turns ON and discharge of the delay capacitance starts.
When the delay capacitance pin drops below the delay capacitance pin threshold voltage, VRESETB changes to Low level.
The time from VIN=VDF until VRESETB changes to Low level is the detect delay tDF (the detect time when the delay capacitance
pin is open is tDF0).
Fig. 1 shows a typical circuit Fig. 2 shows the timing chart of Fig. 1.
* The XC6129N series
(N-ch open drain output)
requires a resistor to pull
up the output.
Power input voltage: VIN
Release voltage: VDF + VHYS
Detect voltage: VDF
Minimum operating voltage (1.3V)
Delay capacitance pin voltage: VCd/MRB
Delay capacitance pin threshold voltage: V
TCD
Output pin voltage: VRESETB
RESETB
Vref
V
IN
Cd/ MRB
V
SS
M1
M2
M3
M4
Comparator
R
1
R
2
Rp
Rn
DELAY/MR
CONTROL
BLOCK
V
DD
RESET
SW
Cd
14/32
XC6129 Series
OPERATIONAL DESCRIPTION (Continued)
(3) The power input pin voltage drops further, and during the interval when it is below the detect voltage VDF and higher than 1.3V,
the delay capacitance pin is discharged to ground level and the output pin voltage VRESETB maintains Low level.
(4) During the interval in which the power input pin voltage drops below 1.3V and then rises back to 1.3V or higher, the output pin
voltage VRESETB may not be able to maintain Low level. Operation during this interval is called “unstable operation”, and the
voltage that appears in VRESETB is called the “unstable operation voltage VUNS”.
(5) The power input pin voltage rises, and during the interval that it is higher than 1.3V until it reaches the release voltage
(1.3VVIN<VDF+VHYS), the output pin voltage VRESETB maintains Low level.
(6) The power input pin voltage continues to rise, and when it reaches the release voltage (VDF+VHYS), the Nch transistor for delay
capacitance discharge turns OFF and charging of the delay capacitance pin through delay resistor Rp starts.
(7) During the interval that the power input pin voltage continues to maintain a voltage higher than the release voltage, the delay
capacitance pin is charged up to the power input pin voltage.
When the delay capacitance pin voltage reaches VTCD, the output pin voltage VRESETB changes to High level.
The time from VIN=VDF+VHYS until VRESETB changes to High level is the release delay time tDR (the release time when the delay
capacitance pin is open is tDR0).
(8) During the time that the power input pin voltage is higher than the detect voltage (VIN>VDF), the output pin voltage VRESETB
maintains High level.
The above operational explanation is for detection using Active Low products.
For Active High products, reverse the logic of VRESETB.
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XC6129
Series
OPERATIONAL DESCRIPTION (Continued)
<Release delay time / detect delay time>
The release delay time and detect delay time are determined by the delay resistance (Rp and Rn) and the delay capacitance (Cd).
The delay resistance is set to 2M (TYP.) internally in the circuit, and thus the delay time can be changed using the delay
capacitance.
You can select a product type that has or does not have the release delay time function and the detect delay time function. (Refer
to the Selection Guide.)
The release delay tDR is calculated using equation (1).
tDR=Rp×Cd×{-ln(1-VTCD/VIN)}+tDR0 …(1) * ln is the natural logarithm.
Rn : Delay resistance 2.0M (TYP.)
V
TCD : Delay capacitance pin threshold voltage VIN/2 (TYP.)
When tDR0 can be neglected, this can be calculated in a simple manner using equation (2).
t
DR=Rp×Cd×[-ln{1-(VIN/2)/VIN}]=Rp×Cd×0.693 …(2)
Example: When the delay capacitance Cd is 0.68μF, the release delay time tDR is 2.0×106×0.68×10-6×0.693=942(ms).
The detect delay tDF is calculated using equation (3).
t
DF=Rn×Cd×-ln(VTCD/VIN1)}+tDF0 …(3) * ln is the natural logarithm.
Rn: Delay resistance 2.0M (TYP.)
V
TCD: Delay capacitance pin threshold voltage VIN2/2 (TYP.) *VIN2 is the power input pin voltage at detection.
V
IN1: Power input pin voltage at release
When VIN=VDF×1.1VVDF×0.9V and tDF0 can be neglected, this can be calculated in a simple manner using equation (4).
t
DF=Rn×Cd×{-ln(VIN2/2)/VIN1}=Rn×Cd×[-ln{(VDF×0.9×0.5)/(VDF×1.1)}]=Rn×Cd×0.894 …(4)
For details of the detect delay time of equation (4), refer to Fig. 3.
Example: When the delay capacitance Cd is 0.68μF at V
IN
=V
DF
×1.1VV
DF
×0.9V, the detect delay time t
DF
is 2.0×10
6
×0.68×10
-6
×0.894=1216(ms).
Fig. 3: Detect delay time of equation (4) (timing chart)
Delay time table
Delay capacitance Cd
(μF)
Release delay time tDR (ms) (*1) Detect delay time tDF (ms) (*1)
TYP. MIN.toMAX. (*2) TYP. MIN.toMAX. (*2)
0.01 13.9 10.4 to 17.7 17.9 12.7 to 22.0
0.022 30.5 22.9 to 38.9 39.3 28.0 to 48.4
0.047 65.1 48.9 to 83.0 84.0 59.8 to 103.3
0.1 139 104 to 177 179 127 to 220
0.22 305 229 to 389 393 280 to 484
0.47 651 489 to 830 840 598 to 1033
1 1386 1042 to 1766 1788 1274 to 2198
The release delay time values are the values calculated from equation (2).
The detect delay time values are the values calculated from equation (4).
(*1) Note that the delay time will vary depending on the actual capacitance value of the delay capacitance Cd.
(*2) The values are calculated with consideration given to deviations in the delay resistance and delay capacitance pin threshold voltage.
Power input pin voltage: VIN
Release state (VIN1)
Release state (VIN1)
Output pin voltage: VRESETB
Delay capacitance pin voltage: VCd/MRB
Detect delay time: tDF
Delay capacitance pin threshold voltage
Detect state
(
VSS
VIN=VDF x 1.1V
VIN2=VDF x 0.9V
VIN1=VDF x 1.1V
VTCD=VIN2/2=0.9x0.5
........... ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
16/32
XC6129 Series
OPERATIONAL DESCRIPTION (Continued)
<Manual reset function>
The reset output pin signal can be forced into the detect state by inputting a voltage into the delay capacitance pin when in the
release state.
When the delay capacitance pin voltage input reaches an HL level signal, the reset output pin outputs an HL level signal.
(RESETBActive Low type)
When the delay capacitance pin voltage input reaches an HL level signal, the reset output pin outputs an LH level signal.
(RESETActive High type)
* During manual reset, there is no delay time even when a delay capacitance is connected.
* When the delay capacitance pin voltage input reaches an LH level signal in the detection state, the reset output pin outputs an
LH level signal.
(RESETBActive Low type)
* When the delay capacitance pin voltage input reaches an LH level signal in the detection state, the reset output pin outputs an
HL level signal.
(RESETActive High type)
Under the detect condition, the condition will be kept even if the RESET switch turns on and off.
In the case that either H level or L level is fed to the Cd/MRB pin without the RESET switch, the behavior of the XC6129 follows
the timing chart in Fig. 4.
L level is fed to the MRB pin under the detect condition, the RESET switch will be kept.
H level is fed to the MRB pin under the detect condition, the RESET switch will be undefined.
Even though the voltage at the VSEN pin changes from a higher voltage than the detect voltage to a lower voltage, as long as H
level is fed to the MRB pin, the release condition is kept.
If H level or L level is fed to the Cd/MRB pin forcibly, then even though Cd is connected to the pin, the XC6129 can’t have any
delay time.
Fig. 4: Manual reset operation by the delay capacitance pin (Active Low product)
<Unstable operation prevention function>
Types B/D/F of the XC6129C series include an unstable operation prevention function.
When the power input pin voltage is less than the minimum operation voltage, the output pin voltage due to unstable operation
is limited to 0.4V (MAX.) or less.
* Types A/C/E of the XC6129C series and each of the XC6129N series do not have an unstable operation prevention function.
Release voltage:V
DF
+V
HYS
Detect voltage:V
DF
MRB High level voltage:V
MRH
MRB Low level voltage:V
MRL
Cd/MRB pin voltage:V
Cd/MRB
(MIN.:V
SS
,MAX.:V
IN
)
Output voltage:V
RESE T B
(MIN.:V
SS
,MAX.:V
IN
(CMOS),V
pu l l
(Nch open drain))
Release voltage:V
DF
+V
HYS
Detect voltage:V
DF
Input Voltage:V
IN
MIN.:0V,MAX.:6.0V)
Cd pin threshold voltage:V
TCd
Undefined
SBD Vw Cd/MRE szsm mmum? VRESETE TOIi’EX
17/32
XC6129
Series
NOTE ON USE
1) Please use this IC within the stated maximum ratings. For temporary, transitional voltage drop or voltage rising phenomenon, the IC is
liable to malfunction should the ratings be exceeded.
2) The power input pin voltage may fall due to the flow through current during IC operation and the resistance component
between the power supply and the power input pin.
In the case of CMOS output, a drop in the power input pin voltage may occur in the same way due to the output current. When
this happens, if the power input pin voltage drops below the minimum operating voltage, malfunctioning may occur.
In addition, when the power input pin voltage is below the detect voltage, the output pin voltage may oscillate. Exercise
caution in particular if a resistor is connected to the power input pin.
3) Note that large, sharp changes of the power input pin voltage may cause malfunctioning.
4) Power supply noise is sometimes a cause of malfunctioning. Sufficiently test using the actual device, such as inserting a
capacitor between VIN and GND.
5) If a capacitor is connected to the delay capacitance pin and the power input pin voltage drops suddenly during release operation (for
example, from 6.0V to 0V), there is a possibility that the delay capacitance pin voltage will exceed the absolute maximum rating. If
there is a possibility that the power input pin voltage will drop suddenly during release operation, connect a Schottky diode
between the power input pin and delay capacitance pin as shown in Fig. 5.
Fig. 5: Circuit example with a Schottky diode connected to the delay capacitance pin
6) When an N-ch open drain output is used, the VRESETB voltage at detection and release is determined by the pull-up resistance
connected to the output pin. Refer to the following when selecting the resistance value.
At detection:
VRESETB=Vpull/(1+Rpull/RON)
Vpull : Voltage after pull-up
RON(*1): ON resistance of N-ch driver M3 (calculated from VRESETB/IRBOUT1 based on electrical characteristics)
Example: When VIN=2.0V(*2), RON=0.5/5.2×10-3=96 (MAX.). If it is desired to make VRESETB at detection 0.1V or less when Vpull is 3.0V,
Rpull=(Vpull/VRESETB-1)×RON=(3/0.1- 1)×96 2.8k
Therefore, to make the output voltage at detection 0.1V or less under the above conditions, the pull-up resistance must be 2.8k or higher.
(*1) Note that RON becomes larger as VIN becomes smaller.
(*2) For VIN in the calculation, use the lowest value of the input voltage range you will use.
At release:
VRESETB=Vpull/(1+Rpull/Roff)
Vpull: Voltage after pull-up
Roff: Resistance when N-ch driver M3 is OFF (calculated from VRESETB/ILEAK based on electrical characteristics)
Example: When Vpull is 6.0V, Roff=6/(0.1×10-6)=60M (MIN.). If it is desired to make VRESETB 5.99V or higher,
Rpull=(Vpull/VRESETB-1)×Roff=(6/5.99-1)×60×106100k
Therefore, to make the output voltage at release 5.99V or higher under the above conditions, the pull-up resistance must be
100k or less.
(not needed with CMOS output)
18/32
XC6129 Series
NOTE ON USE (Continued)
7) If the discharge time of the delay capacitance Cd at detection is short and the delay capacitance Cd cannot be discharged to
ground level, charging will take place at the next release operation with electric charge remaining in the delay capacitance Cd,
and this may cause the release delay time to become noticeably short.
8) If the charging time of the delay capacitance Cd at release is short and the delay capacitance Cd cannot be charged to the
VIN level, the delay capacitance Cd will discharge from less than the VIN level at the next detection operation, and this may
cause the detect delay time to become noticeably short.
9) Even with a non-delay type, a delay time is added when a delay capacitance Cd is connected.
10) For a manual reset function, in case when the function is activated by feeding either MRB H level or MRB L level to Cd/MRB
pin instead of using a reset switch, please note these phenomena below;
The RESET output signal will be undefined when MRB H is fed to Cd/MRB pin under the detect condition.
The RESET output signal will be undefined based on the voltage relationship between VSEN pin and Cd/MRB pin.
11) Torex places an importance on improving our products and their reliability.
We request that users incorporate fail-safe designs and post-aging protection treatment when using Torex products in their
systems.
a; yo: TOIi’EX
19/32
XC6129
Series
TYPICAL PERFORMANCE CHARACTERISTICS
(1) Detect, Release Voltage vs. Ambient Temperature
XC6129 (V
DF(T )
=1.5V )
1.450
1.475
1.500
1.525
1.550
1.575
1.600
-50 -25 0 25 50 75 100
Ambient Temperature : Ta ()
Detect, Release Voltage : V
DFL
, V
DR
(V)
V
DF
V
DR
XC6129 (V
DF(T )
=2.7V )
2.65
2.70
2.75
2.80
2.85
2.90
-50-250 255075100
Ambient Temperature : Ta ()
Detect, Release Voltage : V
DFL
, V
DR
(V)
V
DR
V
DF
(2) Detect, Release Voltage vs. Input Voltage
XC6129 (V
DF(T )
=5.5V )
5.40
5.45
5.50
5.55
5.60
5.65
5.70
5.75
5.80
5.85
-50 -25 0 25 50 75 100
Ambient Temperature : Ta ()
Detect, Release Voltage : V
DFL
, V
DR
(V)
V
DR
V
DF
XC6129C (V
DF(T )
=1.5V )
0
1
2
3
4
5
6
0123456
Input Voltage : V
IN
(V)
OutPut Voltage : V
RESETB
(V)
Ta=- 40
Ta=25
Ta=85
Type : A/C/
E
No Pull-up
: V
DF
: V
DR
XC6129C (V
DF(T)
=2.7V )
0
1
2
3
4
5
6
0123456
Input Voltage : V
IN
(V)
Output Voltage : V
RESETB
(V)
Ta=- 40
Ta=25
Ta=85
Type : A/C/
E
No Pull- up
: V
DF
: V
DR
XC6129C (V
DF(T )
=5.5V )
0
1
2
3
4
5
6
0123456
Input Voltage : V
IN
(V)
Output Voltage : V
RESETB
(V)
Ta=- 40
Ta=25
Ta=85
Type : A /C/
E
No Pull- up
: V
DF
: V
DR
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20/32
XC6129 Series
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(2) Detect, Release Voltage vs. Input Voltage (Continued)
(3) Supply Current vs. Input Voltage
XC6129 (V
DF(T )
=1.5V )
0.00
0.15
0.30
0.45
0.60
0.75
0.90
1.05
1.20
1.35
1.50
0123456
Input Voltage: V
IN
(V)
Supply Current : I
SS
(μA)
Ta=- 40
Ta=25
Ta=85
XC6129 (V
DF(T )
=2.7V )
0.00
0.15
0.30
0.45
0.60
0.75
0.90
1.05
1.20
1.35
1.50
0123456
Input Voltage: V
IN
(V)
Supply Current : I
SS
(μA)
Ta=-40
Ta=25
Ta=85
XC6129 (V
DF(T)
=5.5V )
0.00
0.15
0.30
0.45
0.60
0.75
0.90
1.05
1.20
1.35
1.50
0123456
Input Voltage: V
IN
(V)
Supply Current : I
SS
(μA)
Ta=- 40
Ta=25
Ta=85
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21/32
XC6129
Series
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(4) Supply Current vs. Ambient Temperature
XC6129 (V
DF(T)
=1.5V )
0.00
0.15
0.30
0.45
0.60
0.75
0.90
1.05
1.20
1.35
1.50
-50 -25 0 25 50 75 100
Ambient Temperature : Ta ()
Supply Current : I
SS
(
μ
A)
Det ec t
Release
V
IN
=V
DF
×0.9V (Detect)
V
IN
=V
DF
×1.1V (Release)
XC6129 (V
DF(T)
=2.7V )
0.00
0.15
0.30
0.45
0.60
0.75
0.90
1.05
1.20
1.35
1.50
-50-250 255075100
Ambient Temperature : Ta ()
Supply Current : I
SS
(μA)
De te c t
Rele as e
V
IN
=V
DF
×0.9V (Detect)
V
IN
=V
DF
×1.1V (Release)
(5) Output Current vs. Input Voltage
XC6129 (V
DF(T)
=5.5V )
0.00
0.15
0.30
0.45
0.60
0.75
0.90
1.05
1.20
1.35
1.50
-50 -25 0 25 50 75 100
Ambient Temperature : Ta ()
Supply Current : I
SS
(μA)
Det ec t
Release
V
IN
=V
DF
×0.9V (Detect)
V
IN
=V
DF
×1.1V (Release)
XC6129x55A
0
5
10
15
20
25
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Voltage : VIN (V)
Output Current : I
RBOUT
(mA)
Ta=-40
Ta=25
Ta=85
V
RESETB
=0.5V (Nch)
XC6129C15A
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Voltage : VIN (V)
Output Current : I
RBOUT
(mA)
Ta=- 40
Ta=25
Ta=85
V
RES ET B
=V
IN
-0.5V (Pch)
mamas; V—d/‘ruv Pen) mm Cum um um nu as w «,5 1n :5 w :5 .u 45 an 55 an mu Volu- .vN m Mn
22/32
XC6129 Series
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(5) Output Current vs. Input Voltage (Continued) (6) Delay Resistance vs. Ambient Temperature
XC6129x
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
-50-250 255075100
Ambient Temperature : Ta ()
Delay Resistance : Rp (M
)
V
IN
=6.0V , V
CD/MRB
=0V
(Type : A,B,E,F)
(7) Release Delay Time vs. Ambient Temperature
XC6129x
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
-50 -25 0 25 50 75 100
Ambient Temperature : Ta ()
Delay Resistance : Rn (M
)
V
IN
=V
DF
×0.9V , V
CD/MRB
=6.0V
(Ty pe : C,D, E,F)
XC6129
10
11
12
13
14
15
16
17
18
19
20
-50 -25 0 25 50 75 100
Ambient Temperature : Ta ()
Release Delay Time : t
DR
(ms)
V
IN
=V
DF
×0.9V V
DF
×1.1V
Cd=0.01μF (t
DR
=13.9ms )
(8) Detect Delay Time vs. Ambient Temperature
XC6129
100
110
120
130
140
150
160
170
180
190
200
-50 -25 0 25 50 75 100
Ambient Temperature : Ta ()
Release Delay Time : t
DR
(ms)
V
IN
=V
DF
×0.9V V
DF
×1.1V
Cd=0. 1 μF ( t
DR
=139ms)
XC6129
10
11
12
13
14
15
16
17
18
19
20
-50 -25 0 25 50 75 100
Ambient Temperature : Ta ()
Detect Delay Time : t
DF
(ms)
V
IN
=V
DF
×1.1V V
DF
×0.9V
Cd=0.01μF (t
DR
=17.9ms)
TOIi’EX
23/32
XC6129
Series
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(8) Detect Delay Time vs. Ambient Temperature (Continued) (9) Cd pin MRB High Level Voltage vs. Ambient Temperature
XC6129
100
110
120
130
140
150
160
170
180
190
200
-50 -25 0 25 50 75 100
Ambient Temperature : Ta ()
Detect Delay Time : t
DF
(ms)
V
IN
=V
DF
×1.1V V
DF
×0.9V
Cd=0.1μF (t
DR
=179ms)
XC6129x
0.0
1.0
2.0
3.0
4.0
-50-25 0 25 50 75100
Ambient Temperature : Ta ()
MRB HighLevel Threshold Voltage : V
MRH
(V)
V
IN
=6.0V
V
IN
=2.0V
V
IN
=4.0V
(10) Cd pin MRB High Level Voltage vs. Input Voltage (11) Cd pin MRB Low Level Voltage vs. Ambient Temperature
XC6129
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Voltage : V
IN
(V)
MRB HighLevel Threshold Voltage : V
MRH
(V)
Ta=- 40
Ta=25
Ta=85
XC6129x
0.0
0.3
0.6
0.9
1.2
1.5
-50 -25 0 25 50 75 100
Ambient Temperature : Ta ()
MRB LowLevel Threshold Voltage : V
MRL
(V)
V
IN
=2.0V
V
IN
=6.0V
V
IN
=4.0V
(12) Cd pin MRB Low Level Voltage vs. Input Voltage
XC6129
0.00
0.15
0.30
0.45
0.60
0.75
0.90
1.05
1.20
1.35
1.50
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Voltage : V
IN
(V)
MRB HighLevel Threshold Voltage : V
MRH
(V)
Ta=- 40
Ta=25
Ta=85
.USF’N—4 fig ”mg ”mg ‘% n av mzs Am , ‘nfl ,|\ H m , r mm SHE 5 n ma «é: . . 1.1. m 3 3m: m WW m3 mm 5 m D. W 1 5 w : “““ fl: ‘ 1 ‘ o. m. M. w m m M m “““ u. a ._I 2 n 1 0 ‘mm ““““ m‘l ‘ ‘ $ WI \ 5 . . m§+i mmwu: . mm mm H M o
24/32
XC6129 Series
0.75
0.5
1.85
1.3
0.6
PACKAGING INFORMATION
unit: mm
0.60.25
USPN-4 Reference Pattern Layout
USPN-4 Reference Metal Mask Design
SSOT-24 Reference Pattern Layout
TOIi’EX
25/32
XC6129
Series
PACKAGING INFORMATION (Continued)
unit: mm
1p i n INDENT
12
34
0.25±0.05
1.0±0.05
0.07±0.05
0.32±0.05
(0.65)
0.25±0.05 1.0±0.05
0.05
0.33MAX
●USPQ-4B05
USPQ-4B05 Reference Pattern Layout
USPQ-4B05 Reference Pattern Layout
1.30
0.47
0.25
0.22
0.4 0.4
0.65
12
3
4
0.05 0.1
0.1 0.1
0.1
0.275
0.225
0.9
0.45
0.225
0.25
1.05
0.55 0.25
0.25
12
3
4
¥ SSOT-24 Power Dis Eation 1. Measurement Condition 40.0 28.9 40.0 N J 2L4 1-4 Evaluation Board (Unit mm) 2.5 2.Power Dissipation vs. Ambient Temperature
26/32
XC6129 Series
● SSOT-24 Power Dissipation
Power dissipation data for the SSOT-24 is shown in this page.
The value of power dissipation varies with the mount board conditions.
Please use this data as the reference data taken in the following condition.
1. Measurement Condition
ConditionMount on a board
AmbientNatural convection
SolderingLead (Pb) free
BoardDimensions 40 x 40 mm
(1600 mm2 in one side)
Copper (Cu) traces occupy 50% of the board
area In top and back faces
Package heat-sink is tied to the copper traces
MaterialGlass Epoxy (FR-4)
Thickness1.6mm
Through-hole4 x 0.8 Diameter
Evaluation Board (Unitmm)
2.Power Dissipation vs. Ambient Temperature
Board Mount (Tj max = 125)
Ambient Temperature(℃Power Dissipation PdmWThermal Resistance (℃/W)
25 500 200.00
85 200
0
100
200
300
400
500
600
25 45 65 85 105 125
Power Dissipation Pd (mW)
Ambient Temperature Ta ()
Pd vs Ta
USPN-4 Power DissiEation 1. Measuremem Cond" 40.0 28.9 V ,, 0 JP ‘ 3t 0 ii N V _ M. Li? _ 2.Power Dissigation vs. Ambiem Tem Qerature TOIREX
27/32
XC6129
Series
● USPN-4 Power Dissipation
Power dissipation data for the USPN-4 is shown in this page.
The value of power dissipation varies with the mount board conditions.
Please use this data as the reference data taken in the following condition.
1. Measurement Condition
ConditionMount on a board
AmbientNatural convection
SolderingLead (Pb) free
BoardDimensions 40 x 40 mm
(1600 mm2 in one side)
Copper (Cu) traces occupy 50% of the front
and 50% of the back.
The copper area is divided into four block,
one block is 12.5% of total.
The USPN-4 package has for terminals.
Each terminal connects one copper block in
the front and one in the back.
Material
Glass Epoxy (FR-4)
Thickness
1.6 mm
Through-hole
4 x 0.8 Diameter
Evaluation Board (Unitmm)
2.Power Dissipation vs. Ambient Temperature
Board Mount (Tj max = 125)
Ambient Temperature(℃Power Dissipation PdmWThermal Resistance (℃/W)
25 600 166.67
85 240
0
100
200
300
400
500
600
700
25 45 65 85 105 125
Power Dissipation Pd (mW)
Ambient Temperature Ta ()
Pd vs Ta
¥ Q USPQ-4BOS Power Dissigation 1. Measurement Condition 2.Power Dissigation vs. Ambient Temgerature
28/32
XC6129 Series
 USPQ-4B05 Power Dissipation
Power dissipation data for theUSPQ-4B05 is shown in this page.
The value of power dissipation varies with the mount board conditions.
Please use this data as the reference data taken in the following condition.
1. Measurement Condition
ConditionMount on a board
AmbientNatural convection
SolderingLead (Pb) free
BoardDimensions 40 x 40 mm
(1600 mm2 in one side)
4 Copper Layers
Each layer is connected to the package
heat-sink and terminal pin No.1.
Each layer has approximately 800mm2
copper area
MaterialGlass Epoxy (FR-4)
Thickness1.6mm
Through-hole4 x 0.8 Diameter
Evaluation Board (Unitmm)
2.Power Dissipation vs. Ambient Temperature
Board Mount (Tj max = 125)
Ambient Temperature(℃Power Dissipation PdmWThermal Resistance (℃/W)
25 550 181.82
85 220
0
100
200
300
400
500
600
25 45 65 85 105 125
Power Dissipation Pd (mW)
Ambient Temperature Ta ()
Pd vs. Ta
40.0
40.0
28.9
28.9
2.54
.
1.4
A XC6129C15A‘WG m X06129055A'56 0 l 2 9 £ E E E A Q Q E E E K L E B TOIi’EX
29/32
XC6129
Series
MARKING RULE
Indicates mark (1) product series. Indicates the detect voltage range and output type.
Mark (1)-1 (XC6129C*****-G is underline mark specification.)
MARK OUTPUT
DETECT VOLTAGE
RANGE (V)
TYPE PRODUCT SERIES
0
CMOS
Odd number
A XC6129C15A**-G to XC6129C55A**-G
1 B XC6129C15B**-G to XC6129C55B**-G
2 C XC6129C15C**-G to XC6129C55C**-G
3 D XC6129C15D**-G to XC6129C55D**-G
4 E XC6129C15E**-G to XC6129C55E**-G
5 F XC6129C15F**-G to XC6129C55F**-G
6 G XC6129C15G**-G to XC6129C55G**-G
8 J XC6129C15J**-G to XC6129C55J**-G
A L XC6129C15L**-G to XC6129C55L**-G
C
Even number
A XC6129C16A**-G to XC6129C54A**-G
D B XC6129C16B**-G to XC6129C54B**-G
E C XC6129C16C**-G to XC6129C54C**-G
F D XC6129C16D**-G to XC6129C54D**-G
H E XC6129C16E**-G to XC6129C54E**-G
K F XC6129C16F**-G to XC6129C54F**-G
L G XC6129C16G**-G to XC6129C54G**-G
N J XC6129C16J**-G to XC6129C54J**-G
R L XC6129C16L**-G to XC6129C54L**-G
Mark (1)-2 (XC6129N*****-G is overline mark specification.)
MARK OUTPUT
DETECT VOLTAGE
RANGE (V)
TYPE PRODUCT SERIES
0
N-ch
Odd number
A XC6129N15A**-G XC6129N55A**-G
2 C
XC6129N15C**-G XC6129N55C**-G
4 E
XC6129N15E**-G XC6129N55E**-G
6 G
XC6129N15G**-G XC6129N55G**-G
8 J
XC6129N15J**-G XC6129N55J**-G
A L
XC6129N15L**-G XC6129N55L**-G
C
Even number
A XC6129N16A**-G XC6129N54A**-G
E C
XC6129N16C**-G XC6129N54C**-G
H E
XC6129N16E**-G XC6129N54E**-G
L G
XC6129N16G**-G XC6129N54G**-G
N J
XC6129N16J**-G XC6129N54J**-G
R L
XC6129N16L**-G XC6129N54L**-G
SSOT-24
(with overline mark)
SSOT-24
(with underline mark)
USPQ-4B05
(with underline mark)
USPQ-4B05
(with overline mark)
30/32
XC6129 Series
MARKING RULE (Continued)
represents detect voltage
MARK
DETECT
VOLTEGE(V)
MARK
DETECT
VOLTEGE(V)
MARK
DETECT
VOLTEGE(V)
A 1.5 1.6 K 2.9 3.0 T 4.3 4.4
B 1.7 1.8 L 3.1 3.2 U 4.5 4.6
C 1.9 2.0 M 3.3 3.4 V 4.7 4.8
D 2.1 2.2 N 3.5 3.6 X 4.9 5.0
E 2.3 2.4 P 3.7 3.8 Y 5.1 5.2
F 2.5 2.6 R 3.9 4.0 Z 5.3 5.4
H 2.7 2.8 S 4.1 4.2 0 5.5 -
, represents production lot number
0109, 0A0Z, 119Z, A1A9, AAAZ, B1ZZ repeated.
(GIJOQW excluded)
* No character inversion used.
0 HF UUL TOIi’EX
31/32
XC6129
Series
MARKING RULE (Continued)
USPN-4
represents detect voltage range and product series
represents detect voltage
MARK
DETECT
VOLTEGE(V)
MARK
DETECT
VOLTEGE(V)
MARK
DETECT
VOLTEGE(V)
A 1.5 1.6 K 2.9 3.0 T 4.3 4.4
B 1.7 1.8 L 3.1 3.2 U 4.5 4.6
C 1.9 2.0 M 3.3 3.4 V 4.7 4.8
D 2.1 2.2 N 3.5 3.6 X 4.9 5.0
E 2.3 2.4 P 3.7 3.8 Y 5.1 5.2
F 2.5 2.6 R 3.9 4.0 Z 5.3 5.4
H 2.7 2.8 S 4.1 4.2 0 5.5 -
, represents production lot number
0109, 0A0Z, 119Z, A1A9, AAAZ, B1ZZ repeated.
(GIJOQW excluded)
* No character inversion used.
represents detect voltage
MARK OUTPUT PRODUCT SERIES
K CMOS XC6129C*****-G
L N-ch XC6129N*****-G
MARK
DETECT VOLTAGE
RANGE (V)
TYPE PRODUCT SERIES
0
Odd number
A XC6129*15A**-G XC6129*55A**-G
1 B(*) XC6129*15B**-G XC6129*55B**-G
2 C
XC6129*15C**-G XC6129*55C**-G
3 D(*) XC6129*15D**-G XC6129*55D**-G
4 E
XC6129*15E**-G XC6129*55E**-G
5 F(*) XC6129*15F**-G XC6129*55F**-G
6 G
XC6129*15G**-G XC6129*55G**-G
8 J
XC6129*15J**-G XC6129*55J**-G
A L
XC6129*15L**-G XC6129*55L**-G
C
Even number
A XC6129*16A**-G XC6129*54A**-G
D B(*) XC6129*16B**-G XC6129*54B**-G
E C
XC6129*16C**-G XC6129*54C**-G
F D(*) XC6129*16D**-G XC6129*54D**-G
H E
XC6129*16E**-G XC6129*54E**-G
K F(*) XC6129*16F**-G XC6129*54F**-G
L G
XC6129*16G**-G XC6129*54G**-G
N J
XC6129*16J**-G XC6129*54J**-G
R L
XC6129*16L**-G XC6129*54L**-G
(*) Only supported with CMOS output.
XC5129 Series 32/32
32/32
XC6129 Series
1. The product and product specifications contained herein are subject to change without notice to
improve performance characteristics. Consult us, or our representatives before use, to confirm that
the information in this datasheet is up to date.
2. The information in this datasheet is intended to illustrate the operation and characteristics of our
products. We neither make warranties or representations with respect to the accuracy or
completeness of the information contained in this datasheet nor grant any license to any intellectual
property rights of ours or any third party concerning with the information in this datasheet.
3. Applicable export control laws and regulations should be complied and the procedures required by
such laws and regulations should also be followed, when the product or any information contained in
this datasheet is exported.
4. The product is neither intended nor warranted for use in equipment of systems which require
extremely high levels of quality and/or reliability and/or a malfunction or failure which may cause loss
of human life, bodily injury, serious property damage including but not limited to devices or equipment
used in 1) nuclear facilities, 2) aerospace industry, 3) medical facilities, 4) automobile industry and
other transportation industry and 5) safety devices and safety equipment to control combustions and
explosions. Do not use the product for the above use unless agreed by us in writing in advance.
5. Although we make continuous efforts to improve the quality and reliability of our products;
nevertheless Semiconductors are likely to fail with a certain probability. So in order to prevent
personal injury and/or property damage resulting from such failure, customers are required to
incorporate adequate safety measures in their designs, such as system fail safes, redundancy and
fire prevention features.
6. Our products are not designed to be Radiation-resistant.
7. Please use the product listed in this datasheet within the specified ranges.
8. We assume no responsibility for damage or loss due to abnormal use.
9. All rights reserved. No part of this datasheet may be copied or reproduced unless agreed by Torex
Semiconductor Ltd in writing in advance.
TOREX SEMICONDUCTOR LTD.

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