RoHS (A @ Halogen-Free EPC2204 eGaN” FETs are supplied onl passivated die form with solder bars‘
eGaN® FET DATASHEET EPC2204
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EFFICIENT POWER CONVERSION
HAL
EPC2204 – Enhancement Mode Power Transistor
VDS , 100 V
RDS(on) , 6 mΩ
ID , 29 A
Maximum Ratings
PARAMETER VALUE UNIT
VDS
Drain-to-Source Voltage (Continuous)
100 V
VDS
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150 °C)
120
ID
Continuous (TA = 25°C)
29 A
Pulsed (25°C, TPULSE = 300 µs)
125
VGS
Gate-to-Source Voltage
6V
Gate-to-Source Voltage
-4
TJ
Operating Temperature
-40 to 150 °C
TSTG
Storage Temperature
-40 to 150
Thermal Characteristics
PARAMETER TYP UNIT
RθJC Thermal Resistance, Junction-to-Case 1
°C/W RθJB Thermal Resistance, Junction-to-Board 2.5
RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 64
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
# Defined by design. Not subject to production test.
Static Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.25 mA 100 V
IDSS Drain-Source Leakage VGS = 0 V, VDS = 80 V 0.04 0.2
mA
IGSS
Gate-to-Source Forward Leakage VGS = 5 V 0.01 0.25
Gate-to-Source Forward Leakage#VGS = 5 V, TJ = 125°C 0.3 6.7
Gate-to-Source Reverse Leakage VGS = -4 V 0.03 0.2
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 4 mA 0.8 1.1 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 16 A 4.4 6 mΩ
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.6 V
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows
very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally
low QG and zero QRR. The end result is a device that can handle tasks where very high switching
frequency, and low on-time are beneficial as well as those where on-state losses dominate.
EPC2204 eGaN® FETs are supplied only in
passivated die form with solder bars.
Die Size: 2.5 mm x 1.5 mm
Applications
DC-DC Converters
Isolated DC-DC
Converters
• Lidar
Sync rectification for
AC-DC and DC-DC
Point of Load Converters
• USB-C
Class-D Audio
LED Lighting
• E-Mobility
Benefits
Ultra High Efficiency
No Reverse Recovery
Ultra Low QG
Small Footprint
G
D
S
eGaN® FET DATASHEET EPC2204
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120
100
80
60
40
20
00 0.5 1.0 1.5 2.0 2.5 3.0
ID – Drain Current (A)
Figure 1: Typical Output Characteristics at 25°C
VDS – Drain-to-Source Voltage (V)
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
ID – Drain Current (A)
VGS – Gate-to-Source Voltage (V)
1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 2: Transfer Characteristics
25˚C
125˚C
VDS = 3 V
25˚C
125˚C
VDS = 3 V
120
100
80
60
40
20
0
16
14
12
10
8
6
4
2
02.5 3.02.0 3.5 4.0 4.5 5.0
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
Figure 3: RDS(on) vs. VGS for Various Drain Currents
ID = 8 A
ID = 16 A
ID = 24 A
ID = 32 A
2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 4: RDS(on) vs. VGS for Various Temperatures
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
25˚C
125˚C
VDS = 3 V
25˚C
125˚C
ID = 16 A
16
14
12
10
8
6
4
2
0
Dynamic Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CISS
Input Capacitance#
VDS = 50 V, VGS = 0 V
644 851
pF
CRSS
Reverse Transfer Capacitance
2.3
COSS
Output Capacitance#
304 456
COSS(ER)
Effective Output Capacitance, Energy Related (Note 2)
VDS = 0 to 50 V, VGS = 0 V 401
COSS(TR)
Effective Output Capacitance, Time Related (Note 3)
501
RG
Gate Resistance
0.4 Ω
QG
Total Gate Charge#
VDS = 50 V, VGS = 5 V, ID = 16 A 5.7 7.4
nC
QGS
Gate-to-Source Charge
VDS = 50 V, ID = 16 A
1.8
QGD
Gate-to-Drain Charge
0.8
QG(TH)
Gate Charge at Threshold
1
QOSS
Output Charge#
VDS = 50 V, VGS = 0 V 25 38
QRR
Source-Drain Recovery Charge
0
# Defined by design. Not subject to production test.
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
eGaN® FET DATASHEET EPC2204
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Capacitance (pF)
0 25 50 75 100
Figure 5a: Capacitance (Linear Scale)
VDS – Drain-to-Source Voltage (V)
900
800
700
600
500
400
300
200
100
0
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Capacitance (pF)
1000
100
10
10 25 50 75 100
Figure 5b: Capacitance (Log Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Figure 6: Output Charge and COSS Stored Energy
QOSS Output Charge (nC)
EOSS COSS Stored Energy (µJ)
40
32
24
16
8
00 20 40 60 80 100
VDS – Drain-to-Source Voltage (V)
1.60
1.28
0.96
0.64
0.32
0.00
Figure 7: Gate Charge
VGS Gate-to-Source Voltage (V)
5
4
3
2
1
00 5 64321
QG – Gate Charge (nC)
ID = 16 A
VDS = 50 V
0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
ISD Source-to-Drain Current (A)
VSD – Source-to-Drain Voltage (V)
Figure 8: Reverse Drain-Source Characteristics
120
100
80
60
40
20
0
25˚C
VGS = 0 V
125˚C
Figure 9: Normalized On-State Resistance vs. Temperature
Normalized On-State Resistance RDS(on)
2.0
1.8
1.6
1.4
1.2
1.0
0.8 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 16 A
VGS = 5 V
HL’ HL’
eGaN® FET DATASHEET EPC2204
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Figure 12: Transient Thermal Response Curves
Figure 10: Normalized Threshold Voltage vs. Temperature
Normalized Threshold Voltage
1.4
1.3
1.2
1.1
1.
0.9
0.8
0.7
0.6 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 4 mA
1000
100
10
1
0.10.1 1 10 100 1000
ID – Drain Current (A)
VDS - Drain-Source Voltage (V)
Limited by RDS(on)
Pulse Width
1 ms
100 µs
10 µs
Figure 11: Safe Operating Area
tp, Rectangular Pulse Duration, seconds
ZθJB, Normalized Thermal Impedance
0.5
0.2
0.05
0.02
Single Pulse
0.01
0.1
Duty Cycle:
Junction-to-Board
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
10-5 10-4 10-3 10-2 10-1 1 10+1
1
0.1
0.01
0.001
tp, Rectangular Pulse Duration, seconds
ZθJC, Normalized Thermal Impedance
0.5
Junction-to-Case
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
10-6 10-5 10-4 10-3 10-2 10-1 1
1
0.1
0.01
0.001
0.0001
0.2
0.05
0.02
Single Pulse
0.01
0.1
Duty Cycle:
TJ = Max Rated, TC = +25°C, Single Pulse
eGaN® FET DATASHEET EPC2204
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DIE MARKINGS
DIE OUTLINE
Solder Bump View
Pad 1 is Gate;
Pads 2 ,4, 6 are Source;
Pads 3, 5 are Drain
Side View
YYYY
2204
ZZZZ
TAPE AND REEL CONFIGURATION
4 mm pitch, 8 mm wide tape on 7” reel
7” inch reel Die
orientation
dot
Gate solder bar
is under this
corner
Die is placed into pocket
solder bump side down
(face side down)
Loaded Tape Feed Direction
a
d
e f
g
h
c
b
DIM Dimension (mm)
EPC2204 (Note 1) Target MIN MAX
a8.00 7.90 8.30
b1.75 1.65 1.85
c (Note 2) 3.50 3.45 3.55
d4.00 3.90 4.10
e4.00 3.90 4.10
f (Note 2) 2.00 1.95 2.05
g1.50 1.50 1.60
h0.50 0.45 0.55
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/
JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as
true position of the pocket, not the pocket hole.
Part
Number
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking Line 2
Lot_Date Code
Marking Line 3
EPC2204 2204 YYYY ZZZZ
2204
YYYY
ZZZZ
Die orientation dot
Gate Pad bump is
under this corner
518 ± -25
Seating plane
638
120 ± 12
A
d
j
h
g
B
e
c
f
2
3 4 5 6
1
k
DIM
Micrometers
MIN Nominal MAX
A2470 2500 2530
B1470 1500 1530
c1175
d1350
e500
f250
g300
h825
j787.5
k225
eGaN® FET DATASHEET EPC2204
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RECOMMENDED
LAND PATTERN
(units in µm)
RECOMMENDED
STENCIL DRAWING
(units in µm)
Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing.
The corner has a radius of R60.
Intended for use with SAC305 Type 3 solder, reference 88.5% metals content.
Split stencil design can be provided upon request, but EPC has tested this stencil design and not found any scooping issues.
Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
Information subject to
change without notice.
Revised December, 2020
Land pattern is solder mask defined
Solder mask opening is 180 µm
It is recommended to have on-Cu trace PCB vias
Pad 1 is Gate;
Pads 2 ,4, 6
are Source;
Pads 3, 5 are Drain
A
d1
j
h1 g1
B
e
c1
f1
2
3 4 5 6
1
k
A
d1
j
h1 g1
B
e
c1
f2
f1
R60
k
f2 f2
DIM Nominal
A2500
B1500
c1 1155
d1 1330
e500
f1 230
g1 280
h1 805
j787.5
k225
DIM Nominal
A2500
B1500
c1 1155
d1 1330
e500
f1 230
f2 210
g1 280
h1 805
j787.5
k225

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