MAX22190 Datasheet by Maxim Integrated

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MAX22190 Octal Industrial Digital Input with Diagnostics maxim Integrated ,,
General Description
The MAX22190 is an IEC 61131-2 compliant industrial
digital input device. The MAX22190 translates eight, 24V
current-sinking, industrial inputs to a serialized SPI-
compatible output that interfaces with 3V to 5.5V logic. A
current setting resistor allows the MAX22190 to be
configured for Type 1, Type 2, or Type 3 inputs. Field
wiring is verified for proximity switches, by a second
threshold detector on each input. When wire-break is
enabled, the FAULT output is asserted and a register
flag is set if the input current drops below the wire-break
threshold for more than 20ms. Additional diagnostics that
assert the FAULT pin include: overtemperature, low 24V
field supply, 24V field supply missing, CRC communica-
tion error, etc.
For robust operation in industrial environments, each input
includes a programmable glitch filter. The filter delay on each
channel can be independently programmed to one of eight
values between 50µs and 20ms, or filter bypass.
The MAX22190 has a 4-pin SPI interface and in addition
uses the LATCH input for synchronizing input data across
multiple devices in parallel.
MAX22190 field-side accepts a single 7V to 65V
supply to VDD24 pin. When powered by the field supply,
the MAX22190 generates a 3.3V output from an integrated
LDO regulator, which can provide up to 25mA of current
for external loads in addition to powering the MAX22190.
Alternatively, the MAX22190 can be powered from a 3.0V
to 5.5V logic side supply connected to VDD pin. For flexibil-
ity, the SPI interface operates at 3.3V or 5V logic levels as
controlled by the VL pin.
Applications
Programmable Logic Controllers
Industrial Automation
Process Automation
Building Automation
Benefits and Features
High Integration Reduces BOM Count and Board Space
Eight Input Channels with Serializer
Operates Directly from Field Supply (7V to 65V)
Compatible with 3.3V or 5V Logic
5mm x 5mm TQFN Package
Reduced Power and Heat Dissipation
Accurate Input-Current Limiters
Energyless Field-Side LED Drivers
Fault Tolerant with Built-In Diagnostics
Input Protection to ±40V with Low-Input Leakage
Current
Wire Break Detection
Integrated Field-Supply Voltage Monitors
Integrated Overtemperature Monitors
5-Bit CRC Code Generation and Transmission for
Error Detection
Configurability Enables Wide Range of Applications
Configurable IEC 61131-2 Type 1, 2, 3 Inputs
Configurable Input Current-Limiting from 0.5mA to
3.4mA
Selectable Input Debounce Filtering
Robust Design
±8kV Contact ESD and ±15kV Air Gap ESD Using
Minimum 1kΩ Resistor
±1kV Surge Tolerant Using Minimum 1kΩ Resistor
-40°C to +125°C Ambient Operating Temperature
Ordering Information appears at end of data sheet.
19-100224; Rev 5; 9/20
MAX22190 Octal Industrial Digital Input with Diagnostics
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Isolated Octal Type 1/3 Digital Input
VDD
GND
2.5V
MICRO
CONTROLLER
0.1µF
VDD24
CS
SDO
SDI
SCLK
FAULT
VDD
GND
MAX22190
24V
READY
IN1
LED1
IN2
LED2
IN8
LED8
REFWB
REFDI
INF (INPUT-FIELD) INP (INPUT-PIN)
LATCH
VL
3.3V
SCLK
SDI
SDO
CS
GPI
GPO
GPI or INT
3.3V
2.5V
M1
M0
MAX14483
VDDA
GNDA
OAUX
OSDI
OSCLK
OCS
SBA
IRDY
ISDO
IFAULT
VDDB
GNDB
IAUX
ISDI
ISCLK
ICS
SAA
OSDO
OFAULT
LOGIC SIDE
FIELD SI DE
SDOEN
1µF 0.F 0.1µF
4.7kΩ
4.7kΩ
7.5kΩ
24kΩ
1.5kΩ
1.5kΩ
1.5kΩ
4.7kΩ
1µF 1µF
VL, VDD to GND .....................................................-0.3V to +6V
VDD24 to GND ....................................................... -0.3V to +70V
SCLK, CS, SDI, M0, M1 to GND.............................-0.3V to +6V
LATCH, FAULT, READY to GND ............................-0.3V to +6V
REFWB, REFDI to GND .......................... -0.3V to (VDD + 0.3V)
SDO to GND ................................................ -0.3V to (VL + 0.3V)
IN1–IN8 to GND .....................................................-40V to +40V
LED1–LED8 to GND ...............................................-0.3V to +6V
Continuous Power Dissipation (TA = +70°C)
TQFN (derate at 27.8mW/°C above +70°C) .................2222mW
Operating Temperature Range
Ambient Temperature ..................................................+125°C
Junction Temperature ..................................................+150°C
Storage Temperature Range ............................ -65°C to +150°C
Lead Temperature (soldering, 10s) ................................. +300°C
Soldering (reflow) ............................................................ +260°C
VL - VGND = +3.0V to +5.5V, VDD - VGND = +3.0V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. CL = 15pF. Typical values
are at VL - VGND = +3.3V, VDD - VGND = +3.3V, VDD24 - VGND = +24V, IN_ = +24V, and TA = +25°C. (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLIES
Logic Supply Voltage VL3.0 5.5 V
Logic Supply Current IVL
CS = VL,
All logic pins
static
VVL – VGND = +5.5V 13 30 µA
Supply Voltage VDD24 Normal operation 7 65 V
VDD Powered from an external supply 3.0 5.5 V
Supply Current of VDD24 IDD24 VDD24 = 24V
IN1–IN8 = 0V, LED1–
LED8 = GND, SPI static,
REFDI = 7.5kΩ, REFWB
= 24kΩ.
0.6 1.2 mA
Supply Current
Powered From VDD
IDD VDD = 3.3V
IN1–IN8 = 0V, LED1–
LED8 = GND, SPI static,
REFDI = 7.5kΩ, REFWB
= 24kΩ.
0.6 1.2 mA
PACKAGE TYPE: 32 TQFN
Package Code T3255+6
Outline Number 21-0140
Land Pattern Number 90-0603
THERMAL RESISTANCE, MULTILAYER BOARD
Junction to Ambient (θJA) 36°C/W
Junction to Case (θJC) 3°C/W
MAX22190 Octal Industrial Digital Input with Diagnostics
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Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
DC Electrical Characteristics
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
VL - VGND = +3.0V to +5.5V, VDD - VGND = +3.0V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. CL = 15pF. Typical values
are at VL - VGND = +3.3V, VDD - VGND = +3.3V, VDD24 - VGND = +24V, IN_ = +24V, and TA = +25°C. (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VDD Undervoltage-Lockout
Threshold VUVLO VDD rising 2.4 2.9 V
VDD Undervoltage-Lockout
Threshold Hysteresis VUVHYST 0.07 V
VDD24 Undervoltage-Lockout
Threshold VUVLO24 VDD24 rising 6 6.8 V
VDD24 Undervoltage-Lockout
Threshold Hysteresis VUVHYST24 0.5 V
VL Undervoltage-Lockout
Threshold VUVLOVL VL rising 0.9 1.6 V
VL Undervoltage-Lockout
Threshold Hysteresis VUVHYSTVL 0.07 V
Regulator Output Voltage VDD ILOAD = 1mA, VDD24 ≥ 7V 3.0 3.3 3.6 V
Line Regulation dVDDLINE ILOAD = 1mA, VDD24 = 12V to 24V 0 mV
Load Regulation dVDDLOAD ILOAD = 1mA to 10mA, VDD24 = 24V 4 mV
Regulator Current Capability IDD_CC 25 mA
Short-Circuit Current IDD24_SC VDD24 current when VDD shorted to GND 28 50 mA
READY Threshold VREADY VDD rising, VDD24 = 0V 2.4 2.9 V
READY Threshold Hysteresis VREADY_HYST 0.07 V
READY Delay READYDELAY VDD valid to READY low 1 ms
SUPPLY ALARMS
VDD24 UV Alarm On/Off VALRMOFFUVRising VDD24, under voltage 17 V
VDD24 UV Alarm Off/On VALRMONUV Falling VDD24, under voltage 15 V
Glitch Filter for VDD24 UV 3 µs
VDD24 VM Alarm On/Off VALRMOFFVM Rising VDD24, missing voltage 13.9 V
VDD24 VM Alarm Off/On VALRMONVM Falling VDD24, missing voltage 12.1 V
Glitch Filter for VDD24 VM 3 µs
TEMPERATURE ALARMS
Overtemperature Alarm 1 TALRM1 ALRMT1 bit set in FAULT1 register 115 °C
Overtemperature Alarm 2 TALRM2 ALRMT2 bit set in FAULT1 register 140 °C
Overtemperature Alarm
Hysteresis TALRM_HYS 10 °C
Thermal-Shutdown Threshold TSHDN OTSHDN bit set in FAULT2 register 165 °C
Thermal-Shutdown Hysteresis TSHDN_HYS 10 °C
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DC Electrical Characteristics (continued)
VL - VGND = +3.0V to +5.5V, VDD - VGND = +3.0V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. CL = 15pF. Typical values
are at VL - VGND = +3.3V, VDD - VGND = +3.3V, VDD24 - VGND = +24V, IN_ = +24V, and TA = +25°C. (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
WIRE BREAK ALARMS
REF Wire Break Voltage VREFWB RREFWB = 5.2kΩ to 50kΩ 0.61 V
Wire Break Current Range IWB
RREFWB = 5.2kΩ 470 µA
RREFWB = 50kΩ 48.8 µA
PCB FAULT ALARMS
REFWB Pin Short RWBS RFWBS bit set in FAULT2 Register 550 µA
REFWB Pin Open RWBO RFWBO bit set in FAULT2 Register 6.6 µA
REFDI Pin Short Alarm REFDIS RFDIS bit set in FAULT2 Register 550 µA
REFDI Pin Open REFDIO RFDIO bit set in FAULT2 Register 6.6 µA
IC INPUTS (TYPES 1, 2, 3)
Input Threshold Low-to-High VTHP+ IN1 – IN8 6 V
Input Threshold High-to-Low VTHP- IN1 – IN8 4.4 V
Input Threshold Hysteresis VINPHYST IN1 – IN8 0.8 V
LED On-State Current ILEDON RREFDI = 7.5kΩ, VLED = 3V 1.5 mA
DI Leakage, Current Sources
Disabled IDI_LEAK IN1 – IN8 = 36V 73 µA
IN1 – IN8 = 24V 42 µA
FIELD INPUTS
Current-Limit Setting ICLIM
RREFDI = 5.2kΩ 3.39 mA
RREFDI = 36kΩ 0.48
REFDI Pin Voltage VREFDI RREFDI = from 5.2kΩ to 36kΩ 0.61 V
TYPE 1, 3: External Series Resistor R = 1.5K, RREFDI = 7.5KΩ, WB detection off, unless otherwise noted
Input Current Limit IINLIM 28V > VINx at the pin > 5V,
RREFDI = 7.5kΩ (Note 2) 2.10 2.35 2.60 mA
Field Input Threshold
Low-to-High VINF+ RREFDI = 7.5kΩ, 1.5kΩ external series
resistor 9.9 V
Field Input Threshold
High-to-Low VINF- RREFDI = 7.5kΩ, 1.5kΩ external series
resistor 7.4 V
Field Input Threshold
Hysteresis VINFHYST RREFDI = 7.5kΩ, 1.5kΩ external series
resistor 0.9 V
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DC Electrical Characteristics (continued)
VL - VGND = +3.0V to +5.5V, VDD - VGND = +3.0V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. CL = 15pF. Typical values
are at VL - VGND = +3.3V, VDD - VGND = +3.3V, VDD24 - VGND = +24V, IN_ = +24V, and TA = +25°C. (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TYPE 2: External Series Resistor R = 1K, RREFDI = 5.2KΩ, WB detection off, unless otherwise noted
Input Current Limit IINLIM 28V > VINx at the pin > 5V,
RREFDI = 5.2kΩ (Note 2) 3.05 3.39 3.71 mA
Field Input Threshold
Low-to-High VINF+ RREFDI = 5.2kΩ, 1kΩ external series
resistor 9.9 V
Field Input Threshold
High-to-Low VINF- RREFDI = 5.2kΩ, 1kΩ external series
resistor 7.4 V
Field Input Threshold
Hysteresis VINFHYST RREFDI = 5.2kΩ, 1kΩ external series
resistor 0.9 V
Input Filter Delay
(See bits DELAY[2:0] in FLTx
Register)
tBOUNCE
FBP = 1: bypass filtering 2 µs
FBP = 0, DELAY = 0 0.05
ms
FBP = 0, DELAY = 1 0.1
FBP = 0, DELAY = 2 0.4
FBP = 0, DELAY = 3 0.8
FBP = 0, DELAY = 4 1.6
FBP = 0, DELAY = 5 3.2
FBP = 0, DELAY = 6 12.8
FBP = 0, DELAY = 7 20
Wire Break Filter Delay tWBD 20 ms
DYNAMIC CHARACTERISTICS
Input (IN_) Sampling Rate fIN Input Filter Bypass mode 1000 kHz
Input Filter Not Bypass mode 200
Minimum Detectable IN_
Pulse Width tPW No external capacitors on pins
IN1-IN8 (Note 2) 3 µs
LATCH Delay Assertion of LATCH or CS until input data
is frozen 50 ns
FAULT Minimum Pulse Width tFAULT_PW FAULT low, pullup 4mA 0.8 µs
INTERFACE LOGIC
Input Logic-High Voltage VIH SCLK, CS, SDI, LATCH, M0, M1 relative
to GND
0.7 x
VL
V
Input Logic-Low Voltage VIL SCLK, CS, SDI, LATCH, M0, M1 relative
to GND
0.3 x
VL
V
Output Logic-High Voltage VOH SDO, sourcing 4mA VL -
0.4 V
Output Logic-Low Voltage VOL SDO, FAULT, READY sinking 4mA 0.4 V
Input Pullup Resistance CS,
LATCH RPU 195
Input Pulldown Resistance
SCLK, SDI, M1, M0 RPD 195
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DC Electrical Characteristics (continued)
\ K +‘ W|
VL - VGND = +3.0V to +5.5V, VDD - VGND = +3.0V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. CL = 15pF. Typical values
are at VL - VGND = +3.3V, VDD - VGND = +3.3V, VDD24 - VGND = +24V, INx = +24V, and TA = +25°C. (Note 2)
Note 1: All units are production tested at TA = 25°C. Specifications over temperature are guaranteed by design.
Note 2: External resistor RREFDI is selected to set any desired current limit between 0.5mA and 3.4mA.
Figure 1. SPI Timing Diagram
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SPI CHARACTERISTICS
SCLK Pulse Width-High tSCLKH See Figure 1 20 ns
SCLK Pulse Width-Low tSCLKL See Figure 1 20 ns
SCLK Clock Period tSCLK See Figure 1 100 ns
SCLK Clock Frequency fSCLK 10 MHz
CS Pulse Width tCSBPW See Figure 1 20 ns
SDI-to-SCLK Setup Time tDINSU See Figure 1 5 ns
SDI-to-SCLK Hold Time tDINH See Figure 1 15 ns
CS-Fall-to-SCLK-Rise Time tCLK_SU See Figure 1 80 ns
SCLK-Rise-to-CS-Rise Time tCSBH Rising edge of SCLK to rising
edge of CS (Figure 1)40 ns
SDO Enable Time tCSB_SDOVALID CS falling to SDO valid (Figure 1)50 ns
SDO Disable Time tCSB_SDOTRI CS rising to SDO tri-state (Figure 1)50 ns
Output Data Propagation Delay tDO
SCLK falling edge-to-SDO valid
(Figure 1)50 ns
Rise/Fall Time SDO tR/F SDO 10% to 90% rising, 90% to
10% falling 4 ns
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AC Electrical Characteristics
MSB LSB
...
LSB
MSB
HIGH-Z HIGH-Z
1 2 16151413121110
t
SC L K
t
SC L KL
t
SC L KH
t
C LK _SU
t
C SBH
t
DINSU
t
DINH
t
C SB_SD O VAL I D
t
C SB_S D O T RI
t
DO
t
C SBP W
...
...
CS
SCLK
SDI
SDO
\ \
(VDD24 = 24V, VDD = VL = 3.3V, TA = +25°C, RREFDI = 7.5kΩ, RREFWB = 24kΩ, RIN = 1.5kΩ, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS VALUE UNITS
Surge
Line-to-Line IEC 61000-4-5, 1.2/50µs pulse, minimum 1kΩ
resistor in series with IN1–IN8 ±2
kV
Line-to-Ground IEC 61000-4-5, 1.2/50µs pulse, minimum 1kΩ
resistor in series with IN1–IN8 ±1
ESD
Human Body Model All pins ±2
Contact IEC 61000-4-2, minimum 1kΩ resistor in series
with IN1–IN8 ±8
Air Gap IEC 61000-4-2, minimum 1kΩ resistor in series
with IN1–IN8 ±15
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ESD and EMC Characteristics
Typical Operating Characteristics
0.70
0.71
0.72
0.73
0.74
0.75
515 25 35 45 55 65
SUPPLY CURRENT (mA)
V
DD24
SUPPLY VOLTAGE (V)
V
DD24
SUPPLY CURRENT
vs. V
DD24
SUPPLY VOLTAGE
toc01
CS = V
L
, NO SCLK SWITCHING,
V
DD
UNCONNECTED, ALL V
IN_
= 24V
0.60
0.61
0.62
0.63
0.64
0.65
-50 -25 025 50 75 100 125
SUPPLY CURRENT (mA)
TEMPERATURE (C)
V
DD
SUPPLY CURRENT
vs. TEMPERATURE
toc04
CS = V
L
, NO SCLK SWITCHING,
V
DD
= 3.3V, V
DD24
UNCONNECTED,
ALL V
IN_
= 24V
0.61
0.63
0.65
0.67
0.69
0.71
3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY CURRENT (mA)
V
DD
SUPPLY VOLTAGE (V)
V
DD
SUPPLY CURRENT
vs. V
DD
SUPPLY VOLTAGE
toc02
CS = V
L
, NO SCLK SWITCHING,
V
DD24
UNCONNECTED, ALL V
IN_
= 24V
0.63
0.65
0.67
0.69
0.71
0.73
0 8 16 24 32 40
SUPPLY CURRENT (mA)
INPUT VOLTAGE (V)
V
DD24
SUPPLY CURRENT
vs. V
IN_
INPUT VOLTAGE
toc05
ALL V
IN_
SHORTED TOGETHER
ALL V
IN_
MEASURED AT THE PIN
CS = V
L
, NO SCLK SWITCHING,
V
DD24
= 24V
0.67
0.69
0.71
0.73
0.75
0.77
-50 -25 025 50 75 100 125
SUPPLY CURRENT (mA)
TEMPERATURE (C)
VDD24 SUPPLY CURRENT
vs. TEMPERATURE
toc03
CS = V
L
, NO SCLK SWITCHING,
V
DD24
= 24V, ALL V
IN_
= 24V
0.54
0.56
0.58
0.60
0.62
0.64
0 8 16 24 32 40
SUPPLY CURRENT (mA)
INPUT VOLTAGE (V)
V
DD
SUPPLY CURRENT
vs. V
IN_
INPUT VOLTAGE
toc06
ALL V
IN_
SHORTED TOGETHER
ALL V
IN_
MEASURED AT THE PIN
CS = V
L
, NO SCLK SWITCHING,
V
DD
= 3.3V, V
DD24
UNCONNECTED
(VDD24 = 24V, VDD = VL = 3.3V, TA = +25°C, RREFDI = 7.5kΩ, RREFWB = 24kΩ, RIN = 1.5kΩ, unless otherwise noted.)
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MAX22190 Octal Industrial Digital Input with Diagnostics
Typical Operating Characteristics (continued)
2.0
2.1
2.2
2.3
2.4
2.5
2.6
3.0 3.5 4.0 4.5 5.0 5.5
INPUT CURRENT LIMIT (mA)
V
DD
SUPPLY VOLTAGE (V)
INPUT CURRENT LIMIT IINLIM
vs. VDD SUPPLY VOLTAGE
toc09
V
DD24
UNCONNECTED, V
IN_
= 24V,
R
REFDI
= 7.5k, R
IN
= 1.5k,
WIRE-BREAK OFF
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 5 10 15 20 25 30 35 40
INPUT CURRENT LIMIT (mA)
INPUT VOLTAGE (V)
INPUT CURRENT LIMIT I
INLIM
vs. V
IN_
INPUT VOLTAGE
toc12
V
DD24
= 24V, V
IN_
AT THE PIN,
R
REFDI
= 7.5k, R
IN
= 1.5k,
WIRE-BREAK OFF
0.0
0.8
1.6
2.4
3.2
4.0
0 5 10 15 20 25 30 35 40
INPUT CURRENT LIMIT (mA)
INPUT VOLTAGE (V)
INPUT CURRENT LIMIT I
INLIM
vs. V
IN_
INPUT VOLTAGE
toc15
V
DD24
= 24V, V
IN_
AT FIELD SIDE,
R
REFDI
= 5.2k, R
IN
= 1k,
WIRE-BREAK OFF
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.0 3.5 4.0 4.5 5.0 5.5
INPUT CURRENT LIMIT (mA)
V
DD
SUPPLY VOLTAGE (V)
INPUT CURRENT LIMIT I
INLIM
vs. V
DD
SUPPLY VOLTAGE
toc10
V
DD24
UNCONNECTED, V
IN_
= 24V,
R
REFDI
= 5.2k, R
IN
= 1k,
WIRE-BREAK OFF
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 5 10 15 20 25 30 35 40
INPUT CURRENT LIMIT (mA)
INPUT VOLTAGE (V)
INPUT CURRENT LIMIT I
INLIM
vs. V
IN_
INPUT VOLTAGE
toc13
V
DD24
= 24V, V
IN_
AT FIELD SIDE,
R
REFDI
= 7.5k, R
IN
= 1.5k,
WIRE-BREAK ON
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 5 10 15 20 25 30 35 40
INPUT CURRENT LIMIT (mA)
INPUT VOLTAGE (V)
INPUT CURRENT LIMIT I
INLIM
vs. V
IN_
INPUT VOLTAGE
toc11
V
DD24
= 24V, V
IN_
AT FIELD SIDE,
R
REFDI
= 7.5k, R
IN
= 1.5k,
WIRE-BREAK OFF
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 5 10 15 20 25 30 35 40
INPUT CURRENT LIMIT (mA)
INPUT VOLTAGE (V)
INPUT CURRENT LIMIT I
INLIM
vs. V
IN_
INPUT VOLTAGE
toc14
V
DD24
= 24V, V
IN_
AT THE PIN,
R
REFDI
= 7.5k, R
IN
= 1.5k,
WIRE-BREAK ON
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
510 15 20 25 30 35
INPUT CURRENT LIMIT (mA)
RREFDI (kΩ)
INPUT CURRENT LIMIT I
INLIM
vs. R
REFDI
toc07
VIN_ = 40V
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
-50 -25 025 50 75 100 125
INPUT CURRENT LIMIT (mA)
TEMPERATURE (C)
INPUT CURRENT LIMIT I
INLIM
vs. TEMPERATURE
toc08
V
DD24
= 24V, V
IN_
= 24V,
R
REFDI
= 7.5k
>/
(VDD24 = 24V, VDD = VL = 3.3V, TA = +25°C, RREFDI = 7.5kΩ, RREFWB = 24kΩ, RIN = 1.5kΩ, unless otherwise noted.)
Maxim Integrated
10
www.maximintegrated.com
MAX22190 Octal Industrial Digital Input with Diagnostics
0.6
0.8
1.0
1.2
1.4
-50 -25 025 50 75 100 125
INPUT VOLTAGE HYSTERESIS (V)
TEMPERATURE (C)
INPUT VOLTAGE HYSTERESIS
vs. TEMPERATURE toc22
R
IN
= 0
R
IN
= 1k
R
IN
= 1.5k
Typical Operating Characteristics (continued)
0.0
0.8
1.6
2.4
3.2
4.0
0 5 10 15 20 25 30 35 40
INPUT CURRENT LIMIT (mA)
INPUT VOLTAGE (V)
INPUT CURRENT LIMIT I
INLIM
vs. V
IN_
INPUT VOLTAGE
toc16
V
DD24
= 24V, V
IN_
AT THE PIN,
R
REFDI
= 5.2k, R
IN
= 1k,
WIRE-BREAK OFF
6
7
8
9
10
11
-50 -25 025 50 75 100 125
INPUT VOLTAGE THRESHOLD (V)
TEMPERATURE (C)
INPUT VOLTAGE THRESHOLD
vs. TEMPERATURE
toc19
V
DD24
= 24V, R
REFDI
= 7.5kΩ, R
IN
= 1.5k
LOW-TO-HIGH
HIGH-TO-LOW
0.0
0.8
1.6
2.4
3.2
4.0
0 5 10 15 20 25 30 35 40
INPUT CURRENT LIMIT (mA)
INPUT VOLTAGE (V)
INPUT CURRENT LIMIT I
INLIM
vs. V
IN_
INPUT VOLTAGE
toc17
V
DD24
= 24V, V
IN_
AT FIELD SIDE,
R
REFDI
= 5.2k, R
IN
= 1k,
WIRE-BREAK ON
6
7
8
9
10
11
-50 -25 025 50 75 100 125
INPUT VOLTAGE THRESHOLD (V)
TEMPERATURE (C)
INPUT VOLTAGE THRESHOLD
vs. TEMPERATURE
toc20
V
DD24
= 24V, R
REFDI
= 5.2k, R
IN
= 1k
LOW-TO-HIGH
HIGH-TO-LOW
0.0
0.8
1.6
2.4
3.2
4.0
0 5 10 15 20 25 30 35 40
INPUT CURRENT LIMIT (mA)
INPUT VOLTAGE (V)
INPUT CURRENT LIMIT I
INLIM
vs. V
IN_
INPUT VOLTAGE
toc18
V
DD24
= 24V, V
IN_
AT THE PIN,
R
REFDI
= 5.2k, R
IN
= 1k,
WIRE-BREAK ON
3
4
5
6
7
-50 -25 025 50 75 100 125
INPUT VOLTAGE THRESHOLD (V)
TEMPERATURE (C)
INPUT VOLTAGE THRESHOLD
vs. TEMPERATURE
toc21
V
DD24
= 24V, R
IN
= 0
LOW-TO-HIGH
HIGH-TO-LOW
(VDD24 = 24V, VDD = VL = 3.3V, TA = +25°C, RREFDI = 7.5kΩ, RREFWB = 24kΩ, RIN = 1.5kΩ, unless otherwise noted.)
Maxim Integrated
11
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MAX22190 Octal Industrial Digital Input with Diagnostics
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0246810
V
DD
SUPPLY CURRENT (mA)
SPI DATA RATE (MHz)
V
DD
SUPPLY CURRENT
vs. DATA RATE toc29
V
DD24
UNCONNECTED, V
DD
= V
L
= 3.3V,
ALL V
IN_
= 0V,
CS = GND, DAISY-CHAIN MODE,
SDI = 01010101 PATTERN
Typical Operating Characteristics (continued)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
010 20 30 40 50
WIRE-BREAK CURRENT (mA)
R
REFWB
(kΩ)
WIRE-BREAK CURRENT THRESHOLD
vs. R
REFWB
toc23
3.20
3.24
3.28
3.32
3.36
3.40
-50 -25 025 50 75 100 125
V
DD
OUTPUT VOLTAGE (V)
TEMPERATURE (C)
LDO OUTPUT VOLTAGE
vs. TEMPERATURE
toc26
I
VDD
= 5mA
10
15
20
25
30
35
40
510 15 20 25 30 35 40
SHORT-CIRCUIT CURRENT (mA)
SUPPLY VOLTAGE (V)
LDO SHORT-CIRCUIT CURRENT
vs. V
DD24
SUPPLY VOLTAGE
toc27
THERMAL SHUTDOWN TRIGGERED WHEN
V
DD24
> 40V AND V
DD
SHORT TO GND
3.20
3.23
3.26
3.29
3.32
3.35
515 25 35 45 55 65
V
DD
OUTPUT VOLTAGE (V)
V
DD24
SUPPLY VOLTAGE (V)
LDO LINE REGULATION
toc25
I
VDD
= 5mA
10
15
20
25
30
35
40
-40 -15 10 35 60 85
SHORT-CIRCUIT CURRENT (mA)
TEMPERATURE (C)
LDO SHORT-CIRCUIT CURRENT
vs. TEMPERATURE
toc28
THERMAL SHUTDOWN TRIGGERED T
A
>
85C
MAX22190 Octal Industrial Digital Input with Diagnostics
www.maximintegrated.com Maxim Integrated
12
Pin Configurations
MAX22190
TQFN
5mm x 5mm
TOP VIEW
SCLK
LATCH
SDO
FAULT
READY
CS
V
DD
M1
M0
GND
REFDI
REFWB
9 10
LED2
12 13 14 15
IN3
LED3
IN7
LED7
IN6
LED6
SDI V
DD24
11
IN4 IN5
LED4 LED5
+
IN2
LED8
LED1
IN8
V
L
GND
16
IN1 24
23
22
21
20
19
18
17
252627
282930
31
32
2
1
3
4
5
6
7
8
PIN NAME FUNCTION
POWER SUPPLY
16 VLLogic Interface Supply, 3.0V to 5.5V. Bypass to GND with a 0.1μF capacitor in parallel with a
1μF capacitor.
25, 32 GND Ground return for all data inputs and the field power supply.
30 VDD24 24V field supply. Bypass to GND with 0.1µF capacitor in parallel with 1µF capacitor.
31 VDD
3.3V Output from integrated LDO when powered from VDD24, or 3.0 - 5.5V Supply Input
when VDD24 not driven. Bypass to GND with 0.1µF capacitor in parallel with 1µF capacitor. If
powering MAX22190 from an external supply, leave VDD24 unconnected.
EP Exposed Pad. Connect to GND. Solder entire exposed pad area (EP = exposed pad on back
of package) to ground plane for best thermal performance.
SPI INTERFACE
9CS Chip-Select Input. Assert low to latch input states and enable the SPI interface.
10 SCLK Serial Clock Input.
11 SDI Serial Data Input. Data is clocked into SDI on the rising edge of SCLK.
12 LATCH
LATCH and CS control the data latch at the input of the serializer (after the inputs). The latch
is transparent when both CS and LATCH are high. The data at the input of the serializer is
frozen on the falling edge of either LATCH or CS. LATCH is typically used to synchronize
input timing across multiple MAX22190s.
13 SDO Serial Data Output. Data is updated on the falling edge of SCLK. When CS is high SDO is
high-Z.
14 FAULT
Active-Low Fault Indicator. Open-drain output, FAULT goes low to indicate that one or
more of the flags in the FAULT registers have been set. The faults are: Supply Monitors,
Temperature Monitors, CRC error, wire-break errors, short or open at REFDI or REFWB pins.
15 READY Open-Drain Output. READY goes low indicating that MAX22190 is powered and ready for
operation.
CONFIGURATION PINS
26 REFWB Wire-Break Current-Limit Reference Resistor. Connect a resistor from REFWB to GND to set
Wire-Break threshold.
27 REFDI Digital Input Current-Limit Reference Resistor. For 24V Type 1 and Type 3 inputs, place a
7.5kΩ resistor from REFDI to GND.
28 M0 SPI Control Mode. See Table 1 for details.
29 M1
INPUT PINS
1, 3, 5, 7,
18, 20, 22, 24
IN1–IN8,
respectively
Field inputs. For type 1 and type 3 inputs, place a 1.5kΩ resistor between the field input and
IN_. Capacitors for filtering should not be connected to the IN_ pins. See the Surge Protec-
tion of Field Inputs section for further information.
2, 4, 6, 8,
17, 19, 21, 23
LED1–LED8,
respectively Energyless LED Driver Outputs. Connect to GND if LEDs are not used.
MAX22190 Octal Industrial Digital Input with Diagnostics
www.maximintegrated.com Maxim Integrated
13
Pin Description
MAX22190 Octal Industrial Digital Input with Diagnostics
www.maximintegrated.com Maxim Integrated
14
Functional/Block Diagram
VL
GND
READY
VDD24
INPUT CHANNEL 8
REFWB
FILTER
REFDI
FILTER
REF_WB
REF_DI
3.3V
REGULATOR
TEMPERATURE
MONITOR
SUPPLY
MONITOR
IN1
LED1
INPUT CHANNEL 1,
TYPICAL OF 8
IN8
LED8
VDD
REFWB
REFDI
LATCH
REFERENCE
GENERATORS
REF_WB
REF_DI
M1
M0
S
E
R
I
A
L
I
Z
E
R
L
A
T
C
H
CONTROL REGISTERS
FAULT
SDI
SCLK
CS
SDO
Type 1 Limiis Type : Liiniis on Region Transition On Regiun on Regiun On Region on Region hansilion on Region VL iL VT iT VH iH VL iL VT iT VH IH VL iL VT iT VH M (V) ("W (V) (WA) (V) (MA) (V) WA) (V) (MA) (V) ("W (V) (MA) (V) ("W (V) (WA) Max 15/5 is 15 i5 an is ii/5 30 ii an 30 an ii/s 15 ii is an i5 Min 73 ND 5 us is 2 73 ND 5 2 ii 6 73 ND s is ii 2
Detailed Description
The MAX22190 senses the state (on, high or off, low) of
eight digital inputs. The voltages at the IN1–IN8 input pins
are compared against internal references to deter mine
whether the sensor is on (logic 1) or off (logic 0). All eight
inputs are simultaneously latched by the assertion of either
LATCH or CS, and the data made available in a serial-
ized format through the SPI interface. Placing a 7.5kΩ
current-setting resistor between REFDI and GND, and a
1.5kΩ or 1kΩ resistor between each field input and the
corresponding IN_ input pin ensures that the current at
the ON and OFF trip points as well as the voltage at
the trip points satisfy the requirements of IEC 61131-2
for Type 1 and Type 3 inputs. The current sunk by each
input pin rises linearly with input voltage until the level
set by the current limiter is reached; any volt age increase
beyond this point does not increase the input current.
Limiting the input current ensures compliance with IEC
61131-2 while significantly reducing power dissipation
compared to traditional resistive inputs.
The current-setting resistor RREFDI can be calculated
using this equation:
R
REFDI = 17.63V/IINLIM
Figure 2. Switching Characteristics for IEC61131-2 Type 1, 2, and 3 24VDC Digital Inputs
MAX22190 Octal Industrial Digital Input with Diagnostics
www.maximintegrated.com Maxim Integrated
15
V
Lmin
Type
of
Limit
Type 1 Limits
Type 2 Limits
Type 3 Limits
Off Region
Transition
On Region
Off Region
Transition
On Region
Off Region
Transition
On Region
VL
(V)
IL
(mA)
VT
(V)
IT
(mA)
VH
(V)
IH
(mA)
VL
(V)
IL
(mA)
VT
(V)
IT
(mA)
VH
(V)
IH
(mA)
VL
(V)
IL
(mA)
VT
(V)
IT
(mA)
VH
(V)
IH
(mA)
Max
15/5
15
15
15
30
15
11/5
30
11
30
30
30
11/5
15
11
15
30
15
Min
-3
ND
5
0.5
15
2
-3
ND
5
2
11
6
-3
ND
5
1.5
11
2
0
I
IN
(mA)
V
IN
(V)
OFF REGION
ON REGION
TRANSITION REGION
V
H max
V
Hmin
or V
Tma x
I
Hmin
I
H max
I
Lmin
I
Lmax
V
Lmax
or V
Tmin
I
Tmin
I
Tmax
STANDARD OPERATING RANGE FOR 24V DC DIGITAL INPUTS (C URREN T SINKI NG)
V
Lmax
ND = NOT DEFINED
was; comm m 5mm
Input Filters
Each input (IN1–IN8) has a programmable filter and
input data may be filtered to reduce noise, or it may
be read directly for more rapid response. The input is
sampled and data is updated at 1MHz (typ) when the
input filter is disabled. When the digital filter is enabled,
the input is sampled at 200kHz (typ). Bit FBP in the
corresponding FLTx register is used to bypass the filter or
to enable the filter. One of eight filter delays (50µs, 100µs,
400µs, 800µs, 1.6ms, 3.2ms, 12.8ms, 20ms) may be
independently selected for each channel. Noise rejection
is accomplished through a no-rollover up-down counter
where the state of the field input controls the counting
direction (up or down), the filter uses an up-down counter
fed by a 200kHz clock. If the input is high, it counts up; if
the input is low, it counts down. The filter output is updat-
ed when the counter hits the upper or lower limit, with the
upper limit depending on the selected filter delay and the
lower limit being zero regardless of the filter delay. The
low-to-high transition of the filter occurs when the counter
reaches the upper limit. The high-to-low transition occurs
when the counter reaches the lower limit. There is no
rollover; counting simply stops when the upper or lower
limit is hit. The filter delay is the time it takes to reach the
upper/lower limit in response to a step input when the
counter starts from the lower/upper limit. If the input is not
a step function, but is bouncing, as shown in Figure 3, the
output changes state after a total delay of:
Total Delay = Filter Delay + 2 × (Total Time at the Old State)
In the example in Figure 3, the filter has a nominal delay
of 1.6ms, and the input returns high for two 0.2ms periods
after the first transition from high to low. These transitions
back to the high state extend the time before the output
of the filter switches. Total Delay = 1.6ms + 2 × (0.2ms +
0.2ms) = 2.4ms.
Figure 3. MAX22190 Digital Filter
MAX22190 Octal Industrial Digital Input with Diagnostics
www.maximintegrated.com Maxim Integrated
16
UP/DOWN
COUNTER
(NO ROLLOVER)
REFIN
CLK
TRANSPARENT
LATCH
CS
LATCH
TO SERIALIZER
COUNTER FS CONTROL
50μs TO 20ms
INx
M
U
X
BYPASS CONTROL
FILTER BYPASS
REFWB
CS
LATCH WB STICKY
LATCH TO SERIALIZER
S
20ms
FILTER
CLEAR-ON-READ
SATURATED HIGH (1.6ms)
OUTPUT IS HIGH
SWITCH THRESHOLD = 0.0ms
AT 0.0ms,
OUTPUT SWITCHES FROM HIGH TO LOW
SWITCHING THRESHOLD SET TO FULL SCALE (1.6ms)
INx
COUNTER VALUE
OUTPUT
1.6ms
1.1ms
1.3ms
0.8ms
1.0ms
0.0ms
0.0ms
0.5ms
0.7ms
1.2ms
1.4ms
2.4ms
TOTAL TIME AFTER FIRST EDGE
1MHz SAMPLING
FULL
SCALE
0
Q
Q
R
S
R
200kHz
UP/DOWN
Wire-Break Detection
Each input (IN1 IN8) includes a second threshold
comparator that can be individually enabled to verify the
integrity of field wiring. The comparator senses the pres-
ence of the small input current produced by a two wire
proximity sensor in its open state, or the current from an
open switch with a diagnostic resistor placed across it.
The wire-break current threshold is set by placing a resis-
tor between REFWB and GND, and is adjustable from
50µA to 470µA. If this current is missing, due to an open
wire or a wire shorted to GND, the comparator trips, and
after filtering, sets a corresponding sticky bit in the WB
register. Bits in this register remain set until the register is
read, which automatically clears all bits in the register. All
wire-break detectors include a fixed 20ms filter, and like
the input data, the input to the WB latch is frozen when
either CS or LATCH is held low. The eight wire-break
flags are ORed together to produce the WBG flag in the
FAULT1 register. This flag remains set until all flags in the
WB register have been cleared.
The wire-break threshold resistor RREFWB can be calcu-
lated using this equation:
RREFWB = 2.44V / IWB
Energyless LED Drivers
When IN_ is determined to be on, its input current is
diverted to the LED pin and flows from that pin to GND.
Placing an LED between LED_ and GND provides an
indication of the input state without increasing overall
power dissipation. If the indicator LEDs are not used, connect
LED_ to GND.
Fault Detection and Monitoring
FAULT is an open-drain output that can be wire ORed
with the other open-drain outputs and used to notify the
host processor of a fault. When enabled, FAULT goes low
to indicate that one or more of the flags in the FAULT1
register have been set. These faults are: VDD24 low
voltage alarm (24VL), VDD24 voltage missing alarm
(24VM), overtemperature alarm 1 (ALRMT1), overtem-
perature alarm 2 (ALRMT2), CRC error detected on the
previous SPI frame (CRC), Power-On-Reset event (POR),
wire-break group error detected (WBG), and sources
from FAULT2 register. Enable bits in the FAULT1EN and
FAULT2EN registers select which flags in the FAULT1
and FAULT2 registers asserts the FAULT pin. The enable
bits do not affect the flags in the FAULT1 register, they
only affect the FAULT pin. Flags ALRMT1, ALRMT2,
24VL, and 24VM in the FAULT1 register are latched; they
remain set until read even if the fault goes away. WBG is
equivalent to the ORed output of the individual wire-break
flags WB[7:0] which are latched until cleared by reading
the WB register. CRC is not latched, but remains set until
an uncorrupted SPI frame is received.
The STK bit in the GPO register configures the FAULT
pin to be sticky or to clear when the fault is removed. For
example: if a low voltage condition on VDD24 is detected,
the 24VL bit in the FAULT1 register is set and FAULT
asserts low provided bit 24VLE in the FAULT1EN register
is set. If VDD24 then returns to normal levels, the 24VL bit
in the FAULT1 register remains set until read; however
the state of FAULT pin depends on configuration bit STK.
If STK = 0, the FAULT pin is not sticky and clears when
the fault goes away even though the 24VL bit remains
set. If STK = 1, then FAULT pin reflects the state of the
bit in the FAULT1 register and remains set until the bit is
cleared by reading the FAULT1 register. The minimum
pulse width for FAULT pin asserting low is 1µs typical.
This ensures adequate time for the assertion of FAULT
to be recognized by the host even if the fault was present
for a shorter time.
The power-on default for the FAULT1EN register is to
enable CRC and POR. FAULT pin is in the non-sticky mode.
MAX22190 Octal Industrial Digital Input with Diagnostics
www.maximintegrated.com Maxim Integrated
17
«XOIOOIOIOXNOMNIOI 7 V
Clearing Bits in FAULT1 Register
24VL and 24VM sticky (or latched) bits in the FAULT1 reg-
ister may be read and cleared either through a direct read
of the FAULT1 register, or through a SPI mode 0 or mode
2 read or write command if bit 24VF in the CFG register is
equal to 0. SPI modes 0 and 2 transactions read and clear
bits 24VL, and 24VM (Table 3). This valid SPI transaction
also clears the CRC bit. Note that the CRC bit is only active
in modes 0 and 2 since this is the only time a CRC test is
performed. The WBG bit in the FAULT1 register is the real-
time ORed value of bits WB[7:0] in the WB register and
the WBG bit is not cleared by reading the FAULT1 register.
Reading the bits in the WB register clears the WB register
and for convenience also clears the WBG bit in the FAULT1
register.
CRC Generation
In SPI interface modes 0 and 2, five CRC bits can be used
to check data integrity during transfer between the device
and an external microcontroller. In applications where the
integrity of data transferred is not of concern, the CRC bits
can be disabled by operating in SPI modes 1 and 3. The
CRC uses the following polynomial:
P(x) = x5 + x4 + x2 + x0
The 5-bit CRC value is calculated using the first 19 data
bits padded with the 5-bit initial word 00111. The 5-bit
CRC result is then appended to the original data bits to
create the 24-bit SPI data frame. When the MAX22190
receives a data frame with a CRC error, the CRC error
flag (CRC) in the FAULT1 register is set and, if CRCE is
set, FAULT pin is asserted. The CRC bit is not sticky, but
does remain set until an error-free frame is received. SPI
commands within a corrupted frame are ignored.
SPI Interface
The MAX22190 has an SPI compatible interface used to
read input data, read diagnostic data, and configure all
of the registers. Each configuration register can be read
back to ensure proper configuration. The interface can
be operated in one of four modes as controlled by the
strapping inputs M0 and M1. Asserting CS low latches
the state of all inputs and enables the SPI interface. For
all modes, data at the SDI input is sampled on the rising
edge of SCLK and data at SDO is updated on the falling
edge of SCLK. The MSB (READ/WRITE bit) is always the
first bit of the SPI frame. Transitions of SCLK while CS is
deasserted (high) are ignored. SCLK must idle low when
CS is asserted.
Table 1. SPI Interface Modes
Figure 4. SPI Communication Example
MODE M1: M0 FRAME LENGTH CRC DAISY CHAIN
0 0 0 24-bit Yes No
1 0 1 16-bit No No
2 1 0 24-bit Yes Yes
3 1 1 16-bit No Yes
MAX22190 Octal Industrial Digital Input with Diagnostics
www.maximintegrated.com Maxim Integrated
18
CS
SCLK
SDI
SDO
1 2 3 8 9 10 11 12 13 14 15 16 17 21 22 23
1* A6 A5 A4 A3 A2 A1 A0 D7 D0 0 0 0 C4 C3 C2 C1 C0
DI1 DI0 WB7 WB6 24VL HIGH-Z
DI7 DI6
HIGH-Z DI5 DI3DI4 DI2
4 5 6 7 18 19 20
D6 D5 D4 D3 D2 D1
24
WB5 WB4 WB3 WB2 WB1 WB0 24VM WBG C4 C3 C2 C1 C0
IN[8:1]
INPUTS
MODE 0 WRITE CYCLE
* Read = 0 or Write = 1
CRC[4:0] for SDI is generated by host such as MCU
CRC[4:0] for SDO is generated by MAX22190
Note: Input pins are labelled IN8 – IN1, and map to DI register bits DI7 – DI0, and WB register bits WB7 – WB0
SPI Protocol
The serial output of the device adheres to the SPI proto col,
running with CPHA = 0 and CPOL = 0. In all modes, the
first 8-bits clocked out of SDO after CS is asserted are
data bits showing the status of inputs IN8 – IN1; this
allows for rapid and convenient retrieval of the primary
data. For write operations in Modes 0 and 1, the next
8-bits clocked out of SDO are the status bits of the WB
(wire-break) register. This is true even if wire-break detection
is not enabled, in which case all bits are 0. For reads in
Modes 0 and 1, the second 8 bits are the data from the
specified register.
Modes 2 and 3 are more complex, since the content of the
second byte is determined by the previous instruction. For
non-daisy-chain compatible modes (Modes 0 and 1), the
read instruction is decoded on-the-fly as the SPI frame is
clocked in. The instruction is immediately executed and
data from the specified register is clocked out in the same
SPI frame. This is convenient and quick, but not compat-
ible with daisy-chaining. When daisy-chaining, each unit
does not know which portion of the bit stream it should
decode until CS is deasserted (the frame is finished).
To accommodate this, all daisy-chainable read instruc-
tions require two SPI frames. The first frame contains the
read instruction and register address. The second frame
returns the register data as the second byte of the frame.
This is true regardless of the instruction being clocked in
during the second frame.
LATCH is used to simultaneously capture the input states
of different MAX22190s that are not controlled by the
same CS. This could be multiple MAX22190s in the same
module, or MAX22190s in different modules.
Clock Count for Multiples of 8
For each SPI cycle (between CS going low and going
high), the device counts the number of SCLK pulses. If it
is not a multiple of 8, the SPI input data is discarded and
bit FAULT8CK is set in the FAULT2 register.
SPI Power Status
Only the SPI port buffers are powered from the VL supply;
internal SPI circuits are powered from the VDD supply.
Both VDD and VL must be valid for SPI communication to
take place. In addition to powering the SPI circuits, VDD
also sustains the SPI memory (configuration and status
registers). If power is being supplied through VDD24, then
an auxiliary supply for the memory is also available. The
auxiliary supply only sustains memory, it does not allow
SPI communication. The auxiliary supply takes over if VDD
is lost due to external loading or due to a thermal shutdown
event. When the event is over, the device configuration is
maintained and fault information is available in the FAULT
registers. Refer to Table 2 for power requirement for SPI
communication and register map configuration.
Table 2. SPI Port Power Status
VDD24 VDD VLSPI REGISTER MAP CONFIGURATION SPI PORT COMMUNICATION
Valid Valid Valid Configuration and fault data maintained Normal Operation
Not Valid Valid Valid Configuration and fault data maintained Normal Operation
Valid Not Valid XConfiguration and fault data maintained CS ignored, SDO is High-Z
X Valid Not Valid Configuration and fault data maintained CS ignored, SDO is High-Z
Not Valid Not Valid XConfiguration and fault data lost CS ignored, SDO is High-Z
MAX22190 Octal Industrial Digital Input with Diagnostics
www.maximintegrated.com Maxim Integrated
19
JLH EWMLHJME‘rLerm 171’1 ‘Emmm’1mr111m11 L Lu4111g<:e3c>CX:Lu—QQW 1— 1 fi’:)(:WCWDDDQI:Efl-DDDQIDJ "2
Daisy-Chaining
For systems with more than eight sensor inputs, mul-
tiple devices can be daisy-chained to allow access to
all data inputs through a single serial port. When using
a daisy-chain configuration, connect MOSI to SDI of the
first device in the chain. Connect MISO to SDO of the last
device in the chain. For all middle links, connect SDI to
SDO of the previous device and SDO to SDI of the next
device. CS and SCLK of all devices in the chain should be
connected together in parallel, see Figure 5 which illus-
trates a 16-input application for daisy-chaining and Figure 6,
which shows SPI timing.
Figure 5. SPI Daisy-Chain Operation
Figure 6. SPI Timing Diagram Daisy-Chain
MAX22190 Octal Industrial Digital Input with Diagnostics
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20
CS
MISO
MOSI
SCLK
MICROCONTROLLER
GPI
V
L
CS
SCLK
SDI SDO
MAX22190
DEVICE B
FAULT
V
L
CS
SCLK
SDI SDO
MAX22190
DEVICE A
FAULT
V
L
RPULLUP
LATCH LATCH
+3.3V
+3.3V +3.3V
CS
SCLK
SDI
A
SDOA
SDIB
8 9 10 16
HIGH-Z
SDOB
...
...
1 24 25 26 32......17
0
0 ... 0
“X”
“X” “X”
... HIGH-Z
HIGH-Z
RAA0A
MODE 3, DAISY CHAIN READ
A6A
218
RB00A0B0
A6B
“X” “X”
8 9 10 16......1 24 25 26 32......17
2 18
RB00
A0B... 0
A6B
Frame 1 Frame 2
IN8AIN1A...
IN7AD7AD0A
HIGH-Z
IN8BIN1B...
IN7BD7BD0BIN8AIN1A...
IN7AD7AD0A
“X”
Configuration Flowchart
The MAX22190 powers on with default register settings
and can be used in default mode to read the data inputs,
or it can be configured to match the individual application
requirements. Before any register access for configuration
or reading data, the MCU needs to wait until READY goes
low indicating that the MAX22190 is powered up and
ready for use. Next, the MCU needs to clear the FAULT
pin that asserts low after every power-up event due to the
default state (high) of the POR flag.
Default Mode: (Power-up mode) In this mode, the
Wire-Break (WB) function is disabled, all input channel
filters (FLTx) are set to BYPASS, all input channels are
enabled, and all fault sources are disabled on FAULT pin
except the CRC and POR flags. Upon power-up, the POR
flag is set to 1. If the FAULT pin is being used, then a write
operation must be performed to the FAULT1 register to
reset POR to 0 for normal operating conditions. Now the
MAX22190 can be polled to read data from DI register to
show the logic state of the 8 input channels.
Configurable Mode: The MAX22190 can be configured
for different parameters based upon the application
requirements. The MCU can write to the various registers
to set the options for Wire-Break, Input Channel Filters,
enabling different Fault Sources, or disabling specific
Input Channels. In addition, the user can enable features
such as detecting a short on pin REFDI and making FAULT
pin sticky or not. Once the configuration is complete,
the MAX22190 can be polled to read from DI register
to show the logic state of the 8 input channels.
FAULT Asserted: The MAX22190 uses the open-drain
FAULT pin to indicate to the MCU that a Fault has
occurred, often by using this pin to trigger an interrupt
function within the MCU. The MCU can determine the
source of the fault by reading regsiter FAULT1. If bit 5 of
FAULT1 is set, then register FAULT2 is indicating a fault
and FAULT2 must also be read. Reading the FAULT_
register clears the fault flag, unless the fault condition
persists, which would immediately reset the flag.
MAX22190 Octal Industrial Digital Input with Diagnostics
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J \/ \ / \ /\ /\ / \ rK / \ < é;="">
Figure 7. MAX22190 Configuration Flowchart
MAX22190 Octal Industrial Digital Input with Diagnostics
www.maximintegrated.com Maxim Integrated
22
POWER UP
Wait until MAX22190 is Powered Up
Y
N
READY
asserted
FAULT1: POR bit = 1
FAULT
asserted
READY LOW?
DEFAULT MODE?
Y N
MAX22190 Configured for User Defined Modes
MAX22190 Operates in Default Modes
FLT1 to FLT8
VALUE = 0x08
WB DISABLED
VALUE = 0x00
INEN
VALUE = 0xFF
FAULT1EN
VALUE = 0xC0
All Input Channels are Enabled for
Reading Data
All Fault Sources disabled except
CRC and POR
WRITE FAULT1,
SET POR BIT = 0
READ DI
Wire-Break Feature is Disabled
All Input Channel Filters are set to
Bypass
Clear POR
FAULT
deasserted
Read Input Data (polling)
WRITE FLT1 to FLT8
WRITE WB
WRITE FAULT2EN
WRITE FAULT1EN
Enable individual Fault Sources
Enable individual Fault Sources
WRITE FAULT1,
SET POR BIT = 1
READ DI
Wire-Break Feature can be
enabled on a per channel basis
Input Channel Filters can be set on
a per channel basis
Clear CRC and POR
FAULT
deasserted
Read Input Data (polling)
WRITE CFG, SET CLRF
OR REFDI_SH_ENA BITS
WRITE GPO,
SET STK BIT
Make
FAULT
pin sticky or not
Fix filters at mid-scale, enable
detection of short on REFDI
NORMAL OPERATION
Determine Fault source, Clear bit on read
Is FAULT in register FAULT1 or FAULT2?
FAULT INTERRUPT
Y
NFAULT LOW?
READ FAULT1
READ FAULT1
10 Bit 5: FAULT2 ?
READ FAULT2
Error is in FAULT1 Error is in FAULT2
SERVICE FAULT
SOURCE
FAULT2 is Clear-On-Read
SERVICE FAULT
SOURCE
FAULT LOW?
Some FAULT1 flags
are latched
Ensure FAULT
condition is cleared
Y
N
FAULT LOW?
NORMAL OPERATION
N
Y
Table 3. SPI Frames for SPI Modes
Mode 0: M1 = 0, M0 = 0
Write
SDI MSB = 1
1-bit
Register Address
7-bits
Write Data
8-bits
000 Fill Data
3-bits
CRC from Host LSB
5-bits
SDO Input data: IN8 – IN1
8-bits
WB data: WB7 – WB0
8-bits 24VL 24VM WBG CRC from MAX22190
5-bits
Read
SDI MSB = 0
1-bit
Register Address
7-bits
00000000 Fill Data
8-bits
000 Fill Data
3-bits
CRC from Host LSB
5-bits
SDO Input data: IN8 – IN1
8-bits
Register Data: D7 – D0
8-bits 24VL 24VM WBG CRC from MAX22190
5-bits
Mode 1: M1 = 0, M0 = 1
Write
SDI MSB = 1
1-bit
Register Address
7-bits
Write Data
8-bits
SDO Input data: IN8 – IN1
8-bits
WB data: WB7 – WB0
8-bits
Read
SDI MSB = 0
1-bit
Register Address
7-bits
00000000 Fill Data
8-bits
SDO Input data: IN8 – IN1
8-bits
Register Data: D7 – D0
8-bits
Mode 2: M1 = 1, M0 = 0
Write – Preceding frame was a write or no-op
SDI MSB = 1
1-bit
Register Address
7-bits
Write Data
8-bits
000 Fill Data
3-bits
CRC from Host LSB
5-bits
SDO Input data: IN8 – IN1
8-bits
WB data: WB7 – WB0
8-bits 24VL 24VM WBG CRC from MAX22190
5-bits
Write – Preceding frame was a read
SDI MSB = 1
1-bit
Register Address
7-bits
Write Data
8-bits
000 Fill Data
3-bits
CRC from Host LSB
5-bits
SDO Input data: IN8 – IN1
8-bits
Register Data: D7 – D0
8-bits 24VL 24VM WBG CRC from MAX22190
5-bits
Read – Preceding frame was a write or no-op
SDI MSB = 0
1-bit
Register Address
7-bits
00000000 Fill Data
8-bits
000 Fill Data
3-bits
CRC from Host LSB
5-bits
SDO Input data: IN8 – IN1
8-bits
WB data: WB7 – WB0
8-bits 24VL 24VM WBG CRC from MAX22190
5-bits
MAX22190 Octal Industrial Digital Input with Diagnostics
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23
Notes:
SDI – CRC generated by external device such as MCU, Data D7 - D0 clocked out from MCU
SDO – CRC generated by MAX22190, Data D7 - D0 clocked out from MAX22190 Register
NO-OP – No Operation, i.e. write cycle with no valid data to specified address
Write Cycle – DI[7:0] and WB[7:0] are from internal latches, whose outputs are frozen when CS or LATCH goes low. Bits 24VL,
24VM and WBG are frozen by CS going low but not by LATCH.
Read Cycle – D7 - D0 are the register data addressed through SDI. Bits 24VL, 24VM, and WBG reflect the corresponding bits in the
FAULT1 register.
Input Channel pins are numbered IN1 – IN8, so input IN1 maps to bit DI0, input IN2 to bit DI1 …. and input IN8 to bit DI7
Table 3: SPI Frames for SPI Modes (continued)
Read – Preceding frame was a read
SDI MSB = 0
1-bit
Register Address
7-bits
00000000 Fill Data
8-bits
000 Fill Data
3-bits
CRC from Host LSB
5-bits
SDO Input data: IN8 – IN1
8-bits
Register Data: D7 – D0
8-bits 24VL 24VM WBG CRC from MAX22190
5-bits
Mode 3: M1 = 1, M0 = 1
Write – Preceding frame was a write or no-op
SDI MSB = 1
1-bit
Register Address
7-bits
Write Data
8-bits
SDO Input data: IN8 – IN1
8-bits
WB data: WB7 – WB0
8-bits
Write – Preceding frame was a read
SDI MSB = 1
1-bit
Register Address
7-bits
Write Data
8-bits
SDO Input data: IN8 – IN1
8-bits
Register Data: D7 – D0
8-bits
Read – Preceding frame was a write or no-op
SDI MSB = 0
1-bit
Register Address
7-bits
00000000 Fill Data
8-bits
SDO Input data: IN8 – IN1
8-bits
WB data: WB7 – WB0
8-bits
Read – Preceding frame was a read
SDI MSB = 0
1-bit
Register Address
7-bits
00000000 Fill Data
8-bits
SDO Input data: IN8 – IN1
8-bits
Register Data: D7 – D0
8-bits
MAX22190 Octal Industrial Digital Input with Diagnostics
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Table 4. Register Map
Register Type Legend:
R: Read only
RW: Read and Write
COR: Clear-On-Read
MIXED: Some bits are Clear-On-Read type, others are cleared differently. See bit descriptions for details.
REGISTER ADDRESS SYMBOL TYPE POR
(DEFAULT) 76543210
Wire Break 00h WB COR 00h WB7 WB6 WB5 WB4 WB3 WB2 WB1 WB0
Digital Input 02h DI R00h DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
Fault 1 04h FAULT1 MIXED 46h CRC POR FAULT2 ALRMT2 ALRMT1 24VL 24VM WBG
Filter IN1 06h FLT1 RW 08h 0 0 0 WBE FBP DELAY[2:0]
Filter IN2 08h FLT2 RW 08h 0 0 0 WBE FBP DELAY[2:0]
Filter IN3 0Ah FLT3 RW 08h 0 0 0 WBE FBP DELAY[2:0]
Filter IN4 0Ch FLT4 RW 08h 0 0 0 WBE FBP DELAY[2:0]
Filter IN5 0Eh FLT5 RW 08h 0 0 0 WBE FBP DELAY[2:0]
Filter IN6 10h FLT6 RW 08h 0 0 0 WBE FBP DELAY[2:0]
Filter IN7 12h FLT7 RW 08h 0 0 0 WBE FBP DELAY[2:0]
Filter IN8 14h FLT8 RW 08h 0 0 0 WBE FBP DELAY[2:0]
Configuration 18h CFG RW 00h 0 0 0 24VF CLRF 0 0 REFDI_
SH_ENA
Input Enable 1Ah INEN RW FFh CH[7] CH[6] CH[5] CH[4] CH[3] CH[2] CH[1] CH[0]
Fault 2 1Ch FAULT2 COR 02h 0 0 FAULT8CK OTSHDN RFDIO RFDIS RFWBO RFWBS
Fault 2
Enables 1Eh FAULT2EN RW 00h 0 0 FAULT8CKE OTSHDNE RFDIOE RFDISE RFWBOE RFWBSE
GPO 22h GPO RW 00h STK 0 0 0 0 0 0 0
Fault 1
Enables 24h FAULT1EN RW C0h CRCE PORE FAULT2E ALRMT2E ALRMT1E 24VLE 24VME WBGE
No-Op 26h NOP NA -Dummy register. Contents of registers DI and WB are clocked out normally during
attempted SPI writes to this register. Useful for Daisy-Chain mode.
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WB (Clear-On-Read)
Address = 0x00
Default = 0x00
BIT NAME DESCRIPTION
7:0 WB[7:0]
0: No Wire-Break condition detected for channel x
1: Wire-Break condition detected for channel x
Wire-break status for each channel. The bit remains high even if the wire-break condition disappears and is only
cleared upon reading the register. Not cleared if the wire-break condition is still present upon reading the register.
Note: Input Channels are numbered IN1–IN8, so IN1 maps to WB0, IN2 to WB1... and IN8 to WB7.
Register Detailed Description
DI (Read)
Address = 0x02
Default = 0x00
BIT NAME DESCRIPTION
7:0 DI[7:0]
0: Channel x is driven low
1: Channel x is driven high
Digital input state. DI_ is the state of the corresponding input pin.
Note: Input Channels are numbered IN1–IN8, so IN1 maps to DI0, IN2 to DI1... and IN8 to DI7.
FAULT1 (Mixed)
Address = 0x04
Default = 0x46
BIT NAME DESCRIPTION
7CRC
0: The last received SPI frame was not corrupted
1: The last received SPI frame was corrupted
It is not cleared upon read, but when an uncorrupted SPI frame is received.
CRC is only active in SPI Interface Modes 0 and 2
6POR
0: Normal operating conditions
1: POR event has reset the register map to its power-on-reset state
This bit is cleared only if the user writes “0” to it. The other bits in this register are unaffected by the write
access.
5FAULT2
0: An enabled bit in the FAULT2 register is not set
1: An enabled bit in the FAULT2 register is set
This bit is cleared on read only if the FAULT2 register is cleared or the bit is disabled.
4ALRMT2*
0: Temperature Alarm 2 threshold has not been exceeded
1: Temperature Alarm 2 threshold has been exceeded
Cleared upon reading this register.
3ALRMT1*
0: Temperature Alarm 1 threshold has not been exceeded
1: Temperature Alarm 1 threshold has been exceeded
Cleared upon reading this register.
224VL*
0: 24V supply is normal (above the 24VL threshold)
1: 24V supply is low (below the 24VL threshold)
Cleared upon reading this register. If bit 4 in CFG Register (24VF) is 0, 24VL can also be cleared after any
SPI transaction while operation in modes 0 or 2.
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FLT1 to FLT8 (Read/Write)
Address = 0x06 0x14 (increments of 2)
Default = 0x08
BIT NAME DESCRIPTION
7:5 0 Reserved
4 WBE
0: Wire-Break detection is disabled for channel x
1: Wire-Break detection is enabled for channel x
If WBE = 0 the corresponding WBx bit is always low and the WB detection circuits for channel x are off.
The REFWB resistor on pin REFWB can be removed if the WBE bits of all the channels are low.
The RFWBO bit in the FAULT2 register is set if WBE bits of all channels are low.
3FBP 0: Programmable filter on INx is used
1: Programmable filter on INx is bypassed
2:0 DELAY[2:0]
Programmable filter values for INx (the WBx filter value is 20ms and is not programmable).
DELAY[2:0] = 000 = 50µs
DELAY[2:0] = 001 = 100µs
DELAY[2:0] = 010 = 400µs
DELAY[2:0] = 011 = 800µs
DELAY[2:0] = 100 = 1.6ms
DELAY[2:0] = 101 = 3.2ms
DELAY[2:0] = 110 = 12.8ms
DELAY[2:0] = 111 = 20ms
BIT NAME DESCRIPTION
124VM*
0: 24V supply is normal (above the 24VM threshold)
1: 24V supply is missing (below the 24VM threshold)
Cleared upon reading this register. If bit 4 in CFG Register (24VF) is 0, 24VM can also be cleared after any
SPI transaction while operation in modes 0 or 2.
0WBG
0: No bit in the WB register is set
1: One or more bits in the WB register are set
Cleared upon reading the WB register.
*These flags are “latched” and they remain set until read even if the fault goes away, and are not cleared if the fault condition is still
present when the register is read.
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CFG (Read/Write)
Address = 0x18
Default = 0x00
BIT NAME DESCRIPTION
7:5 0 Reserved
424VF
0: Flags 24VL and 24VM are cleared after any full frame SPI transaction or by reading the FAULT1 register
1: 24VL and 24VM are cleared only by reading the FAULT1 register
Only affects SPI modes 0 and 2.
3CLRF
0: Filters (INx and WBx) operate normally
1: All the filters (INx and WBx) are fixed at the mid-scale value for the chosen delay
The filters resume normal operation when CLRF is cleared.
2:1 0 Reserved
0REFDI_
SH_ENA
0: Disables the detection of a short-circuit condition on the REFDI pin
1: Enables the detection of a short-circuit condition on the REFDI pin
INEN (Read/Write)
Address = 0x1A
Default = 0xFF
BIT NAME DESCRIPTION
7:0 CH[7:0] 0: CH[x] = 0, INx is disabled and the current source is set to 0mA and the DIx bit in the DI register is set to
0.
1: CH[x] = 1, INx is enabled
Note: Input channels are numbered IN1–IN8, so IN1 maps to CH0, IN2 to CH1... and IN8 to CH7.
FAULT2 (Clear-On-Read)
Address = 0x1C
Default = 0x02
BIT NAME DESCRIPTION
7:6 0 Reserved
5FAULT8CK 0: SPI receives a number of clock pulses equal to a multiple of eight, valid transaction
1: SPI receives a number of clock pulses not equal to a multiple of eight, the SPI command is rejected
4OTSHDN
0: Normal operating conditions
1: Overtemperature shutdown (the safe operating temperature has been exceeded).
Overtemperature Shutdown: all inputs and LED drivers are turned off to reduce power dissipation and
protect the device. The SPI interface and internal regulator remain active and if the temperature continues
to rise, the regulator will be turned off.
3RFDIO
0: Normal operating conditions
1: Open condition is detected on the REFDI pin
This bit remains 1 even if the fault condition disappears and is cleared upon reading this register.
This bit is 1 when thermal shutdown happens, because REFDI function turns off in thermal shutdown.
No action on the input channels when this condition occurs.
2RFDIS
0: Normal operating conditions
1: Short condition is detected on the REFDI pin
The bit remains 1 even if the fault condition disappears and is cleared upon reading this register.
All the input channels are disabled as long as the short condition on REFDI is present.
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FAULT2EN (Read/Write)
Address = 0x1E
Default = 0x00
BIT NAME DESCRIPTION
7:6 0 Reserved
5FAULT8CKE 0: Disable bit FAULT2 in FAULT1 Register
1: Enable bit FAULT2 in FAULT1 register to be set when FAULT8CK is high
4OTSHDNE 0: Disable bit FAULT2 in FAULT1 Register
1: Enable bit FAULT2 in FAULT1 register to be set when OTSHDN is high
3RFDIOE 0: Disable bit FAULT2 in FAULT1 Register
1: Enable bit FAULT2 in FAULT1 register to be set when RFDIO is high
2RFDISE 0: Disable bit FAULT2 in FAULT1 Register
1: Enable bit FAULT2 in FAULT1 register to be set when RFDIS is high
1RFWBOE 0: Disable bit FAULT2 in FAULT1 Register
1: Enable bit FAULT2 in FAULT1 register to be set when RFWBO is high
0RFWBSE 0: Disable bit FAULT2 in FAULT1 Register
1: Enable bit FAULT2 in FAULT1 register to be set when RFWBS is high
GPO (Read/Write)
Address = 0x22
Default = 0x00
BIT NAME DESCRIPTION
7 STK
0: FAULT pin is not sticky. FAULT condition is determined by the logical OR of the unmasked real-time
FAULT1 register sources, and not the FAULT1 register bits.
1: FAULT pin is sticky. If at least one bit in the FAULT1 register is set and unmasked, FAULT remains low
until FAULT1 register is read (Figure 8).
6:0 0 Reserved
BIT NAME DESCRIPTION
1RFWBO
0: Normal operating conditions
1: Open condition is detected on the REFWB pin
This bit remains 1 even if the fault condition disappears and is cleared upon reading this register.
This bit is 1 when thermal shutdown happens, because REFWB function turns off in thermal shutdown.
This bit is 1 after power-on-reset when all input channels’ wire-break detection functions are off.
No action on the input channels when this condition occurs and one or more channels’ wire-break function
is enabled.
0RFWBS
0: Normal operating conditions
1: Short condition is detected on the REFWB pin
This bit remains 1 even if the fault condition disappears and is cleared upon reading this register.
No action on the input channels when this condition occurs and one or more channels’ wire-break function
is enabled.
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FAULT1EN (Read/Write)
Address = 0x24
Default = 0xC0
BIT NAME DESCRIPTION
7CRCE 0: FAULT pin is not asserted when CRC is 1
1: FAULT pin is asserted when CRC is 1
6PORE 0: FAULT pin is not asserted when POR is 1
1: FAULT pin is asserted when POR is 1
5FAULT2E 0: FAULT pin is not asserted when FAULT2 is 1
1: FAULT pin is asserted when FAULT2 is 1
4ALRMT2E 0: FAULT pin is not asserted when ALRMT2 is 1
1: FAULT pin is asserted when ALRMT2 is 1
3ALRMT1E 0: FAULT pin is not asserted when ALRMT1 is 1
1: FAULT pin is asserted when ALRMT1 is 1
2 24VLE 0: FAULT pin is not asserted when 24VL is 1
1: FAULT pin is asserted when 24VL is 1
1 24VME 0: FAULT pin is not asserted when 24VM is 1
1: FAULT pin is asserted when 24VM is 1
0WBGE 0: FAULT pin is not asserted when WBG is 1
1: FAULT pin is asserted when WBG is 1
NOP (N/A)
Address = 0x26
Default = N/A
BIT NAME DESCRIPTION
7:0 NOP[7:0] Dummy register. DI[7:0] and WB[7:0] bits are clocked out normally during attempted writes to this register.
Useful for Daisy-Chain mode.
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nun: REGISYER mm nzomzx wa 52:stsz
Applications Information
Power Supply Sequencing
The MAX22190 does not require special power sup-
ply sequencing. The SPI interface logic level (VL) is set
independently from the field supply (VDD24) or LDO out-
put (VDD) levels.
Power Supply Decoupling
To reduce ripple and the chance of introducing data errors,
bypass VDD24, VL, and VDD with 0.1µF||1µF ceramic
capacitors to GND, respectively. Place the bypass capaci-
tors as close as possible to the power supply input pins.
Powering the MAX22190 With the VDD Pin
The MAX22190 can alternatively be powered using a 3.0 -
5.5V supply connected to the VDD pin. In this case a 24V
supply is no longer needed and the VDD24 pin must be left
unconnected. This configuration has lower power consump-
tion and heat dissipation since the on-chip LDO voltage
regulator is disabled (the VDD24 undervoltage lockout is
below threshold and automatically disables the LDO).
In this configuration, the device always indicates a “24V
FAULT” due to bits 24VL and 24VM in the FAULT1 regis-
ter, and the FAULT pin is always active (low) if the bits are
enabled in the FAULT1EN register. To overcome this, set
bits 24VLE and 24VME in the FAULT1EN register to 0.
PCB Layout Recommendations
The PCB designer should follow some critical recommenda-
tions in order to get the best performance from the design.
Keep the input/output traces as short as possible. Avoid
using vias to make low-inductance paths for the signals.
Have a solid ground plane underneath the entire EP area
with multiple thermal vias for best thermal performance.
Isolating the SPI Interface
A companion product, the MAX14483, is available which
is optimized to support the MAX22190. The MAX14483
is an 6-channel, 3.75kVRMS, low-power Digital Isolator
ideal for interfacing to low-voltage products such as
microcontrollers or FPGAs. Figure 9 demonstrates daisy-
chain operation, showing SPI signals, control signals, and
power monitoring signals isolated between the “field” and
“logic” sides of the design. A single MAX14483 can be
used for multiple MAX22190s.
Figure 10 demonstrates two MAX22190s connected as
Independent Slaves, meaning they have separate Chip Select
(CS) signals from the master (MCU). In order to support the
extra isolated CS channel, a second isolator, MAX12930, is
used. Care must be taken to ensure both MAX22190s are not
enabled simultaneously to avoid SPI-bus contention.
In both Figure 9 and Figure 10, the READY signal from
both MAX22190 devices are connected together to the
IRDY pin of the MAX14483. The IRDY is pulled low when
one of the MAX22190 devices is ready for operation. Care
must be taken with the software to determine if both of
the MAX22190 devices are ready. Alternatively, an OR
gate can be used between READY signals to guarantee
the IRDY signal is only pulled low when both the READY
signals are low.
Figure 8. FAULT Output Sources
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31
FAULT
VL
FAULT1 REGISTER
CRC*
POR*
FAULT2*
ALRMT2**
WBG*
ALRMT1**
24VL**
24VM**
FAULT2 REGISTER
0
0
FAULT8CK
OTSHDN
RFWBS
RFDIO
RFDIS
RFWBO
CLEAR-ON-READ
(COR)
Set bits in FAULT2EN to enable each error flag
Set bits in FAULT1EN to enable each error flag
WB REGISTER
WB7
WB6
WB5
WB4
WB0
WB3
WB2
WB1
CLEAR-ON-READ
(COR)
Register GPO, bit 7 STK:
STK = 0:
FAULT
pin is not sticky
STK = 1:
FAULT
pin is sticky
* DYNAMIC
** CLEAR-ON-READ (COR)
Ll, L1,, W, LIV LIV LIV W W W W. W
Figure 9. 16-Channel Type 1/3 Digital Input, SPI Daisy Chain
MAX22190 Octal Industrial Digital Input with Diagnostics
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32
V
DD
GND
2.5V
MICRO
CONTROLLER
0.1µF
SCLK
SDI
SDO
CS
GPI
GPO
GPI or INT
2.5V
MAX14483
V
DDA
GNDA
OAUX
OSDI
OSCLK
OCS
SBA
IRDY
ISDO
IFAULT
V
DDB
GNDB
IAUX
ISDI
ISCLK
ICS
SAA
OSDO
OFAULT
SDOEN
LOGIC SIDE
FIELD SIDE
V
DD24
CS
SDO
SCLK
FAULT
V
DD
GND
MAX22190
#1
24V
READY
IN1
LED1
IN2
LED2
IN8
LED8
REFWB
REFDI
LATCH
V
L
3.3V
V
DD24
CS
SDO
SDI
SCLK
FAULT
V
DD
GND
MAX22190
#2
24V
READY
IN1
LED1
IN2
LED2
IN8
LED8
REFWB
REFDI
LATCH
V
L
3.3V
M1
M0
3.3V
M1
M0
3.3V
SDI
0.1µF
0.1µF
1µF
0.1µF
4.7kΩ
4.7kΩ
4.7kΩ
7.5kΩ
24kΩ
1.5kΩ
1.5kΩ
1.5kΩ
7.5kΩ
24kΩ
1.5kΩ
1.5kΩ
1.5kΩ
NOTE: READY IS PULLED LOW WHEN ONE OF THE MAX22190s IS READY FOR COMMUNICATION. CARE MUST BE TAKEN ON THE SOFTWARE TO DETERMINE IF BOTH OF THE MAX22190s ARE READY.
0.1µF
1µF 1µF
1µF
1µF
4,, LI, L: WTSI LIT 1:1,, 1,, LIV L V r H rva v LTV J: v LTV ‘ LIV 1 41v iv \V L 7 WV “LTV LIV fiv Krv WV V .ilv
Figure 10. 16-Channel Type 1/3 Digital Input, Independent Slave SPI (Separate CS for Each SPI Slave)
MAX22190 Octal Industrial Digital Input with Diagnostics
www.maximintegrated.com Maxim Integrated
33
V
DD
GND
2.5V
0.1μF
SCLK
SDI
SDO
CS1
GPI
GPO
GPI or INT
2.5V
MAX14483
V
DDA
OAUX
OSDI
OSCLK
OCS
SBA
IRDY
ISDO
IFAULT
V
DDB
IAUX
ISDI
ISCLK
ICS
SAA
OSDO
OFAULT
SDOEN
LOGIC SIDE
FIELD SIDE
V
DD24
CS1
SDO
SCLK
FAULT
V
DD
GND
MAX22190
#1
24V
READY
IN1
LED1
IN2
LED2
IN8
LED8
REFWB
REFDI
LATCH
V
L
3.3V
V
DD24
CS2
SDO
SCLK
FAULT
V
DD
GND
MAX22190
#2
24V
READY
IN1
LED1
IN2
LED2
IN8
LED8
REFWB
REFDI
LATCH
V
L
3.3V
M1
M0
3.3V
M1
M0
SDI
SDI
MAX12930
V
DDA
IN1
OUT1
IN2
OUT2
CS1
CS2OSDO
0
0
1
0
01
1
1
DRIVEN BY SDO2
DRIVEN BY SDO1
HIGH IMPEDANCE
NOT A VALID STATE (BUS CONTENTION)
CS2
0.1µF
0.1µF
1µF
4.7kΩ
4.7kΩ
4.7kΩ
0.1µF
7.5kΩ
24kΩ
1.5kΩ
1.5kΩ
1.5kΩ
1µF
7.5kΩ
24kΩ
1.5kΩ
1.5kΩ
1.5kΩ
1µF
3.3V
V
DDB
GNDA
GNDB
MICRO
CONTROLLER
0.1µF
2.5V
NOTE: READY IS PULLED LOW WHEN ONE OF THE MAX22190s IS READY FOR COMMUNICATION. CARE MUST BE TAKEN ON THE SOFTWARE TO DETERMINE IF BOTH OF THE MAX22190s ARE READY.
1µF
1μF
1µF
0.1µF 0.1µF 1µF
Type 2 Sensor Inputs
The additional input current (6mA min) and associated
power dissipation of Type 2 input requires the use of two
MAX22190 inputs in parallel. The current of each channel
is set to a nominal 3.39mA (6.78mA total) by placing a
5.2kΩ resistor from REFDI to GND. The proper voltage
drop across the input resistor is maintained by reducing
the resistance from 1.5kΩ to 1kΩ for each MAX22190
channel. For proper surge protection, it is important that
each MAX22190 input has its own resistor. Any two
MAX22190 channels may be used; they need not be con-
tiguous (Figure 11). Either channel may be read to deter-
mine the input state. The additional power dissipation from
this Type 2 configuration reduces the maximum ambient
operating temperature to 120°C, when all inputs are at
30V, and the MAX22190 is powered from a 30V supply
and there is no additional load on VDD.
Figure 11. Implementing Type 2 Digital Inputs with MAX22190
MAX22190 Octal Industrial Digital Input with Diagnostics
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34
MAX22190 IMPLEMENTIN G A 4-CH ANNEL TYPE 2 DIGITAL INPUT SERIALIZER
CS
SDO
SCLK
FAULT
MAX22190
READY
REFDI
M1
M0
SDI
4.7kΩ
IN1
LED1
REFWB
IN2
LED2
IN7
LED7
IN8
LED8
CH1
CH4
V
L
4.7kΩ
V
L
CS
MISO
SCLK
GPI
MOSI
GPI
MCU
LATCH GPO
0.F 0.F
V
DD24
V
DD
V
L
5.2kΩ
24kΩ
1kΩ
1kΩ
1kΩ
1kΩ
GND
V
DD24
V
DD
= V
L
= 3.3V
V
L
GND
24V
1µF F
iTv LTV LTv LTV
IEC 61131-2 EMC Requirement
The MAX22190 is required to operate reliably in harsh
industrial environments. The device can meet the tran-
sient immunity requirements as specified in IEC 61131-2,
including Electrostatic Discharge (ESD) per IEC 61000-
4-2, Electrical Fast Transient/Burst (EFT) per IEC 61000-
4-4, and Surge Immunity per IEC 61000-4-5. Maxim’s
proprietary process technology provides robust input
channels and field supply with internal ESD structures
and high Absolute Maximum Ratings (see the Absolute
Maximum Ratings section), but external components are
also required to absorb excessive energy from ESD and
surge transients. The circuit with external components
shown in Figure 12 allows the device to meet and exceed
the transient immunity requirements as specified in IEC
61131-2 and related IEC 61000-4-x standards. The sys-
tem shown in Figure 12, using the components shown in
Table 5, is designed to be robust against ESD, EFT, and
Surge specifications as listed in Table 6. In all these tests,
the part or DUT is soldered onto a properly designed
application board (e.g., the MAX22190EVKIT#) with nec-
essary external components. Refer to Application Note
7132 for details.
Figure 12. Typical EMC Protection Circuitry for the MAX22190
MAX22190 Octal Industrial Digital Input with Diagnostics
www.maximintegrated.com Maxim Integrated
35
V
DD24
CS
SDO
SDI
SCLK
FAULT
V
DD
GND
MAX22190
READY
IN1
LED1
R1
IN8
LED8
REFWB
REFDI
LATCH
V
L
3.3V
3.3V
M1
M0
C1C2C4 C3
D1
R1
GND
C5
EARTH
MICRO
CONTROLLER
7.5kΩ
24kΩ
4.7kΩ
GND
VL
4.7kΩ
24V
ESD Protection of Field Inputs
The input resistor limits the energy into the MAX22190
IN_ pins and protects the internal ESD structure from
excessive transient energy. An input series resistor is
required and should be rated to withstand such ESD
levels. The MAX22190 input channels can withstand up
to ±8kV ESD contact discharge and ±15kV ESD air-gap
discharge with an input series resistor of 1kΩ or larger.
The input resistor value shifts the field voltage switching
threshold scaled by the input current; thus, it determines
the input characteristics of the application. The package
of the resistor should be large enough to prevent the arc-
ing across the two resistor pads. Arcing depends on the
ESD level applied to the field input and the application’s
pollution degree.
EFT Protection of Field Inputs
The input channels can withstand up to ±4kV, 5kHz or
100kHz fast transients (Figure 14) with performance
criterion A, normal operation within specification limits. A
capacitive coupling clamp is used to couple the fast tran-
sients (burst) from the EFT generator to the field inputs
of the MAX22190 without any galvanic connection to the
MAX22190 input pins.
Surge Protection of Field Inputs
In order to protect the IN_ pins against 1kV/42Ω, 1.2/50µs
surges (Figure 15 and Figure 16), two options exist. The
first option is to use a series pulse withstanding resistor
as shown in the various application diagrams in the data
sheet. A pulse resistor greater or equal to 1kΩ should be
used for safe operation. The pulse resistor should sup-
port dissipation of the surge energy. Examples of suitable
resistors are CMB0207 MELF or CRCW-IF thick film as
well as others. The resistor value is defined by the Type 1,
2, 3, or other input characteristics. Capacitors for filtering
should not be connected to the IN_ pins.
The second option, which can result in a smaller overall
footprint, is to use a bidirectional TVS to GND at the field
input with a low-power series resistor, greater or equal to
1kΩ. The TVS must be able to absorb the surge energy
and has the function of limiting the peak voltage so that
the resistor only sees a low differential voltage. Suitable
TVS with a small footprint are SPT02-236 or PDFN3-32,
offering protection against 1kV/42Ω surge.
Surge Protection of 24V Supply
In order to protect the VDD24 pin against 500V/42Ω,
1.2/50µs surges (Figure 15), a SMBJ33A TVS can be
applied to the VDD24 pin.
Table 5. Recommended Components
COMPONENT DESCRIPTION REQUIRED/RECOMMENDED/OPTIONAL
C1 1μF, 100V ceramic capacitor Required
C2 0.1μF, 100V ceramic capacitor Required
C3 1μF, 10V low ESR ceramic capacitor Required
C4 0.1μF, 10V ceramic capacitor Required
C5 3300pF safety rated Y capacitor (2220) Recommended
D1 Unidirectional TVS diode, SMBJ33A (42Ω) or SM30T39AY (2Ω) Recommended
R1 1.5kΩ or 1kΩ, 1W pulse withstanding resistor (CMB0207 or similar) Required
All other resistors 0603, 0.1W resistors Required
D1 - D8 LEDs for visual input status indication Recommended
MAX22190 Octal Industrial Digital Input with Diagnostics
www.maximintegrated.com Maxim Integrated
36
<—>1 1 > 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 6. Transient Immunity Test Results
Figure 13a. ESD Test Circuit Figure 13b. ESD Contact Discharge Test Waveform
Figure 14. Electrical Fast Transient/Burst Waveform
Table 6. Transient Immunity Test Results
TEST RESULT
IEC 61000-4-2 Electrostatic Discharge (ESD) Contact ESD ±8kV
Air-Gap ESD ±15kV
IEC 61000-4-4 Electrical Fast Transient/Burst (EFT) Input Line ±4kV
IEC 61000-4-5 Surge Immunity (1.2/50µs, 42Ω)
Line-to-Ground ±1kV
Line-to-Line ±2kV
Power Supply ±500V
MAX22190 Octal Industrial Digital Input with Diagnostics
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37
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
150pF
RC
50M TO 100M
RD
330
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
tr = 0.7ns TO 1ns 30ns
60ns
t
100%
90%
10%
I
PEAK
I
...
V
t
...
EFT/BURST
BURST
DURATION
15ms AT 5kHz
0.75ms AT 100kHz
BURST PERIOD 300ms
V
t
EFT PULSE
REPETITION FREQUENCY
EFT VOLTAGE
EFT VOLTAGE
200µs AT 5kHz
10µs AT 100kHz
FRONT T‘ME n =12“: 1 30% TIME TO HALF VALUE ‘2 = sous : 20% Ops Surge Vanage Waveform
Figure 16. Surge Testing Methods
Figure 15. 1.2/50µs Surge Voltage Waveform
MAX22190 Octal Industrial Digital Input with Diagnostics
www.maximintegrated.com Maxim Integrated
38
100%
90%
50%
0
V
t
t
1
t
2
30% MAX
FRONT TIME: t
1
= 1.2µs ± 30%
TIME TO HALF VALUE: t
2
= 50µs ± 20%
0.5μF
GENERATOR
IN1
IN2
GND
A
B
A = LINE-TO-LINE
B = LINE-TO-GND
COUPLING/DECOUPLING NETWORK
MAX221 90
1kΩ
1kΩ
40Ω
2Ω
PART TEMP RANGE PIN-PACKAGE
MAX22190ATJ+ -40°C to +125°C 32-TQFN
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
MAX22190 Octal Industrial Digital Input with Diagnostics
www.maximintegrated.com Maxim Integrated
39
Ordering Information
Chip Information
PROCESS: BiCMOS
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
012/17 Initial release
16/18
Added READY in Electrical Characteristics table VOL row, updated figures, updated
FAULT1EN register table, updated Type 2 Sensor Inputs detailed description, updated
EMC Standard Compliance detailed description, updated Table 5, fixed various typos
and format in the Detailed Descriptions
1–39
211/18
Updated the Isolated Octal Digital Input, Pin Description, CRC Generation, SPI Inter-
face, Configurable Mode, FAULT Asserted, Isolating the SPI Interface, IEC 61000-4-4
Electrical Fast Transient/Burst (EFT) sections, and Table 5; updated the WB (Clear-
On-Read), DI (Read), FLT1 to FLT8 (Read/Write), and INEN (Read/Write) register
tables; update Figure 7, Figure 9–Figure 12; corrected typos
12, 12, 17
2021, 25
2627, 3036
312/18
Updated the Isolated Octal Digital Input diagram, Fault Detection and Monitoring, and
Powering the MAX22190 With the VDD Pin sections, and Figure 9–10; updated the
ESD and EMC Characteristics table; replaced all the Typical Operating Characteristics
2, 810,
16, 3032
41/19 Replaced TOC11–TOC14, added new TOC15–TOC18, and renumbered remaining
TOCs; updated the Detailed Description section; corrected typos
6, 911,
15, 33
59/20
Updated the Isolated Octal Digital Input, DC Electrical Characteristics, Pin Description,
Input Filters and Power Supply Decoupling sections, Figure 9–12, Figure 14–16, Table
1, and new Table 6; removed Table 6 and renumbered subsequent tables; removed
the EMC Standard Compliance, Test Levels and Methodology, IEC 61000-4-2 Electro-
static Discharge (ESD), Contact Discharge Method, Air Gap Discharge Method, IEC
61000-4-4 Electrical Fast Transient Burst (EFT), and IEC 61000-4-5 Surge Immunity
sections; added the IEC 61131-2 EMC Requirement, ESD Protection of Field Inputs,
EFT Protection of Field Inputs, Surge Protection of Field Inputs, and Surge Protection
of 24V Supply sections
2, 6, 13,
16, 3139
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2020 Maxim Integrated Products, Inc.
40
MAX22190 Octal Industrial Digital Input with Diagnostics
Revision History
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