IDT2308A Datasheet by Renesas Electronics America Inc

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1
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
AUGUST 2012
2012 Integrated Device Technology, Inc. DSC 6587/9c
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Phase-Lock Loop Clock Distribution for Applications ranging
from 10MHz to 133MHz operating frequency
Distributes one clock input to two banks of four outputs
Separate output enable for each output bank
External feedback (FBK) pin is used to synchronize the outputs
to the clock input
Output Skew <200 ps
Low jitter <200 ps cycle-to-cycle
1x, 2x, 4x output options (see table):
IDT2308A-1 1x
IDT2308A-2 1x, 2x
IDT2308A-3 2x, 4x
IDT2308A-4 2x
IDT2308A-1H and -2H for High Drive
No external RC network required
Operates at 3.3V VDD
Available in SOIC and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is
designed to address high-speed clock distribution and multiplication applica-
tions. The zero delay is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10 to 133MHz.
The IDT2308A has two banks of four outputs each that are controlled via two
select addresses. By proper selection of input addresses, both banks can be
put in tri-state mode. In test mode, the PLL is turned off, and the input clock
directly drives the outputs for system testing purposes. In the absence of an
input clock, the IDT2308A enters power down. In this mode, the device will
draw less than 12µA for Commercial Temperature range and less than 25µA
for Industrial temperature range, and the outputs are tri-stated.
The IDT2308A is available in six unique configurations for both pre-
scaling and multiplication of the Input REF Clock. (See available options
table.)
The PLL is closed externally to provide more flexibility by allowing the user
to control the delay between the input clock and the outputs.
The IDT2308A is characterized for both Industrial and Commercial opera-
tion.
IDT2308A
3.3V ZERO DELAY CLOCK
MULTIPLIER
PLL
S1
2
14
15
3
CLKA1
CLKA2
CLKA3
CLKA4
6
10
11
CLKB1
CLKB2
CLKB3
CLKB4
9
FBK 16
Control
Logic
7
8
1
REF
S2
(-2, -3)
(-3, -4)
2
2
ABSOLUTE MAXIMUM RATINGS
2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
PIN CONFIGURATION
SOIC/ TSSOP
TOP VIEW
REF
CLKA1
S2
2
3
4
5
6
7
89
10
11
12
13
14
15
161
CLKA2
GND
CLKB1
FBK
CLKA4
GND
S1
VDD
VDD
CLKB2 CLKB3
CLKB4
CLKA3
Symbol Rating Max. Unit
VDD Supply Voltage Range –0.5 to +4.6 V
VI (2) Input Voltage Range (REF) –0.5 to +5.5 V
VIInput Voltage Range –0.5 to V
(except REF) VDD+0.5
IIK (VI < 0) Input Clamp Current 50 mA
IOContinuous Output Current ±50 mA
(VO = 0 to VDD)
VDD or GND Continuous Current ±100 mA
TA = 55°C Maximum Power Dissipation 0.7 W
(in still air)(3)
TSTG Storage Temperature Range –65 to +150 ° C
Operating Commercial Temperature 0 to +70 °C
Temperature Range
Operating Industrial Temperature -40 to +85 °C
Temperature Range
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
APPLICATIONS:
• SDRAM
• Telecom
• Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
Pin Number Functional Description
REF 1 Input Reference Clock, 5 Volt Tolerant Input
CLKA1(1) 2 Clock Output for Bank A
CLKA2(1) 3 Clock Output for Bank A
VDD 4 3.3V Supply
GND 5 Ground
CLKB1(1) 6 Clock Output for Bank B
CLKB2(1) 7 Clock Output for Bank B
S2(2) 8 Select Input, Bit 2
S1(2) 9 Select Input, Bit 1
CLKB3(1) 10 Clock Output for Bank B
CLKB4(1) 11 Clock Output for Bank B
GND 12 Ground
VDD 13 3.3V Supply
CLKA3(1) 14 Clock Output for Bank A
CLKA4(1) 15 Clock Output for Bank A
FBK 16 PLL Feedback Input
NOTES:
1. Weak pull down on all outputs.
2. Weak pull ups on these inputs.
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS(1)
3
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
Device Feedback From Bank A Frequency Bank B Frequency
IDT2308A-1 Bank A or Bank B Reference Reference
IDT2308A-1H Bank A or Bank B Reference Reference
IDT2308A-2 Bank A Reference Reference/2
IDT2308A-2 Bank B 2 x Reference Reference
IDT2308A-2H Bank A Reference Reference/2
IDT2308A-2H Bank B 2 x Reference Reference
IDT2308A-3 Bank A 2 x Reference Reference or Reference(1)
IDT2308A-3 Bank B 4 x Reference 2 x Reference
IDT2308A-4 Bank A or Bank B 2 x Reference 2 x Reference
NOTE:
1. Output phase is indeterminant (0° or 180° from input clock).
AVAILABLE OPTIONS FOR IDT2308A
S2 S1 CLK A CLK B Output Source PLL Shut Down
L L Tri-State Tri-State PLL Y
L H Driven Tri-State PLL N
H L Driven Driven REF Y
H H Driven Driven PLL N
FUNCTION TABLE(1) SELECT INPUT DECODING
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
ZERO DELAY AND SKEW CONTROL
To close the feedback loop of the IDT2308A, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin
will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust
the input-output delay.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. Ensure the outputs are
loaded equally, for zero output-output skew.
4
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
Symbol Parameter Conditions Min. Typ.(1) Max. Unit
VIL Input LOW Voltage Level 0.8 V
VIH Input HIGH Voltage Level 2 V
IIL Input LOW Current VIN = 0V 50 µA
IIH Input HIGH Current VIN = VDD 100 µA
VOL Output LOW Voltage IOL = 8mA (-1, -2, -3, -4) 0.4 V
IOL = 12mA (-1H, -2H)
VOH Output HIGH Voltage IOH = -8mA (-1, -2, -3, -4) 2.4 V
IOH = -12mA (-1H, -2H)
IDD_PD Power Down Current REF = 0MHz (S2 = S1 = H) 12 µA
100MHz CLKA (-1, -2, -3, -4) 45
100MHz CLKA (-1H, -2H) 70
IDD Supply Current Unloaded Outputs 66MHz CLKA (-1, -2, -3, -4) 32 mA
Select Inputs at VDD or GND 66MHz CLKA (-1H, -2H) 50
33MHz CLKA (-1, -2, -3, -4) 18
33MHz CLKA (-1H, -2H) 30
NOTE:
1. Applies to both REF and FBK.
Symbol Parameter Test Conditions Min. Max. Unit
VDD Supply Voltage 3 3.6 V
TAOperating Temperature (Ambient Temperature) 0 70 °C
CLLoad Capacitance below 100MHz 30 pF
Load Capacitance from 100MHz to 133MHz 15 pF
CIN Input Capacitance(1) —7pF
OPERATING CONDITIONS- COMMERCIAL
5
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
SWITCHING CHARACTERISTICS - COMMERCIAL
Symbol Parameter Conditions Min. Typ. Max. Unit
t1Output Frequency 30pF Load, all devices 10 100 MHz
t1Output Frequency 20pF Load, -1H, -2H Devices 10 133.3 MHz
t1Output Frequency 15pF Load, -1, -2, -3, -4 devices 10 133.3 MHz
Duty Cycle = t2 ÷ t1Measured at 1.4V, FOUT = 66.66MHz 40 50 60 %
(-1, -2, -3, -4, -1H, -2H) 30pF Load
Duty Cycle = t2 ÷ t1Measured at 1.4V, FOUT = 50MHz 45 50 55 %
(-1, -2, -3, -4, -1H, -2H) 15pF Load
t3Rise Time (-1, -2, -3, -4) Measured between 0.8V and 2V, 30pF Load 2.2 ns
t3Rise Time (-1, -2, -3, -4) Measured between 0.8V and 2V, 15pF Load 1.5 ns
t3Rise Time (-1H, -2H) Measured between 0.8V and 2V, 30pF Load 1.5 ns
t4Fall Time (-1, -2, -3, -4) Measured between 0.8V and 2V, 30pF Load 2.2 ns
t4Fall Time (-1, -2, -3, -4) Measured between 0.8V and 2V, 15pF Load 1.5 ns
t4Fall Time (-1H) Measured between 0.8V and 2V, 30pF Load 1.25 ns
t5Output to Output Skew on same Bank All outputs equally loaded 200 ps
(-1, -2, -3, -4)
Output to Output Skew (-1H, -2H) All outputs equally loaded 200 ps
Output Bank A to Output Bank B (-1, -4, -2H) All outputs equally loaded 200 ps
Output Bank A to Output Bank B Skew (-2, -3) All outputs equally loaded 400 ps
t6Delay, REF Rising Edge to FBK Rising Edge Measured at VDD/2 0 ±250 ps
t7Device to Device Skew Measured at VDD/2 on the FBK pins of devices 0 700 ps
t8Output Slew Rate Measured between 0.8V and 2V on -1H, -2H 1 V/ns
device using Test Circuit 2
tJCycle to Cycle Jitter Measured at 66.67 MHz, loaded outputs, 15pF Load 200
(-1, -1H, -4) Measured at 66.67 MHz, loaded outputs, 30pF Load 200 ps
Measured at 133.3 MHz, loaded outputs, 15pF Load 100
tJ Cycle to Cycle Jitter Measured at 66.67 MHz, loaded outputs, 30pF Load 400 ps
(-2, -2H, -3) Measured at 66.67 MHz, loaded outputs, 15pF Load 400
tLOCK PLL Lock Time Stable Power Supply, valid clocks presented 1 ms
on REF and FBK pins
6
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
NOTE:
1. Applies to both REF and FBK.
DC ELECTRICAL CHARACTERISTICS - INDUSTRIAL
Symbol Parameter Conditions Min. Typ.(1) Max. Unit
VIL Input LOW Voltage Level 0.8 V
VIH Input HIGH Voltage Level 2 V
IIL Input LOW Current VIN = 0V 50 µA
IIH Input HIGH Current VIN = VDD 100 µA
VOL Output LOW Voltage IOL = 8mA (-1, -2, -3, -4) 0.4 V
IOL = 12mA (-1H, -2H)
VOH Output HIGH Voltage IOH = -8mA (-1, -2, -3, -4) 2.4 V
IOH = -12mA (-1H, -2H)
IDD_PD Power Down Current REF = 0MHz (S2 = S1 = H) 25 µA
100MHz CLKA (-1, -2, -3, -4) 45
100MHz CLKA (-1H, -2H) 70
IDD Supply Current Unloaded Outputs 66MHz CLKA (-1, -2, -3, -4) 32 mA
Select Inputs at VDD or GND 66MHz CLKA (-1H, -2H) 50
33MHz CLKA (-1, -2, -3, -4) 18
33MHz CLKA (-1H, -2H) 30
Symbol Parameter Test Conditions Min. Max. Unit
VDD Supply Voltage 3 3.6 V
TAOperating Temperature (Ambient Temperature) -40 +85 °C
CLLoad Capacitance below 100MHz 30 pF
Load Capacitance from 100MHz to 133MHz 15 pF
CIN Input Capacitance(1) —7pF
OPERATING CONDITIONS- INDUSTRIAL
7
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
SWITCHING CHARACTERISTICS - INDUSTRIAL
Symbol Parameter Conditions Min. Typ. Max. Unit
t1Output Frequency 30pF Load, all devices 10 100 MHz
t1Output Frequency 20pF Load, -1H, -2H Devices 10 133.3 MHz
t1Output Frequency 15pF Load, -1, -2, -3, -4 devices 10 133.3 MHz
Duty Cycle = t2 ÷ t1Measured at 1.4V, FOUT = 66.66MHz 40 50 60 %
(-1, -2, -3, -4, -1H, -2H) 30pF Load
Duty Cycle = t2 ÷ t1Measured at 1.4V, FOUT = 50MHz 45 50 55 %
(-1, -2, -3, -4, -1H, -2H) 15pF Load
t3Rise Time (-1, -2, -3, -4) Measured between 0.8V and 2V, 30pF Load ⎯⎯2.2 ns
t3Rise Time (-1, -2, -3, -4) Measured between 0.8V and 2V, 15pF Load ⎯⎯1.5 ns
t3Rise Time (-1H, -2H) Measured between 0.8V and 2V, 30pF Load ⎯⎯1.5 ns
t4Fall Time (-1, -2, -3, -4) Measured between 0.8V and 2V, 30pF Load ⎯⎯2.2 ns
t4Fall Time (-1, -2, -3, -4) Measured between 0.8V and 2V, 15pF Load ⎯⎯1.5 ns
t4Fall Time (-1H) Measured between 0.8V and 2V, 30pF Load ⎯⎯1.25 ns
t5Output to Output Skew on same Bank All outputs equally loaded ⎯⎯200 ps
(-1, -2, -3, -4)
Output to Output Skew (-1H, -2H) All outputs equally loaded ⎯⎯200 ps
Output Bank A to Output Bank B (-1, -4, -2H) All outputs equally loaded ⎯⎯200 ps
Output Bank A to Output Bank B Skew (-2, -3) All outputs equally loaded ⎯⎯400 ps
t6Delay, REF Rising Edge to FBK Rising Edge Measured at VDD/2 250ps
t7Device to Device Skew Measured at VDD/2 on the FBK pins of devices 0 700 ps
t8Output Slew Rate Measured between 0.8V and 2V on -1H, -2H 1 ⎯⎯V/ns
device using Test Circuit 2
tJCycle to Cycle Jitter Measured at 66.67 MHz, loaded outputs, 15pF Load ⎯⎯200
(-1, -1H, -4) Measured at 66.67 MHz, loaded outputs, 30pF Load ⎯⎯200 ps
Measured at 133.3 MHz, loaded outputs, 15pF Load ⎯⎯100
tJ Cycle to Cycle Jitter Measured at 66.67 MHz, loaded outputs, 30pF Load ⎯⎯400 ps
(-2, -2H, -3) Measured at 66.67 MHz, loaded outputs, 15pF Load ⎯⎯400
tLOCK PLL Lock Time Stable Power Supply, valid clocks presented ⎯⎯1ms
on REF and FBK pins
8
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
Output 1.4V
1.4V
t5
Output
Input VDD/2
t6
FBK
FBK,
Device 1
t7
FBK,
Device 2
VDD/2
VDD/2
VDD/2
1.4V
t2
t1
2V
0.8V
t3 t4
0.8V 3.3V
0V
2V
Output
1.4V 1.4V
SWITCHING WAVEFORMS
Duty Cycle Timing
All Outputs Rise/Fall Time
Output to Output Skew
Input to Output Propagation Delay
Device to Device Skew
9
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
TEST CIRCUITS
TEST CIRCUIT 1 TEST CIRCUIT 2
Test Circuit for all Parameters Except t8 Test Circuit for t8, Output Slew Rate On -1H and -2H Devices
VDD
OUTPUTS
CLKOUT
CLOAD
VDD
GND GND
0.1 F
0.1 F
VDD
OUTPUTS
10pF
VDD
GND GND
0.1 F
0.1 F
1K
1K CLKOUT
‘DIDT.
10
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
ORDERING INFORMATION
IDT XXXXX XX X
Package Process
Device Type
Blank
I
2308A-1
2308A-2
2308A-3
2308A-4
2308A-1H
2308A-2H
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
Zero Delay Clock Buffer with Standard Drive
DC
DCG
PG
PGG
Small Outline
SOIC - Green
Thin Shrink Small Outline Package
TSSOP - Green
Zero Delay Clock Buffer with High Drive
}
}
Ordering Code Package Type Operating Range
IDT2308A-1DCG 16-Pin SOIC Commercial
IDT2308A-1DCGI 16-Pin SOIC Industrial
IDT2308A-1HDCG 16-Pin SOIC Commercial
IDT2308A-1HDCGI 16-Pin SOIC Industrial
IDT2308A-1HPG 16-Pin TSSOP Commercial
IDT2308A-1HPGG 16-Pin TSSOP Commercial
IDT2308A-1HPGGI 16-Pin TSSOP Industrial
IDT2308A-1HPGI 16-Pin TSSOP Industrial
IDT2308A-2DCG 16-Pin SOIC Commercial
IDT2308A-2DCGI 16-Pin SOIC Industrial
IDT2308A-2HDCG 16-Pin SOIC Commercial
IDT2308A-2HDCGI 16-Pin SOIC Industrial
IDT2308A-3DCG 16-Pin SOIC Commercial
IDT2308A-3DCGI 16-Pin SOIC Industrial
IDT2308A-4DCG 16-Pin SOIC Commercial
IDT2308A-4DCGI 16-Pin SOIC Industrial
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 clockhelp@idt.com
San Jose, CA 95138 fax: 408-284-2775
www.idt.com

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