TIBPAL16L8/R4/6/8-7C, -10M Datasheet by Texas Instruments

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TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-XPAL® CIRCUITS
SRPS006E D3115, MAY 1988 REVISED DECEMBER 2010
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 2010, Texas Instruments Incorporated
1
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
High-Performance Operation:
fmax (no feedback)
TIBPAL16R’-7C Series . . . 100 MHz Min
TIBPAL16R’-10M Series . . . 62.5 MHz Min
fmax (internal feedback)
TIBPAL16R’-7C Series . . . 100 MHz Min
TIBPAL16R’-10M Series . . . 62.5 MHz Min
fmax (external feedback)
TIBPAL16R’-7C Series . . . 74 MHz Min
TIBPAL16R’-10M Series . . . 52.5 MHz Min
Propagation Delay
TIBPAL16L’-7C Series . . . 7 ns Max
TIBPAL16L’-10M Series . . . 10 ns Max
Functionally Equivalent, but Faster than,
Existing 20-Pin PLDs
Preload Capability on Output Registers
Simplifies Testing
Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
Security Fuse Prevents Duplication
Dependable Texas Instruments Quality and
Reliability
DEVICE I
INPUTS
3-STATE
O OUTPUTS
REGISTERED
Q OUTPUTS
I/O
PORT
S
PAL16L8 10 2 0 6
PAL16R4 8 0 4 (3-state buffers) 4
PAL16R6 8 0 6 (3-state buffers) 2
PAL16R8 8 0 8 (3-state buffers) 0
description
These programmable array logic devices feature high speed and functional equivalency when compared with
currently available devices. These IMPACT-X circuits combine the latest Advanced Low-Power Schottky
technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for
conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically
results in a more compact circuit board. In addition, chip carriers are available for futher reduction in board
space.
All of the register outputs are set to a low level during power-up. Extra circuitry has been provided to allow loading
of each register asynchronously to either a high or low state. This feature simplifies testing because the registers
can be set to an initial state prior to executing the test sequence.
The TIBPAL16’ C series is characterized from 0°C to 75°C. The TIBPAL16’ M series is characterized for
operation over the full military temperature range of 55°C to 125°C.
IMPACT-X is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
Pin assignments in operating mode
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
I
I
I
I
I
I
I
I
I
GND
VCC
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
TIBPAL16L8’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
TIBPAL16L8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
I
I
I
O
I/O O
I
GND
I
VCC
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TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-XPAL® CIRCUITS
SRPS006E D3115, MAY 1988 REVISED DECEMBER 2010
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
2
Pin assignments in operating mode
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK
I
I
I
I
I
I
I
I
GND
VCC
I/O
I/O
Q
Q
Q
Q
I/O
I/O
OE
(TOP VIEW)
TIBPAL16R4’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK
I
I
I
I
I
I
I
I
GND
VCC
I/O
Q
Q
Q
Q
Q
Q
I/O
OE
(TOP VIEW)
TIBPAL16R6’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK
I
I
I
I
I
I
I
I
GND
VCC
Q
Q
Q
Q
Q
Q
Q
Q
OE
(TOP VIEW)
TIBPAL16R8’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
I
I
CLK
I/O
I/O I/O
I
GND
VCC
OE
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
I/O
Q
Q
Q
Q
I
I
I
I
I
(TOP VIEW)
TIBPAL16R4’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
I
I
CLK
I/O
QI/O
I
GND
VCC
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
Q
Q
Q
Q
Q
I
I
I
I
I
(TOP VIEW)
OE
TIBPAL16R6’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
I
I
CLK
Q
QQ
I
GND
VCC
OE
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
Q
Q
Q
Q
Q
I
I
I
I
I
(TOP VIEW)
TIBPAL16R8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
OBSOLETE - No Longer Available
OBSOLETE - No Longer Available TEXAS {9 INSTRUMENTS
TIBPAL16L8-7C, TIBPAL16R4-7C
TIBPAL16L8-10M, TIBPAL16R4-10M
HIGH-PERFORMANCE IMPACT-XPAL® CIRCUITS
SRPS006E D3115, MAY 1988 REVISED DECEMBER 2010
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 3
functional block diagrams (positive logic)
denotes fused inputs
TIBPAL16L8
TIBPAL16R4
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I
EN 1
&
32 X 64
10 16
166
7
7
7
7
7
7
7
7
6
16 x
Q
I/O
I/O
I/O
I/O
I
EN
816
164
7
7
7
8
8
8
7
4
16 x
1
&
32 X 64
1
8
Q
Q
Q
4
1D
I = 0 2
CLK C1
EN 2
OE
4
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OBSOLETE - No Longer Available / 4 TEXAS {9 INSTRUMENTS
TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-XPAL® CIRCUITS
SRPS006E D3115, MAY 1988 REVISED DECEMBER 2010
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
4
functional block diagrams (positive logic)
denotes fused inputs
TIBPAL16R6
TIBPAL16R8
Q
I/O
I/O
I
EN
816
162
7
8
8
8
7
2
16 x
1
&
32 X 64
1
8
Q
Q
Q
6
1D
I = 0 2
CLK C1
EN 2
OE
6
8Q
8Q
Q
I816
168
8
8
8
8
16 x
8
Q
Q
Q
1D
I = 0 2
CLK C1
EN 2
8Q
8Q
&
32 X 64
1
OE
8Q
8Q
OBSOLETE - No Longer Available
OBSOLETE - No Longer Available 1 Flrst Fuse Numbers 15 u :2 so as 125 0 15a Increment I/O I/O I/O I/O I/O I/O 9 Fuse number: Flrsl vuse number + Incremenl TEXAS {9 INSTRUMENTS
0 4 8 12 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
O
12
I
11
Increment
I1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
First
Fuse
Numbers
TIBPAL16L8-7C
TIBPAL16L8-10M
HIGH-PERFORMANCE IMPACT-XPAL® CIRCUITS
SRPS006E D3115, MAY 1988 REVISED DECEMBER 2010
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 5
logic diagram (positive logic)
OBSOLETE - No Longer Available
OBSOLETE - No Longer Available K 4‘ > Increment Flrst Fuse Numbers 0 4 a 12 Is 20 24 25 31 n a: an 95 ‘23 IIO mo ‘92 224 IIO IIO IIO Fuse number : First use number + Increment TEXAS {9 INSTRUMENTS
04812 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
I/O
19
I/O
18
Q
17
Q
16
Q
15
Q
14
I/O
13
I/O
12
11
Increment
CLK 1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
First
Fuse
Numbers
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
OE
TIBPAL16R4-7C
TIBPAL16R4-10M
HIGH-PERFORMANCE IMPACT-XPAL® CIRCUITS
SRPS006E D3115, MAY 1988 REVISED DECEMBER 2010
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
6
logic diagram (positive logic)
OBSOLETE - No Longer Available
OBSOLETE - No Longer Available 1 CLK Flrst Fuse Numbers 1) a: an 95 125 151) 192 2 224 s | Fuse number : First use number + Increment Increment /\ 15 TEXAS {9 INSTRUMENTS 19 1a 17 16 15 14 13 12 11 IIO IIO
0 4 8 12 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
I/O
19
Q
17
Q
16
Q
15
Q
14
I/O
12
11
Increment
CLK 1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
First
Fuse
Numbers
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
OE
Q
18
C1
1D
I = 0
Q
13
C1
1D
I = 0
TIBPAL16R6-7C
TIBPAL16R6-10M
HIGH-PERFORMANCE IMPACT-XPAL® CIRCUITS
SRPS006E D3115, MAY 1988 REVISED DECEMBER 2010
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 7
logic diagram (positive logic)
OBSOLETE - No Longer Available
1 CLK Flrst Fuse Numbers 1) a: an 95 125 151) 192 2 224 s | OBSOLETE - No Longer Available Increment 1s Fuse number : First use number + Increment TEXAS {9 INSTRUMENTS 19 1a 17 16 15 14 13 12 11
0 4 8 12 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
Q
17
Q
16
Q
15
Q
14
11
Increment
CLK 1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
First
Fuse
Numbers
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
OE
Q
18
C1
1D
I = 0
Q
13
C1
1D
I = 0
Q
19
C1
1D
I = 0
Q
12
C1
1D
I = 0
TIBPAL16R8-7C
TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-XPAL® CIRCUITS
SRPS006E D3115, MAY 1988 REVISED DECEMBER 2010
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
8
logic diagram (positive logic)
OBSOLETE - No Longer Available
OBSOLETE - No Longer Available TEXAS {9 INSTRUMENTS
TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
HIGH-PERFORMANCE IMPACT-XPAL® CIRCUITS
SRPS006E D3115, MAY 1988 REVISED DECEMBER 2010
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 9
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VIH High-level input voltage (see Note 2) 2 5.5 V
VIL Low-level input voltage (see Note 2) 0.8 V
IOH High-level output current 3.2 mA
IOL Low-level output current 24 mA
fclock Clock frequency 0 100 MHz
High 5
Low 5
tsu Setup time, input or feedback before clock7 ns
thHold time, input or feedback after clock0 ns
TAOperating free-air temperature 0 25 75 °C
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYPMAX UNIT
VIK VCC = 4.75 V, II = 18 mA 0.8 1.5 V
VOH VCC = 4.75 V, IOH = 3.2 mA 2.4 3.2 V
VOL VCC = 4.75 V, IOL = 24 mA 0.3 0.5 V
IOZHVCC = 5.25 V, VO = 2.7 V 100 μA
IOZLVCC = 5.25 V, VO = 0.4 V 100 μA
IIVCC = 5.25 V, VI = 5.5 V 100 μA
IIHVCC = 5.25 V, VI = 2.7 V 25 μA
IILVCC = 5.25 V, VI = 0.4 V 80 250 μA
IOS§VCC = 5.25 V, VO = 0.5 V 30 70 130 mA
ICC VCC = 5.25 V, VI = 0, Outputs open 160 180 mA
Cif = 1 MHz, VI = 2 V 5 pF
Cof = 1 MHz, VO = 2 V 6 pF
Cclk f = 1 MHz, VCLK = 2 V 6 pF
All typical values are at VCC = 5 V, TA = 25°C.
I/O leakage is the worst case of IOZL and IIL or IOZH and IIH respectively.
§Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
ns
Pulse duration, clock (see Note 2)tw
OBSOLETE - No Longer Available
OBSOLETE - No Longer Available TEXAS {9 INSTRUMENTS
I, I/O O, I/Otpd ns
TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
HIGH-PERFORMANCE IMPACT-XPAL® CIRCUITS
SRPS006E D3115, MAY 1988 REVISED DECEMBER 2010
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
10
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER FROM
(INPUT)
TO
(OUTPUT) TEST CONDITION MIN TYPMAX UNIT
without feedback 100
fmaxwith internal feedback
(counter configuration) 100 MHz
with external feedback 74
1 or 2 outputs switching 3 5.5 7
8 outputs switching R1 = 200 Ω, 3 6 7.5
tpd CLKQR2 = 390 Ω, 2 4 6.5 ns
tpd§CLKFeedback input See Figure 6 3 ns
ten OEQ 4 7.5 ns
tdis OEQ 4 7.5 ns
ten I, I/O O, I/O 6 9 ns
tdis I, I/O O, I/O 6 9 ns
tsk(o)Skew between registered outputs 0.5 ns
All typical values are at VCC = 5 V, TA = 25°C.
See section for fmax specifications.
§This parameter applies to TIBPAL16R4’ and TIBPAL16R6’ only (see Figure 4 for illustration) and is calculated from the measured fmax with internal
feedback in the counter configuration.
This parameter is the measurement of the difference between the fastest and slowest tpd (CLK-to-Q) observed when multiple registered outputs
are switching in the same direction.
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OBSOLETE - No Longer Available TEXAS {9 INSTRUMENTS
μAVI = 2.7 V
VO = 0.4 V
VCC = 5.5 V,
IIH
IOZLVCC = 5.5 V, mA
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-XPAL® CIRCUITS
SRPS006E D3115, MAY 1988 REVISED DECEMBER 2010
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 11
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0.8 V
IOH High-level output current 2 mA
IOL Low-level output current 12 mA
fclockClock frequency 0 62.5 MHz
High 8
Low 8
tsuSetup time, input or feedback before clock10 ns
thHold time, input or feedback after clock0 ns
TAOperating free-air temperature 55 25 125 °C
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYPMAX UNIT
VIK VCC = 4.5 V, II = 18 mA 0.8 1.5 V
VOH VCC = 4.5 V, IOH = 2 mA 2.4 3.2 V
VOL VCC = 4.5 V, IOL = 12 mA 0.3 0.5 V
IOZHVCC = 5.5 V, VO = 2.7 V 100 μA
0, Q outputs 0.1
I/O ports 0.25
IIVCC = 5.5 V, VI = 5.5 V 1 mA
I/O ports 100
All others 25
IILVCC = 5.5 V, VI = 0.4 V 0.08 0.25 mA
IOS§VCC = 5.5 V, VO = 0.5 V 30 70 130 mA
ICC VCC = 5.5 V, VI = GND, Outputs open 140 200 mA
Cif = 1 MHz, VI = 2 V 5 pF
Cof = 1 MHz, VO = 2 V 6 pF
Cclk/oe f = 1 MHz, VCLK/OE = 2 V 6 pF
All typical values are at VCC = 5 V, TA = 25°C.
I/O leakage is the worst case of IOZL and IIL or IOZH and IIH respectively.
§Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
ns
Pulse duration, clock (see Note 2)tw
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TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-XPAL® CIRCUITS
SRPS006E D3115, MAY 1988 REVISED DECEMBER 2010
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
12
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER FROM
(INPUT)
TO
(OUTPUT) TEST CONDITION MIN TYPMAX UNIT
without feedback 62.5
fmaxwith internal feedback
(counter configuration) 62.5 MHz
with external feedback 52.5
tpd I, I/O O, I/O R1 = 390 Ω, 2 6 10 ns
tpd CLKQR2 = 750 Ω, 1 4 9 ns
tpd§CLKFeedback input See Figure 6 5 ns
ten OEQ 1 4 10 ns
tdis OEQ 1 4 10 ns
ten I, I/O O, I/O 2 6 12 ns
tdis I, I/O O, I/O 1 6 10 ns
All typical values are at VCC = 5 V, TA = 25°C.
See section for fmax specifications. fmax with external feedback is not production tested but is calculated from the equation found in the fmax
section.
§This parameter applies to TIBPAL16R4’ and TIBPAL16R6’ only (see Figure 4 for illustration) and is calculated from the measured fmax with internal
feedback in the counter configuration.
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TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-XPAL® CIRCUITS
SRPS006E D3115, MAY 1988 REVISED DECEMBER 2010
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 13
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
preload procedure for registered outputs (see Figure 1 and Note 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.
Step 1. With VCC at 5 volts and Pin 1 at VIL, raise Pin 11 to VIHH.
Step 2. Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Step 3. Pulse Pin 1, clocking in preload data.
Step 4. Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing the
voltage level at the output pin.
td
tsu
tw
td
VIHH
VIL
VIL
VOL
VOH
VIH
Pin 11
Pin 1
Registered I/O Input Output
VIH
VIL
Figure 1. Preload Waveforms
NOTE 3: td = tsu = th = 100 ns to 1000 ns VIHH = 10.25 V to 10.75 v
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TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-XPAL® CIRCUITS
SRPS006E D3115, MAY 1988 REVISED DECEMBER 2010
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
14
power-up reset (see Figure 2)
Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not
occur until all applicable input and feedback setup times are met.
1.5 V
tsu
tpd
tw
VIL
VIH
5 V
VCC
Active Low
Registered Output
CLK
4 V
VOH
VOL
1.5 V
(600 ns TYP, 1000 ns MAX)
1.5 V
This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
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TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-XPAL® CIRCUITS
SRPS006E D3115, MAY 1988 REVISED DECEMBER 2010
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 15
fmax SPECIFICATIONS
fmax without feedback, see Figure 3
In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no feedback.
Under this condition, the clock period is limited by the sum of the data setup time and the data hold time (tsu + th).
However, the minimum fmax is determined by the minimum clock period (tw high + tw low).
Thus, fmax without feedback +1
(twhigh )twlow) or 1
(tsu )th).
CLK
LOGIC
ARRAY
tsu + th
or
tw high + tw low
C1
1D
Figure 3. fmax Without Feedback
fmax with internal feedback, see Figure 4
This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal delay
from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.
Thus, fmax with internal feedback +1
(tsu )tpd CLK *to *FB).
Where tpd CLK-to-FB is the deduced value of the delay from CLK to the input of the logic array.
CLK
LOGIC
ARRAY
tsu tpd CLK - to-FB
C1
1D
Figure 4. fmax With Internal Feedback
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TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-XPAL® CIRCUITS
SRPS006E D3115, MAY 1988 REVISED DECEMBER 2010
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
16
fmax SPECIFICATIONS
fmax with external feedback, see Figure 5
This configuration is a typical state-machine design with feedback signals sent off-chip. This external feedback
could go back to the device inputs or to a second device in a multi-chip state machine. The slowest path defining
the period is the sum of the clock-to-output time and the input setup time for the external signals
(tsu + tpd CLK-to-Q).
Thus, fmax with external feedback +1
(tsu )tpd CLK *to *Q).
tpd CLK - to- Q tsu
CLK
LOGIC
ARRAY
NEXT DEVICE
tsu
C1
1D
Figure 5. fmax With External Feedback
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TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-XPAL® CIRCUITS
SRPS006E D3115, MAY 1988 REVISED DECEMBER 2010
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 17
PARAMETER MEASUREMENT INFORMATION
tsu
S1
R2
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
(3.5 V) [3 V]
(0.3 V) [0]
1.5 V
1.5 V
th
1.5 V
tpd
tpd
tpd
tpd
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOH
VOH
VOL
VOL
1.5 V 1.5 V
1.5 V 1.5 V
tw
1.5 V 1.5 V
3.3 V
VOL
VOH
VOH 0.5 V
0 V
ten
ten
tdis
tdis
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
R1
VOL +0.5 V
5 V
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
From Output
Under Test
Test
Point
Input
Out-of-Phase
Output
(see Note D)
Timing
Input
Data
Input
In-Phase
Output
High-Level
Pulse
Low-Level
Pulse
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: For C suffix, use the voltage levels indicated in parentheses ( ), PRR 1 MHz,
tr = tf = 2 ns, duty cycle = 50%; For M suffix, use the voltage levels indicated in brackets [ ], PRR 10 MHz, tr and tf 2 ns, duty
cycle = 50%
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 6. Load Circuit and Voltage Waveforms
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OBSOLETE - No Longer Available ~\ \ v c t -\ \ C 55v Voc :5-25 - v \ ~\\ % =5 ~\ \ V \ l/ \ CC 4,75 v0 1/ 0:451, \ m (I, m m 0, we} (I. I/O to O. l/O) vcc=sv CL=50pF R1=200f£ R2=390f£ TEXAS {9 INSTRUMENTS TA=25°C CL=50pF RI =ZDDQ R2=JBDQ 1pm (I. HO :0 o, my 1 L (CLK to Q) R2 = 3900 / \\\\ / // 4 cm (CLKto o Q~ um (CLK m a) ‘ rm (I, m :‘o 0, we} tr:
TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-XPAL® CIRCUITS
SRPS006E D3115, MAY 1988 REVISED DECEMBER 2010
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
18
TYPICAL CHARACTERISTICS
160
140
120
100
75 50 25 0 25 50
Figure 7
180
200
SUPPLY CURRENT
vs
FREE- AIR TEMPERATURE
220
75 100 125
TA Free - Air Temperature °C
ICC Supply Current mA
4
2
1
0
4.5 4.75 5
Figure 8
Propagation Delay Time ns
6
7
PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE
8
5.25 5.5
5
3
VCC Supply Voltage V
TA = 25 °C
CL = 50 pF
R1 = 200 Ω
R2 = 390 Ω
tPHL (I, I/O to O, I/O)
tPLH (I, I/O to O, I/O)
tPHL (CLK to Q)
tPLH (CLK to Q)
1 Output Switching
CL Load Capacitance pF
4
2
1
0
75 50 25 0 25 50
Figure 9
Propagation Delay Time ns
6
7
8
75 100 125
5
3
PROPAGATION DELAY TIME
vs
FREE- AIR TEMPERATURE
VCC = 5 V
CL = 50 pF
R1 = 200 Ω
R2 = 390 Ω
1 Output Switching
tPHL (I, I/O to O, I/O)
tPLH (I, I/O to O, I/O)
tPHL (CLK to Q)
tPLH (CLK to Q)
TA Free - Air Temperature °C
8
4
2
0
100 200 300 400
Figure 10
Propagation Delay Time ns
12
14
16
500
10
6
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
tPHL (I, I/O to O, I/O)
tPLH (I, I/O to O, I/O)
tPHL (CLK to Q)
tPLH (CLK to Q)
VCC = 5 V
TA = 25 °C
R1 = 200 Ω
R2 = 390 Ω
1 Output Switching
0 600
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TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-XPAL® CIRCUITS
SRPS006E D3115, MAY 1988 REVISED DECEMBER 2010
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 19
TYPICAL CHARACTERISTICS
Number of Outputs Switching
0.4
0.2
0.1
0
23 4 5 6
Figure 12
0.6
0.7
0.8
78
0.5
0.3
PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
VCC = 5 V
TA = 25 °C
R1 = 200 Ω
R2 = 390 Ω
CL = 50 pF
8-Bit Counter
4
2
1
0
012345
Figure 13
Propagation Delay Time ns
6
7
8
678
5
3
PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
tskew Skew Between Outputs Switching ns
VCC = 5 V
TA = 25 °C
CL = 50 pF
R1 = 200 Ω
R2 = 390 Ω
Number of Outputs Switching
tPHL (I, I/O to O, I/O)
tPLH (I, I/O to O, I/O)
tPHL (CLK to Q)
tPLH (CLK to Q)
1 4 10 40 100
Figure 11
F Frequency MHz
POWER DISSIPATION
vs
FREQUENCY
8- BIT COUNTER MODE
800
600
1000
700
900
VCC = 5 V
PD Power Dissipation mW
TA = 0 °C
TA = 25 °C
TA = 80 °C
Outputs switching in the same direction (tPLH compared to tPLH/tPHL to tPHL)
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D0892
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233-5200; Wyle (214) 235-9953; Zeus (214) 783-7010;
Houston: Arrow/Schweber (713) 530-4700; Hall-Mark
(713) 781-6100; Marshall (713) 467-1666; Wyle (713)
879-9953.
UTAH: Anthem (801) 973-8555; Arrow/Schweber (801)
973-6913; Marshall (801) 973-2288; Wyle (801) 974-9953.
WASHINGTON: Almac/Arrow (206) 643-9992, Anthem
(206) 483-1700; Marshall (206) 486-5747; Wyle (206)
881-1150.
WISCONSIN: Arrow/Schweber (414) 792-0150; Hall-Mark
(414) 797-7844; Marshall (414) 797-8400.
CANADA: Calgary: Future (403) 235-5325;
Edmonton: Future (403) 438-2858;
Montreal: Arrow/Schweber (514) 421-7411; Future (514)
694-7710; Marshall (514) 694-8142
Ottawa: Arrow/Schweber (613) 226-6903; Future (613)
820-8313.
Quebec: Future (418) 897-6666.
Toronto: Arrow/Schweber (416) 670-7769;
Future (416) 612-9200; Marshall (416) 458-8046.
Vancouver: Arrow/Schweber (604) 421-2333;
Future (604) 294-1166.
OBSOLETE - No Longer Available
{5" TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 5-May-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-85155172A OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125
5962-8515517RA OBSOLETE CDIP J 20 TBD Call TI Call TI -55 to 125
5962-8515517SA OBSOLETE CFP W 20 TBD Call TI Call TI -55 to 125
5962-85155182A NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
85155182A
TIBPAL16
R8-10MFKB
5962-8515518RA NRND CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8515518RA
TIBPAL16R8-10M
JB
5962-8515518SA NRND CFP W 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8515518SA
TIBPAL16R8-10M
WB
5962-85155192A OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125
5962-8515519RA OBSOLETE CDIP J 20 TBD Call TI Call TI -55 to 125
5962-8515519SA OBSOLETE CFP W 20 TBD Call TI Call TI -55 to 125
5962-85155202A OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125
5962-8515520RA OBSOLETE CDIP J 20 TBD Call TI Call TI -55 to 125
5962-8515520SA OBSOLETE CFP W 20 TBD Call TI Call TI -55 to 125
TIBPAL16L8-10MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125 5962-
85155172A
TIBPAL16
L8-10MFKB
TIBPAL16L8-10MJB OBSOLETE CDIP J 20 TBD A42 N / A for Pkg Type -55 to 125 5962-8515517RA
TIBPAL16L8-10M
JB
TIBPAL16L8-10MWB OBSOLETE CFP W 20 TBD Call TI Call TI -55 to 125 5962-8515517SA
TIBPAL16L8-10M
WB
TIBPAL16L8-7CFN ACTIVE PLCC FN 20 46 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-245C-168 HR 0 to 75 16L8-7
TIBPAL16L8-7CN ACTIVE PDIP N 20 20 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type 0 to 75 TIBPAL16L8-7CN
TIBPAL16R4-10MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125
l TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 5-May-2015
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TIBPAL16R4-10MJB OBSOLETE CDIP J 20 TBD Call TI Call TI -55 to 125
TIBPAL16R4-10MWB OBSOLETE CFP W 20 TBD Call TI Call TI -55 to 125
TIBPAL16R4-7CFN OBSOLETE PLCC FN 20 TBD Call TI Call TI 0 to 75
TIBPAL16R4-7CN OBSOLETE PDIP N 20 TBD Call TI Call TI 0 to 75
TIBPAL16R6-10MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125 5962-
85155192A
TIBPAL16
R6-10MFKB
TIBPAL16R6-10MJB OBSOLETE CDIP J 20 TBD Call TI Call TI -55 to 125 5962-8515519RA
TIBPAL16R6-10M
JB
TIBPAL16R6-10MWB OBSOLETE CFP W 20 TBD Call TI Call TI -55 to 125 5962-8515519SA
TIBPAL16R6-10M
WB
TIBPAL16R6-7CFN OBSOLETE PLCC FN 20 TBD Call TI Call TI 0 to 75 16R6-7
TIBPAL16R6-7CN OBSOLETE PDIP N 20 TBD Call TI Call TI 0 to 75 TIBPAL16R6-7CN
TIBPAL16R8-10MFKB NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
85155182A
TIBPAL16
R8-10MFKB
TIBPAL16R8-10MJB NRND CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8515518RA
TIBPAL16R8-10M
JB
TIBPAL16R8-10MWB NRND CFP W 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8515518SA
TIBPAL16R8-10M
WB
TIBPAL16R8-7CFN OBSOLETE PLCC FN 20 TBD Call TI Call TI 0 to 75
TIBPAL16R8-7CN OBSOLETE PDIP N 20 TBD Call TI Call TI 0 to 75
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 5-May-2015
Addendum-Page 3
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
J (R76D1P7TM) CERAVVHC DUAL 1N7L1NE PACKAGE )4 LEADS SHOWN PWS u . W 14 e 18 20 0300 0300 0300 0300 E (7.52) (7.52) (7.62) (7.62) w 5 Est ass ass ass fl fl m m m m m E MAX 0.755 540 0.950 1.060 (19.94) (21.34) (24.35) (25.92) I ..15,,, 1 0 500 0,300 0,310 0.300 U U U U U U U C W (7.52) (7.52) (7.57) (7.52) 0.245 0.245 0.220 0.245 0.005 (1.65) 0 MW 0045 (1.14) (6.22) (6.22) (5.50) (6.22) 0000 ( . ) a «0005(0.13)MN m r ~ 0200 (5.05) MAX 7 ; Seatmg Pmne , 0 (3.30) MN 4 0 020 (0. 66) 0014 (0.36) 0715' 0100 (.)254 0.014 (0.36) 0,000 (0.20) 4040083/F 03/03 VOTES: A. AH Hneur d1mens1ons are 1’1 1mm (muhmeters) a, This druwmg '3 subject m change w'thout nnt'ce. 0, 1m package 15 hermehcoHy sewed mm a cemm 11a usmg q1ass mt. D. 11an pom 1’s prowded on cap fo' 1mm) 1den1111ca0an umy on press cemrmc 9055 m sea) 00W. E FaHs thin ML 513 1035 0011417114. 001141416. GDPPTTB 0'10 001017120
MECHANICAL DATA W (R—GDFP—FZO) CERAWC DUAL FLATPACK Base and Szafing Hana (114111045 0.500 (7.62) f7 [1026 (0 as) 0.245 (6.22) f .: i ‘ ‘ 0.009 (023) fl? 0.004 0.10 <7 0.520="" (0.13)="" max="" 4»="" i="" 20="" :3="" i3:="" 0.022="" 0.56="" i:="" 3="" e="" )="" :i="" i:="" i="" 0.015="" (0.30)="" :3="" i:="" t="" :3="" ::i="" :3="" ::i="" 0.540="" (13.72)="" max="" [:3="" |::l="" [:3="" |::l="" [:3="" |::l="" [:3="" |::l="" “-005="" (m)="" m="" 4="" race:="" [:3="" i3:="" i="" 10="" i1="" 0="" 370="" (9,40)="" 0.370="" (9.40)="" 0.250="" (6.35)="" 0,250="" (5.35)="" 404013074/r="" 04/14="" notes:="" a.="" wpflw="" f0”:="" wilhin="" mh—std="" 1835="" gdfpz—fzo="" ah="" hnear="" dimensions="" are="" in="" inches="" (mhhmeters).="" this="" drawing="" ts="" sumeu="" \o="" cnange="" wunom="" nofice.="" this="" package="" can="" be="" hermelicahy="" semi="" win="" a="" ceramic="" lid="" using="" glass="" iril="" )ndex="" point="" is="" provided="" on="" cup="" (or="" lermina)="" identifica‘ion="" any.="" i="" texas="" instruments="" www.mmm="">
MECHANICAL DATA AME; CHEF“ ELAR‘REE ?< (a="" cm;="" w”)="" ,eamess="" c="" ’7="" flflflflflfl\="" f="" e="" e="" e="" e="" ,="" kwwwg="" qfijrm“="" a="" i:="" i7="" i4="" i:="" i:="" e7="" eiflfiiflfizj="" vvwwttflfl="" 1="" notes="" ah="" ineur="" dimensions="" are="" in="" inches="" (minmeiers).="" this="" cruwg="" i5="" subjeci="" i0="" chcnge="" without="" noiice="" this="" package="" car="" he="" hermeticuiiy="" secied="" mm="" a="" metai="" ic="" i'ciis="" wiihi="" jedec="" n87004="" 50m)="" {mm="" instruments="" w.="" (i.="" cam="">
MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘fi: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): nofice /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmflder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkflh INSI'RUMENTS www.1i.com
1—11—11—11—11—1 1_l)_l)_l)_ll_l 0.000 10.20) NOM J L NO_ OF D/E Dl/E1 D2IE2 PINS " MIN MAX MIN MAX MIN MAX 20 0.3051978) 0,395110,03) 03501809) 035619104) 0.141 (3155) 0.1691429) 20 048511232) 049511257) 0450111143) 0.45611155) 0.1911405) 0.2191556) 44 058511140) 059511755) 055011551) 065511566) 0.2911739) 0.3191510) 52 078511994) 079512019) 075011905) 075611920) 0.3411066) 0.3691937) 50 098512502) 099512527) 095012413) 095012433) 044111120) 046911191) 54 115513010) 119513035) 115012921) 1.15012941) 054111074) 055911445) 4040005/ B 03/9 9051 OFFICE BOX 555303 - DALLAS TEXAS 75255
MECHANICAL DATA
MPLC004A – OCTOBER 1994
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER
4040005/B 03/95
20 PIN SHOWN
0.026 (0,66)
0.032 (0,81)
D2/E2
0.020 (0,51) MIN
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D2/E2
0.013 (0,33)
0.021 (0,53)
Seating Plane
MAX
D2/E2
0.219 (5,56)
0.169 (4,29)
0.319 (8,10)
0.469 (11,91)
0.569 (14,45)
0.369 (9,37)
MAX
0.356 (9,04)
0.456 (11,58)
0.656 (16,66)
0.008 (0,20) NOM
1.158 (29,41)
0.958 (24,33)
0.756 (19,20)
0.191 (4,85)
0.141 (3,58)
MIN
0.441 (11,20)
0.541 (13,74)
0.291 (7,39)
0.341 (8,66)
18
19
14
13
D
D1
13
9
E1E
4
8
MINMAXMIN
PINS
**
20
28
44
0.385 (9,78)
0.485 (12,32)
0.685 (17,40)
52
68
84 1.185 (30,10)
0.985 (25,02)
0.785 (19,94)
D/E
0.395 (10,03)
0.495 (12,57)
1.195 (30,35)
0.995 (25,27)
0.695 (17,65)
0.795 (20,19)
NO. OF D1/E1
0.350 (8,89)
0.450 (11,43)
1.150 (29,21)
0.950 (24,13)
0.650 (16,51)
0.750 (19,05)
0.004 (0,10)
M
0.007 (0,18)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
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