SN74LVC4245A Datasheet by Texas Instruments

V'.‘ 1!. B X E I TEXAS INSTRUMENTS _;LY {
DIR
OE
A1
B1
To Seven Other Channels
2
3
22
21
Product
Folder
Order
Now
Technical
Documents
Tools &
Software
Support &
Community
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC4245A
SCAS375I –MARCH 1994–REVISED JANUARY 2015
SN74LVC4245A Octal Bus Transceiver and 3.3-V to 5-V Shifter
With 3-State Outputs
1
1 Features
1• Bidirectional Voltage Translator
• 5.5 V on A Port and 2.7 V to 3.6 V on B Port
• Control Inputs VIH/VIL Levels Are Referenced to
VCCA Voltage
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 200-V Machine Model
– 1000-V Charged-Device Model
2 Applications
• ATCA Solutions
• CPAP Machines
• Cameras: Surveillance Analog
• Chemical or Gas Sensors
• CT Scanners
• DLP 3D Machine Vision and Optical Networking
• Digital Signage
• ECGs: Electrocardiograms
• Field Transmitters: Pressure Sensors and
Temperature Sensors
• High-Speed Data Acquisition and Generation
• HMI (Human Machine Interface)
• RF4CE Remote Controls
• Server Motherboards
• Software Defined Radios (SDR)
• Wireless LAN Cards and Data Access Cards
• X-ray: Medical, Dental, and Baggage Scanners
3 Description
This 8-bit (octal) noninverting bus transceiver
contains two separate supply rails; B port has VCCB,
which is set at 3.3 V, and A port has VCCA, which is
set at 5 V. This allows for translation from a 3.3-V to
a 5-V environment, and vice versa.
The SN74LVC4245A device is designed for
asynchronous communication between data buses.
The device transmits data from the A bus to the B
bus or from the B bus to the A bus, depending on the
logic level at the direction-control (DIR) input. The
output-enable (OE) input can be used to disable the
device so the buses are effectively isolated. The
control circuitry (DIR, OE) is powered by VCCA.
The SN74LVC4245A device terminal out allows the
designer to switch to a normal all-3.3-V or all-5-V 20-
terminal SN74LVC4245 device without board re-
layout. The designer uses the data paths for pins
2–11 and 14–23 of the SN74LVC4245A device to
align with the conventional '245 terminal out.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LVC4245A
SSOP (24) 8.20 mm × 5.30 mm
SOIC (24) 15.40 mm × 7.50 mm
TSSOP (24) 7.80 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
l TEXAS INSTRUMENTS
2
SN74LVC4245A
SCAS375I –MARCH 1994–REVISED JANUARY 2015
www.ti.com
Product Folder Links: SN74LVC4245A
Submit Documentation Feedback Copyright © 1994–2015, Texas Instruments Incorporated
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Simplified Schematic............................................. 1
5 Revision History..................................................... 2
6 Pin Configuration and Functions......................... 3
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 Absolute Maximum Ratings ...................................... 4
7.3 ESD Ratings.............................................................. 4
7.4 Recommended Operating Conditions....................... 5
7.5 Recommended Operating Conditions....................... 5
7.6 Thermal Information.................................................. 5
7.7 Electrical Characteristics........................................... 6
7.8 Electrical Characteristics........................................... 6
7.9 Switching Characteristics.......................................... 7
7.10 Operating Characteristics........................................ 7
7.11 Typical Characteristics............................................ 7
8 Parameter Measurement Information .................. 8
8.1 A Port ........................................................................ 8
8.2 B Port ........................................................................ 9
9 Detailed Description............................................ 10
9.1 Overview ................................................................. 10
9.2 Functional Block Diagram....................................... 10
9.3 Feature Description................................................. 10
9.4 Device Functional Modes........................................ 10
10 Application and Implementation........................ 11
10.1 Application Information.......................................... 11
10.2 Typical Application ............................................... 11
11 Power Supply Recommendations ..................... 13
11.1 Power-Up Consideration ...................................... 13
12 Layout................................................................... 13
12.1 Layout Guidelines ................................................. 13
12.2 Layout Example .................................................... 13
13 Device and Documentation Support ................. 14
13.1 Trademarks........................................................... 14
13.2 Electrostatic Discharge Caution............................ 14
13.3 Glossary................................................................ 14
14 Mechanical, Packaging, and Orderable
Information ........................................................... 14
5 Revision History
Changes from Revision H (March 2005) to Revision I Page
• Added Applications,Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics,Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.................................................................................................. 1
• Deleted Ordering Information table. ....................................................................................................................................... 1
l TEXAS INSTRUMENTS DB, DW, OR PW PACKAGE U [ [ [ [ [ [ [ [ [ [ [ [
DB, DW, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
(5 V) VCCA
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
GND
VCCB (3.3 V)
VCCB (3.3 V)
OE
B1
B2
B3
B4
B5
B6
B7
B8
GND
3
SN74LVC4245A
www.ti.com
SCAS375I –MARCH 1994–REVISED JANUARY 2015
Product Folder Links: SN74LVC4245A
Submit Documentation FeedbackCopyright © 1994–2015, Texas Instruments Incorporated
6 Pin Configuration and Functions
Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
1 VCCA — Power supply for side A
2 DIR I Direction control
3 A1 I/O Transceiver I/O pin
4 A2 I/O Transceiver I/O pin
5 A3 I/O Transceiver I/O pin
6 A4 I/O Transceiver I/O pin
7 A5 I/O Transceiver I/O pin
8 A6 I/O Transceiver I/O pin
9 A7 I/O Transceiver I/O pin
10 A8 I/O Transceiver I/O pin
11 GND — Ground
12 GND — Ground
13 GND — Ground
14 B8 I/O Transceiver I/O pin
15 B7 I/O Transceiver I/O pin
16 B6 I/O Transceiver I/O pin
17 B5 I/O Transceiver I/O pin
18 B4 I/O Transceiver I/O pin
19 B3 I/O Transceiver I/O pin
20 B2 I/O Transceiver I/O pin
21 B1 I/O Transceiver I/O pin
22 OE I Output Enable
23 VCCB — Power supply for side B
24 VCCB — Power supply for side B
l TEXAS INSTRUMENTS
4
SN74LVC4245A
SCAS375I –MARCH 1994–REVISED JANUARY 2015
www.ti.com
Product Folder Links: SN74LVC4245A
Submit Documentation Feedback Copyright © 1994–2015, Texas Instruments Incorporated
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) This value is limited to 6 V maximum.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range for VCCA = 4.5 V to 5.5 V (unless otherwise noted)(1)
MIN MAX UNIT
VCCA Supply voltage range –0.5 6.5 V
VIInput voltage range A port(2) –0.5 VCCA + 0.5 V
Control inputs –0.5 6
VOOutput voltage range A port(2) –0.5 VCCA + 0.5 V
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50 mA
IOContinuous output current ±50 mA
Continuous current through each VCCA or GND ±100 mA
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) This value is limited to 4.6 V maximum.
7.2 Absolute Maximum Ratings
over operating free-air temperature range for VCCB = 2.7 V to 3.6 V (unless otherwise noted)(1)
MIN MAX UNIT
VCCB Supply voltage range –0.5 4.6 V
VIInput voltage range B port(2) –0.5 VCCB + 0.5 V
VOOutput voltage range B port(2) –0.5 VCCB + 0.5 V
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50 mA
IOContinuous output current ±50 mA
Continuous current through VCCB or GND ±100 mA
Tstg Storage temperature range –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 ESD Ratings
PARAMETER DEFINITION VALUE UNIT
V(ESD) Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) 1000
l TEXAS INSTRUMENTS
5
SN74LVC4245A
www.ti.com
SCAS375I –MARCH 1994–REVISED JANUARY 2015
Product Folder Links: SN74LVC4245A
Submit Documentation FeedbackCopyright © 1994–2015, Texas Instruments Incorporated
(1) All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI
application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.4 Recommended Operating Conditions
for VCCA = 4.5 V to 5.5 V(1)
MIN MAX UNIT
VCCA Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIA Input voltage 0 VCCA V
VOA Output voltage 0 VCCA V
IOH High-level output current –24 mA
IOL Low-level output current 24 mA
TAOperating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI
application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.5 Recommended Operating Conditions
for VCCB = 2.7 V to 3.6 V(1)
MIN MAX UNIT
VCCB Supply voltage 2.7 3.6 V
VIH High-level input voltage VCCB = 2.7 V to 3.6 V 2 V
VIL Low-level input voltage VCCB = 2.7 V to 3.6 V 0.8 V
VIB Input voltage 0 VCCB V
VOB Output voltage 0 VCCB V
IOH High-level output current VCCB = 2.7 V –12 mA
VCCB = 3 V –24
IOL Low-level output current VCCB = 2.7 V 12 mA
VCCB = 3 V 24
TAOperating free-air temperature –40 85 °C
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.6 Thermal Information
THERMAL METRIC(1)
SN74LVC4245A
UNITDB DW PW
24 PINS
RθJA Junction-to-ambient thermal resistance 63 46 88 °C/W
l TEXAS INSTRUMENTS
6
SN74LVC4245A
SCAS375I –MARCH 1994–REVISED JANUARY 2015
www.ti.com
Product Folder Links: SN74LVC4245A
Submit Documentation Feedback Copyright © 1994–2015, Texas Instruments Incorporated
(1) VCCB = 2.7 V to 3.6 V.
(2) All typical values are measured at VCC = 5 V, TA= 25°C.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
(4) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or the associated
VCC.
7.7 Electrical Characteristics
over recommended operating free-air temperature range for VCCA = 4.5 V to 5.5 V (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCCA MIN TYP(2) MAX UNIT
VOH
IOH = –100 μA4.5 V 4.3
V
5.5 V 5.3
IOH = –24 mA 4.5 V 3.7
5.5 V 4.7
VOL
IOL = 100 μA4.5 V 0.2
V
5.5 V 0.2
IOL = 24 mA 4.5 V 0.55
5.5 V 0.55
IIControl inputs VI= VCCA or GND 5.5 V ±1 μA
IOZ(3) A port VO= VCCA or GND 5.5 V ±5 μA
ICCA VI= VCCA or GND, IO= 0 5.5 V 80 μA
ΔICCA(4) One input at 3.4 V, Other inputs at VCCA or GND 5.5 V 1.5 mA
CiControl inputs VI= VCCA or GND Open 5 pF
Cio A port VO= VCCA or GND 5 V 11 pF
(1) VCCA = 5 V ± 0.5 V.
(2) All typical values are measured at VCC = 3.3 V, TA= 25°C.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
(4) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or the associated
VCC.
7.8 Electrical Characteristics
over recommended operating free-air temperature range for VCCB = 2.7 V to 3.6 V (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCCB MIN TYP(2) MAX UNIT
VOH
IOH = –100 μA 2.7 V to 3.6 V VCC – 0.2
VIOH = –12 mA 2.7 V 2.2
3 V 2.4
IOH = –24 mA 3 V 2
VOL
IOL = 100 μA 2.7 V to 3.6 V 0.2
VIOL = 12 mA 2.7 V 0.4
IOL = 24 mA 3 V 0.55
IOZ(3) B port VO= VCCB or GND 3.6 V ±5 μA
ICCB VI= VCCB or GND, IO= 0 3.6 V 50 μA
ΔICCB(4) One input at VCCB – 0.6
V, Other inputs at VCCB or GND 2.7 V to 3.6 V 0.5 mA
Cio B port VO= VCCB or GND 3.3 V 11 pF
‘5‘ TEXAS INSTRUMENTS 1a m: \ 25 Fun 5:332; \ . 14 m: ‘ 2:: 53 5.338; ‘ .
2
4
6
8
10
12
14
0 50 100 150 200 250 300
CL– Load Capacitance – pF
VCC = 3 V,
TA= 25°C
One Output Switching
Four Outputs Switching
Eight Outputs Switching
t – Propagation Delay Time – ns
pd
2
4
6
8
10
0 50 100 150 200 250 300
CL– Load Capacitance – pF
t – Propagation Delay Time – ns
pd
VCC = 3 V,
TA= 25°C
One Output Switching
Four Outputs Switching
Eight Outputs Switching
7
SN74LVC4245A
www.ti.com
SCAS375I –MARCH 1994–REVISED JANUARY 2015
Product Folder Links: SN74LVC4245A
Submit Documentation FeedbackCopyright © 1994–2015, Texas Instruments Incorporated
7.9 Switching Characteristics
over recommended operating free-air temperature range, CL= 50 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER FROM
(INPUT) TO
(OUTPUT)
VCCA = 5 V ± 0.5 V,
VCCB = 2.7 V to 3.6 V UNIT
MIN MAX
tPHL A B 1 6.3 ns
tPLH 1 6.7
tPHL B A 1 6.1 ns
tPLH 1 5
tPZL OE A 1 9 ns
tPZH 1 8.1
tPZL OE B 1 8.8 ns
tPZH 1 9.8
tPLZ OE A 1 7 ns
tPHZ 1 5.8
tPLZ OE B 1 7.7 ns
tPHZ 1 7.8
7.10 Operating Characteristics
VCCA = 4.5 V to 5.5 V, VCCB = 2.7 V to 3.6 V, TA= 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per transceiver Outputs enabled CL= 0, f = 10 MHz 39.5 pF
Outputs disabled 5
7.11 Typical Characteristics
Figure 1. Propagation Delay (Low to High Transition)
vs Load Capacitance Figure 2. Propagation Delay (High to Low Transition)
vs Load Capacitance
l TEXAS INSTRUMENTS ozxv E An paramemrs and wavefurms are not apphcame to an names.
8
SN74LVC4245A
SCAS375I –MARCH 1994–REVISED JANUARY 2015
www.ti.com
Product Folder Links: SN74LVC4245A
Submit Documentation Feedback Copyright © 1994–2015, Texas Instruments Incorporated
8 Parameter Measurement Information
8.1 A Port
Figure 3. Load Circuit and Voltage Waveforms
TEXAS INSTRUMENTS 07v E An paramemrs and wavefurms are not apphcame to an names.
9
SN74LVC4245A
www.ti.com
SCAS375I –MARCH 1994–REVISED JANUARY 2015
Product Folder Links: SN74LVC4245A
Submit Documentation FeedbackCopyright © 1994–2015, Texas Instruments Incorporated
8.2 B Port
Figure 4. Load Circuit and Voltage Waveforms
l TEXAS INSTRUMENTS _;LY { "J
DIR
OE
A1
B1
To Seven Other Channels
2
3
22
21
10
SN74LVC4245A
SCAS375I –MARCH 1994–REVISED JANUARY 2015
www.ti.com
Product Folder Links: SN74LVC4245A
Submit Documentation Feedback Copyright © 1994–2015, Texas Instruments Incorporated
9 Detailed Description
9.1 Overview
SN74LVC4245A is an 8-bit (octal) noninverting bus transceiver contains two separate supply rails; B port has
VCCB, which is set at 3.3 V, and A port has VCCA, which is set at 5 V. This allows for translation from a 3.3-V to a
5-V environment, and vice versa, designed for asynchronous communication between data buses. The device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated. The control circuitry (DIR, OE) is powered by VCCA.
9.2 Functional Block Diagram
Figure 5. Logic Diagram (Positive Logic)
9.3 Feature Description
• 24 mA drive at 3-V supply
– Good for heavier loads and longer traces
• Low VIH
– Allows 3.3-V to 5-V translation
9.4 Device Functional Modes
Function Table
INPUTS OPERATION
OE DIR
L L B data to A bus
L H A data to B bus
H X Isolation
! TEXAS INSTRUMENTS cc- cc-
C or System
Logic A1
A8
B1
B8
VCCB
GND
C/System
Logic/LEDs
3 V
5 V
OE
VCCA
DIR
11
SN74LVC4245A
www.ti.com
SCAS375I –MARCH 1994–REVISED JANUARY 2015
Product Folder Links: SN74LVC4245A
Submit Documentation FeedbackCopyright © 1994–2015, Texas Instruments Incorporated
10 Application and Implementation
10.1 Application Information
The SN74LVC4245A device pinout allows the designer to switch to a normal all-3.3-V or all-5-V 20-pin '245
device without board re-layout. The designer uses the data paths for pins 2–11 and 14–23 of the
SN74LVC4245A to align with the conventional SN74LVC4245 device's pinout. SN74LVC4245A is a high drive
CMOS device that can be used for a multitude of bus interface type applications where output drive or PCB trace
length is a concern.
10.2 Typical Application
Figure 6. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifcations, see (Δt/ΔV) in the Recommended Operating Conditions table.
– For specified high and low levels, see (VIH and VIL) in the Recommended Operating Conditions table.
2. Recommend Output Conditions:
– Load currents should not exceed (IOmax) per output and should not exceed (Continuous current through
VCC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table.
– Outputs should not be pulled above VCC.
– Series resistors on the output may be used if the user desires to slow the output edge signal or limit the
output current.
l TEXAS INSTRUMENTS 100 so —mA VOL VOH
–100
–80
–60
–40
–20
0
20
40
60
–1 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
TA= 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
VOH – V
IOH – mA
VOL – V
–20
0
20
40
60
80
100
–0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
TA= 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
IOL – mA
12
SN74LVC4245A
SCAS375I –MARCH 1994–REVISED JANUARY 2015
www.ti.com
Product Folder Links: SN74LVC4245A
Submit Documentation Feedback Copyright © 1994–2015, Texas Instruments Incorporated
Typical Application (continued)
10.2.3 Application Curves
Figure 7. Output Drive Current (IOL)
vs LOW-level Output Voltage (VOL)Figure 8. Output Drive Current (IOH)
vs HIGH-level Output Voltage (VOH)
l TEXAS INSTRUMENTS
VCC
Unused Input
Input
Output Output
Input
Unused Input
13
SN74LVC4245A
www.ti.com
SCAS375I –MARCH 1994–REVISED JANUARY 2015
Product Folder Links: SN74LVC4245A
Submit Documentation FeedbackCopyright © 1994–2015, Texas Instruments Incorporated
(1) Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices, literature number SCEA021.
11 Power Supply Recommendations
11.1 Power-Up Consideration
(1)TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up
sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other
anomalies caused by improperly biased device terminals. Take these precautions to guard against such power-
up problems:
1. Connect ground before any supply voltage is applied.
2. Power up the control side of the device (VCCA for all four of these devices).
3. Tie OE to VCCA with a pullup resistor so that it ramps with VCCA.
4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus),
ramp it with VCCA. Otherwise, keep DIR low.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 9 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.
12.2 Layout Example
Figure 9. Layout Diagram
l TEXAS INSTRUMENTS
14
SN74LVC4245A
SCAS375I –MARCH 1994–REVISED JANUARY 2015
www.ti.com
Product Folder Links: SN74LVC4245A
Submit Documentation Feedback Copyright © 1994–2015, Texas Instruments Incorporated
13 Device and Documentation Support
13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LVC4245ADBR ACTIVE SSOP DB 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LJ245A
SN74LVC4245ADBRE4 ACTIVE SSOP DB 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LJ245A
SN74LVC4245ADW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC4245A
SN74LVC4245ADWE4 ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC4245A
SN74LVC4245ADWG4 ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC4245A
SN74LVC4245ADWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 LVC4245A
SN74LVC4245ADWRE4 ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC4245A
SN74LVC4245ADWRG4 ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC4245A
SN74LVC4245APW ACTIVE TSSOP PW 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LJ245A
SN74LVC4245APWG4 ACTIVE TSSOP PW 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LJ245A
SN74LVC4245APWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LJ245A
SN74LVC4245APWRE4 ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LJ245A
SN74LVC4245APWRG4 ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LJ245A
SN74LVC4245APWT ACTIVE TSSOP PW 24 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LJ245A
SN74LVC4245APWTG4 ACTIVE TSSOP PW 24 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LJ245A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC4245A :
•Enhanced Product: SN74LVC4245A-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
I TEXAS INSTRUMENTS 5:. V.’
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Aug-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC4245ADBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1
SN74LVC4245ADWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
SN74LVC4245ADWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
SN74LVC4245ADWRG4 SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
SN74LVC4245APWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
SN74LVC4245APWT TSSOP PW 24 250 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC4245ADBR SSOP DB 24 2000 356.0 356.0 35.0
SN74LVC4245ADWR SOIC DW 24 2000 364.0 361.0 36.0
SN74LVC4245ADWR SOIC DW 24 2000 350.0 350.0 43.0
SN74LVC4245ADWRG4 SOIC DW 24 2000 350.0 350.0 43.0
SN74LVC4245APWR TSSOP PW 24 2000 356.0 356.0 35.0
SN74LVC4245APWT TSSOP PW 24 250 356.0 356.0 35.0
Pack Materials-Page 2
I TEXAS INSTRUMENTS
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Aug-2022
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN74LVC4245ADW DW SOIC 24 25 506.98 12.7 4826 6.6
SN74LVC4245ADWE4 DW SOIC 24 25 506.98 12.7 4826 6.6
SN74LVC4245ADWG4 DW SOIC 24 25 506.98 12.7 4826 6.6
SN74LVC4245APW PW TSSOP 24 60 530 10.2 3600 3.5
SN74LVC4245APW PW TSSOP 24 60 530 10.2 3600 3.5
SN74LVC4245APWG4 PW TSSOP 24 60 530 10.2 3600 3.5
SN74LVC4245APWG4 PW TSSOP 24 60 530 10.2 3600 3.5
Pack Materials-Page 3
I ,/ x /. \_ , ‘ .\ ,, /x ,, S 1 EL fig
www.ti.com
PACKAGE OUTLINE
C
22X 0.65
2X
7.15
24X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
B
NOTE 4
4.5
4.3
A
NOTE 3
7.9
7.7
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0024A
SMALL OUTLINE PACKAGE
4220208/A 02/2017
1
12 13
24
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.000
gmmmflgmmfij ‘w“““‘+“‘w““‘ Emma—5% R
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
24X (1.5)
24X (0.45)
22X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0024A
SMALL OUTLINE PACKAGE
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
12 13
24
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
fiflmmmmmfimmmfi$% Emma—5%g
www.ti.com
EXAMPLE STENCIL DESIGN
24X (1.5)
24X (0.45)
22X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0024A
SMALL OUTLINE PACKAGE
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
12 13
24
MECHANICAL DATA DW «#:5075220 JLASW‘ SMALL 0U J\L HHHHHHHHHHHH’fi N A AH Hnec' d'vnensm m ‘mmes (mammaers) D'ws'nmng md tu‘ermc'mq per ASME w 5M 1994, B TH: drawmq ‘5 Sn :0 change wan: nohce. a Body dimensmns ca nut inc‘ude mom flcsh ur mum" rut m exceed 0035 (055) D FONS WMHH JEDEC MSiOH vermin" ADV NOTES: {if TEXAS INSTRUMENTS wwvmi .com
LAND PATTERN DATA DW (RiPD807024) PLASTIC SMALL OUTLTNE Examp‘e Board Layom (Nuke 9) Non Solder Mask Define Pad ! I — — 0.6 Samar Mask Opening | (No‘e E) I 2,0 V T k I Pad Geometry (Note c) + 0,07 All Around \_./ % 22x1,27 9,4 mm Openin s (New D) g a *24x0.55 22x1.27 @fiflflflfiwfir W 9.4 Anaemia/r 08/13 NOTES: NI Hneur dimensions are In meeters‘ This drawing 15 subjed To Change without noh'ce. Reler To IPC7351 for a‘ternule board design, 905”? Laser cumng aperlures mm (rupezoidal waHS and a‘so rounding corners MU ofler bener pasle release, Cuslomers shou‘d con‘ac‘ Their board assembly 51‘s for s‘encil design recommendations Reler To |PC*7525 Cuswmers should Contact their board fubricah'un site lor so‘der musk lu‘erances between and around STgnul pods, {I} TEXAS INSTRUMENTS www.ti.com
oo A‘ioyi 55 fiHHHHHHHHHHHHfi {'3 TEXAS INSTRUMENTS
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated