SN74LVC1G80 Datasheet by Texas Instruments

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I TEXAS INSTRUMENTS D TG TG TG \ f \ C C C
C
C
TG
C
C
TG
C
C
C
C
C
CLK
D
Q
C
TG
TG
2
1
4
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G80
SCES221S –APRIL 1999REVISED NOVEMBER 2016
SN74LVC1G80 Single Positive-Edge-Triggered D-Type Flip-Flop
1
1 Features
1 Available in the Texas Instruments
NanoFree™ Package
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Supports Down Translation to VCC
Maximum tpd of 4.2 ns at 3.3 V
Low Power Consumption, 10-µA Maximum ICC
±24-mA Output Drive at 3.3 V
• Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
2 Applications
Test and Measurement
Enterprise Switching
Telecom Infrastructure
Motor Drives
3 Description
This single positive-edge-triggered D-type flip-flop is
designed for 1.65-V to 5.5-V VCC operation.
When data at the data (D) input meets the setup time
requirement, the data is transferred to the Q output
on the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following
the hold-time interval, data at the D input can be
changed without affecting the level at the output.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LVC1G80DBV SOT-23 (5) 2.90 mm × 1.60 mm
SN74LVC1G80DCK SC70 (5) 2.00 mm × 1.25 mm
SN74LVC1G80YZP DSBGA (5) 1.41 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
(1) TG - Transmission Gate
l TEXAS INSTRUMENTS
2
SN74LVC1G80
SCES221S –APRIL 1999REVISED NOVEMBER 2016
www.ti.com
Product Folder Links: SN74LVC1G80
Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements: TA= –40°C to +85°C ............ 6
6.7 Timing Requirements: TA= –40°C to +125°C .......... 6
6.8 Switching Characteristics: TA= –40°C to +85°C, CL=
15 pF.......................................................................... 7
6.9 Switching Characteristics: TA= –40°C to +85°C, CL=
30 pF or 50 pF ........................................................... 7
6.10 Switching Characteristics: TA= –40°C to +125°C,
CL= 30 pF or 50 pF................................................... 7
6.11 Operating Characteristics........................................ 7
6.12 Typical Characteristics............................................ 8
7 Parameter Measurement Information .................. 9
8 Detailed Description............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram....................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 11
9 Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 14
12 Device and Documentation Support ................. 15
12.1 Documentation Support ........................................ 15
12.2 Receiving Notification of Documentation Updates 15
12.3 Community Resources.......................................... 15
12.4 Trademarks........................................................... 15
12.5 Electrostatic Discharge Caution............................ 15
12.6 Glossary................................................................ 15
13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision R (December 2013) to Revision S Page
Added Applications section, Device Information table, ESD Ratings table, Thermal Information table, Typical
Characteristics section, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.................................................................................................. 1
Added max junction temperature to the Recommended Operating Conditions table ........................................................... 5
Added operating free-air temperature for YZP package to the Recommended Operating Conditions table ........................ 5
Changed RθJA value for DBV package from: 206°C/W to: 243.4°C/W................................................................................... 5
Changed RθJA value for DCK package from: 252°C/W to: 278.9°C/W................................................................................... 5
Changed RθJA value for YZP package from: 132°C/W to: 136.9°C/W.................................................................................... 5
Changes from Revision Q (January 2007) to Revision R Page
Updated document to new TI data sheet format.................................................................................................................... 1
Removed Ordering Information table. .................................................................................................................................... 1
Updated Ioff in Features. ......................................................................................................................................................... 1
Updated operating temperature range. .................................................................................................................................. 4
Added ESD warning ............................................................................................................................................................ 15
l TEXAS INSTRUMENTS [E [E [E
5
1VCC
D
2
CLK
34
GND Q
2
CLK
34
GND
VCC
5
D
Q
1
2
CLK
VCC
15
D
GND 4
3Q
3
SN74LVC1G80
www.ti.com
SCES221S –APRIL 1999REVISED NOVEMBER 2016
Product Folder Links: SN74LVC1G80
Submit Documentation FeedbackCopyright © 1999–2016, Texas Instruments Incorporated
5 Pin Configuration and Functions
YZP Package
5-Pin DSBGA
Bottom View
DCK Package
5-Pin SC70
Top View
DBV Package
5-Pin SOT-23
Top View
(1) See Mechanical, Packaging, and Orderable Information for dimensions
Pin Functions(1)
PIN I/O DESCRIPTION
NO. NAME
1 D I Data input
2 CLK I Clocking input
3 GND Ground pin
4 Q O Flip-flop output
5 VCC Power pin
l TEXAS INSTRUMENTS
4
SN74LVC1G80
SCES221S –APRIL 1999REVISED NOVEMBER 2016
www.ti.com
Product Folder Links: SN74LVC1G80
Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The value of VCC is provided in Recommended Operating Conditions.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 6.5 V
VIInput voltage(2) –0.5 6.5 V
VOVoltage applied to any output in the high-impedance or power-off state(2) –0.5 6.5 V
VOVoltage applied to any output in the high or low state(2)(3) 0.5 VCC + 0.5 V
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50 mA
IOContinuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
TJJunction temperature 150 °C
Tstg Storage temperature –65 150 ºC
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
VCharged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
Machine model (MM) ±200
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage Operating 1.65 5.5 V
Data retention only 1.5
VIH High-level input voltage
VCC = 1.65 V to 1.95 V 0.65 × VCC
V
VCC = 2.3 V to 2.7 V 1.7
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VIL Low-level input voltage
VCC = 1.65 V to 1.95 V 0.35 × VCC
V
VCC = 2.3 V to 2.7 V 0.7
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VIInput voltage 0 5.5 V
VOOutput voltage 0 VCC V
IOH High-level output current
VCC = 1.65 V –4
mA
VCC = 2.3 V –8
VCC = 3 V –16
–24
VCC = 4.5 V –32
l TEXAS INSTRUMENTS
5
SN74LVC1G80
www.ti.com
SCES221S –APRIL 1999REVISED NOVEMBER 2016
Product Folder Links: SN74LVC1G80
Submit Documentation FeedbackCopyright © 1999–2016, Texas Instruments Incorporated
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
IOL Low-level output current
VCC = 1.65 V 4
mA
VCC = 2.3 V 8
VCC = 3 V 16
24
VCC = 4.5 V 32
Δt/Δv Input transition rise or fall rate
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
ns/VVCC = 3.3 V ± 0.3 V 10
VCC = 5 V ± 0.5 V 5
TJJunction temperature 150 °C
TAOperating free-air temperature DBV and DCK packages –40 125 °C
YZP package –40 85
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1)
SN74LVC1G80
UNITDBV (SOT-23) DCK (SC70) YZP (DSBGA)
5 PINS 5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 243.4 278.9 136.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 179 121.3 1.3 °C/W
RθJB Junction-to-board thermal resistance 77.6 65.6 32.6 °C/W
ψJT Junction-to-top characterization parameter 58.4 7.5 6.3 °C/W
ψJB Junction-to-board characterization parameter 77 64.9 32.6 °C/W
(1) All typical values are at VCC = 3.3 V, TA= 25°C.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT
VOH
IOH = –100 µA 1.65 V to 5.5 V VCC – 0.1
V
IOH = –4 mA 1.65 V 1.2
IOH = –8 mA 2.3 V 1.9
IOH = –16 mA 3 V 2.4
IOH = –24 mA 2.3
IOH = –32 mA 4.5 V 3.8
VOL
IOL = 100 µA 1.65 V to 5.5 V 0.1
V
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.3
IOL = 16 mA 3 V 0.4
IOL = 24 mA 0.55
IOL = 32 mA 4.5 V 0.55
IICLK or D inputs VI= 5.5 V or GND 0 to 5.5 V ±10 µA
Ioff VIor VO= 5.5 V 0 ±10 µA
ICC VI= 5.5 V or GND, IO= 0 1.65 V to 5.5 V 10 µA
ΔICC One input at VCC – 0.6 V,
Other inputs at VCC or GND 3 V to 5.5 V 500 µA
CiVI= VCC or GND TA= –40°C to
85°C 3.3 V 3.5 pF
l TEXAS INSTRUMENTS
6
SN74LVC1G80
SCES221S –APRIL 1999REVISED NOVEMBER 2016
www.ti.com
Product Folder Links: SN74LVC1G80
Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated
6.6 Timing Requirements: TA= –40°C to +85°C
over recommended operating free-air temperature range, TA= –40°C to +85°C (unless otherwise noted) (see Figure 2)
VCC MIN MAX UNIT
fclock Clock frequency
VCC = 1.8 V ± 0.15 V
160 MHz
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5.5 V ± 0.5 V
twPulse duration, CLK high or low
VCC = 1.8 V ± 0.15 V
2.5 ns
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5.5 V ± 0.5 V
tsu Setup time before CLK
Data high
VCC = 1.8 V ± 0.15 V 2.3
ns
VCC = 2.5 V ± 0.2 V 1.5
VCC = 3.3 V ± 0.3 V 1.3
VCC = 5.5 V ± 0.5 V 1.1
Data low
VCC = 1.8 V ± 0.15 V 2.5
VCC = 2.5 V ± 0.2 V 1.5
VCC = 3.3 V ± 0.3 V 1.3
VCC = 5.5 V ± 0.5 V 1.1
thHold time, data after CLK
VCC = 1.8 V ± 0.15 V 0
ns
VCC = 2.5 V ± 0.2 V 0.2
VCC = 3.3 V ± 0.3 V 0.9
VCC = 5.5 V ± 0.5 V 0.4
6.7 Timing Requirements: TA= –40°C to +125°C
over recommended operating free-air temperature range, TA= –40°C to +125°C (unless otherwise noted) (see Figure 2)
VCC MIN MAX UNIT
fclock Clock frequency
VCC = 1.8 V ± 0.15 V
160 MHz
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5.5 V ± 0.5 V
twPulse duration, CLK high or low
VCC = 1.8 V ± 0.15 V
2.5 ns
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5.5 V ± 0.5 V
tsu Setup time before CLK
Data high
VCC = 1.8 V ± 0.15 V 2.3
ns
VCC = 2.5 V ± 0.2 V 1.5
VCC = 3.3 V ± 0.3 V 1.3
VCC = 5.5 V ± 0.5 V 1.1
Data low
VCC = 1.8 V ± 0.15 V 2.5
VCC = 2.5 V ± 0.2 V 1.5
VCC = 3.3 V ± 0.3 V 1.3
VCC = 5.5 V ± 0.5 V 1.1
thHold time, data after CLK
VCC = 1.8 V ± 0.15 V 0
ns
VCC = 2.5 V ± 0.2 V 0.2
VCC = 3.3 V ± 0.3 V 0.9
VCC = 5.5 V ± 0.5 V 0.4
l TEXAS INSTRUMENTS
7
SN74LVC1G80
www.ti.com
SCES221S –APRIL 1999REVISED NOVEMBER 2016
Product Folder Links: SN74LVC1G80
Submit Documentation FeedbackCopyright © 1999–2016, Texas Instruments Incorporated
6.8 Switching Characteristics: TA= –40°C to +85°C, CL= 15 pF
over recommended operating free-air temperature range, TA= –40°C to +85°C, CL= 15 pF (unless otherwise noted) (see
Figure 2)
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC MIN MAX UNIT
fmax
VCC = 1.8 V ± 0.15 V
160 MHz
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
tpd CLK Q
VCC = 1.8 V ± 0.15 V 3 9.1
ns
VCC = 2.5 V ± 0.2 V 1.5 6
VCC = 3.3 V ± 0.3 V 1.3 4.2
VCC = 5 V ± 0.5 V 1.1 3.8
6.9 Switching Characteristics: TA= –40°C to +85°C, CL= 30 pF or 50 pF
over recommended operating free-air temperature range, TA= –40°C to +85°C, CL= 30 pF or 50 pF (unless otherwise noted)
(see Figure 3)
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC MIN MAX UNIT
fmax
VCC = 1.8 V ± 0.15 V
160 MHz
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
tpd CLK Q
VCC = 1.8 V ± 0.15 V 4.4 9.9
ns
VCC = 2.5 V ± 0.2 V 2.3 7
VCC = 3.3 V ± 0.3 V 2 5.2
VCC = 5 V ± 0.5 V 1.3 4.5
6.10 Switching Characteristics: TA= –40°C to +125°C, CL= 30 pF or 50 pF
over recommended operating free-air temperature range, TA= –40°C to +125°C, CL= 30 pF or 50 pF (unless otherwise
noted) (see Figure 3)
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC MIN MAX UNIT
fmax
VCC = 1.8 V ± 0.15 V
160 MHz
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
tpd CLK Q
VCC = 1.8 V ± 0.15 V 4.4 12.5
ns
VCC = 2.5 V ± 0.2 V 2.3 8.5
VCC = 3.3 V ± 0.3 V 2 6
VCC = 5 V ± 0.5 V 1.3 5.5
6.11 Operating Characteristics
TA= 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
Cpd Power dissipation capacitance f = 10 MHz
VCC = 1.8 V 24
pF
VCC = 2.5 V 24
VCC = 3.3 V 25
VCC = 5 V 27
l TEXAS INSTRUMENTS
8
SN74LVC1G80
SCES221S –APRIL 1999REVISED NOVEMBER 2016
www.ti.com
Product Folder Links: SN74LVC1G80
Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated
6.12 Typical Characteristics
This plot shows the different ICC values for various voltages on the data input (D). Voltage sweep on the input is from 0 V to 7
V. VCC = 5 V.
Figure 1. ICC vs VIN
*9 TEXAS INSTRUMENTS «H ; H; ‘ll‘ 1
th
tsu
FromOutput
UnderTest
C
(seeNote A)
L
LOADCIRCUIT
S1
VLOAD
Open
GND
RL
DataInput
TimingInput
0V
0V
0V
tW
Input
0V
Input
Output
Waveform1
S1atV
(seeNoteB)
LOAD
Output
Waveform2
S1atGND
(seeNoteB)
VOL
VOH
0V
»0V
Output
Output
t /t
PLH PHL Open
TEST S1
Output
Control
VM
VMVM
VM
VM
1.8V 0.15V±
2.5V 0.2V±
3.3V 0.3V±
5V 0.5V±
1MW
1MW
1MW
1MW
VCC RL
2× VCC
2× VCC
6V
2× VCC
VLOAD CL
15pF
15pF
15pF
15pF
0.15V
0.15V
0.3V
0.3V
VD
3V
VI
VCC/2
VCC/2
1.5V
VCC/2
VM
£2ns
£2ns
£2.5ns
£2.5ns
INPUTS
RL
t /t
r f
VCC
VCC
VCC
VLOAD
t /t
PLZ PZL
GND
t /t
PHZ PZH
VOLTAGEWAVEFORMS
ENABLE ANDDISABLETIMES
LOW- ANDHIGH-LEVEL ENABLING
VOLTAGEWAVEFORMS
PROPAGATIONDELAY TIMES
INVERTING ANDNONINVERTINGOUTPUTS
NOTES: A. C includesprobeandjigcapacitance.
B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutputcontrol.
Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutputcontrol.
C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR 10MHz,Z =50 .
D. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement.
E. t andt arethesameast .
F. t andt arethesameast .
G. t andt arethesameast .
H. Allparametersandwaveformsarenotapplicabletoalldevices.
L
O
PLZ PHZ dis
PZL PZH en
PLH PHL pd
£ W
VOLTAGEWAVEFORMS
PULSEDURATION
VOLTAGEWAVEFORMS
SETUP ANDHOLDTIMES
VI
VI
VI
VM
VM
V /2
LOAD
tPZL tPLZ
tPHZ
tPZH
V – V
OH D
V +V
OL D
VM
VMVM
VM
VOL
VOH
VI
VI
VOH
VOL
VM
VM
VM
VM
tPLH tPHL
tPLH
tPHL
9
SN74LVC1G80
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SCES221S –APRIL 1999REVISED NOVEMBER 2016
Product Folder Links: SN74LVC1G80
Submit Documentation FeedbackCopyright © 1999–2016, Texas Instruments Incorporated
7 Parameter Measurement Information
Figure 2. Load Circuit and Voltage Waveforms
*9 TEXAS INSTRUMENTS
th
tsu
FromOutput
UnderTest
C
(seeNote A)
L
LOADCIRCUIT
S1
VLOAD
Open
GND
RL
DataInput
TimingInput
0V
0V
0V
tW
Input
0V
Input
Output
Waveform1
S1atV
(seeNoteB)
LOAD
Output
Waveform2
S1atGND
(seeNoteB)
VOL
VOH
0V
»0V
Output
Output
TEST S1
t /t
PLH PHL Open
Output
Control
VM
VMVM
VM
VM
1.8V 0.15V±
2.5V 0.2V±
3.3V 0.3V±
5V 0.5V±
1kW
500 W
500 W
500 W
VCC RL
2× VCC
2× VCC
6V
2× VCC
VLOAD CL
30pF
30pF
50pF
50pF
0.15V
0.15V
0.3V
0.3V
VD
3V
VI
VCC/2
VCC/2
1.5V
VCC/2
VM
£2ns
£2ns
£2.5ns
£2.5ns
INPUTS
RL
t /t
r f
VCC
VCC
VCC
VLOAD
t /t
PLZ PZL
GND
t /t
PHZ PZH
VOLTAGEWAVEFORMS
ENABLE ANDDISABLETIMES
LOW- ANDHIGH-LEVEL ENABLING
VOLTAGEWAVEFORMS
PROPAGATIONDELAY TIMES
INVERTING ANDNONINVERTINGOUTPUTS
NOTES: A. C includesprobeandjigcapacitance.
B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutputcontrol.
Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutputcontrol.
C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR 10MHz,Z =50 .
D. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement.
E. t andt arethesameast .
F. t andt arethesameast .
G. t andt arethesameast .
H. Allparametersandwaveformsarenotapplicabletoalldevices.
L
O
PLZ PHZ dis
PZL PZH en
PLH PHL pd
£ W
VOLTAGEWAVEFORMS
PULSEDURATION
VOLTAGEWAVEFORMS
SETUP ANDHOLDTIMES
VI
VI
VI
VM
VM
V /2
LOAD
tPZL tPLZ
tPHZ
tPZH
V – V
OH D
V +V
OL D
VM
VMVM
VM
VOL
VOH
VI
VI
VOH
VOL
VM
VM
VM
VM
tPLH tPHL
tPLH
tPHL
10
SN74LVC1G80
SCES221S –APRIL 1999REVISED NOVEMBER 2016
www.ti.com
Product Folder Links: SN74LVC1G80
Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated
Parameter Measurement Information (continued)
Figure 3. Load Circuit and Voltage Waveforms
l TEXAS INSTRUMENTS C C J; \ D TG TG \ f C C 070 TG
C
C
TG
C
C
TG
C
C
C
C
C
CLK
D
Q
C
TG
TG
2
1
4
11
SN74LVC1G80
www.ti.com
SCES221S –APRIL 1999REVISED NOVEMBER 2016
Product Folder Links: SN74LVC1G80
Submit Documentation FeedbackCopyright © 1999–2016, Texas Instruments Incorporated
8 Detailed Description
8.1 Overview
The SN74LVC1G80 is a single positive-edge-trigger D-type flip-flop. Data at the input (D) is transferred to the
output (Q) on the positive-going edge of the clock pulse when the setup time requirement is met. Because the
clock triggering occurs at a voltage level, it is not directly related to the rise time of the clock pulse. This allows
for data at the input to be changed without affecting the level at the output, following the hold-time interval.
8.2 Functional Block Diagram
Figure 4. Logic Diagram (Positive Logic)
8.3 Feature Description
This device has a wide operating VCC range of 1.65 V to 5.5 V. The wide operating range allows for a broad
range of systems the device can be used in. The output can handle This device is full specified for partial-power-
down applications. When VCC = 0, the Ioff circuitry disables the outputs, preventing damaging current backflow
through the device.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74LVC1G80.
Table 1. Function Table
INPUTS OUTPUT
Q
CLK D
H L
L H
L X Q0
l TEXAS INSTRUMENTS
MCU
VCC
10 k
GPIO Output
CLK
CLK/2
Q
D
2
1
34
5
CLK
SN74LVC1G80
12
SN74LVC1G80
SCES221S –APRIL 1999REVISED NOVEMBER 2016
www.ti.com
Product Folder Links: SN74LVC1G80
Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A useful application for the SN74LVC1G80 is using it as a frequency divider. By feeding back the output (Q) to
the input (D), the output will toggle on every rising edge of the clock waveform. In other words, the output goes
HIGH once every two clock cycles so essentially the frequency of the clock signal is divided by a factor of two.
The SN74LVC1G80 does not have preset or clear functions so the initial state of the output is unknown. This
application implements the use of a microcontroller GPIO pin to initially set the input HIGH, so the output LOW.
Initialization is not needed, but should be kept in mind. Post initialization, the GPIO pin is set to a high
impedance mode. Depending on the microcontroller, the GPIO pin could be set to an input and used to monitor
the clock division.
9.2 Typical Application
Figure 5. Clock Frequency Division
9.2.1 Design Requirements
For this application a resistor needs to be placed on the feedback line in order for the initialization voltage from
the microcontroller to overpower the signal coming from the output (Q). Without it the state at the input would be
challenged by the GPIO from the microcontroller and from the output of the SN74LVC1G80.
The SN74LVC1G80 device uses CMOS technology and has balanced output drive. Take care to avoid bus
contention because it can drive currents that would exceed maximum limits.
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
For rise time and fall time specifications, see Δt/ΔvinRecommended Operating Conditions.
For specified high and low levels, see VIH and VIL in Recommended Operating Conditions.
Input voltages are recommended to not go below 0 V and not exceed 5.5 V for any VCC. See
Recommended Operating Conditions.
2. Recommended output conditions:
Load currents should not exceed ±50 mA. See Absolute Maximum Ratings .
Output voltages are recommended to not go below 0 V and not exceed the VCC voltage. See
Recommended Operating Conditions.
l TEXAS INSTRUMENTS TekSlop [—1—] H w ch1 Freq l.001kHz I) - - - - chz Freq 500.6 Hz + 5‘ “III-III!— ——-—-—-— -\ 1.00VQ Ch2‘ 1.00VQ M400ps A‘ Ch2 .r 1.56V 28 on 2016 I+v\4.00000ps 14:09:03
13
SN74LVC1G80
www.ti.com
SCES221S –APRIL 1999REVISED NOVEMBER 2016
Product Folder Links: SN74LVC1G80
Submit Documentation FeedbackCopyright © 1999–2016, Texas Instruments Incorporated
Typical Application (continued)
3. Feedback resistor:
A 10-kΩresistor is chosen here to bias the input so the microcontroller GPIO output can initialize the
input and output. The resistor value is important because a resistance too high, say at 1 MΩ, would
cause too much of a voltage drop, causing the output to no longer be able to drive the input. On the other
hand, a resistor too low, such as a 1 Ω, would not bias enough and might cause current to flow into the
microcontroller, possibly damaging the device.
9.2.3 Application Curve
Figure 6. Frequency Division
l TEXAS INSTRUMENTS WORST BETTER / /
WORST BETTER BEST
1W min.
W
2W
14
SN74LVC1G80
SCES221S –APRIL 1999REVISED NOVEMBER 2016
www.ti.com
Product Folder Links: SN74LVC1G80
Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in
Absolute Maximum Ratings . Each VCC terminal must have a good bypass capacitor to prevent power
disturbance. For devices with a single supply, a 0.1-µF bypass capacitor is recommended. If multiple pins are
labeled VCC, then a 0.01-µF or 0.022-µF capacitor is recommended for each VCC because the VCC pins are
tied together internally. For devices with dual-supply pins operating at different voltages, for example VCC and
VDD, a 0.1-µF bypass capacitor is recommended for each supply pin. To reject different frequencies of noise,
use multiple bypass capacitors in parallel. Capacitors with values of 0.1 µF and 1 µF are commonly used in
parallel. The bypass capacitor must be installed as close to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed
separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection
occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to
1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed
capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight
and therefore some traces must turn corners. Figure 7 shows progressively better techniques of rounding
corners. Only the last example (BEST) maintains constant trace width and minimizes reflections.
11.2 Layout Example
Figure 7. Trace Example
l TEXAS INSTRUMENTS
15
SN74LVC1G80
www.ti.com
SCES221S –APRIL 1999REVISED NOVEMBER 2016
Product Folder Links: SN74LVC1G80
Submit Documentation FeedbackCopyright © 1999–2016, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs (SCBA004).
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I TEXAS INSTRUMENTS Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LVC1G80DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C805, C80F, C80J,
C80R)
SN74LVC1G80DBVRE4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C80F
SN74LVC1G80DBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C80F
SN74LVC1G80DBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C805, C80F, C80J,
C80R)
SN74LVC1G80DBVTG4 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C80F
SN74LVC1G80DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CX5, CXF, CXJ, CX
K, CXR)
SN74LVC1G80DCKRE4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CX5
SN74LVC1G80DCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CX5
SN74LVC1G80DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CX5, CXF, CXJ, CX
K, CXR)
SN74LVC1G80YZPR ACTIVE DSBGA YZP 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 (CX7, CXN)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G80 :
Automotive: SN74LVC1G80-Q1
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS Reel Dlameter Cavtty AD Dimension destgned to accommodate the component wmth Eu Dimension destgned to accommodate the componenl Iength K0 Dtmenston destgned to accommodate the component thickness 7 w Ovevau with at the earner tape i Pt PIlCh between successtve cavtty cemers f T ReelWidIh(W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE C) O O O C) O O O ispmckeIHuIes —> User Dtrecllnn OI Feed \I/ Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC1G80DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
SN74LVC1G80DBVR SOT-23 DBV 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1G80DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G80DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G80DBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G80DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
SN74LVC1G80DBVT SOT-23 DBV 5 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1G80DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G80DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
SN74LVC1G80DBVTG4 SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G80DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3
SN74LVC1G80DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G80DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G80DCKRG4 SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G80DCKT SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G80DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G80YZPR DSBGA YZP 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Jul-2020
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G80DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1G80DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1G80DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0
SN74LVC1G80DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1G80DBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1G80DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1G80DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1G80DBVT SOT-23 DBV 5 250 202.0 201.0 28.0
SN74LVC1G80DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1G80DBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1G80DCKR SC70 DCK 5 3000 202.0 201.0 28.0
SN74LVC1G80DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1G80DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1G80DCKRG4 SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1G80DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G80DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G80YZPR DSBGA YZP 5 3000 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Jul-2020
Pack Materials-Page 2
MECHANICAL DATA DCK (R—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE E was 5 47 Fl Fl f f 240 \ ,i, w 1,80 1,10 Pm/ \ ‘ $ ‘ . maexArea Wm H 1* MO Um Gauge Mane Seanng Mane fit Scam Mane gig/Em 409555575/8 U‘ /200/ , m m hmeters NO'FS AH \mec' dwmensiur: Umm> FuHs an JFDFC M07763 vunuhcn AA Tm drawmq \s sumsc: 0 change wmu: nome Body mmensmns do nut mc‘ude mom flcsh m aroms'm Mom Has» and pruvuswon W m exceed 015 :2r m INSrRUMEm-s www.1i.com
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www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.9
1.45
0.90
0.15
0.00 TYP
5X 0.5
0.3
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/E 09/2019
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
‘ ‘ E g ***** $1 Li, ‘0 Q) / n ‘ --II- (£4
www.ti.com
PACKAGE OUTLINE
C
0.5 MAX
0.19
0.15
1
TYP
0.5 TYP
5X 0.25
0.21
0.5
TYP
B E A
D
4219492/A 05/2017
DSBGA - 0.5 mm max heightYZP0005
DIE SIZE BALL GRID ARRAY
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
BALL A1
CORNER
SEATING PLANE
BALL TYP 0.05 C
B
1 2
0.015 C A B
SYMM
SYMM
C
A
SCALE 8.000
D: Max =
E: Max =
1.418 mm, Min =
0.918 mm, Min =
1.358 mm
0.858 mm
www.ti.com
EXAMPLE BOARD LAYOUT
5X ( 0.23)
(0.5) TYP
(0.5) TYP
( 0.23)
METAL
0.05 MAX ( 0.23)
SOLDER MASK
OPENING
0.05 MIN
4219492/A 05/2017
DSBGA - 0.5 mm max heightYZP0005
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
12
A
B
C
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
www.ti.com
EXAMPLE STENCIL DESIGN
(0.5)
TYP
(0.5) TYP
5X ( 0.25) (R0.05) TYP
METAL
TYP
4219492/A 05/2017
DSBGA - 0.5 mm max heightYZP0005
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
12
A
B
C
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