XA Zynq UltraScale+ MPSoC Overview Datasheet by Xilinx Inc.

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Product Specification 1
© Copyright 2016–2017 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of
Xilinx in the United States and other countries. AMBA, AMBA Designer, ARM, ARM1176JZ-S, CoreSight, Cortex, and PrimeCell are trademarks of ARM in the EU and other
countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and are used under license. All other trademarks are the property of their respective owners.
General Description
The XA Zynq® UltraScale+™ MPSoC family is based on the Xilinx® UltraScale™ MPSoC architecture. This
family of products integrates a feature-rich 64-bit quad-core ARM® Cortex™-A53 and dual-core ARM
Cortex-R5 based processing system (PS) and Xilinx programmable logic (PL) UltraScale architecture in a
single device. Also included are on-chip memory, multiport external memory interfaces, and a rich set of
peripheral connectivity interfaces.
Processing System (PS)
ARM Cortex-A53 Based Application
Processing Unit (APU)
Quad-core
CPU frequency: Up to 1.2GHz
Extendable cache coherency
ARMv8-A Architecture
o64-bit or 32-bit operating modes
oTrustZone security
oA64 instruction set in 64-bit mode,
A32/T32 instruction set in 32-bit mode
NEON Advanced SIMD media-processing engine
Single/double precision Floating Point Unit (FPU)
CoreSight™ and Embedded Trace Macrocell (ETM)
Accelerator Coherency Port (ACP)
AXI Coherency Extension (ACE)
Power island gating for each processor core
Timer and Interrupts
oARM Generic timers support
oTwo system level triple-timer counters
oOne watchdog timer
oOne global system timer
Caches
o32KB Level 1, 2-way set-associative
instruction cache with parity (independent for
each CPU)
o32KB Level 1, 4-way set-associative data
cache with ECC (independent for each CPU)
o1MB 16-way set-associative Level 2 cache
with ECC (shared between the CPUs)
Dual-core ARM Cortex-R5 Based
Real-Time Processing Unit (RPU)
CPU frequency: Up to 500MHz
ARMv7-R Architecture
oA32/T32 instruction set
Single/double precision Floating Point Unit (FPU)
CoreSight™ and Embedded Trace Macrocell
(ETM)
Lock-step or independent operation
Timer and Interrupts:
oOne watchdog timer
oTwo triple-timer counters
Caches and Tightly Coupled Memories (TCMs)
o32KB Level 1, 4-way set-associative
instruction and data cache with ECC
(independent for each CPU)
o128KB TCM with ECC (independent for each
CPU) that can be combined to become 256KB
in lockstep mode
On-Chip Memory
256KB on-chip RAM (OCM) in PS with ECC
Up to 18Mb on-chip RAM (UltraRAM) with ECC in
PL
Up to 7.6Mb on-chip RAM (block RAM) with ECC
in PL
Up to 3.5Mb on-chip RAM (distributed RAM) in
PL
XA Zynq UltraScale+ MPSoC
Data Sheet: Overview
DS894 (v1.2) July 13, 2017 Product Specification
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Product Specification 2
ARM Mali-400 Based GPU
Supports OpenGL ES 1.1 and 2.0
Supports OpenVG 1.1
GPU frequency: Up to 600MHz
Single Geometry Processor, Two Pixel Processors
Vertex processing: 66 M Triangles/s
Pixel processing: 1.2 G Pixels/s
64KB L2 Cache
Power island gating
External Memory Interfaces
Multi-protocol dynamic memory controller
32-bit or 64-bit interfaces to DDR4, DDR3,
DDR3L, or LPDDR3 memories, and 32-bit
interface to LPDDR4 memory
ECC support in 64-bit and 32-bit modes
Up to 32GB of address space using single or dual
rank of 8-, 16-, or 32-bit-wide memories
Static memory interfaces
oeMMC4.51 Managed NAND flash support
oONFI3.1 NAND flash with 24-bit ECC
o1-bit SPI, 2-bit SPI, 4-bit SPI (Quad-SPI), or
two Quad-SPI (8-bit) serial NOR flash
8-Channel DMA Controller
Two DMA controllers of 8-channels each
Memory-to-memory, memory-to-peripheral,
peripheral-to-memory, and scatter-gather
transaction support
Serial Transceivers
Four dedicated PS-GTR receivers and
transmitters supports up to 6.0Gb/s data rates
oSupports SGMII tri-speed Ethernet, PCI
Express® Gen2, Serial-ATA (SATA), USB3.0,
and DisplayPort
Dedicated I/O Peripherals and
Interfaces
PCI Express — Compliant with PCIe® 2.1 base
specification
oRoot complex and End Point configurations
ox1, x2, and x4 at Gen1 or Gen2 rates
SATA Host
o1.5, 3.0, and 6.0Gb/s data rates as defined by
SATA Specification, revision 3.1
oSupports up to two channels
DisplayPort Controller
oUp to 5.4Gb/s rate
oUp to two TX lanes (no RX support)
Four 10/100/1000 tri-speed Ethernet MAC
peripherals with IEEE Std 802.3 and IEEE Std 1588
revision 2.0 support
oScatter-gather DMA capability
oRecognition of IEEE Std 1588 rev.2 PTP frames
oGMII, RGMII, and SGMII interfaces
oJumbo frames
Two USB 3.0/2.0 Device, Host, or OTG peripherals,
each supporting up to 12 endpoints
oUSB 3.0/2.0 compliant device IP core
oSuper-speed, high- speed, full-speed, and
low-speed modes
oIntel XHCI- compliant USB host
Two full CAN 2.0B-compliant CAN bus interfaces
oCAN 2.0-A and CAN 2.0-B and ISO 118981-1
standard compliant
Two SD/SDIO 2.0/eMMC4.51 compliant
controllers
Two full-duplex SPI ports with three peripheral
chip selects
Two high-speed UARTs (up to 1Mb/s)
Two master and slave I2C interfaces
Up to 78 flexible multiplexed I/O (MIO) (up to
three banks of 26 I/Os) for peripheral pin
assignment
Up to 96 EMIOs (up to three banks of 32 I/Os)
connected to the PL
Interconnect
High-bandwidth connectivity within PS
and between PS and PL
ARM AMBA® AXI4-based
QoS support for latency and bandwidth control
Cache Coherent Interconnect (CCI)
System Memory Management
System Memory Management Unit (SMMU)
Xilinx Memory Protection Unit (XMPU)
Platform Management Unit
Power gates PS peripherals, power islands, and
power domains
Clock gates PS peripheral user firmware option
Configuration and Security Unit
Boots PS and configures PL
Supports secure and non-secure boot modes
System Monitor in PS
On-chip voltage and temperature sensing
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Product Specification 3
Programmable Logic (PL)
Configurable Logic Blocks (CLB)
Look-up tables (LUT)
Flip-flops
Cascadable adders
36Kb Block RAM
True dual-port
Up to 72 bits wide
Configurable as dual 18Kb
UltraRAM
288Kb dual-port
72 bits wide
Error checking and correction
DSP Blocks
27 x 18 signed multiply
48-bit adder/accumulator
27-bit pre-adder
Programmable I/O Blocks
Supports LVCMOS, LVDS, and SSTL
1.0V to 3.3V I/O
Programmable I/O delay and SerDes
JTAG Boundary-Scan
IEEE Std 1149.1 Compatible Test Interface
PCI Express
Supports Root complex and End Point
configurations
Supports up to Gen3 speeds
Up to two integrated blocks in select devices
Video Encoder/Decoder (VCU)
Available in EV devices
Accessible from either PS or PL
Simultaneous encode and decode
H.264 and H.265 support
System Monitor in PL
On-chip voltage and temperature sensing
10-bit 200KSPS ADC with up to 17 external inputs
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Product Specification 4
Feature Summary
Table 1: XA Zynq UltraScale+ MPSoC: EG Device Feature Summary
XAZU2EG XAZU3EG
Application Processing Unit Quad-core ARM Cortex-A53 MPCore with CoreSight; NEON & Single/Double Precision Floating Point;
32KB/32KB L1 Cache, 1MB L2 Cache
Real-Time Processing Unit Dual-core ARM Cortex-R5 with CoreSight; Single/Double Precision Floating Point; 32KB/32KB L1
Cache, and TCM
Embedded and External
Memory 256KB On-Chip Memory w/ECC; External DDR4; DDR3; DDR3L; LPDDR4; LPDDR3;
External Quad-SPI; NAND; eMMC
General Connectivity 214 PS I/O; UART; CAN; USB 2.0; I2C; SPI; 32b GPIO; Real Time Clock; WatchDog Timers; Triple
Timer Counters
High-Speed Connectivity 4 PS-GTR; PCIe Gen1/2; Serial ATA 3.1; DisplayPort 1.2a; USB 3.0; SGMII
Graphic Processing Unit ARM Mali™-400 MP2; 64KB L2 Cache
System Logic Cells 103,320 154,350
CLB Flip-Flops 94,464 141,120
CLB LUTs 47,232 70,560
Distributed RAM (Mb) 1.2 1.8
Block RAM Blocks 150 216
Block RAM (Mb) 5.3 7.6
UltraRAM Blocks 0 0
UltraRAM (Mb) 0 0
DSP Slices 240 360
CMTs 3 3
Max. HP I/O(1) 156 156
Max. HD I/O(2) 96 96
System Monitor 2 2
GTH Transceiver 12.5Gb/s 0 0
Transceiver Fractional PLLs 0 0
PCIe Gen3 x16 0 0
Notes:
1. HP = High-performance I/O with support for I/O voltage from 1.0V to 1.8V.
2. HD = High-density I/O with support for I/O voltage from 1.2V to 3.3V.
Table 2: XA Zynq UltraScale+ MPSoC: EG Device-Package Combinations and Maximum I/Os
Package
(1)(2)(3) Package Dimensions
(mm) XAZU2EG XAZU3EG
HD, HP, GTH HD, HP, GTH
SBVA484(4) 19x19 24, 58, 0 24, 58, 0
SFVA625 21x21 24, 156, 0 24, 156, 0
SFVC784 23x23 96, 156, 0 96, 156, 0
Notes:
1. Go to Ordering Information for package designation details.
2. All device package combinations bond out 4 PS-GTR transceivers.
3. All device package combinations bond out 214 PS I/O except ZU2EG and ZU3EG in the SBVA484 and SFVA625 packages,
which bond out 170 PS I/Os.
4. All 58 HP I/O pins are powered by the same VCCO supply.
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Product Specification 5
Table 3: XA Zynq UltraScale+ MPSoC: EV Device Feature Summary
XAZU4EV XAZU5EV
Application Processing Unit Quad-core ARM Cortex-A53 MPCore with CoreSight; NEON & Single/Double Precision
Floating Point; 32KB/32KB L1 Cache, 1MB L2 Cache
Real-Time Processing Unit Dual-core ARM Cortex-R5 with CoreSight; Single/Double Precision Floating Point;
32KB/32KB L1 Cache, and TCM
Embedded and External Memory 256KB On-Chip Memory w/ECC; External DDR4; DDR3; DDR3L; LPDDR4; LPDDR3;
External Quad-SPI; NAND; eMMC
General Connectivity 214 PS I/O; UART; CAN; USB 2.0; I2C; SPI; 32b GPIO; Real Time Clock; WatchDog Timers;
Triple Timer Counters
High-Speed Connectivity 4 PS-GTR; PCIe Gen1/2; Serial ATA 3.1; DisplayPort 1.2a; USB 3.0; SGMII
Graphic Processing Unit ARM Mali™-400 MP2; 64KB L2 Cache
Video Codec 1 1
System Logic Cells 192,150 256,200
CLB Flip-Flops 175,680 234,240
CLB LUTs 87,840 117,120
Distributed RAM (Mb) 2.6 3.5
Block RAM Blocks 128 144
Block RAM (Mb) 4.5 5.1
UltraRAM Blocks 48 64
UltraRAM (Mb) 13.5 18.0
DSP Slices 728 1,248
CMTs 4 4
Max. HP I/O(1) 156 156
Max. HD I/O(2) 96 96
System Monitor 2 2
GTH Transceiver 12.5Gb/s 4 4
Transceiver Fractional PLLs 2 2
PCIe Gen3 x16 2 2
Notes:
1. HP = High-performance I/O with support for I/O voltage from 1.0V to 1.8V.
2. HD = High-density I/O with support for I/O voltage from 1.2V to 3.3V.
Table 4: XA Zynq UltraScale+ MPSoC: EV Device-Package Combinations and Maximum I/Os
Package
(1)(2)
Package
Dimensions
(mm)
XAZU4EV XAZU5EV
HD, HP, GTH HD, HP, GTH
SFVC784(3) 23x23 96, 156, 4 96, 156, 4
Notes:
1. Go to Ordering Information for package designation details.
2. All device package combinations bond out 4 PS-GTR transceivers.
3. GTH transceivers in the SFVC784 package support data rates up to 12.5Gb/s.
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Product Specification 6
Zynq UltraScale+ MPSoCs
A comprehensive device family, Zynq UltraScale+ MPSoCs offer single-chip, all programmable,
heterogeneous multiprocessors that provide designers with software, hardware, interconnect, power,
security, and I/O programmability. The range of devices in the Zynq UltraScale+ MPSoC family allows
designers to target cost-sensitive as well as high-performance applications from a single platform using
industry-standard tools. While each Zynq UltraScale+ MPSoC contains the same PS, the PL, Video hard
blocks, and I/O resources vary between the devices.
XA Zynq UltraScale+ MPSoCs are able to serve a wide range of Automotive applications including
multi-camera multi-feature driver assistance systems, high resolution and video graphic infotainment
systems, and driver information.
The UltraScale MPSoC architecture provides processor scalability from 32 to 64 bits with support for
virtualization, the combination of soft and hard engines for real-time control, graphics/video processing,
waveform and packet processing, next-generation interconnect and memory, advanced power
management, and technology enhancements that deliver multi-level security, safety, and reliability. Xilinx
offers a large number of soft IP for the XA Zynq UltraScale+ MPSoC family. Stand-alone and Linux device
drivers are available for the peripherals in the PS and the PL. Xilinx’s Vivado® Design Suite, SDK™, and
PetaLinux development environments enable rapid product development for software, hardware, and
systems engineers. The ARM-based PS also brings a broad range of third-party tools and IP providers in
combination with Xilinx's existing PL ecosystem.
The XA Zynq UltraScale+ MPSoC family delivers unprecedented processing, I/O, and memory bandwidth
in the form of an optimized mix of heterogeneous processing engines embedded in a next-generation,
high-performance, on-chip interconnect with appropriate on-chip memory subsystems. The
heterogeneous processing and programmable engines, which are optimized for different application
tasks, enable the XA Zynq UltraScale+ MPSoC to deliver the extensive performance and efficiency
required to address next-generation smarter systems while retaining backwards compatibility with the
original XA Zynq-7000 All Programmable SoC family. The UltraScale MPSoC architecture also incorporates
multiple levels of security, increased safety, and advanced power management, which are critical
requirements of next-generation smarter systems. Xilinx’s embedded UltraFast™ design methodology fully
exploits the ASIC-class capabilities afforded by the UltraScale MPSoC architecture while supporting rapid
system development.
The inclusion of an application processor enables high-level operating system support (e.g., AutoSAR and
Linux). Other standard operating systems used with the Cortex-A53 processor are also available for the
XA Zynq UltraScale+ MPSoC family. The PS and the PL are on separate power domains, enabling users to
power down the PL for power management if required. The processors in the PS always boot first, allowing
a software centric approach for PL configuration. PL configuration is managed by software running on the
CPU, so it boots similar to an ASSP.
Table 5: XA Zynq UltraScale+ MPSoC Device Features
EG Devices EV Devices
APU Quad-core ARM Cortex-A53 Quad-core ARM Cortex-A53
RPU Dual-core ARM Cortex-R5 Dual-core ARM Cortex-R5
GPU Mali-400MP2 Mali-400MP2
VCU – H.264/H.265
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Product Specification 7
Processing System
Application Processing Unit (APU)
The key features of the APU include:
64-bit quad-core ARM Cortex-A53 MPCores. Features associated with each core include:
oARM v8-A Architecture
oOperating target frequency: up to 1.2GHz
oSingle and double precision floating point:
4SP/2DP FLOPS/MHz
oNEON Advanced SIMD support with single and double precision floating point instructions
oA64 instruction set in 64-bit operating mode, A32/T32 instruction set in 32-bit operating mode
oLevel 1 cache (separate instruction and data, 32KB each for each Cortex-A53 CPU)
2-way set-associative Instruction Cache with parity support
4-way set-associative Data Cache with ECC support
oIntegrated memory management unit (MMU) per processor core
oTrustZone for secure mode operation
oVirtualization support
Ability to operate in single processor, symmetric quad processor, and asymmetric quad-processor modes
Integrated 16-way set-associative 1MB Unified Level 2 cache with ECC support
Interrupts and Timers
oGeneric interrupt controller (GIC-400)
oARM generic timers (4 timers per CPU)
oOne watchdog timer (WDT)
oOne global timer
oTwo triple timers/counters (TTC)
CoreSight debug and trace support
oEmbedded Trace Macrocell (ETM) for instruction trace
oCross trigger interface (CTI) enabling hardware breakpoints and triggers
ACP interface to PL for I/O coherency and Level 2 cache allocation
ACE interface to PL for full coherency
Power island gating on each processor core
Optional eFUSE disable per core
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Product Specification 8
Real-Time Processing Unit (RPU)
Dual-core ARM Cortex-R5 MPCores. Features associated with each core include:
oARM v7-R Architecture (32-bit)
oOperating target frequency: Up to 500MHz
oA32/T32 instruction set support
o4-way set-associative Level 1 caches (separate instruction and data, 32KB each) with ECC support
oIntegrated Memory Protection Unit (MPU) per processor
o128KB Tightly Coupled Memory (TCM) with ECC support
oTCMs can be combined to become 256KB in lockstep mode
Ability to operate in single-processor or dual-processor modes (split and lock-step)
Dedicated SWDT and two Triple Timer Counters (TTC)
CoreSight debug and trace support
oEmbedded Trace Macrocell (ETM) for instruction and trace
oCross trigger interface (CTI) enabling hardware breakpoints and triggers
Optional eFUSE disable
Full-Power Domain DMA (FPD-DMA) and Low-Power Domain DMA
(LPD-DMA)
Two general-purpose DMA controllers one in the full-power domain (FPD-DMA) and one in the low-power
domain (LPD-DMA)
Eight independent channels per DMA
Multiple transfer types:
oMemory-to-memory
oMemory-to-peripheral
oPeripheral-to-memory and
oScatter-gather
8 peripheral interfaces per DMA
TrustZone per DMA for optional secure operation
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Product Specification 9
Xilinx Memory Protection Unit (XMPU)
Region based memory protection unit
Up to 16 regions
Each region supports address alignment of 1MB or 4KB
Regions can overlap; the higher region number has priority
Each region can be independently enabled or disabled
Each region has a start and end address
Graphics Processing Unit (GPU)
Supports OpenGL ES 1.1 & 2.0
Supports OpenVG 1.1
Operating target frequency: up to 600MHz
Single Geometry Processor and two Pixel processor
Vertex processing: 66 M Triangles/s
Pixel processing: 1.2 G Pixels/s
64KB Level 2 Cache (read-only)
4X and 16X Anti-aliasing Support
ETC texture compression to reduce external memory bandwidth
Extensive texture format support
oRGBA 8888, 565, 1556
oMono 8, 16
oYUV format support
Automatic load balancing across different graphics shader engines
2D and 3D graphic acceleration with performance scalable up to 1080p resolutions
Each geometry processor and pixel processor supports 4KB page MMU
Power island gating on each GPU engine and shared cache
Optional eFUSE disable
Dynamic Memory Controller (DDRC)
DDR3, DDR3L, DDR4, LPDDR3, LPDDR4
Target data rate: Up to 2,400Mb/s DDR4 operation in -1 speed grade
32-bit and 64-bit bus width support for DDR4, DDR3, DDR3L, or LPDDR3 memories, and 32-bit bus width
support for LPDDR4 memory
ECC support (using extra bits)
Up to a total DRAM capacity of 32GB
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Product Specification 10
Low power modes
oActive/precharge power down
oSelf-refresh, including clean exit from self-refresh after a controller power cycle
Enhanced DDR training by allowing software to measure read/write eye and make delay adjustments
dynamically
Independent performance monitors for read path and write path
Integration of PHY Debug Access Port (DAP) into JTAG for testing
The DDR memory controller is multi-ported and enables the PS and the PL to have shared access to a
common memory. The DDR controller features six AXI slave ports for this purpose:
Two 128-bit AXI ports from the ARM Cortex-A53 CPU(s), RPU (ARM Cortex-R5 and LPD peripherals), GPU,
high speed peripherals (USB3, PCIe & SATA), and High Performance Ports (HP0 & HP1) from the PL
through the Cache Coherent Interconnect (CCI)
One 64-bit port is dedicated for the ARM Cortex-R5 CPU(s)
One 128-bit AXI port from the DisplayPort and HP2 port from the PL
One 128-bit AXI port from HP3 and HP4 ports from the PL
One 128-bit AXI port from General DMA and HP5 from the PL
High-Speed Connectivity Peripherals
PCIe
Compliant with the PCI Express Base Specification 2.1
Fully compliant with PCI Express transaction ordering rules
Lane width: x1, x2, or x4 at Gen1 or Gen2 rates
1 Virtual Channel
Full duplex PCIe port
End Point and single PCIe link Root Port
Root Port supports Enhanced Configuration Access Mechanism (ECAM), Cfg Transaction generation
Root Port support for INTx, and MSI
Endpoint support for MSI or MSI-X
o1 physical function, no SR-IOV
oNo relaxed or ID ordering
oFully configurable BARs
oINTx not recommended, but can be generated
oEndpoint to support configurable target/slave apertures with address translation and Interrupt
capability
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Product Specification 11
SATA
Compliant with SATA 3.1 Specification
SATA host port supports up to 2 external devices
Compliant with Advanced Host Controller Interface ('AHCI') ver. 1.3
1.5Gb/s, 3.0Gb/s, and 6.0Gb/s data rates
Power management features: supports partial and slumber modes
USB 3.0
Two USB controllers (configurable as USB 2.0 or USB 3.0)
Up to 5.0Gb/s data rate
Host and Device modes
oSuper Speed, High Speed, Full Speed, and Low Speed
oUp to 12 endpoints
oThe USB host controller registers and data structures are compliant to Intel xHCI specifications
o64-bit AXI master port with built-in DMA
oPower management features: Hibernation mode
DisplayPort Controller
4K Display Processing with DisplayPort output
oMaximum resolution of 4K x 2K-30 (30Hz pixel rate)
oDisplayPort AUX channel, and Hot Plug Detect (HPD) on the output
oRGB YCbCr, 4:2:0; 4:2:2, 4:4:4 with 6, 8, 10, and 12b/c
oY-only, xvYCC, RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2, and YCbCr 4:2:0 video format with 6,8,10 and
12-bits per color component
o256-color palette
oMultiple frame buffer formats
o1, 2, 4, 8 bits per pixel (bpp) via a palette
o16, 24, 32bpp
oGraphics formats such as RGBA8888, RGB555, etc.
Accepts streaming video from the PL or dedicated DMA controller
Enables Alpha blending of graphics and Chroma keying
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Product Specification 12
Audio support
oA single stream carries up to 8 LPCM channels at 192kHz with 24-bit resolution
oSupports compressed formats including DRA, Dolby MAT, and DTS HD
oMulti-Stream Transport can extend the number of audio channels
oAudio copy protection
o2-channel streaming or input from the PL
oMulti-channel non-streaming audio from a memory audio frame buffer
Includes a System Time Clock (STC) compliant with ISO/IEC 13818-1
Boot-time display using minimum resources
Platform Management Unit (PMU)
Performs system initialization during boot
Acts as a delegate to the application and real-time processors during sleep state
Initiates power-up and restart after the wake-up request
Maintains the system power state at all time
Manages the sequence of low-level events required for power-up, power-down, reset, clock gating, and
power gating of islands and domains
Provides error management (error handling and reporting)
Provides safety check functions (e.g., memory scrubbing)
The PMU includes the following blocks:
Platform management processor
Fixed ROM for boot-up of the device
128KB RAM with ECC for optional user/firmware code
Local and global registers to manage power-down, power-up, reset, clock gating, and power gating
requests
Interrupt controller with 16 interrupts from other modules and the inter-processor communication
interface (IPI)
GPI and GPO interfaces to and from PS I/O and PL
JTAG interface for PMU debug
Optional User-Defined Firmware
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Product Specification 13
Configuration Security Unit (CSU)
Triple redundant Secure Processor Block (SPB) with built-in ECC
Crypto Interface Block consisting of
o256-bit AES-GCM
oSHA-3/384
o4,096-bit RSA
Key Management Unit
Built-in DMA
PCAP interface
Supports ROM validation during pre-configuration stage
Loads First Stage Boot Loader (FSBL) into OCM in either secure or non-secure boot modes
Supports voltage, temperature, and frequency monitoring after configuration
Xilinx Peripheral Protection Unit (XPPU)
Provides peripheral protection support
Up to 20 masters simultaneously
Multiple aperture sizes
Access control for a specified set of address apertures on a per master basis
64KB peripheral apertures and controls access on per peripheral basis
I/O Peripherals
The IOP unit contains the data communication peripherals. Key features of the IOP include:
Triple-Speed Gigabit Ethernet
Compatible with IEEE Std 802.3 and supports 10/100/1,000Mb/s transfer rates (Full and Half duplex)
Supports jumbo frames
Built-in Scatter-Gather DMA capability
Statistics counter registers for RMON/MIB
Multiple I/O types (1.8, 2.5, 3.3V) on RGMII interface with external PHY
GMII interface to PL to support interfaces as: TBI, SGMII, and RGMII v2.0 support
Automatic pad and cyclic redundancy check (CRC) generation on transmitted frames
Transmitter and Receive IP, TCP, and UDP checksum offload
MDIO interface for physical layer management
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Product Specification 14
Full duplex flow control with recognition of incoming pause frames and hardware generation of
transmitted pause frames
802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged frames
Supports IEEE Std 1588 v2
SD/SDIO 3.0 Controller
In addition to secure digital (SD) devices, this controller also supports eMMC 4.51.
Host mode support only
Built-in DMA
1/4-Bit SD Specification, version 3.0
1/4/8-Bit eMMC Specification, version 4.51
Supports primary boot from SD Card and eMMC (Managed NAND)
High speed, default speed, and low-speed support
1 and 4-bit data interface support
oLow-speed clock 0–400KHz
oDefault speed 0–25MHz
oHigh speed clock 0–50MHz
High-speed Interface
oSD UHS-1: 208MHz
oeMMC HS200: 200MHz
Memory, I/O, and SD cards
Power control modes
Data FIFO interface up to 512B
UART
Programmable baud rate generator
6, 7, or 8 data bits
1, 1.5, or 2 stop bits
Odd, even, space, mark, or no parity
Parity, framing, and overrun error detection
Line break generation and detection
Automatic echo, local loopback, and remote loopback channel modes
Modem control signals: CTS, RTS, DSR, DTR, RI, and DCD (from EMIO only)
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Product Specification 15
SPI
Full-duplex operation offers simultaneous receive and transmit
128B deep read and write FIFO
Master or slave SPI mode
Up to 3 chip select lines
Multi-master environment
Identifies an error condition if more than one master detected
Selectable master clock reference
Software can poll for status or be interrupt driven
I2C
128-bit buffer size
Both normal (100kHz) and fast bus data rates (400kHz)
Master or slave mode
Normal or extended addressing
I2C bus hold for slow host service
GPIO
Up to 128 GPIO bits
oUp to 78-bits from MIO and 96-bits from EMIO
Each GPIO bit can be dynamically programmed as input or output
Independent reset values for each bit of all registers
Interrupt request generation for each GPIO signals
Single Channel (Bit) write capability for all control registers include data output register, direction control
register, and interrupt clear register
Read back in output mode
CAN
Conforms to the ISO 11898 -1, CAN2.0A, and CAN 2.0B standards
Both standard (11-bit identifier) and extended (29-bit identifier) frames
Bit rates up to 1Mb/s
Transmit and Receive message FIFO with a depth of 64 messages
Watermark interrupts for TXFIFO and RXFIFO
Automatic re-transmission on errors or arbitration loss in normal mode
Acceptance filtering of 4 acceptance filters
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Product Specification 16
Sleep Mode with automatic wake-up
Snoop Mode
16-bit time-stamping for receive messages
Both internal generated reference clock and external reference clock input from MIO
Guarantee clock sampling edge between 80 to 83% at 24MHz reference clock input
Optional eFUSE disable per port
USB 2.0
Two USB controllers (configurable as USB 2.0 or USB 3.0)
Host, device and On-The-Go (OTG) modes
High Speed, Full Speed, and Low Speed
Up to 12 endpoints
8-bit ULPI External PHY Interface
The USB host controller registers and data structures are compliant to Intel xHCI specifications.
64-bit AXI master port with built-in DMA
Power management features: hibernation mode
Static Memory Interfaces
The static memory interfaces support external static memories.
ONFI 3.1 NAND flash support with up to 24-bit ECC
1-bit SPI, 2-bit SPI, 4-bit SPI (Quad-SPI), or two Quad-SPI (8-bit) serial NOR flash
8-bit eMMC interface supporting managed NAND flash
NAND ONFI 3.1 Flash Controller
ONFI 3.1 compliant
Supports chip select reduction per ONFI 3.1 spec
SLC NAND for boot/configuration and data storage
ECC options based on SLC NAND
o1, 4, or 8 bits per 512+spare bytes
o24 bits per 1,024+spare bytes
Max bandwidth as follows
oAsynchronous mode (SDR) at 50MHz
oSynchronous mode (NV-DDR) at 100MHz (200Mb/s)
8-bit SDR NAND interface
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Product Specification 17
2 chip selects
Programmable access timing
1.8V and 3.3V I/O
Built-in DMA for improved performance
Quad-SPI Controller
4 bytes (32-bit) and 3 bytes (24-bit) address width
Maximum SPI Clock at Master Mode at 150MHz
Single, Dual-Parallel, and Dual-Stacked mode
32-bit AXI Linear Address Mapping Interface for read operation
Up to 2 chip select signals
Write Protection Signal
Hold signals
4-bit bidirectional I/O signals
x1/x2/x4 Read speed required
x1 write speed required only
64 byte Entry FIFO depth to improve QSPI read efficiency
Built-in DMA for improved performance
Video Encoder/Decoder (VCU)
Zynq UltraScale+ MPSoCs include a Video codec (encoder/decoder) available in the devices designated
with the EV suffix. The VCU is located in the PL and can be accessed from either the PL or PS.
Simultaneous Encode and Decode through separate cores
H.264 high profile level 5.2 (4Kx2K-60)
H.265 (HEVC) main, main10 profile, level 5.1, high Tier, up to 4Kx2K-60 rate
8 and 10 bit encoding
4:2:0 and 4:2:2 chroma sampling
8Kx4K-15 rate
Multi-stream up to total of 4Kx2K-60 rate
Low Latency mode
Can share the PS DRAM or use dedicated DRAM in the PL
Clock/power management
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Product Specification 18
Interconnect
All the blocks are connected to each other and to the PL through a multi-layered ARM Advanced
Microprocessor Bus Architecture (AMBA) AXI interconnect. The interconnect is non-blocking and supports
multiple simultaneous master-slave transactions.
The interconnect is designed with latency sensitive masters, such as the ARM CPU, having the shortest
paths to memory, and bandwidth critical masters, such as the potential PL masters, having high
throughput connections to the slaves with which they need to communicate.
Traffic through the interconnect can be regulated through the Quality of Service (QoS) block in the
interconnect. The QoS feature is used to regulate traffic generated by the CPU, DMA controller, and a
combined entity representing the masters in the IOP.
PS Interfaces
PS interfaces include external interfaces going off-chip or signals going from PS to PL.
PS External Interfaces
The Zynq UltraScale+ MPSoC’s external interfaces use dedicated pins that cannot be assigned as PL pins.
These include:
Clock, reset, boot mode, and voltage reference
Up to 78 dedicated multiplexed I/O (MIO) pins, software-configurable to connect to any of the internal I/O
peripherals and static memory controllers
32-bit or 64-bit DDR4/DDR3/DDR3L/LPDDR3 memories with optional ECC
32-bit LPDDR4 memory with optional ECC
4 channels (TX and RX pair) for transceivers
MIO Overview
The IOP peripherals communicate to external devices through a shared pool of up to 78 dedicated
multiplexed I/O (MIO) pins. Each peripheral can be assigned one of several pre-defined groups of pins,
enabling a flexible assignment of multiple devices simultaneously. Although 78 pins are not enough for
simultaneous use of all the I/O peripherals, most IOP interface signals are available to the PL, allowing use
of standard PL I/O pins when powered up and properly configured. Extended multiplexed I/O (EMIO) allows
unmapped PS peripherals to access PL I/O.
Port mappings can appear in multiple locations. For example, there are up to 12 possible port mappings
for CAN pins. The PS Configuration Wizard (PCW) tool aids in peripheral and static memory pin mapping.
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Transceiver (PS-GTR)
The four PS-GTR transceivers, which reside in the full power domain (FPD), support data rates of up to
6.0Gb/s. All the protocols cannot be pinned out at the same time. At any given time, four differential pairs
can be pinned out using the transceivers. This is user programmable via the high-speed I/O multiplexer
(HS-MIO).
A Quad transceiver PS-GTR (TX/RX pair) able to support following standards simultaneously
ox1, x2, or x4 lane of PCIe at Gen1 (2.5Gb/s) or Gen2 (5.0Gb/s) rates
o1 or 2 lanes of DisplayPort (TX only) at 1.62Gb/s, 2.7Gb/s, or 5.4Gb/s
o1 or 2 SATA channels at 1.5Gb/s, 3.0Gb/s, or 6.0Gb/s
o1 or 2 USB3.0 channels at 5.0Gb/s
o1-4 Ethernet SGMII channels at 1.25Gb/s
Provides flexible host-programmable multiplexing function for connecting the transceiver resources to the
PS masters (DisplayPort, PCIe, Serial-ATA, USB3.0, and GigE).
Table 6: MIO Peripheral Interface Mapping
Peripheral
Interface MIO EMIO
Quad-SPI
NAND Yes No
USB2.0: 0,1 Yes: External PHY No
SDIO 0,1 Yes Yes
SPI: 0,1
I2C: 0,1
CAN: 0,1
GPIO
Yes
CAN: External PHY
GPIO: Up to 78 bits
Yes
CAN: External PHY
GPIO: Up to 96 bits
GigE: 0,1,2,3 RGMII v2.0:
External PHY Supports GMII, RGMII v2.0 (HSTL), RGMII v1.3, MII, SGMII, and
1000BASE-X in Programmable Logic
UART: 0,1 Simple UART:
Only two pins (TX and RX) Full UART (TX, RX, DTR, DCD, DSR, RI, RTS, and CTS) requires either:
Two Processing System (PS) pins (RX and TX) through MIO and six
additional Programmable Logic (PL) pins, or
Eight Programmable Logic (PL) pins
Debug Trace Ports Yes: Up to 16 trace bits Yes: Up to 32 trace bits
Processor JTAG Yes Yes
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Product Specification 20
HS-MIO
The function of the HS-MIO is to multiplex access from the high-speed PS peripheral to the differential
pair on the PS-GTR transceiver as defined in the configuration registers. Up to 4 channels of the
transceiver are available for use by the high-speed interfaces in the PS.
PS-PL Interface
The PS-PL interface includes:
AMBA AXI4 interfaces for primary data communication
oSix 128-bit/64-bit/32-bit High Performance (HP) Slave AXI interfaces from PL to PS.
Four 128-bit/64-bit/32-bit HP AXI interfaces from PL to PS DDR.
Two 128-bit/64-bit/32-bit high-performance coherent (HPC) ports from PL to cache coherent
interconnect (CCI).
oTwo 128-bit/64-bit/32-bit HP Master AXI interfaces from PS to PL.
oOne 128-bit/64-bit/32-bit interface from PL to RPU in PS (PL_LPD) for low latency access to OCM.
oOne 128-bit/64-bit/32-bit AXI interface from RPU in PS to PL (LPD_PL) for low latency access to PL.
oOne 128-bit AXI interface (ACP port) for I/O coherent access from PL to Cortex-A53 cache memory.
This interface provides coherency in hardware for Cortex-A53 cache memory.
oOne 128-bit AXI interface (ACE Port) for Fully coherent access from PL to Cortex-A53. This interface
provides coherency in hardware for Cortex-A53 cache memory and the PL.
Clocks and resets
oFour PS clock outputs to the PL with start/stop control.
oFour PS reset outputs to the PL.
Table 7: HS-MIO Peripheral Interface Mapping
Peripheral Interface Lane0 Lane1 Lane2 Lane3
PCIe (x1, x2 or x4) PCIe0 PCIe1 PCIe2 PCIe3
SATA (1 or 2 channels) SATA0 SATA1 SATA0 SATA1
DisplayPort (TX only) DP1 DP0 DP1 DP0
USB0 USB0 USB0 USB0
USB1 – USB1
SGMII0 SGMII0 – – –
SGMII1 – SGMII1 –
SGMII2 – SGMII2 –
SGMII3 – SGMII3
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High-Performance AXI Ports
The high-performance AXI4 ports provide access from the PL to DDR and high-speed interconnect in the
PS. The six dedicated AXI memory ports from the PL to the PS are configurable as either 128-bit, 64-bit,
or 32-bit interfaces. These interfaces connect the PL to the memory interconnect via a FIFO interface. Two
of the AXI interfaces support I/O coherent access to the APU caches.
Each high-performance AXI port has these characteristics:
Reduced latency between PL and processing system memory
1KB deep FIFO
Configurable either as 128-bit, 64-bit, or 32-bit AXI interfaces
Multiple AXI command issuing to DDR
Accelerator Coherency Port (ACP)
The Zynq UltraScale+ MPSoC accelerator coherency port (ACP) is a 64-bit AXI slave interface that provides
connectivity between the APU and a potential accelerator function in the PL. The ACP directly connects the
PL to the snoop control unit (SCU) of the ARM Cortex-A53 processors, enabling cache-coherent access to
CPU data in the L2 cache. The ACP provides a low latency path between the PS and a PL-based accelerator
when compared with a legacy cache flushing and loading scheme. The ACP only snoops access in the CPU
L2 cache, providing coherency in hardware. It does not support coherency on the PL side. So this interface
is ideal for a DMA or an accelerator in the PL that only requires coherency on the CPU cache memories. For
example, if a MicroBlaze™ processor in the PL is attached to the ACP interface, the cache of MicroBlaze
processor will not be coherent with Cortex-A53 caches.
AXI Coherency Extension (ACE)
The Zynq UltraScale+ MPSoC AXI coherency extension (ACE) is a 64-bit AXI4 slave interface that provides
connectivity between the APU and a potential accelerator function in the PL. The ACE directly connects the
PL to the snoop control unit (SCU) of the ARM Cortex-A53 processors, enabling cache-coherent access to
Cache Coherent Interconnect (CCI). The ACE provides a low-latency path between the PS and a PL-based
accelerator when compared with a legacy cache flushing and loading scheme. The ACE snoops accesses to
the CCI and the PL side, thus, providing full coherency in hardware. This interface can be used to hook up
a cached interface in the PL to the PS as caches on both the Cortex-A53 memories and the PL master are
snooped thus providing full coherency. For example, if a MicroBlaze processor in the PL is hooked up using
an ACE interface, then Cortex-A53 and MicroBlaze processor caches will be coherent with each other.
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Product Specification 22
Programmable Logic
This section covers the information about blocks in the Programmable Logic (PL).
Device Layout
UltraScale architecture-based devices are arranged in a column-and-grid layout. Columns of resources are
combined in different ratios to provide the optimum capability for the device density, target market or
application, and device cost. At the core of UltraScale+ MPSoCs is the processing system that displaces
some of the full or partial columns of programmable logic resources. Figure 1 shows a device-level view
with resources grouped together. For simplicity, certain resources such as the processing system,
integrated blocks for PCIe, configuration logic, and System Monitor are not shown.
Resources within the device are divided into segmented clock regions. The height of a clock region is
60 CLBs. A bank of 52 I/Os, 24 DSP slices, 12 block RAMs, or 4 transceiver channels also matches the height
of a clock region. The width of a clock region is essentially the same in all cases, regardless of device size
or the mix of resources in the region, enabling repeatable timing results. Each segmented clock region
contains vertical and horizontal clock routing that span its full height and width. These horizontal and
vertical clock routes can be segmented at the clock region boundary to provide a flexible,
high-performance, low-power clock distribution architecture. Figure 2 is a representation of a device
divided into regions.
X-Ref Target - Figure 1
Figure 1: Device with Columnar Resources
I/O, Clocking, Memory Interface Logic
I/O, Clocking, Memory Interface Logic
CLB, DSP, Block RAM
CLB, DSP, Block RAM
Transceivers
Transceivers
CLB, DSP, Block RAM
DS891_01_012915
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Input/Output
All Zynq UltraScale+ MPSoCs have I/O pins for communicating to external components. In addition, in the
MPSoC’s PS, there are another 78 I/Os that the I/O peripherals use to communicate to external
components, referred to as multiplexed I/O (MIO). If more than 78 pins are required by the I/O peripherals,
the I/O pins in the PL can be used to extend the MPSoC interfacing capability, referred to as extended MIO
(EMIO).
The number of I/O pins in the PL of Zynq UltraScale+ MPSoCs varies depending on device and package.
Each I/O is configurable and can comply with a large number of I/O standards. The I/Os are classed as
high-performance (HP), or high-density (HD). The HP I/Os are optimized for highest performance
operation, from 1.0V to 1.8V. The HD I/Os are reduced-feature I/Os organized in banks of 24, providing
voltage support from 1.2V to 3.3V.
All I/O pins are organized in banks, with 52 HP pins per bank or 24 HD pins per bank. Each bank has one
common VCCO output buffer power supply, which also powers certain input buffers. Some single-ended
input buffers require an internally generated or an externally applied reference voltage (VREF). VREF pins
can be driven directly from the PCB or internally generated using the internal VREF generator circuitry
present in each bank.
I/O Electrical Characteristics
Single-ended outputs use a conventional CMOS push/pull output structure driving High towards VCCO or
Low towards ground, and can be put into a high-Z state. The system designer can specify the slew rate and
the output strength. The input is always active but is usually ignored while the output is active. Each pin
can optionally have a weak pull-up or a weak pull-down resistor.
Most signal pin pairs can be configured as differential input pairs or output pairs. Differential input pin
pairs can optionally be terminated with a 100Ω internal resistor. All UltraScale architecture-based devices
support differential standards beyond LVDS, including RSDS, BLVDS, differential SSTL, and differential
HSTL. Each of the I/Os supports memory I/O standards, such as single-ended and differential HSTL as well
as single-ended and differential SSTL.
X-Ref Target - Figure 2
Figure 2: Column-Based Device Divided into Clock Regions
Clock Region Width
Clock
Region
Height
DS891_02_012915
For graphical representation only, does not represent a real device.
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Product Specification 24
3-State Digitally Controlled Impedance and Low Power I/O Features
The 3-state Digitally Controlled Impedance (T_DCI) can control the output drive impedance (series
termination) or can provide parallel termination of an input signal to VCCO or split (Thevenin) termination
to VCCO/2. This allows users to eliminate off-chip termination for signals using T_DCI. In addition to board
space savings, the termination automatically turns off when in output mode or when 3-stated, saving
considerable power compared to off-chip termination. The I/Os also have low power modes for IBUF and
IDELAY to provide further power savings, especially when used to implement memory interfaces.
I/O Logic
Input and Output Delay
All inputs and outputs can be configured as either combinatorial or registered. Double data rate (DDR) is
supported by all inputs and outputs. Any input or output can be individually delayed by up to 1,250ps of
delay with a resolution of 5–15ps. Such delays are implemented as IDELAY and ODELAY. The number of
delay steps can be set by configuration and can also be incremented or decremented while in use. The
IDELAY and ODELAY can be cascaded together to double the amount of delay in a single direction.
ISERDES and OSERDES
Many applications combine high-speed, bit-serial I/O with slower parallel operation inside the device. This
requires a serializer and deserializer (SerDes) inside the I/O logic. Each I/O pin possesses an IOSERDES
(ISERDES and OSERDES) capable of performing serial-to-parallel or parallel-to-serial conversions with
programmable widths of 2, 4, or 8 bits. These I/O logic features enable high-performance interfaces, such
as Gigabit Ethernet/1000BaseX/SGMII, to be moved from the transceivers to the SelectIO™ interface.
High-Speed Serial Transceivers
Ultra-fast serial data transmission between devices on the same PCB, over backplanes, and across even
longer distances is becoming increasingly important for scaling to 100Gb/s and 400Gb/s line cards.
Specialized dedicated on-chip circuitry and differential I/O capable of coping with the signal integrity
issues are required at these high data rates.
Two types of transceivers are used in the XA Zynq UltraScale+ MPSoC: GTH and PS-GTR. Both transceivers
are arranged in groups of four, known as a transceiver Quad. Each serial transceiver is a combined
transmitter and receiver. Table 8 compares the available transceivers.
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Product Specification 25
The following information in this section pertains to the GTH only.
The serial transmitter and receiver are independent circuits that use an advanced phase-locked loop (PLL)
architecture to multiply the reference frequency input by certain programmable numbers between 4 and
25 to become the bit-serial data clock. Each transceiver has a large number of user-definable features and
parameters. All of these can be defined during device configuration, and many can also be modified
during operation.
Transmitter
The transmitter is fundamentally a parallel-to-serial converter with a conversion ratio of 16, 20, 32, 40, 64,
or 80 for the GTH. This allows the designer to trade off datapath width against timing margin in
high-performance designs. These transmitter outputs drive the PC board with a single-channel differential
output signal. TXOUTCLK is the appropriately divided serial data clock and can be used directly to register
the parallel data coming from the internal logic. The incoming parallel data is fed through an optional FIFO
and has additional hardware support for the 8B/10B, 64B/66B, or 64B/67B encoding schemes to provide a
sufficient number of transitions. The bit-serial output signal drives two package pins with differential
signals. This output signal pair has programmable signal swing as well as programmable pre- and
post-emphasis to compensate for PC board losses and other interconnect characteristics. For shorter
channels, the swing can be reduced to reduce power consumption.
Receiver
The receiver is fundamentally a serial-to-parallel converter, changing the incoming bit-serial differential
signal into a parallel stream of words, each 16, 20, 32, 40, 64, or 80 bits in the GTH. This allows the designer
to trade off internal datapath width against logic timing margin. The receiver takes the incoming
differential data stream, feeds it through programmable DC automatic gain control, linear and decision
feedback equalizers (to compensate for PC board, cable, optical and other interconnect characteristics),
and uses the reference clock input to initiate clock recognition. There is no need for a separate clock line.
The data pattern uses non-return-to-zero (NRZ) encoding and optionally ensures sufficient data
transitions by using the selected encoding scheme. Parallel data is then transferred into the device logic
using the RXUSRCLK clock. For short channels, the transceivers offer a special low-power mode (LPM) to
reduce power consumption by approximately 30%. The receiver DC automatic gain control and linear and
decision feedback equalizers can optionally “auto-adapt” to automatically learn and compensate for
different interconnect characteristics. This enables even more margin for tough 10G+ and 25G+
backplanes.
Table 8: Transceiver Information
XA Zynq UltraScale+ MPSoC
Type PS-GTR GTH
Qty 4 0–4
Max. Data Rate 6.0Gb/s 12.5Gb/s
Min. Data Rate 1.25Gb/s 0.5Gb/s
Applications
PCIe Gen2
USB
Ethernet
Backplane
PCIe Gen3
HMC
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Product Specification 26
Out-of-Band Signaling
The transceivers provide out-of-band (OOB) signaling, often used to send low-speed signals from the
transmitter to the receiver while high-speed serial data transmission is not active. This is typically done
when the link is in a powered-down state or has not yet been initialized. This benefits PCIe and SATA/SAS
and QPI applications.
Integrated Interface Blocks for PCI Express Designs
The MPSoC PL includes integrated blocks for PCIe technology that can be configured as an Endpoint or
Root Port, compliant to the PCI Express Base Specification Revision 3.1 for Gen3 and lower data rates. The
Root Port can be used to build the basis for a compatible Root Complex, to allow custom chip-to-chip
communication via the PCI Express protocol, and to attach ASSP Endpoint devices, such as Ethernet
Controllers or Fibre Channel HBAs, to the MPSoC.
This block is highly configurable to system design requirements and can operate 1, 2, 4, 8, or 16 lanes at
up to 2.5Gb/s, 5.0Gb/s, or 8.0Gb/s data rates. For high-performance applications, advanced buffering
techniques of the block offer a flexible maximum payload size of up to 1,024 bytes. The integrated block
interfaces to the integrated high-speed transceivers for serial connectivity and to block RAMs for data
buffering. Combined, these elements implement the Physical Layer, Data Link Layer, and Transaction Layer
of the PCI Express protocol.
Xilinx provides a light-weight, configurable, easy-to-use LogiCORE™ IP wrapper that ties the various
building blocks (the integrated block for PCIe, the transceivers, block RAM, and clocking resources) into an
Endpoint or Root Port solution. The system designer has control over many configurable parameters: link
width and speed, maximum payload size, MPSoC logic interface speeds, reference clock frequency, and
base address register decoding and filtering.
Clock Management
The clock generation and distribution components in UltraScale architecture-based devices are located
adjacent to the columns that contain the memory interfacing and input and output circuitry. This tight
coupling of clocking and I/O provides low-latency clocking to the I/O for memory interfaces and other I/O
protocols. Within every clock management tile (CMT) resides one mixed-mode clock manager (MMCM),
two PLLs, clock distribution buffers and routing, and dedicated circuitry for implementing external
memory interfaces.
Mixed-Mode Clock Manager
The mixed-mode clock manager (MMCM) can serve as a frequency synthesizer for a wide range of
frequencies and as a jitter filter for incoming clocks. At the center of the MMCM is a voltage-controlled
oscillator (VCO), which speeds up and slows down depending on the input voltage it receives from the
phase frequency detector (PFD).
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Three sets of programmable frequency dividers (D, M, and O) are programmable by configuration and
during normal operation via the Dynamic Reconfiguration Port (DRP). The pre-divider D reduces the input
frequency and feeds one input of the phase/frequency comparator. The feedback divider M acts as a
multiplier because it divides the VCO output frequency before feeding the other input of the phase
comparator. D and M must be chosen appropriately to keep the VCO within its specified frequency range.
The VCO has eight equally-spaced output phases (0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). Each
phase can be selected to drive one of the output dividers, and each divider is programmable by
configuration to divide by any integer from 1 to 128.
The MMCM has three input-jitter filter options: low bandwidth, high bandwidth, or optimized mode.
Low-Bandwidth mode has the best jitter attenuation. High-Bandwidth mode has the best phase offset.
Optimized mode allows the tools to find the best setting.
The MMCM can have a fractional counter in either the feedback path (acting as a multiplier) or in one
output path. Fractional counters allow non-integer increments of 1/8 and can thus increase frequency
synthesis capabilities by a factor of 8. The MMCM can also provide fixed or dynamic phase shift in small
increments that depend on the VCO frequency. At 1,600MHz, the phase-shift timing increment is 11.2ps.
PLL
With fewer features than the MMCM, the two PLLs in a clock management tile are primarily present to
provide the necessary clocks to the dedicated memory interface circuitry. The circuit at the center of the
PLLs is similar to the MMCM, with PFD feeding a VCO and programmable M, D, and O counters. There are
two divided outputs to the device fabric per PLL as well as one clock plus one enable signal to the memory
interface circuitry.
Zynq UltraScale+ MPSoCs are equipped with five additional PLLs in the PS for independently configuring
the four primary clock domains with the PS: the APU, the RPU, the DDR controller, and the I/O peripherals.
Clock Distribution
Clocks are distributed throughout Zynq UltraScale+ MPSoCs via buffers that drive a number of vertical
and horizontal tracks. There are 24 horizontal clock routes per clock region and 24 vertical clock routes per
clock region with 24 additional vertical clock routes adjacent to the MMCM and PLL. Within a clock region,
clock signals are routed to the device logic (CLBs, etc.) via 16 gateable leaf clocks.
Several types of clock buffers are available. The BUFGCE and BUFCE_LEAF buffers provide clock gating at
the global and leaf levels, respectively. BUFGCTRL provides glitchless clock muxing and gating capability.
BUFGCE_DIV has clock gating capability and can divide a clock by 1 to 8. BUFG_GT performs clock division
from 1 to 8 for the transceiver clocks. In MPSoCs, clocks can be transferred from the PS to the PL using
dedicated buffers.
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Memory Interfaces
Memory interface data rates continue to increase, driving the need for dedicated circuitry that enables
high performance, reliable interfacing to current and next-generation memory technologies. Every
Zynq UltraScale+ MPSoC includes dedicated physical interfaces (PHY) blocks located between the CMT
and I/O columns that support implementation of high-performance PHY blocks to external memories such
as DDR4, DDR3, QDRII+, and RLDRAM3. The PHY blocks in each I/O bank generate the address/control
and data bus signaling protocols as well as the precision clock/data alignment required to reliably
communicate with a variety of high-performance memory standards. Multiple I/O banks can be used to
create wider memory interfaces.
As well as external parallel memory interfaces, Zynq UltraScale+ MPSoC can communicate to external
serial memories, such as Hybrid Memory Cube (HMC), via the high-speed serial transceivers. All
transceivers in the UltraScale architecture support the HMC protocol, up to 12.5Gb/s line rates. UltraScale
architecture-based devices support the highest bandwidth HMC configuration of 64 lanes with a single
device.
Configurable Logic Block
Every Configurable Logic Block (CLB) in the UltraScale architecture contains 8 LUTs and 16 flip-flops. The
LUTs can be configured as either one 6-input LUT with one output, or as two 5-input LUTs with separate
outputs but common inputs. Each LUT can optionally be registered in a flip-flop. In addition to the LUTs
and flip-flops, the CLB contains arithmetic carry logic and multiplexers to create wider logic functions.
Each CLB contains one slice. There are two types of slices: SLICEL and SLICEM. LUTs in the SLICEM can be
configured as 64-bit RAM, as 32-bit shift registers (SRL32), or as two SRL16s. CLBs in the UltraScale
architecture have increased routing and connectivity compared to CLBs in previous-generation Xilinx
devices. They also have additional control signals to enable superior register packing, resulting in overall
higher device utilization.
Interconnect
Various length vertical and horizontal routing resources in the UltraScale architecture that span 1, 2, 4, 5,
12, or 16 CLBs ensure that all signals can be transported from source to destination with ease, providing
support for the next generation of wide data buses to be routed across even the highest capacity devices
while simultaneously improving quality of results and software run time.
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Product Specification 29
Block RAM
Every UltraScale architecture-based device contains a number of 36Kb block RAMs, each with two
completely independent ports that share only the stored data. Each block RAM can be configured as one
36Kb RAM or two independent 18Kb RAMs. Each memory access, read or write, is controlled by the clock.
Connections in every block RAM column enable signals to be cascaded between vertically adjacent block
RAMs, providing an easy method to create large, fast memory arrays, and FIFOs with greatly reduced
power consumption.
All inputs, data, address, clock enables, and write enables are registered. The input address is always
clocked (unless address latching is turned off), retaining data until the next operation. An optional output
data pipeline register allows higher clock rates at the cost of an extra cycle of latency. During a write
operation, the data output can reflect either the previously stored data or the newly written data, or it can
remain unchanged. Block RAM sites that remain unused in the user design are automatically powered
down to reduce total power consumption. There is an additional pin on every block RAM to control the
dynamic power gating feature.
Programmable Data Width
Each port can be configured as 32K × 1; 16K × 2; 8K × 4; 4K × 9 (or 8); 2K × 18 (or 16); 1K × 36 (or 32); or
512 × 72 (or 64). Whether configured as block RAM or FIFO, the two ports can have different aspect ratios
without any constraints. Each block RAM can be divided into two completely independent 18Kb block
RAMs that can each be configured to any aspect ratio from 16K × 1 to 512 × 36. Everything described
previously for the full 36Kb block RAM also applies to each of the smaller 18Kb block RAMs. Only in simple
dual-port (SDP) mode can data widths of greater than 18 bits (18Kb RAM) or 36 bits (36Kb RAM) be
accessed. In this mode, one port is dedicated to read operation, the other to write operation. In SDP mode,
one side (read or write) can be variable, while the other is fixed to 32/36 or 64/72. Both sides of the
dual-port 36Kb RAM can be of variable width.
Error Detection and Correction
Each 64-bit-wide block RAM can generate, store, and utilize eight additional Hamming code bits and
perform single-bit error correction and double-bit error detection (ECC) during the read process. The ECC
logic can also be used when writing to or reading from external 64- to 72-bit-wide memories.
FIFO Controller
Each block RAM can be configured as a 36Kb FIFO or an 18Kb FIFO. The built-in FIFO controller for
single-clock (synchronous) or dual-clock (asynchronous or multirate) operation increments the internal
addresses and provides four handshaking flags: full, empty, programmable full, and programmable empty.
The programmable flags allow the user to specify the FIFO counter values that make these flags go active.
The FIFO width and depth are programmable with support for different read port and write port widths on
a single FIFO. A dedicated cascade path allows for easy creation of deeper FIFOs.
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UltraRAM
UltraRAM is a high-density, dual-port, synchronous memory block used in some UltraScale+ families. Both
of the ports share the same clock and can address all of the 4K x 72 bits. Each port can independently read
from or write to the memory array. UltraRAM supports two types of write enable schemes. The first mode
is consistent with the block RAM byte write enable mode. The second mode allows gating the data and
parity byte writes separately. Multiple UltraRAM blocks can be cascaded together to create larger memory
arrays. UltraRAM blocks can be connected together to create larger memory arrays. Dedicated routing in
the UltraRAM column enables the entire column height to be connected together. This makes UltraRAM an
ideal solution for replacing external memories such as SRAM. Cascadable anywhere from 288Kb to 36Mb,
UltraRAM provides the flexibility to fulfill many different memory requirements.
Error Detection and Correction
Each 64-bit-wide UltraRAM can generate, store and utilize eight additional Hamming code bits and
perform single-bit error correction and double-bit error detection (ECC) during the read process.
Digital Signal Processing
DSP applications use many binary multipliers and accumulators, best implemented in dedicated DSP
slices. All UltraScale architecture-based devices have many dedicated, low-power DSP slices, combining
high speed with small size while retaining system design flexibility.
Each DSP slice fundamentally consists of a dedicated 27 × 18 bit twos complement multiplier and a 48-bit
accumulator. The multiplier can be dynamically bypassed, and two 48-bit inputs can feed a
single-instruction-multiple-data (SIMD) arithmetic unit (dual 24-bit add/subtract/accumulate or quad
12-bit add/subtract/accumulate), or a logic unit that can generate any one of ten different logic functions
of the two operands.
The DSP includes an additional pre-adder, typically used in symmetrical filters. This pre-adder improves
performance in densely packed designs and reduces the DSP slice count by up to 50%. The 96-bit-wide
XOR function, programmable to 12, 24, 48, or 96-bit widths, enables performance improvements when
implementing forward error correction and cyclic redundancy checking algorithms.
The DSP also includes a 48-bit-wide pattern detector that can be used for convergent or symmetric
rounding. The pattern detector is also capable of implementing 96-bit-wide logic functions when used in
conjunction with the logic unit.
The DSP slice provides extensive pipelining and extension capabilities that enhance the speed and
efficiency of many applications beyond digital signal processing, such as wide dynamic bus shifters,
memory address generators, wide bus multiplexers, and memory-mapped I/O register files. The
accumulator can also be used as a synchronous up/down counter.
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Product Specification 31
System Monitor
The System Monitor blocks in the UltraScale architecture are used to enhance the overall safety, security,
and reliability of the system by monitoring the physical environment via on-chip power supply and
temperature sensors.
All UltraScale architecture-based devices contain at least one System Monitor. The System Monitor in
UltraScale+ devices is similar to the Kintex UltraScale and Virtex UltraScale devices but with the addition
of a PMBus interface.
Zynq UltraScale+ MPSoCs contain one System Monitor in the PL and an additional block in the PS. The
System Monitor in the PL has the same features as the block in UltraScale+ FPGAs. See Table 9.
In FPGAs and the MPSoC PL, sensor outputs and up to 17 user-allocated external analog inputs are
digitized using a 10-bit 200 kilo-sample-per-second (kSPS) ADC, and the measurements are stored in
registers that can be accessed via internal FPGA (DRP), JTAG, PMBus, or I2C interfaces. The I2C interface
and PMBus allow the on-chip monitoring to be easily accessed by the System Manager/Host before and
after device configuration.
The System Monitor in the MPSoC PS uses a 10-bit, 1 mega-sample-per-second (MSPS) ADC to digitize the
sensor inputs. The measurements are stored in registers and are accessed via the Advanced Peripheral Bus
(APB) interface by the processors and the PMU in the PS.
Packaging
The UltraScale architecture-based devices are available in a variety of organic flip-chip and lidless flip-chip
packages supporting different quantities of I/Os and transceivers. Maximum supported performance can
depend on the style of package and its material. Always refer to the specific device data sheet for
performance specifications by package type.
In flip-chip packages, the silicon device is attached to the package substrate using a high-performance
flip-chip process. Decoupling capacitors are mounted on the package substrate to optimize signal
integrity under simultaneous switching of outputs (SSO) conditions.
Table 9: Key System Monitor Features
Zynq UltraScale+ MPSoC PL Zynq UltraScale+ MPSoC PS
ADC 10-bit 200kSPS 10-bit 1MSPS
Interfaces JTAG, I2C, DRP, PMBus APB
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Product Specification 32
System-Level Features
Several functions span both the PS and PL and include:
Reset Management
Clock Management
Power Domains
PS Boot and Device Configuration
Hardware and Software Debug Support
Reset Management
The reset management function provides the ability to reset the entire device or individual units within it.
The PS supports these reset functions and signals:
External and internal power-on reset signal
Warm reset
Watchdog timer reset
User resets to PL
Software, watchdog timer, or JTAG provided resets
Security violation reset (locked down reset)
Clock Management
The PS in Zynq UltraScale+ MPSoCs is equipped with five phase-locked loops (PLLs), providing flexibility
in configuring the clock domains within the PS. There are four primary clock domains of interest within the
PS. These include the APU, the RPU, the DDR controller, and the I/O peripherals (IOP). The frequencies of
all of these domains can be configured independently under software control.
Power Domains
The Zynq UltraScale+ MPSoC contains four separate power domains. When they are connected to
separate power supplies, they can be completely powered down independently of each other without
consuming any dynamic or static power. The processing system includes:
Full Power Domain (FPD)
Low Power Domain (LPD)
Battery Powered Domain (BPD)
In addition to these three Processing System power domains, the PL can also be completely powered
down if connected to separate power supplies.
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Product Specification 33
The Full Power Domain (FPD) consists of the following major blocks:
Application Processing Unit (APU)
DMA (FP-DMA)
Graphics Processing Unit (GPU)
Dynamic Memory Controller (DDRC)
High-Speed I/O Peripherals
The Low Power Domain (LPD) consists of the following major blocks:
Real-Time Processing Unit (RPU)
DMA (LP-DMA)
Platform Management Unit (PMU)
Configuration Security Unit (CSU)
Low-Speed I/O Peripherals
Static Memory Interfaces
The Battery Power Domain (BPD) is the lowest power domain of the Zynq UltraScale+ MPSoC processing
system. In this mode, all the PS is powered off except the Real-Time Clock (RTC) and battery-backed RAM
(BBRAM).
Power Examples
Power for the Zynq UltraScale+ MPSoCs varies depending on the utilization of the PL resources, and the
frequency of the PS and PL. To estimate power, use the Xilinx Power Estimator (XPE) at:
http://www.xilinx.com/products/design_tools/logic_design/xpe.htm
PS Boot and Device Configuration
Zynq UltraScale+ MPSoCs use a multi-stage boot process that supports both a non-secure and a secure
boot. The PS is the master of the boot and configuration process. For a secure boot, the AES-GCM,
SHA-3/384 decrypts and authenticates the images while the 4,096-bit RSA block authenticates the image.
Upon reset, the device mode pins are read to determine the primary boot device to be used: NAND,
Quad-SPI, SD, eMMC, or JTAG. JTAG can only be used as a non-secure boot source and is intended for
debugging purposes. The CSU executes code out of on-chip ROM and copies the first stage boot loader
(FSBL) from the boot device to the OCM.
After copying the FSBL to OCM, one of the processors, either the Cortex-A53 or Cortex-R5, executes the
FSBL. Xilinx supplies example FSBLs or users can create their own. The FSBL initiates the boot of the PS and
can load and configure the PL, or configuration of the PL can be deferred to a later stage. The FSBL
typically loads either a user application or an optional second stage boot loader (SSBL), such as U-Boot.
Users obtain example SSBL from Xilinx or a third party, or they can create their own SSBL. The SSBL
continues the boot process by loading code from any of the primary boot devices or from other sources
such as USB, Ethernet, etc. If the FSBL did not configure the PL, the SSBL can do so, or again, the
configuration can be deferred to a later stage.
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Product Specification 34
The static memory interface controller (NAND, eMMC, or Quad-SPI) is configured using default settings.
To improve device configuration speed, these settings can be modified by information provided in the
boot image header. The ROM boot image is not user readable or callable after boot.
Hardware and Software Debug Support
The debug system used in Zynq UltraScale+ MPSoCs is based on the ARM CoreSight architecture. It uses
ARM CoreSight components including an embedded trace controller (ETC), an embedded trace Macrocell
(ETM) for each Cortex-A53 and Cortex-R5 processor, and a system trace Macrocell (STM). This enables
advanced debug features like event trace, debug breakpoints and triggers, cross-trigger, and debug bus
dump to memory. The programmable logic can be debugged with the Xilinx Vivado Logic Analyzer.
Debug Ports
Three JTAG ports are available and can be chained together or used separately. When chained together, a
single port is used for chip-level JTAG functions, ARM processor code downloads and run-time control
operations, PL configuration, and PL debug with the Vivado Logic Analyzer. This enables tools such as the
Xilinx Software Development Kit (SDK) and Vivado Logic Analyzer to share a single download cable from
Xilinx.
When the JTAG chain is split, one port is used to directly access the ARM DAP interface. This CoreSight
interface enables the use of ARM-compliant debug and software development tools such as Development
Studio 5 (DS-5™). The other JTAG port can then be used by the Xilinx FPGA tools for access to the PL,
including configuration bitstream downloads and PL debug with the Vivado Logic Analyzer. In this mode,
users can download to and debug the PL in the same manner as a stand-alone FPGA.
w
XA Zynq UltraScale+ MPSoC Data Sheet: Overview
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Product Specification 35
Ordering Information
Table 10 shows the speed and temperature grades available in the different device families.
The ordering information shown in Figure 3 applies to all packages in the XA Zynq UltraScale+ MPSoC.
Table 10: Speed Grades, Temperature Grades, and Operating Voltages
Device Family Devices
Speed Grade and Temperature Grade
Industrial
(I) Automotive
(Q)
–40°C to +100°C –40°C to +125°C
XA Zynq UltraScale+ EG and EV Devices -1I (0.85V) -1Q (0.85V)
-1L (0.72V)
Notes:
1. In Zynq UltraScale+ MPSoCs, when operating the PL at low voltage (0.72V), the PS operates at nominal voltage (0.85V).
X-Ref Target - Figure 3
Figure 3: XA Zynq UltraScale+ MPSoC Ordering Information
XA
Example:
Xilinx Automotive
5
ZU: Zynq UltraScale+
Speed Grade
-1: Standard
-L1: Low-Power
-L1 is the ordering code for the -1L speed grade.
Temperature Grade
I: Industrial
Q: Automotive
F: Lid
B: Lidless
Package Designator and Pin Count
(Footprint Identifier)
S: Flip-chip with 0.8mm Ball Pitch
DS894_03_022317
ZU -1 V C784 QS
F
V: RoHS 6/6
E
Value Index
Processor System Identifier
E: Quad APU; Dual RPU; Single GPU
V
Engine Type
G: General Purpose
V: Video
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Product Specification 36
Revision History
The following table shows the revision history for this document:
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Date Version Description of Revisions
07/13/2017 1.2 Updated Table 3, Application Processing Unit (APU), and Real-Time Processing Unit (RPU).
03/23/2017 1.1 Updated Table 3, Table 10, and Figure 3.
11/09/2016 1.0 Initial Xilinx release.

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