MAX1816, 1994 Datasheet by Analog Devices Inc./Maxim Integrated

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[VI/JXI/VI lM/JXIIVI
General Description
The MAX1816/MAX1994 are dual step-down controllers
for notebook computer applications. BUCK1 is a CPU
core regulator with dynamically adjustable output, ultra-
fast transient response, high DC accuracy, and high effi-
ciency. BUCK2 is an adjustable step-down regulator for
I/O and memory supplies. Both regulators employ Maxim’s
proprietary Quick-PWM™ control architecture. This fast-
response, constant-on-time PWM control scheme handles
wide input/output voltage ratios with ease and provides
100ns “instant” on-response to load transients, while main-
taining a relatively constant switching frequency. The
MAX1816/MAX1994 also have a linear-regulator controller
for low-voltage auxiliary power supplies.
The CPU regulator supports “active voltage positioning”
to reduce output bulk capacitance and lower power dis-
sipation. A programmable gain amplifier allows the use
of lower value sense resistors. Four fixed-gain settings
are available (0, 1.5, 2, and 4). A differential remote-
sense amplifier is also included to more accurately con-
trol the voltage at the load. Accuracy is further
enhanced with an internal integrator.
The MAX1816/MAX1994 include a specialized digital
interface that makes them suitable for mobile CPU and
video processor applications. The power-good
(PGOOD) output for the core regulator is forced high
during VID transitions, and the LINGOOD output for the
linear regulator includes a 1ms (min) turn-on delay.
BUCK1, BUCK2, and the linear regulator feature overvolt-
age protection (OVP). The detection threshold for BUCK1
is adjusted with an external resistive voltage-divider, while
the OVP thresholds for BUCK2 and the linear regulator
are fixed. Connecting the OVPSET pin to VCC disables
OVP for BUCK1 and BUCK2, but not the linear regulator.
The MAX1816 features an output-voltage adjustment
range from 0.6V to 1.75V. Similarly, the MAX1994 is
adjustable from 0.925V to 2.0V, using an alternate VID
code set. While in suspend mode, the adjustment range
is 0.7V to 1.075V for both the MAX1816 and MAX1994.
Both parts are available in 48-pin thin QFN packages.
Applications
Mobile CPU Core and Video Processors
Memory I/O and VID Supplies
3- to 4-Cell Li+ Battery to CPU Core Supply
Small Notebook Computers
Features
Dual Quick-PWM Architecture
±1% VOUT Accuracy
5-Bit On-Board D/A Converter
+0.60V to +1.75V Output Adjust Range (MAX1816)
+0.70V to +2.00V Output Adjust Range (MAX1994)
Voltage-Positioning Gain and Offset Control
+2V to +28V Battery Input Range
Differential Remote Sense (BUCK1)
Linear-Regulator Controller
200/300/550/1000kHz Switching Frequency
2.2mA (typ) ICC Supply Current
20µA (max) Shutdown Supply Current
Independent Power-Good Outputs
(PGOOD, LINGOOD)
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
________________________________________________________________ Maxim Integrated Products 1
19-2569; Rev 0; 10/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX1816ETM -40°C to +100°C 48 Thin QFN
MAX1994ETM -40°C to +100°C 48 Thin QFN
ILIM2
CS2
FB2
REF
LINBSE
LINGOOD
LINFB
OVPSET
TIME
VCC
AGND
OUT2
CS1+
CS1-
FBS
GDS
GAIN
OFS0
OFS1
DPSLP
OFS2
SUS
CC
ILIM1 1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
D4
S0
S1
SKP2/SDN
TON
PGOOD
LIN/SDN
D3
D2
D1
D0
LX1
DH1
PERF
DL1
PGND
VDD
DL2
DH2
LX2
V+
BST2
BST1
THIN QFN 7mm × 7mm
MAX1816
MAX1994
SKP1/SDN
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
Pin Configuration
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
[MAXI/VI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V+ to AGND............................................................-0.3V to +30V
VCC, VDD to AGND...................................................-0.3V to +6V
PGND, GDS to AGND .........................................................±0.3V
SKP1/SDN, SKP2/SDN, LIN/SDN to AGND............-0.3V to +16V
LINBSE, SUS, PERF, DPSLP, PGOOD,
LINGOOD, CS1+, CS1-, FBS, D0D4,
OUT2 to AGND.....................................................-0.3V to +6V
OFS0, OFS1, OFS2, ILIM1, ILIM2,
FB2, REF, TON, TIME, OVPSET, S0, S1,
GAIN, CC, LINFB to AGND ....................-0.3V to (VCC + 0.3V)
DL1, DL2 to PGND .....................................-0.3V to (VDD + 0.3V)
DH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V)
DH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V)
BST1 to LX1..............................................................-0.3V to +6V
BST2 to LX2..............................................................-0.3V to +6V
LX1, LX2, CS2 to AGND ............................................-2V to +30V
REF Short Circuit to AGND.........................................Continuous
LINBSE Short Circuit to +6V.......................................Continuous
Continuous Power Dissipation (TA= +70°C)
48-Pin Thin QFN (derate 26.3mW/°C above +70°C) .2105mW
Operating Temperature Range .........................-40°C to +100°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,
TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETER CONDITIONS MIN
TYP MAX
UNITS
TON = REF, open, or VCC 228
Battery voltage V+ TON = GND 2 16
Input Voltage Range
VCC, VDD 4.5 5.5
V
DAC codes from 0.600V to
1.750V (MAX1816)
BUCK1 DC Output Voltage
Accuracy
V+ = 4.5V to 28V,
includes load
regulation errors,
OFS_ = GDS = AGND,
CS1+ = CS1- = FBS
DAC codes from 0.700V to
2.000V (MAX1994)
-1 +1 %
FB2 = GND
2.475 2.500 2.525
FB2 = VCC
1.782 1.800 1.818
BUCK2 Error Comparator Threshold
(DC Output Voltage Accuracy)
(Note 1)
V+ = 4.5V to 28V
FB2 = OUT2
0.990 1.000 1.010
V
OUT2 Adjust Range 1.0 5.5 V
FB2 GND Level Voltage level to enable internal feedback for BUCK2
with VOUT2 = 2.5V
0.05
V
FB2 External Feedback Level Voltage level to enable external feedback for BUCK2
with FB2 regulated to 1.0V nominal 0.15
1.90
V
FB2 VCC Level Voltage level to enable internal feedback for BUCK2
with VOUT2 = 1.8V 2.10 V
GAIN = GND 0
GAIN = REF
1.425 1.500 1.575
GAIN = open
1.900 2.000 2.100
Voltage-Positioning Gain
GAIN = VCC
3.800 4.000 4.200
V/V
[VIAXIIVI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,
TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETER CONDITIONS MIN
TYP MAX
UNITS
Current-Sense Differential Input
Range (CS1+, CS1-) 200 mV
Remote-Sense Differential Input
Range (CS1+, FBS) 300 mV
Remote-Sense Differential Input
Range (GDS, AGND) 200 mV
CS1+, FBS Input Bias Current -300mV < VCS1+ - VFBS < +300mV -60
+60
µA
CS1- Input Bias Current -100mV < VCS1+ - VCS1- < +100mV, VCS1- = VFBS -60
+60
µA
GDS Input Bias Current -3 +3 µA
FB2 Input Bias Current -0.2
+0.2
µA
OUT2 Input Resistance 70 k
252kHz nominal, RTIME = 143k-8 +8
TIME Frequency Accuracy 53kHz nominal to 530kHz nominal,
RTIME = 680k to 68k-12
+12
%
V+ = 5V, CS1- = 1.2V TON = GND (1000kHz) 230
260
290
TON = REF (550kHz) 165
190
215
TON = open (300kHz) 320
355
390
BUCK1 On-Time (Note 2) V+ = 12V, CS1- = 1.2V
TON = VCC (200kHz) 465
515
565
ns
V+ = 5V, OUT2 = 2.5V TON = GND (715kHz) 630
720
810
TON = REF (390kHz) 495
550
605
TON = open (390kHz) 495
550
605
BUCK2 On-Time (Note 2)
V+ = 12V, OUT2 = 2.5V
TON = VCC (260kHz) 740
825
910
ns
TON = open, TON = VCC (Note 2)
425
500
Minimum Off-Time TON = GND, TON = REF (Note 2)
325
375
ns
Quiescent Supply Current (VCC)
Measured at VCC, with FBS, OUT2, FB2, and LINFB
forced above the no-load regulation point
2200 3800
µA
Partial Shutdown Supply Current
(Linear Regulator On Only)
VSKP1/SDN = 0V, VSKP2/SDN = 0V, VLIN/SDN = 5V;
measured at VCC, with FBS and LINFB forced above
the no-load regulation point
425
650 µA
Partial Shutdown Supply Current
(BUCK1 and Linear Regulator)
VSKP1/SDN = 5V, VSKP2/SDN = 0V, VLIN/SDN = 5V;
measured at VCC, with FBS and LINFB forced above
the no-load regulation point
1825 3000
µA
Partial Shutdown Supply Current
(BUCK2 Only)
VSKP1/SDN = 0V, VSKP2/SDN = 5V, VLIN/SDN = 0V;
measured at VCC, with OUT2 and FB2 forced above
the regulation point
600 1100
µA
Quiescent Supply Current (VDD) Measured at VDD, with FBS, OUT2, and FB2 forced
above the no-load regulation point <1 5 µA
[VIAXIIVI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,
TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETER CONDITIONS MIN
TYP MAX
UNITS
Quiescent Battery Current Measured at V+ 25 40 µA
Shutdown Supply Current (VCC)
VSKP1/SDN = 0V, VSKP2/SDN = 0V, and VLIN/SDN = 0V
4 10 µA
Shutdown Supply Current (VDD)
VSKP1/SDN = 0V, VSKP2/SDN = 0V, and VLIN/SDN = 0V
<1 5 µA
Shutdown Battery Current VSKP1/SDN = VSKP2/SDN = 0V, measured at V+, with
VCC = VDD = 0V or 5V <1 5 µA
Reference Voltage VCC = 4.5V to 5.5V, IREF = 50µA sourcing 1.98
2.00 2.02
V
IREF = 0 to 50µA 0 7
Reference Load Regulation IREF = 50µA to 100µA 0 7
mV
Reference Sink Current REF in regulation 10 µA
OVPSET Disable Mode Threshold Voltage at OVPSET above which the OVP functions
are disabled for BUCK1 and BUCK2
VCC -
1.5
VCC -
0.5 V
OVPSET Default Mode Threshold
for BUCK1
Voltage at OVPSET below which the OVP thresholds
are set to their default values 0.4 0.6 V
MAX1816 1.95
2.00 2.05
Overvoltage Trip Threshold for
BUCK1 (Fixed OVP Threshold)
OVPSET = GND,
measured at FBS MAX1994 2.20
2.25 2.30
V
MAX1816 0.95
1.00 1.05
VOVPSET = 1.0V,
measured at FBS MAX1994
1.075 1.125 1.175
MAX1816 1.95
2.00 2.05
Overvoltage Trip Threshold for
BUCK1 (Adjustable Threshold) VOVPSET = 2.0V,
measured at FBS MAX1994 2.20
2.25 2.30
V
Overvoltage Trip Threshold for
BUCK2
Measured at OUT2 (or FB2 if external feedback is
used) 113
115
117 %
OVPSET Bias Current 0V < VOVPSET < VCC -100
+100
nA
Overvoltage Fault Propagation
Delay
FBS, OUT2, FB2, and LINFB forced 2% above the
no-load trip threshold 10 µs
Output Undervoltage Protection
Threshold
With respect to unloaded output voltage, FBS, and
OUT2 (FB2 in external feedback) 65 70 75 %
Output Undervoltage Fault
Propagation Delay
FBS, OUT2, FB2, and LINFB forced 2% below trip
threshold 10 µs
Output Undervoltage Protection
Blanking Time for FBS
From SKP1/SDN signal going high; clock speed set
by RTIME (Note 3)
256
Clks
Output Undervoltage Protection
Blanking Time for OUT2
From SKP2/SHDN signal going high; clock speed set
by RTIME (Note 3)
4096
Clks
Linear Regulator (LINFB)
Undervoltage Protection Blanking
Time
Linear regulator; from LIN/SDN signal going high;
clock speed set by RTIME (Note 3)
512
Clks
[VIAXIIVI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,
TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETER CONDITIONS MIN
TYP MAX UNITS
ILIM1 Default Threshold
VCC -
1.5
VCC -
1.0
VCC -
0.5
V
BUCK1 Current-Limit Threshold
(Fixed) CS1+ - CS1-; VILIM1 = VCC 40 50 60 mV
CS1+ - CS1-; VILIM1 = 0.5V 40 50 60
BUCK1 Current-Limit Threshold
(Adjustable) CS1+ - CS1-; VILIM1 = 2.0V 160
200
240
mV
BUCK1 Negative Current-Limit
Threshold (Fixed) CS1+ - CS1-; VILIM1 = VCC -90 -72 -55 mV
ILIM1 Input Bias Current 0 to 2V -100
+100
nA
CS2 Input Bias Current 0 to 28V -1 +1 µA
ILIM2 Default Threshold
VCC -
1.5
VCC -
1.0
VCC -
0.5 V
BUCK2 Current-Limit Threshold
(Fixed) AGND - CS2; VILIM2 = VCC 40 50 60 mV
AGND - CS2; VILIM2 = 0.5V 40 50 60
BUCK2 Current-Limit Threshold
(Adjustable) AGND - CS2; VILIM2 = 2.0V 160
200
240
mV
BUCK2 Negative Current-Limit
Threshold (Fixed) AGND - CS2; VILIM2 = VCC -90 -72 -55 mV
ILIM2 Input Bias Current 0 to 2V -100
+100
nA
Thermal-Shutdown Threshold 15°C hysteresis
160
oC
VCC Undervoltage Lockout
Threshold Rising edge, hysteresis = 20mV 4.10
4.45
V
DH1 Gate-Driver On-Resistance BST1LX1 forced to 5V (Note 4) 1 4.5
DL1 high state (pullup) (Note 4) 1 4.5
DL1 Gate-Driver On-Resistance DL1 low state (pulldown) (Note 4)
0.35
2
DH1 Gate-Driver Source/Sink
Current DH1 forced to 2.5V, BSTLX forced to 5V 1.5 A
DL1 Gate-Driver Sink Current DL1 forced to 2.5V 5 A
DL1 Gate-Driver Source Current DL1 forced to 2.5V 1.5 A
DL1 rising 35
Dead Time DH1 rising 26
ns
DH2 Gate-Driver On-Resistance BST2LX2 forced to 5V (Note 4) 2 8
DL2 high state (pullup) (Note 4) 2 8
DL2 Gate-Driver On-Resistance DL2 low state (pulldown) (Note 4) 0.7 3
[VIAXIIVI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,
TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETER CONDITIONS MIN
TYP MAX
UNITS
D H 2 G ate- D r i ver S our ce/S i nk C ur r ent
DH2 forced to 2.5V, BST2LX2 forced to 5V
0.75
A
DL2 Gate-Driver Sink Current DL2 forced to 2.5V 2.5 A
DL2 Gate-Driver Source Current DL2 forced to 2.5V
0.75
A
DL2 rising 35
Dead Time DH2 rising 26
ns
LINFB Input Bias Current VLINFB = 1.035V -100
+100
nA
VLINFB = 1.05V, VLINBSE = 5V 0.4
LINBSE Drive Current VLINFB = 0.965V, VLINBSE = 0.5V 20
mA
LINFB Regulation Voltage VLINBSE = 5V, ILINBSE = 4mA (sink)
0.988 1.000 1.017
V
LINFB Load Regulation VLINBSE = 5V, ILINBSE = 2mA to 10mA (sink) -2.2
-1.2
%
Logic Input High Voltage D0D4, SUS, PERF, LIN/SDN 2.4 V
Logic Input Low Voltage D0D4, SUS, PERF, LIN/SDN 0.8 V
Logic Input High Voltage DPSLP 0.8 V
Logic Input Low Voltage DPSLP 0.4 V
Logic Input Current D0D4, SUS, PERF, LIN/SDN, DPSLP = 0V or 5V -1 +1 µA
Four-Level Logic VCC Level TON, S0, S1, GAIN logic input high level VCC -
0.4 V
Four-Level Logic Float Level TON, S0, S1, GAIN logic input upper midlevel 3.15
3.85
V
Four-Level Logic REF Level TON, S0, S1. GAIN logic input lower midlevel 1.65
2.35
V
Four-Level Logic GND Level TON, S0, S1, GAIN logic input low level 0.5 V
SKP1/SDN, SKP2/SDN, S0, S1,
GAIN, and TON Logic-Input Current
SKP1/SDN, SKP2/SDN, TON, S0, S1, GAIN forced to
GND or VCC
-3 +3 µA
SKP1/SDN, SKP2/SDN Skip Level SKP1/SDN, SKP2/SDN logic input high level 2.8 V
SKP1/SDN, SKP2/SDN PWM Level
SKP1/SDN, SKP2/SDN logic input float level 1.4 2.2 V
SKP1/SDN, SKP2/SDN Shutdown
Level SKP1/SDN, SKP2/SDN logic input low level 0.4 V
SKP1/SDN Test Mode Input Voltage
Range To enable no-fault mode, 4.5V < VCC < 5.5V 10.8
13.2
V
PGOOD Lower Trip Threshold
Measured at FBS, OUT2, and FB2 with respect to
unloaded output voltage, falling edge, typical
hysteresis = 1%
-12.0 -10.0 -8.0
%
LINGOOD Lower Trip Threshold
and LINFB Undervoltage Protection
Threshold
Measured at LINFB with respect to unloaded output
voltage, falling edge (Note 5)
-12.0 -10.0 -8.0
%
PGOOD Upper Trip Threshold
Measured at FBS, OUT_, FB2 with respect to
unloaded output voltage, rising edge, typical
hysteresis = 1%
8.0
10.0 12.0
%
[VIAXIIVI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,
TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETER CONDITIONS MIN
TYP
MAX
LINGOOD Upper Trip Threshold
and LINFB Overvoltage Trip
Threshold
Measured at LINFB with respect to unloaded output
voltage, rising edge (Note 5) 8.0
10.0 12.0
%
PGOOD Propagation Delay OUT_, FB2 forced 2% above or below PGOOD trip
threshold 10 µs
LINGOOD Turn-On Delay LINFB forced 2% above LINGOOD lower trip
threshold 1 ms
LINGOOD Turn-Off Delay LINFB forced 2% below LINGOOD lower trip
threshold 10 µs
PGOOD Transition Delay
After the output-voltage transition on BUCK1 is
complete (PGOOD blanking is enabled for N + 4
clocks, blanking is excluded in startup and
shutdown)
4 Clk
Forced-PWM Mode Transition Delay
After the output-voltage transition on BUCK1 is
complete (forced-PWM mode persists for N + 32
clocks for all transitions)
32 Clk
Open-Drain Output Low Voltage
(PGOOD, LINGOOD) ISINK = 3mA 0.4 V
Open-Drain Leakage Current
(PGOOD, LINGOOD) High state, forced to 5.5V 1 µA
Input Current OFS0OFS2 -0.1
+0.1
µA
OFS Positive Offset when
Programmed to Zero
Deviation in the output voltage when tested with
OFS_ connected to REF 2 mV
VOUT / VOFS, VOFS = (0.8V - 0V)
0.119 0.125 0.131
OFS Gain VOUT / VOFS, VOFS = (2.0V - 1.2V)
0.119 0.125 0.131
V/V
[VIAXIIVI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
8 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,
TA= -40°C to +100°C, unless otherwise noted.) (Note 6)
PARAMETER CONDITIONS
MIN TYP MAX
UNITS
TON = REF, open, or VCC 228
Battery voltage V+ TON = GND 2 16
Input Voltage Range
VCC, VDD 4.5 5.5
V
DAC codes from 0.600V to
1.750V (MAX1816)
BUCK1 DC Output-Voltage
Accuracy
V+ = 4.5V to 28V, includes
load regulation errors,
OFS_ = GDS = AGND,
CS1+ = CS1- = FBS
DAC codes from 0.700V to
2.000V (MAX1994)
-1.5 +1.5
%
FB2 = GND
2.463 2.538
FB2 = VCC
1.773 1.827
BUCK2 Error Comparator
Threshold (DC Output-Voltage
Accuracy) (Note 1)
V+ = 4.5V to 28V
FB2 = OUT2
0.985 1.015
V
OUT2 Adjust Range 1.0 5.5 V
GAIN = REF
1.425 1.575
GAIN = open
1.900 2.100
Voltage-Positioning Gain
GAIN = VCC
3.800 4.200
V/V
Current-Sense Differential Input
Range (CS1+, CS1-)
200
mV
Remote-Sense Differential Input
Range (CS1+, FBS)
300
mV
Remote-Sense Differential Input
Range (GDS, AGND)
200
mV
CS1+, FBS Input Bias Current -300mV < VCS1+ - VFBS < +300mV -60
+60
µA
CS1- Input Bias Current -100mV < VCS1+ - VCS1- < +100mV, VCS1- = VFBS -60
+60
µA
252kHz nominal; RTIME =143k-8 +8
TIME Frequency Accuracy
53kHz nominal to 530kHz nominal; RTIME = 680k to 68k
-12
+12
%
V+ = 5V, CS1- = 1.2V TON = GND (1000kHz)
230 290
TON = REF (550kHz)
165 215
TON = open (300kHz)
320 390
BUCK1 On-Time (Note 2) V+ = 12V, CS1- = 1.2V
TON = VCC (200kHz)
465 565
ns
V+ = 5V, OUT2 = 2.5V TON = GND (715kHz)
630 810
TON = REF (390kHz)
495 605
TON = open (390kHz)
495 605
BUCK2 On-Time (Note 2) V+ = 12V, OUT2 = 2.5V
TON = VCC (260kHz)
740 910
ns
TON = open, TON = VCC (Note 2)
500
Minimum Off-Time TON = GND, TON = REF (Note 2)
375
ns
Quiescent Supply Current (VCC)
Measured at VCC, with FBS, OUT2, FB2, and LINFB
forced above the no-load regulation point
4500
µA
[VIAXIIVI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
_______________________________________________________________________________________ 9
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,
TA= -40°C to +100°C, unless otherwise noted.) (Note 6)
PARAMETER CONDITIONS
MIN TYP MAX
UNITS
Partial Shutdown Supply Current
(Linear Regulator On Only)
VSKP1/SDN = 0V, VSKP2/SDN = 0V, VLIN/SDN = 5V;
measured at VCC, with FBS and LINFB forced above the
no-load regulation point
750
µA
Partial Shutdown Supply Current
(BUCK1 and Linear Regulator)
VSKP1/SDN = 5V, VSKP2/SDN = 0V, VLIN/SDN = 5V;
measured at VCC, with FBS and LINFB forced above the
no-load regulation point
3400
µA
Partial Shutdown Supply Current
(BUCK2 Only)
VSKP1/SDN = 0V, VSKP2/SDN = 5V, VLIN/SDN = 0V;
measured at VCC, with OUT2 and FB2 forced above the
regulation point
1400
µA
Quiescent Supply Current (VDD)
Measured at VDD, with FBS, OUT2, and FB2 forced above
the no-load regulation point, TA = -40°C to +85°C 5 µA
Quiescent Battery Current Measured at V+ 40 µA
Shutdown Supply Current (VCC) VSKP1/SDN = 0V, VSKP2/SDN = 0V, and VLIN/SDN = 0V,
TA = -40°C to +85°C 10 µA
Shutdown Supply Current (VDD) VSKP1/SDN = 0V, VSKP2/SDN = 0V, and VLIN/SDN = 0V,
TA = -40°C to +85°C 5 µA
Shutdown Battery Current VSKP1/SDN = VSKP2/SDN = 0V, measured at V+, with
VCC = VDD = 0V or 5V, TA = -40°C to +85°C 5 µA
Reference Voltage VCC = 4.5V to 5.5V, IREF = 50µA sourcing
1.98
2.02
V
IREF = 0 to 50µA 0 7
Reference Load Regulation IREF = 50µA to 100µA 0 7
mV
Reference Sink Current REF in regulation 10 µA
OVPSET Disable Mode Threshold
Voltage at OVPSET above which the OVP functions are
disabled for BUCK1 and BUCK2
VCC -
1.5
VCC -
0.5 V
OVPSET Default Mode Threshold
for BUCK1
Voltage at OVPSET below which the OVP thresholds are
set to their default values 0.4 0.6 V
MAX1816
1.95 2.05
Overvoltage Trip Threshold for
BUCK1 (Fixed OVP Threshold)
OVPSET = GND,
measured at FBS MAX1994
2.20 2.30
V
MAX1816
0.95 1.05
VOVPSET = 1.0V,
measured at FBS MAX1994
1.075 1.175
MAX1816
1.95 2.05
Overvoltage Trip Threshold for
BUCK1 (Adjustable Threshold) VOVPSET = 2.0V,
measured at FBS MAX1994
2.20 2.30
V
Overvoltage Trip Threshold for
BUCK2 Measured at OUT2 (or FB2 if external feedback is used)
113 117
%
Output Undervoltage Protection
Threshold
With respect to unloaded output voltage FBS and OUT2
(FB2 in external feedback) 65 75 %
[VIAXIIVI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
10 ______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,
TA= -40°C to +100°C, unless otherwise noted.) (Note 6)
PARAMETER CONDITIONS
MIN TYP MAX
UNITS
ILIM1 Default Threshold
VCC -
1.5
VCC -
0.5 V
BUCK1 Current-Limit Threshold
(Fixed) CS1+ - CS1-; VILIM1 = VCC 40 60 mV
CS1+ - CS1-; VILIM1 = 0.5V 40 60
BUCK1 Current-Limit Threshold
(Adjustable) CS1+ - CS1-; VILIM1 = 2.0V
160
240
mV
BUCK1 Negative Current-Limit
Threshold (Fixed) CS1+ - CS1-; VILIM1 = VCC -90 -55 mV
ILIM2 Default Threshold
VCC -
1.5
VCC -
0.5 V
BUCK2 Current-Limit Threshold
(Fixed) AGND - CS2; VILIM2 = VCC 40 60 mV
AGND - CS2; VILIM2 = 0.5V 40 60
BUCK2 Current-Limit Threshold
(Adjustable) AGND - CS2; VILIM2 = 2.0V
160
240
mV
BUCK2 Negative Current-Limit
Threshold (Fixed) AGND - CS2; VILIM2 = VCC -90 -55 mV
VCC Undervoltage Lockout
Threshold Rising edge, hysteresis = 20mV
4.10
4.45
V
DH1 Gate-Driver On-Resistance BST1LX1 forced to 5V (Note 4) 4.5
DL1 high state (pullup) (Note 4) 4.5
DL1 Gate-Driver On-Resistance
DL1 low state (pulldown) (Note 4) 2
DH2 Gate-Driver On-Resistance BST2LX1 forced to 5V (Note 4) 8
DL2 high state (pullup) (Note 4) 8
DL2 Gate-Driver On-Resistance
DL2 low state (pulldown) (Note 4) 3
VLINFB = 1.05V, VLINBSE = 5V 0.4
LINBSE Drive Current VLINFB = 0.965V, VLINBSE = 0.5V 20
mA
LINFB Regulation Voltage VLINBSE = 5V, ILINBSE = 4mA (sink)
0.988
1.017
V
LINFB Load Regulation VLINBSE = 5V, ILINBSE = 2mA to 10mA (sink)
-2.2
%
Logic Input High Voltage D0D4, SUS, PERF, LIN/SDN 2.4 V
Logic Input Low Voltage D0D4, SUS, PERF, LIN/SDN 0.8 V
Logic Input High Voltage DPSLP 0.8 V
Logic Input Low Voltage DPSLP 0.4 V
Four-Level Logic VCC Level TON, S0, S1, GAIN logic input high level VCC -
0.4 V
Four-Level Logic Float Level TON, S0, S1, GAIN logic input upper midlevel
3.15
3.85
V
Four-Level Logic REF Level TON, S0, S1, GAIN logic input lower midlevel
1.65
2.35
V
Four-Level Logic GND Level TON, S0, S1, GAIN logic input low level 0.5 V
[VIAXIIVI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________ 11
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,
TA= -40°C to +100°C, unless otherwise noted.) (Note 6)
PARAMETER CONDITIONS
MIN TYP MAX
UNITS
SKP1/SDN, SKP2/SDN Skip
Level SKP1/SDN, SKP2/SDN logic input high level 2.8 V
SKP1/SDN, SKP2/SDN PWM
Level SKP1/SDN, SKP2/SDN logic input float level 1.4 2.2 V
SKP1/SDN, SKP2/SDN Shutdown
Level SKP1/SDN, SKP2/SDN logic input low level 0.4 V
PGOOD Lower Trip Threshold M easur ed at FBS , OU T2, and FB2 w i th r esp ect to unl oad ed
outp ut vol tag e, fal l i ng ed g e, typ i cal hyster esi s = 1%
-12.5
-7.5
%
LINGOOD Lower Trip Threshold
and LINFB Undervoltage
Protection Threshold
Measured at LINFB with respect to unloaded output
voltage, falling edge (Note 5)
-12.5
-7.5
%
PGOOD Upper Trip Threshold Measured at FBS, OUT_, FB2 with respect to unloaded
output voltage, rising edge, typical hysteresis = 1% 7.5
12.5
%
LINGOOD Upper Trip Threshold
and LINFB Overvoltage Trip
Threshold
Measured at LINFB with respect to unloaded output
voltage, rising edge (Note 5) 7.5
12.5
%
LINGOOD Turn-On Delay LINFB forced 2% above LINGOOD lower trip threshold 1 ms
Open-Drain Output Low Voltage
(PGOOD, LINGOOD) ISINK = 3mA 0.4 V
OFS Positive Offset when
Programmed to Zero
Deviation in the output voltage when tested with OFS_
connected to REF 2 mV
VOUT / VOFS, VOFS = (0.8V - 0V)
0.119
0.131
OFS Gain VOUT / VOFS, VOFS = (2.0V - 1.2V)
0.119
0.131
V/V
Note 1: DC output accuracy specifications for BUCK2 refer to the trip level of the error amp. The output voltage has a DC regulation
higher than the trip level by 50% of the ripple. In SKIP mode, the output rises by approximately 1.5% when transitioning from
continuous conduction to no load.
Note 2: On-time and minimum off-time specifications for both BUCK1 and BUCK2 are measured from 50% to 50% at the DH_ pin
with LX_ forced to zero, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate
capacitance. Actual in-circuit times can be different due to MOSFET switching speeds.
Note 3: This does not include the time for REF to start up if required.
Note 4: Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the thin
QFN package.
Note 5: The LINGOOD signal is latched low under a fault condition of LINFB dropping below 90% or rising above 110% of the nomi-
nal set point. The LINGOOD signal does not go high again until the fault latch is reset.
Note 6: Specifications from -40°C to +100°C are guaranteed by design, not production tested.
[MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
12 ______________________________________________________________________________________
Figure 1. Standard Application Circuit
0
AGND
FLOAT
LINGOOD
PGOOD
D1: CMSH5-40
D2: EC31QS03L
D3, D4: CMPSH-3
PGND
DAC INPUTS SUSPEND
INPUTS
CONTROL
INPUTS
FLOAT
(GAIN = 2)
ILIM2
R5
100
R2
0.005
1%
3.3V
BIAS SUPPLY
R6
10
R3
280k
1%
R4
49.9k
1%
R1
0.001
1%
R19
2
R20
2
R17
196k
1%
R11
100k
R8
20k
1 %
R9
100k
1 %
R7
220
R12
100k
R10
143k
REF
Q5 FZT749
VLIN
1.20V
C5
1000pF
C8
4.7µF
C9
10µF
C6 0.22µF
C7
1µF
C3
0.1µF
C2
0.1µF
C10
22nF
C1
2.2µF
C11
0.047µF
C12
0.047µF
C4
47pF
CS2
FB2
REF
LINBSE
LINGOOD
LINFB
OVPSET
TIME
VCC
AGND
OUT2
CS1+
CS1-
FBS
GDS
GAIN
OFS0
OFS1
DPSLP
OFS2
SUS
CC
ILIM1
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
D4
S0
S1
SKP2/SDN
TON
PGOOD
LIN/SDN
D3
D2
D1
D0
LX1
DH1
PERF
DL1
PGND
VDD
DL2
DH2
LX2
V+
BST2
BST1
MAX1816
MAX1994
SKP1/SDN
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
R15
196k
1%
R13
196k
1%
R18
4.99k
1%
R16
3.48k
1%
R14
2k
1%
Q4
D2
COUT2
330µF
CIN2
10µF
VOUT2
2.5V
CIN1
3 × 10µF
COUT1
3 × 330µF
CREMOTE
VOUT1
0.6V TO 1.75V
(MAX1816)
0.7V TO 2.0V
(MAX1994)
PC BOARD TRACE
RESISTANCE
INPUT VOLTAGE
7V TO 24V
PC BOARD TRACE
RESISTANCE
L2
1.2µH
Q3
Q1
Q2
D3D4
D1
L1
0.6µH
VDD, 5V BIAS SUPPLY
REF
VDD
[MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________ 13
Figure 2. High-Current Master-Slave Application Circuit
AGND
(MASTER)
AGND
(SLAVE)
FLOAT
PGOOD
PGND
DAC INPUTS SUSPEND
INPUTS
CONTROL
INPUTS
FLOAT
(GAIN = 2)
ILIM2
R5
100
R2
0.005
1%
3.3V
BIAS SUPPLY
R6
10
00
R3
280k
1%
R4
49.9k
1%
R1
0.001
1%
R19
2
R20
2
R17
196k
1%
R8
.20k
1%
R9
100k
1%
R7
220
R12
100k
R10
143k
REF
Q5
VLIN
1.2V
FZT749
C5
1000pF
C8
4.7µF
C9
10µF
C6 0.22µF
C7
1µF
C3
0.1µF
C2
0.1µF
C10
22nF
C19
100pF
C1
2.2µF
C4 47pF CS2
FB2
REF
LINBSE
LINGOOD
LINFB
OVPSET
TIME
VCC
AGND
OUT2
CS1+
CS1-
FBS
GDS
GAIN
OFS0
OFS1
DPSLP
OFS2
SUS
CC
REF
ILIM1
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
D4
S0
S1
SKP2/SDN
TON
PGOOD
LIN/SDN
D3
D2
D1
D0
LX1
DH1
PERF
DL1
PGND
VDD
DL2
DH2
LX2
V+
BST2
BST1
MAX1816
MAX1994
SKP1/SDN
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
R15
196k
1%
R13
196k
1%
R18
4.99k
1%
R16
3.48k
1%
R14
2k
1%
R28
2
R26
20
R27
2
R23
49.9k
1%
R22
280k
1%
R21
34.8k
Q4
D2
COUT2
2 × 270µF
CIN2
10µF
CIN3
3 × 10µF
VOUT2
2.5V
CIN1
3 × 10µF
COUT1
6 × 330µF
CREMOTE
VOUT1
0.6V TO 1.75V
(MAX1816)
0.7V TO 2.0V
(MAX1994)
PC BOARD TRACE
RESISTANCE
INPUT VOLTAGE
7V TO 24V
PC BOARD TRACE
RESISTANCE
L2
1.2µH
Q3
Q1
Q2
Q6
Q7
D3D4
D5
D1
L1
0.6µH
VDD, 5V BIAS SUPPLY
C12
0.1µF
C13
1µF
C16
22nF
C15
270pF
C14
0.22µF
REF
VDD
REF
R24
0.001
1%
L3
0.6µH
D6
C17
0.047µF
C18
0.047µF
LX CM+
CM-
TON FLOAT
CS-
CS+
DH
VCC
VDD
DD
DL
PGND
GND
POL
COMP TRIG
ILIM
LIMIT
V+
BST
MAX1980
D1, D6: CMSH5-40
D2: EC31QS03L
D3, D4, D5: CMPSH-3
\ HHHH DE” WM I / [MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
14 ______________________________________________________________________________________
EFFICIENCY vs. LOAD CURRENT
(BUCK1 VOUT1 = 1.25V)
MAX1816 toc01
LOAD CURRENT (A)
EFFICIENCY (%)
1010.1
60
70
80
90
100
50
0.01 100
SKIP MODE
VIN = 20V
FORCED PWM
VIN = 7V
VIN = 12V
OUTPUT VOLTAGE vs. LOAD CURRENT
(BUCK1)
MAX1816 toc02
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
252015105
1.21
1.22
1.23
1.24
1.25
1.26
1.20
030
SKIP MODE
FORCED PWM
EFFICIENCY vs. LOAD CURRENT
(BUCK2 VOUT2 = 2.5V)
MAX1816 toc03
LOAD CURRENT (A)
EFFICIENCY (%)
10.1
60
70
80
90
100
50
0.01 10
SKIP MODE
FORCED PWM
VIN = 20V
VIN = 7V
VIN = 12V
Typical Operating Characteristics
(Circuit of Figure 1, V+ = 12V, VDD = VCC = VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5V; VIN(LDO) = 3.3V, VOUT(BUCK1) = 1.25V,
VOUT(BUCK2) = 2.5V; TA= +25°C, unless otherwise noted.)
OUTPUT VOLTAGE vs. LOAD CURRENT
(BUCK2)
MAX1816 toc04
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
82 64
2.52
2.54
2.56
2.58
2.50
010
SKIP MODE
FORCED PWM
FREQUENCY vs. LOAD CURRENT
(BUCK1 AND BUCK2)
MAX1816 toc05
LOAD CURRENT (A)
FREQUENCY (kHz)
15105
100
200
300
400
0
020
BUCK2 PWM MODE
BUCK2 SKIP MODE
BUCK1 PWM MODE
BUCK1 SKIP MODE
FREQUENCY vs. INPUT VOLTAGE
(BUCK1 AND BUCK2)
MAX1816 toc06
INPUT VOLTAGE (V)
FREQUENCY (kHz)
201510
300
350
400
250
525
BUCK2 IOUT2 = 8A
BUCK2 IOUT2 = 1A
BUCK1 IOUT1 = 20A
BUCK1 IOUT1 = 3A
FREQUENCY vs. TEMPERATURE
(BUCK1 AND BUCK2)
MAX1816 toc07
TEMPERATURE (°C)
FREQUENCY (kHz)
806040200-20
300
350
400
450
250
-40 100
BUCK2 IOUT2 = 8A
BUCK1 IOUT1 = 20A
OUTPUT CURRENT AT CURRENT LIMIT
vs. TEMPERATURE
MAX1816 toc08
TEMPERATURE (°C)
OUTPUT CURRENT AT CURRENT LIMIT (A)
806040200-20
10
20
30
40
0
-40 100
BUCK1
BUCK2
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (SKIP MODE)
MAX1816 toc09
INPUT VOLTAGE (V)
SUPPLY CURRENT (µA)
201510
300
600
900
1200
1500
1800
2100
2400
2700
3000
0
525
I+
ICC + IDD
[MAXI/VI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________ 15
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (PWM MODE)
MAX1816 toc10
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
201510
10
20
30
40
50
0
525
I+
ICC + IDD
BUCK1 LOAD TRANSIENT RESPONSE
(SKIP MODE)
MAX1816 toc11
20µs/div
B
A
C
1.25V
20A
20A
A: LOAD CURRENT, 20A/div
B: OUTPUT VOLTAGE, 100mV/div, AC-COUPLED
C: INDUCTOR CURRENT, 20A/div
1.15V
0
0
1.35V
BUCK1 LOAD TRANSIENT RESPONSE
(PWM MODE)
MAX1816 toc12
20µs/div
B
A
C
1.25V
20A
20A
A: LOAD CURRENT, 20A/div
B: OUTPUT VOLTAGE, 100mV/div, AC-COUPLED
C: INDUCTOR CURRENT, 20A/div
1.15V
0
0
1.35V
BUCK2 LOAD TRANSIENT RESPONSE
(SKIP MODE)
MAX1816 toc13
20µs/div
B
A
2.6V
5A
A: OUTPUT VOLTAGE, 100mV/div, AC-COUPLED
B: INDUCTOR CURRENT, 5A/div
10A
2.5V
0
2.4V
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = 12V, VDD = VCC = VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5V; VIN(LDO) = 3.3V, VOUT(BUCK1) = 1.25V,
VOUT(BUCK2) = 2.5V; TA= +25°C, unless otherwise noted.)
[VI/JXIIVI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
16 ______________________________________________________________________________________
BUCK2 LOAD TRANSIENT RESPONSE
(PWM MODE)
MAX1816 toc14
20µs/div
B
A
2.6V
5A
A: OUTPUT VOLTAGE, 100mV/div, AC-COUPLED
B: INDUCTOR CURRENT, 5A/div
10A
2.5V
0
2.4V
BUCK1 STARTUP WAVEFORM
(PWM MODE, NO LOAD)
MAX1816 toc15
100µs/div
B
A
C
10A
2V
2V
A: OUTPUT VOLTAGE, 1V/div
B: INDUCTOR CURRENT, 10A/div
C: SKP1/SDN SIGNAL, 2V/div
0
1V
0
0
BUCK1 STARTUP WAVEFORM
(PWM MODE, IOUT1 = 20A)
MAX1816 toc16
100µs/div
B
A
C
10A
2V
2V
A: OUTPUT VOLTAGE, 1V/div
B: INDUCTOR CURRENT, 10A/div
C: SKP1/SDN SIGNAL, 2V/div
0
1V
0
0
20A
BUCK2 STARTUP WAVEFORM
(PWM MODE, NO LOAD)
MAX1816 toc17
40µs/div
B
A
C
10A
4V
2V
A: OUTPUT VOLTAGE, 2V/div
B: INDUCTOR CURRENT, 10A/div
C: SKP2/SDN SIGNAL, 2V/div
0
2V
0
0
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = 12V, VDD = VCC = VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5V; VIN(LDO) = 3.3V, VOUT(BUCK1) = 1.25V,
VOUT(BUCK2) = 2.5V; TA= +25°C, unless otherwise noted.)
[MAXI/VI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________ 17
BUCK2 STARTUP WAVEFORM
(PWM MODE, IOUT2 = 8A)
MAX1816 toc18
40µs/div
B
A
C
10A
4V
2V
A: OUTPUT VOLTAGE, 2V/div
B: INDUCTOR CURRENT, 10A/div
C: SKP2/SDN SIGNAL, 2V/div
0
2V
0
0
BUCK1 DYNAMIC OUTPUT-VOLTAGE TRANSITION
(PWM MODE)
MAX1816 toc19
100µs/div
B
A
C
0
10A
5V
VOUT1 = 1.40V TO 1.00V TO 1.40V
IOUT1 = 3A, RTIME = 143k
A: OUTPUT VOLTAGE, 500mV/div
B: INDUCTOR CURRENT, 10A/div
C: PGOOD SIGNAL, 5V/div
D: VID BIT, 5V/div
5V
1.5V
0
1V
0
D
BUCK1 DYNAMIC OUTPUT-VOLTAGE TRANSITION
(SKIP MODE)
MAX1816 toc20
100µs/div
B
A
C
0
10A
5V
VOUT1 = 1.40V TO 1.00V TO 1.40V
IOUT1 = 1A, RTIME = 143k
A: OUTPUT VOLTAGE, 500mV/div
B: INDUCTOR CURRENT, 10A/div
C: PGOOD SIGNAL, 5V/div
D: VID BIT, 5V/div
5V
1.5V
0
1V
0
D
BUCK1 DYNAMIC OUTPUT-VOLTAGE TRANSITION
(SKIP MODE)
MAX1816 toc21
100µs/div
B
A
C
0
10A
5V
VOUT1 = 1.00V TO 0.60V TO 1.00V
IOUT1 = 1A, RTIME = 143k
A: OUTPUT VOLTAGE, 500mV/div
B: INDUCTOR CURRENT, 10A/div
C: PGOOD SIGNAL, 5V/div
D: SUS SIGNAL, 5V/div
5V
1V
0
0.5V
0
D
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = 12V, VDD = VCC = VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5V; VIN(LDO) = 3.3V, VOUT(BUCK1) = 1.25V,
VOUT(BUCK2) = 2.5V; TA= +25°C, unless otherwise noted.)
nH [VI/JXIIVI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
18 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = 12V, VDD = VCC = VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5V; VIN(LDO) = 3.3V, VOUT(BUCK1) = 1.25V,
VOUT(BUCK2) = 2.5V; TA= +25°C, unless otherwise noted.)
BUCK1 SHUTDOWN WAVEFORM
(SKIP MODE, NO LOAD)
MAX1816 toc22
100µs/div
B
A
C
10A
2V
5V
A: OUTPUT VOLTAGE, 1V/div
B: INDUCTOR CURRENT, 10A/div
C: SKP1/SDN SIGNAL, 5V/div
0
1V
0
0
-10A
BUCK1 SHUTDOWN WAVEFORM
(PWM MODE, IOUT2 = 20A)
MAX1816 toc23
100µs/div
B
A
C
10A
2V
5V
A: OUTPUT VOLTAGE, 1V/div
B: INDUCTOR CURRENT, 10A/div
C: SKP1/SDN SIGNAL, 5V/div
0
1V
0
0
20A
OUTPUT OFFSET
vs. OFS INPUT VOLTAGE
MAX1816 toc24
VOFS (V)
OUTPUT OFFSET (mV)
1.50.5 1.0
-100
0
100
200
-200
0 2.0
UNDEFINED
REGION
BUCK1 OUTPUT-VOLTAGE DISTRIBUTION
(VOUT1 = 1.25V, SAMPLE SIZE = 55)
MAX1816 toc25
BUCK1 OUTPUT VOLTAGE (V)
SAMPLE PERCENTAGE (%)
1.250
10
20
30
0
1.248 1.252
1.249 1.251
[MAXI/VI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________ 19
REFERENCE VOLTAGE DISTRIBUTION
(VREF = 2.0V, SAMPLE SIZE = 55)
MAX1816 toc26
REFERENCE VOLTAGE (V)
SAMPLE PERCENTAGE (%)
2.000
10
20
30
0
2.002
1.999 2.001
LINEAR REGULATOR LOAD REGULATION
MAX1816 toc27
LOAD CURRENT (mA)
OUTPUT VOLTAGE (V)
100101
1.202
1.204
1.206
1.208
1.210
1.200
0.1 1000
LINEAR REGULATOR LINE REGULATION
MAX1816 toc28
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
108642
1.17
1.18
1.19
1.20
1.21
1.22
1.16
012
LINEAR REGULATOR LOAD
TRANSIENT RESPONSE
MAX1816 toc29
20µs/div
B
A
1.2V
A: LOAD CURRENT, 200mA/div
B: OUTPUT VOLTAGE, 10mV/div, AC-COUPLED
400mA
1.19V
200mA
0
LINEAR REGULATOR STARTUP WAVEFORM
MAX1816 toc30
20µs/div
B
A
C
2V
200mA
A: VLIN/SDN, 5V/div
B: VLIN = 1.2V, 1V/div
C: ILIN = 300mA, 200mA/div
0
5V
0
0
400mA
1V
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = 12V, VDD = VCC = VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5V; VIN(LDO) = 3.3V, VOUT(BUCK1) = 1.25V,
VOUT(BUCK2) = 2.5V; TA= +25°C, unless otherwise noted.)
[VIAXIIVI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
20 ______________________________________________________________________________________
PIN NAME FUNCTION
1 ILIM1
BUCK1 Current-Limit Adjustment. The CS1+ - CS1- current-limit threshold defaults to 50mV if ILIM1 is
connected to VCC. In adjustable mode, the current-limit threshold voltage is precisely 1/10th of the voltage
at ILIM1. The logic threshold for switchover to the default value is approximately VCC - 1V.
2 CC
Integrator Time Constant Control Input. This pin allows the integrator to be compensated independent of
the voltage-positioning sense feedback path. Connect a 47pF to 1000pF capacitor from this pin to ground
to control the integration time constant.
3 CS1+
Positive Voltage-Positioning and Current-Sense Input for BUCK1. The current-limit sense voltage for
CS1+ - CS1- is 1/10th of the voltage at the ILIM1 input. The CS1+ and CS1- inputs are also used for active
voltage positioning, with the voltage-positioning gain set with the GAIN pin. Connecting the GAIN pin to
ground disables voltage positioning. Positive and negative current limits are always active.
4 CS1-
Negative Voltage-Positioning and Current-Sense Input for BUCK1. CS1- is also the output sense input for
calculating TON. The current-limit sense voltage for CS1+ - CS1- is 1/10th of the voltage at the ILIM1 input.
The CS1+ and CS1- inputs are also used for active voltage positioning, with the voltage-positioning gain
set with the GAIN pin. Connecting the GAIN pin to ground disables voltage positioning. Positive and
negative current limits are always active.
5 FBS
Output Feedback Remote-Sense Input for BUCK1. Connect FBS directly to the load. FBS internally
connects to an amplifier that fine-tunes the output voltage, compensating for voltage drops from the
regulator output to the load.
6 GDS
Ground Remote-Sense Input for BUCK1. Connect GDS directly to the load. GDS internally connects to an
amplifier that fine-tunes the output voltage, compensating for voltage drops from the regulator ground to
the load ground.
7 GAIN
Voltage-Positioning Gain Control. GAIN is a four-level logic input that selects the voltage-positioning gain
(see CS1+, CS1- pins). The gain setting does not affect current-limit functions. Connecting GAIN to GND
disables the voltage positioning by setting the gain to zero. Connecting GAIN to REF sets the gain to 1.5.
Leaving GAIN open sets the gain to 2. Connecting GAIN to VCC sets the gain to 4.
GND = 0; REF = 1.5; open = 2; VCC = 4.
8 OFS0
Voltage-Divider Input for Voltage-Positioning Offset Control. OFS0OFS2 are selected based on the SUS,
PERF, and DPSLP signals. For 0V < OFS_ < 0.8V, 0.125 times the voltage at OFS_ is subtracted from the
output. For 1.2V < OFS_ < 2.0V, 0.125 times the difference between REF and OFS_ is added to the output.
Voltages in the range of 0.8V < OFS_ < 1.2V are not permitted (see Table 7).
9 OFS1
Voltage-Divider Input for Voltage-Positioning Offset Control. OFS0OFS2 are selected based on the SUS,
PERF, and DPSLP signals. For 0V < OFS_ < 0.8V, 0.125 times the voltage at OFS_ is subtracted from the
output. For 1.2V < OFS_ < 2.0V, 0.125 times the difference between REF and OFS_ is added to the output.
Voltages in the range of 0.8V < OFS_ < 1.2V are not permitted (see Table 7).
10 OFS2
Voltage-Divider Input for Voltage-Positioning Offset Control. OFS0OFS2 are selected based on the SUS,
PERF, and DPSLP signals. For 0V < OFS_ < 0.8V, 0.125 times the voltage at OFS_ is subtracted from the
output. For 1.2V < OFS_ < 2.0V, 0.125 times the difference between REF and OFS_ is added to the output.
Voltages in the range of 0.8V < OFS_ < 1.2V are not permitted (see Table 7).
11 SUS
Suspend Mode Control Input. The SUS signal causes the S0 and S1 inputs to take precedence over the
VID code setting and OFS inputs. When SUS is high, the state of the S0 and S1 inputs are decoded to
select the appropriate DAC code and the offset is forced to zero (see the DAC Inputs and Internal
Multiplexer section).
12 DPSLP
Deep Sleep Control Input. This logic control input goes to the offset selection multiplexer that determines
which, if any, offset control inputs are read (OFS0OFS2). This input is compatible with 1.5V logic (see
Table 7).
13 D0 VID Code Input. D0 is the least significant bit (LSB).
Pin Description
[VIAXIIVI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________ 21
PIN NAME FUNCTION
14 D1 VID Code Input
15 D2 VID Code Input
16 D3 VID Code Input
17 D4 VID Code Input. D4 is the most significant bit (MSB).
18 S0
Suspend Mode Voltage-Select Input. S0 and S1 are four-level logic inputs that select the suspend mode
VID code for the suspend mode multiplexer inputs. If SUS is high, the suspend mode VID code is delivered
to the DAC overriding any other voltage setting (see the DAC Inputs and Internal Multiplexer section).
19 S1
Suspend Mode Voltage-Select Input. S0 and S1 are four-level logic inputs that select the suspend mode
VID code for the suspend mode multiplexer inputs. If SUS is high, the suspend mode VID code is delivered
to the DAC overriding any other voltage setting (see the DAC Inputs and Internal Multiplexer section).
20 SKP1/SDN
Combined Shutdown and Skip-Mode Control Input for BUCK1. Always start BUCK2 before starting BUCK1.
Connect SKP1/SDN to VCC or drive the pin above 2.8V with external 3.3V-powered CMOS logic for normal
PFM/PWM operation. Connect SKP1/SDN to GND or drive the pin below 0.5V to shut down BUCK1. In
shutdown mode, DL1 is forced to VDD in order to enforce overvoltage protection when the regulator is
powered down. Leave SKP1/SDN floating for the low-noise forced PWM operation. Low-noise forced-PWM
mode causes the inductor current to reverse at light loads and suppresses pulse-skipping operation.
SKP1/SDN can also be used to disable both over- and undervoltage protection circuits and clear the fault
latch. This test mode is enabled by forcing the pin to 10.8V < VSKP1/SDN < 13.2V. While in the test mode,
the regulator performs the normal PFM/PWM operation. SKP1/SDN cannot withstand the battery voltage.
21 SKP2/SDN
Combined Shutdown and Skip-Mode Control Input for BUCK2. Always start BUCK2 before starting BUCK1.
Connect SKP2/SDN to VCC or drive the pin above 2.8V with external 3.3V-powered CMOS logic for normal
PFM/PWM operation. Connect SKP2/SDN to GND or drive the pin below 0.5V to shut down BUCK2. In
shutdown mode, DL2 is forced to VDD if the overvoltage protection is enabled. This is done in order to
enforce overvoltage protection even when the regulator is powered down. Leave SKP2/SDN floating for the
low-noise forced PWM operation. Low-noise forced-PWM mode causes the inductor current to recirculate
at light loads and suppresses pulse-skipping operation. If OVPSET = VCC, then DL2 is forced LOW in
shutdown mode. SKP2/SDN cannot withstand the battery voltage.
22 LIN/SDN
Linear Regulator Shutdown Control Input. Connect LIN/SDN to VCC or drive the pin above 2.4V to turn on
the linear regulator. Connect LIN/SDN to GND or drive the pin below 0.8V to shut down the linear regulator.
In shutdown mode, LINBSE is forced to a high-impedance state preventing sufficient drive to the external
PNP power transistor in the regulator. LIN/SDN cannot withstand the battery voltage.
23 PGOOD
Open-Drain Power-Good Output. PGOOD is forced low during power-up and power-down transitions on
BUCK1. In normal operation, if FBS and OUT2 (FB2) are in regulation, then PGOOD is high. PGOOD is
forced low when SKP1/SDN is low. If SKP2/SDN is low, OUT2 (FB2) does not affect PGOOD. Normally,
PGOOD is forced high for all VID transitions, and stays high for 4 TIME clock periods after the D/A count is
equalized. If OUT2 is enabled during these conditions and a fault occurs on BUCK2, then PGOOD goes
low. A pullup resistor on PGOOD causes additional finite shutdown current.
24 TON
On-Time Selection Control Input. This four-level input sets the K factor that determines the DH on-time. The
TON times for BUCK2 are shifted to minimize beating between the two regulators. GND = 1000kHz
(BUCK1) and 715kHz (BUCK2), REF = 550kHz (BUCK1) and 390kHz (BUCK2), open = 300kHz (BUCK1)
and 390kHz (BUCK2), VCC = 200kHz (BUCK1) and 260kHz (BUCK2).
Pin Description (continued)
[VIAXIIVI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
22 ______________________________________________________________________________________
PIN NAME FUNCTION
25 OVPSET
Overvoltage Protection Control Input. This pin controls the OVP functions for BUCK1 and BUCK2. LINFB is
not affected by OVPSET. Connect OVPSET to VCC to disable overvoltage protection for both BUCK1 and
BUCK2. Connect OVPSET to GND for default overvoltage threshold of 2.0V (MAX1816) or 2.25V (MAX1994)
for BUCK1, measured at FBS. The OVP threshold for BUCK2 is always at 115% of the nominal output
voltage. The OVP threshold for BUCK1 can be adjusted by connecting OVPSET between 1.0V and 2.0V. An
overvoltage condition occurs if VFBS > VOVPSET (MAX1816) or VFBS > 1.125 × VOVPSET (MAX1994).
Undervoltage protection thresholds are always enabled and are not affected by this pin.
26 TIME Slew Rate Adjustment Input. Connect a resistor from TIME to GND to set the internal slew-rate clock. A
680k to 68k resistor to GND sets the clock from 53kHz to 530kHz, fSLEW = 252kHz × (143k / RTIME).
27 LINFB
Linear Regulator Feedback Input. The linear regulators feedback set point is 1.0V. Connect a resistive
voltage-divider from the collector of the external PNP pass transistor to LINFB. The DC bias current in the
voltage-divider should be greater than 10µA. The linear regulator is active whenever LIN/SDN is high.
28 LINGOOD
Open-Drain Power-Good Output for the Linear Regulator. As soon as LINFB is in regulation, LINGOOD
goes high after a 1ms minimum delay. When the output goes out of regulation or LIN/SDN goes low,
LINGOOD is forced low within approximately 10µs. A pullup resistor on LINGOOD causes additional
shutdown current.
29 LINBSE Linear Regulator Base Drive. Connect LINBSE to the base of an external PNP power transistor. Add a 220
pullup resistor between the base and the emitter.
30 AGND Analog Ground. Connect the MAX1816/MAX1994s exposed backside pad and low-current ground
terminations to AGND. The current-limit comparators ground sense for BUCK2 also connects to AGND.
31 VCC
Analog Supply Voltage Input for BUCK1, BUCK2, and the Linear Regulator. This pin supplies all power to
the device except for the MOSFET drivers. The range for VCC is 4.5V to 5.5V. Bypass VCC to GND with a
minimum capacitance of 1µF. The maximum resistance between VCC and VDD should be 10.
32 REF
2.0V Reference Output. Bypass REF to GND with a minimum capacitance of 0.22µF. The reference is
trimmed with a nominal 50µA load, and can source a total of 100µA for external loads. Loading REF greater
or less than 50µA decreases output-voltage accuracy according to the limits defined in the Electrical
Characteristics table.
33 FB2 Adjustable Feedback Input for BUCK2. In adjustable mode, FB2 regulates to 1.00V. It also selects default
voltage. Connect FB2 to GND for 2.5V output, or connect FB2 to VCC for 1.8V output.
34 OUT2
Output Voltage Connection for BUCK2. Connect directly to the junction of the output filter capacitors. OUT2
senses the output voltage to determine the on-time and also serve as the feedback input in fixed-output
modes.
35 CS2
Current-Sense Input for BUCK2. For accurate current limit, connect CS2 to a sense resistor between the
source of the low-side MOSFET and ground. Alternatively, CS2 can be connected to LX2 for lossless
current sensing across the low-side MOSFET. The current-limit sense voltage for CS2 is set at the ILIM2
36 ILIM2
BUCK2 Current-Limit Adjustment Input. The current-limit threshold measured between AGND and CS2
defaults to 50mV when ILIM2 is connected to VCC. In adjustable mode, the current-limit threshold voltage is
precisely 1/10th of the voltage at ILIM2. The logic threshold for switchover to the default value is
approximately VCC - 1V.
37 V+ Battery Voltage Sense Input. V+ is used only for PWM one-shot timing. DH1 and DH2 on-times are inversely
proportional to input voltage over a 2V to 28V range.
38 BST2 BUCK2 Boost Flying Capacitor Connection. An optional resistor in series with BST2 allows the DH1 pullup
current to be adjusted.
Pin Description (continued)
[VIAXIIVI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________ 23
Detailed Description
The MAX1816/MAX1994 are dual step-down controllers
for notebook computer applications. The controllers
include a CPU regulator (BUCK1) that features a
dynamically adjustable output with offset control and a
programmable suspend mode voltage. This regulator is
capable of delivering very large currents at the high
efficiencies needed for leading-edge CPU core appli-
cations. A second step-down regulator (BUCK2) is
included to generate I/O or memory supplies. Both reg-
ulators employ Maxims proprietary Quick-PWM control
architecture. A linear-regulator controller is also includ-
ed for low-voltage auxiliary power supplies. All of the
regulators have independent shutdown control inputs.
The linear regulator includes a power-good output that
is independent of the combined power-good output for
BUCK1 and BUCK2.
5V Bias Supply (VCC and VDD)
The MAX1816/MAX1994 require an external 5V bias
supply in addition to the battery. Typically, this 5V bias
supply is the notebook computers 5V system supply.
Keeping the bias supply external to the IC improves effi-
ciency and eliminates the cost associated with the 5V
linear regulator that would otherwise be needed to sup-
ply the PWM controllers and gate drivers of BUCK1 and
BUCK2. If stand-alone capability is needed, the 5V sup-
ply can be generated with an external linear regulator.
The 5V bias supply must provide VCC for the PWM con-
trollers internal reference, bias, and logic; and VDD for
the gate drivers. The maximum bias supply current is:
IBIAS = ICC + f (QG1 + QG2 + QG3 + QG4)
= 20mA to 80mA (typ)
where ICC is 2.2mA (typ), f is the switching frequency,
and QG1,Q
G2,Q
G3, and QG4 are the total gate charge
specifications at VGS = 5V in the MOSFET data sheets.
V+ and VDD can be connected if the input power source
is a fixed 4.5V to 5.5V supply. If the 5V bias supply is
powered up prior to the battery supply, the enable signals
(SKP_/SDN) must be delayed until the battery voltage is
present to ensure startup.
PIN NAME FUNCTION
39 LX2 BUCK2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver.
40 DH2 BUCK2 High-Side Gate-Driver Output. DH2 swings from LX2 to BST2.
41 DL2
BUCK2 Low-Side Gate-Driver Output. DL2 swings from PGND to VDD. DL2 is forced high when
MAX1816/MAX1994 detect an overvoltage fault. When the regulator powers down, DL2 is forced high if
OVP is enabled, and is forced low if OVP is disabled.
42 VDD Supply Voltage Input for DL1 and DL2 Gate Drivers. Connect VDD to the system supply voltage (4.5V to
5.5V). Bypass VDD to PGND with a 2.2µF or greater ceramic capacitor.
43 PGND Power Ground. Ground connection for low-side gate drivers DL1 and DL2.
44 DL1 BUCK1 Low-Side Gate-Driver Output. DL1 swings from PGND to VDD. DL1 is forced high when
MAX1816/MAX1994 detect an overvoltage fault. When the regulator powers down, DL1 is forced high.
45 PERF
Performance Mode Control Input. This logic-control input goes to the offset selection mux that determines
which, if any, offset control inputs are read (OFS0OFS2). This input is compatible with 3.3V logic (see
Table 7).
46 DH1 BUCK1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1.
47 LX1 BUCK1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver.
48 BST1 BUCK1 Boost Flying Capacitor Connection. An optional resistor in series with BST1 allows the DH1 pullup
current to be adjusted.
Pin Description (continued)
[VIAXIIVI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
24 ______________________________________________________________________________________
Table 1. Component Selection for Standard Applications
COMPONENT BUCK1 (CIRCUITS OF
FIGURES 1 AND 2)
BUCK2 (CIRCUITS OF
FIGURES 1 AND 2) SLAVE (CIRCUIT OF FIGURE 2)
Input Voltage Range 7V to 24V 7V to 24V 7V to 24V
Output Voltage 0.6V to 1.75V (MAX1816),
0.7V to 2.0V (MAX1994) 2.5V 0.6V to 1.75V (MAX1816),
0.7V to 2.0V (MAX1994)
Output Current 20A 7A 20A
Frequency 300kHz 300kHz 300kHz
High-Side MOSFET (2) N-channel
International Rectifier IRF7811W
N-channel
International Rectifier IRF7811W
(2) N-channel
International Rectifier IRF7811W
Low-Side MOSFET
(2) N-channel
International Rectifier IRF7822
Fairchild FDS7764A
N-channel
International Rectifier IRF7822
Fairchild FDS7764A
(2) N-channel
International Rectifier IRF7822
Fairchild FDS7764A
Input Capacitor
(3) 10µF, 25V X5R ceramic
Taiyo Yuden TMK432BJ106KM
TDK C4532X5R1E106M
10µF, 25V X5R ceramic
Taiyo Yuden TMK432BJ106KM
TDK C4532X5R1E106M
(3) 10µF, 25V X5R ceramic
Taiyo Yuden TMK432BJ106KM
TDK C4532X5R1E106M
Output Capacitor (3) 330µF, 2.5V, 10m SP
Panasonic EEFUE0E331XR
(1) 330µF, 2.5V, 10m SP
Panasonic EEFUE0E331XR
(3) 330µF, 2.5V, 10m SP
Panasonic EEFUE0E331XR
Inductor
0.6µH
Panasonic ETQP6F0R6BFA
Toko EH125C-R60N
Sumida CDEP134H-0R6
1.2µH
Toko EH125C-1R2N
Sumida CDEP134H-1R2
Panasonic ETQP6F1R2BFA
0.6µH
Panasonic ETQP6F0R6BFA
Toko EH125C-R60N
Sumida CDEP134H-0R6
Current-Sense Resistor 1m ±1%, 1W
Panasonic ERJM1WTJ1M0U
5m ±1%, 1W
Panasonic ERJM1WSF5M0U
1m ±1%, 1W
Panasonic ERJM1WTJ1M0U
Table 2. Component Suppliers
SUPPLIER PHONE WEBSITE
CAPACITORS
Panasonic 847-468-5624 www.panasonic.com
Sanyo 619-661-6835 www.sanyovideo.com
Taiyo Yuden 408-573-4150 www.t-yuden.com
TDK 847-803-6100 www. tdk.com
INDUCTORS
Panasonic 847-468-5624 www.panasonic.com
Sumida 408-982-9660 www.sumida.com
MOSFETs
Fairchild Semiconductor 888-522-5372 www.fairchildsemi.com
International Rectifier 310-322-3331 www.irf.com
Siliconix 203-268-6261 www.vishay.com
H \+ [VIAXIIVI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________ 25
Free-Running, Constant On-Time PWM
Controller with Input Feed-Forward
Both BUCK1 and BUCK2 employ Maxims proprietary
Quick-PWM control architecture. The control scheme is
a pseudo fixed-frequency, constant-on-time current-
mode type with voltage feed forward (Figures 3, 4, and
5). It relies on the output ripple voltage to provide the
PWM ramp signal. This signal can come from the out-
put filter capacitors ESR or a dedicated sense resistor.
The control algorithm is simple: the high-side switch on-
time is determined solely by a one-shot whose period is
inversely proportional to input voltage and directly pro-
portional to output voltage. Another one-shot sets a
minimum off-time (425ns, typ). The on-time one-shot is
triggered if the error comparator is low, the low-side
switch current is below the current-limit threshold, and
the minimum off-time one-shot has timed out.
On-Time One-Shot (TON)
The heart of the PWM core is the one-shot that sets the
high-side switch on-time (Figures 4 and 5). This fast,
low-jitter, adjustable one-shot includes circuitry that
varies the on-time in response to battery and output
voltages. The high-side switch on-time is inversely pro-
portional to the battery voltage as measured by the V+
input, and proportional to the output voltage. This algo-
rithm results in a nearly constant switching frequency
despite the lack of a fixed-frequency clock generator.
The benefits of a constant switching frequency are
twofold: first, the frequency can be selected to avoid
noise-sensitive regions such as the 455kHz IF band;
second, the inductor ripple-current operating point
remains relatively constant, resulting in easy design
methodology and predictable output-voltage ripple:
On-Time = K (VOUT + 0.075V) / VIN
where K is set by the TON pin-strap connection and
0.075V is an approximation to accommodate for the
expected drop across the low-side MOSFET switch
(Table 3).
The on-times for BUCK1 have nominal frequency set-
tings of 200kHz, 300kHz, 550kHz, or 1000kHz, while the
on-times for BUCK2 are shifted to minimize beating
between the two regulators. The corresponding fre-
quency settings for BUCK2 are 260kHz, 390kHz,
390kHz, and 715kHz. The BUCK2 on-times for TON =
open and TON = VCC are shifted down to improve the
efficiency. The BUCK2 on-times for TON = GND and
TON = REF are shifted up to avoid beating, yet maintain
the efficiency. The latter settings were not shifted down
because the resulting frequencies would be too high.
The on-time one-shot has good accuracy at the operat-
ing points specified in the Electrical Characteristics
(±10% at 200kHz and 300kHz, ±12.5% at 550kHz and
1000kHz for BUCK1). On-times at operating points far
removed from the conditions specified in the Electrical
Characteristics can vary over a wider range.
For example, the 1000kHz setting typically runs about
10% slower with inputs much greater than 5V due to the
very short on-times required.
On-times translate only roughly to switching frequencies.
The on-times guaranteed in the Electrical Characteristics
are influenced by switching delays in the external high-
side MOSFETs. Resistive losses, including the inductor,
both MOSFETs, output capacitor ESR, and PC board
copper losses tend to raise the switching frequency at
higher output currents. Also, the dead-time effect
increases the effective on-time, reducing the switching
frequency. It occurs only in PWM mode (SKP_/SDN =
open) and during dynamic output-voltage transitions
(BUCK1) when the inductor current reverses at light or
negative load currents. With reversed inductor current,
the inductors EMF causes LX to go high earlier than
normal, extending the on-time by a period equal to the
DH_ low-to-high dead time.
Table 3. Approximate K-Factor Errors
TON
BUCK1
K-FACTOR
(µs)
BUCK1
FREQUENCY
(kHz)
BUCK1
K-FACTOR ERROR
(%)
BUCK2
K-FACTOR
(µs)
BUCK2
FREQUENCY
(kHz)
BUCK2
K-FACTOR
ERROR (%)
GND 1.0 1000 ±12.5 1.4 715 ±12.5
Open 1.8 550 ±12.5 2.56 390 ±10
REF 3.3 300 ±10 2.56 390 ±10
VCC 5.0 200 ±10 3.84 260 ±10
[MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
26 ______________________________________________________________________________________
Figure 3. Functional Diagram
CS1-
REF
5V BIAS
SUPPLY
VOUT1
BUCK2
DH2
V+
DL2
CS2
OUT2
FB2
ILIM2
PGOOD2
OVPEN
TON2
REF
TON2
PGOOD1
OVPEN
TON1
TON1
REF
V+
DH1
DL1
CS1+
CS1-
FBS
GDS
ILIM1
CC
DH2
LX2
BST2
DL2
VDD
CS2
OUT2
FB2
ILIM2 REF
DH1
BST1
LX1
DL1
CS1+
FBS
GDS
ILIM1
CC
REF
MUX
OUT
BITS
IN
BITS
OUT
VID0–VID4
VID MUX
SUS
D0–D4
FOUR-LEVEL
DECODE
REGISTER
S0-S1
SUS SUS
OFS
CONTROL
STATE
MACHINE
PERF
OFS0–OFS2
SEL
I_OFFSET I_OFFSET
OVPSET
FAULT
THRESHOLD
CONTROL
OFS_SEL
OFFSET CONTROL
INPUT
0
PGND AGND
OVPSET
PERF
ON-TIME
SELECTOR
TON1
TON2
TON
N.C.
D0-D4
V+
BUCK1
5
5
2
SUSPEND
INPUTS
DAC
INPUTS
DAC
BITS
DAC
BITS
I_OFFSET I_OFFSET VOUT2
2.5V
SKP2/SDN
SKP1/SDN
VCC
VDD
INPUT
7V TO 24V
LIN/SDN
LIN/SDN
2V REF REF
AGND
REF
PGND
CONTROL
INPUTS
OVPEN
SKP1/SDN SKP2/SDN
GAIN GAIN
TON1
PRESENT-STATE
DAC BITS
REGISTER
VID ROM
DIGITAL
COMPARATOR
TON2
OVPEN
FAULTLR
LINBSE
LINGOOD
P GOOD
LINFB
3.3V
BIAS SUPPLY
LINGOOD
LINEAR
REG
5 5
X
X < Y
X > Y
X = Y
RTIME TIME
UP
DOWN
OSC OUT
CLOCK
UP/DOWN
COUNTER
OSCILLATOR
DAC
BITS OUT
DAC BITS
DAC BITS
Y
OFFSET
CONTROL 3
55
DPSLP DPSLP
LIN/SDN
VLIN
PGOOD
MAX1816
MAX1994
[MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________ 27
For loads above the critical conduction point, where the
dead-time effect is no longer a factor, the actual switch-
ing frequency is:
where VDROP1 is the sum of the parasitic voltage drops
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; VDROP2 is
the sum of the parasitic voltage drops in the inductor
charge path, including high-side switch, inductor, and
PC board resistances; and tON is the on-time calculat-
ed by the MAX1816/MAX1994.
fVV
tVV
OUT DROP
ON IN DROP
=+
+
1
2
()
Figure 4. BUCK1 PWM Control Diagram
S
R
Q
TOFF
ONE-SHOT
Q
Q
TRIG
ZERO CROSSING
OVP/UVP
DETECTOR
RESET OUT
TIMER
ON/OFF
CONTROL
TON ONE-SHOT
Q
TRIG
ON-TIME
COMPUTE
GAIN-
STATE
DECODER
R-2R
DAC
DAC
AMPLIFIER
10k
ERROR
AMPLIFIER
V+
OUT1
TON1
REF
CC
PGOOD1
SKP1/SDN
DAC BITS
TO DH1 DRIVER
INPUT
TO DL1 DRIVER
INPUT
ILIM1
FBS
I_OFFSET
CS1+
CS1-
GAIN
REF - 10%
REF + 10%
10k
10k/AVPS
10k/AVPS
10k
70k
8.6R1
0.4R1
R1
FBS
GDS
GND
I_GDS
S
R
Q
GM
GM
OVPEN OVPEN
[MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
28 ______________________________________________________________________________________
BUCK1 Integrator
BUCK1 includes a transconductance integrator (Figure
4) that provides a fine adjustment to the output regula-
tion point. The integrator forces the DC average of the
feedback voltage to equal the VID DAC setting. The cir-
cuit has the ability to lower the output voltage by 3%
and raise it by 3%.
The differential input voltage range for the amplifier is at
least ±60mV total, including DC offset and AC ripple.
The integration time constant can be easily set with a
capacitor at the CC pin. Use a capacitance of 47pF to
1000pF (47pF typ). The transconductance of the ampli-
fier is 80µS (typ).
Figure 5. BUCK2 PWM Control Diagram
S
R
Q
TOFF
ONE-SHOT
Q
Q
TRIG
ZERO CROSSING
OVP/UVP
DETECTOR
RESET OUT
TIMER
ON/OFF
CONTROL
TON ONE-SHOT
Q
TRIG
ON-TIME
COMPUTE
ERROR
AMPLIFIER
V+
OUT2
TON2
REF
PGOOD2
SKP2/SDN
TO DH2 DRIVER
INPUT
TO DL2 DRIVER
INPUT
ILIM2
CS2
GND
FB2
OUT2
FIXED 1.5V
DUAL-MODE FEEDBACK MUX
FIXED 1.8V
REF - 10%
REF + 10%
1V
2V
S
R
Q
OVPEN
OVPEN
R
R
[MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
BUCK1 Differential Remote-Sense
Amplifier (FBS, GDS)
The MAX1816/MAX1994 include differential remote-
sense inputs to eliminate the effect of voltage drops
down the PC board traces and through the processors
power leads. The FBS and GDS inputs enable true differ-
ential remote sense of the load voltage. The two inputs
measure the voltage directly across the load to provide a
signal that is summed with the feedback signals that set
the voltage-positioned output. Connect the feedback
sense input (FBS) directly to the positive load terminal
and connect the ground sense input (GDS) directly to
the negative load terminal. Modern microprocessors now
include dedicated VCC and ground-sense pins to
facilitate the measurement of the chips supply voltage.
BUCK1 Voltage-Positioning and
Current-Sense Inputs (CS1+, CS1-)
The CS1+ and CS1- pins are differential inputs that
measure the voltage drop across the sense resistor of
BUCK1 for current-limiting, zero-crossing detection and
active voltage positioning (Figure 4). The current-limit
threshold is adjusted with an external resistive voltage-
divider at ILIM1. A 10µA (min) divider current is recom-
mended. The current-limit threshold adjustment range
is from 25mV to 250mV. In adjustable mode, the cur-
rent-limit threshold is precisely 1/10th of the voltage at
ILIM1. The default current limit is 50mV when ILIM1 is
connected to VCC. The logic threshold for switchover to
the default value is approximately VCC - 1V.The default
current limit accommodates the low voltage drop
expected across the sense resistor.
The current-limit circuit of BUCK1 employs a unique
valley current-sensing algorithm (Figure 6). If the
magnitude of the current-sense voltage between CS1+
and CS1- is above the current-limit threshold, the PWM
is not allowed to initiate a new cycle. The actual peak
current is greater than the current-limit threshold by an
amount equal to the inductor ripple current. Therefore,
the exact current-limit characteristic and maximum load
capability are a function of the sense resistance, induc-
tor value, and battery voltage.
There is also a negative current limit that prevents
excessive reverse inductor currents when VOUT1 is
sinking current in PWM mode.
The negative current-limit threshold is set to approxi-
mately 140% of the positive current limit and therefore
tracks the positive current limit when ILIM1 is adjusted.
The GAIN pin controls the voltage-positioning gain. The
slope of the output voltage as a function of load current
is set by measuring the output current with a sense
resistor (RSENSE) in series with the inductor. An ampli-
fied version of this signal is fed back into the loop to
decrease the output voltage. The required offset is
added through the OFS0OFS2 inputs (see the BUCK1
Output-Voltage Offset Control section). The exact rela-
tionship for the output of BUCK1 can be described with
the following equation:
VOUT1 = VSET - AVPS ×(VCS1+ - VCS1-) + VOS ×SF
where VSET is the programmed output voltage (see
Tables 5 and 6), VOS is the offset voltage generated
from the selected OFS_ pin, SF is a scale factor (0.125)
for the offset voltage, and AVPS is the differential volt-
age-positioning gain set with the GAIN pin.
Since VCS1+ - VCS1- = ILOAD ×RSENSE, substituting the
differential sense voltage yields:
VOUT1 = VSET - AVPS ×ILOAD ×RSENSE + VOS ×SF
The GAIN pin is a four-level logic input. When GAIN is
set to GND, REF, open, and VCC, the differential volt-
age gains are 0, 1.5, 2, and 4, respectively. Grounding
GAIN disables the voltage-positioning function but
does not disable the current limit.
BUCK2 Current-Sense Input (CS2)
BUCK2 uses the voltage at the CS2 pin to estimate the
inductor current and determine the zero crossing for
controlling pulse-skipping operation (Figure 5).
Connect CS2 to the current-sense resistor (Figure 1) for
the best possible current-limit accuracy. However, the
improved accuracy is achieved at the expense of the
additional power loss in the sense resistor. CS2 can be
connected to LX2 for lossless current sensing. In this
case, the trade-off is that the current limit becomes
dependent on the low-side MOSFETs RDS(ON) with its
inherent inaccuracies and thermal drift.
INDUCTOR CURRENT
ILIMIT
ILOAD
0 TIME
IPEAK
Figure 6. Valley Current-Limit Threshold Point
______________________________________________________________________________________________________ 29
[MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
30 ______________________________________________________________________________________
Like BUCK1, the current-limit circuit of BUCK2 also
employs valley current sensing (Figure 6). If the magni-
tude of the current-sense voltage at CS2 is above the
current-limit threshold, the PWM is not allowed to initiate a
new cycle. The actual peak current is greater than the
current-limit threshold by an amount equal to the inductor
ripple current. Therefore, the exact current-limit character-
istic and maximum load capability are a function of the
sense resistance, inductor value, and battery voltage.
There is also a negative current limit that prevents
excessive reverse inductor currents when VOUT2 is
sinking current in PWM mode. The negative current-
limit threshold is set to approximately 140% of the posi-
tive current limit and therefore tracks the positive
current limit when ILIM2 is adjusted.
The current-limit threshold is adjusted with an external
resistive voltage-divider at ILIM2. A 10µA (min) divider
current is recommended. The current-limit threshold
adjustment range is from 25mV to 250mV. In adjustable
mode, the current-limit threshold voltage is precisely
1/10th of the voltage at ILIM2. The threshold defaults to
50mV when ILIM2 is connected to VCC. The logic
threshold for switchover to the 50mV default value is
approximately VCC - 1V. The default current limit
accommodates the low voltage drop expected across
the sense resistor.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the cur-
rent-sense signal seen by CS2. Because CS2 is not a
real differential current-sense input, minimize the return
impedance from the sense resistor to the power ground
to reduce voltage errors when measuring the current.
In Figure 1, the Schottky diode (D2) provides a current
path parallel to the Q4/R2 current path. Accurate cur-
rent sensing demands D2 to be off while Q4 conducts.
Avoid large current-sense voltages. The combined volt-
age across Q4 and R2 can cause D2 to conduct. If very
large sense voltages are used, connect D2 directly
from Q4s source to drain.
Forced-PWM Mode
BUCK1 and BUCK2 operate in forced-PWM mode
when SKP1/SDN and SKP2/SDN are unconnected. The
low-noise forced-PWM mode disables the zero-cross-
ing comparator, allowing the inductor current to reverse
at light loads. This causes the low-side gate-drive
waveform to become the complement of the high-side
gate-drive waveform. This in turn causes the inductor
current to reverse at light loads while DH_ maintains a
duty factor of VOUT_/VIN. The benefit of forced-PWM
mode is to keep the switching frequency fairly constant,
but it comes at a cost: the no-load 5V bias supply cur-
rent can be 20mA to 80mA total for both BUCK1 and
BUCK2, depending on the external MOSFETs and
switching frequency.
Forced-PWM mode is most useful for reducing audio-
frequency noise, improving load-transient response,
providing sink-current capability for dynamic-output
voltage adjustment, and improving the cross-regulation
of multiple-output applications that use a flyback trans-
former or coupled inductor. BUCK1 uses PWM mode
during all output transitions, while the slew-rate con-
troller is active and for 32 clock cycles thereafter.
Automatic Pulse-Skipping Mode
In skip mode (SKP_/SDN = high), an inherent automatic
switchover to PFM takes place at light loads. This
switchover is affected by a comparator that truncates
the low-side switch on-time at the inductor currents
zero crossing. This mechanism causes the threshold
between pulse-skipping PFM and nonskipping PWM
operation to coincide with the boundary between con-
tinuous and discontinuous inductor-current operation
(also known as the critical conduction point).
In low duty-cycle applications, this threshold is relative-
ly constant, with only a minor dependence on battery
voltage.
where K is the on-time scale factor (Table 3). The load
current level at which PFM/PWM crossover occurs,
ILOAD(SKIP), is equal to 1/2 the peak-to-peak ripple cur-
rent, which is a function of the inductor value (Figure 7).
For example, in the standard application circuit with K
= 3.3µs (Table 3), VOUT1 = 1.25V, VIN = 12V, and L1 =
0.68µH, switchover to pulse-skipping operation occurs
at ILOAD1 = 2.7A. The crossover point occurs at an
even lower value if a swinging (soft-saturation) inductor
is used.
The switching waveforms can appear noisy and asyn-
chronous when light loading causes pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs in PFM
noise vs. light-load efficiency are made by varying the
inductor value. Generally, low inductor values produce
a broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the
coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values
include larger physical size and degraded load-tran-
sient response, especially at low-input-voltage levels.
IKV
L
VV
V
LOAD SKIP OUT IN OUT
IN
_( ) __
_
2
[MAXIM [MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________ 31
DC output accuracy specifications for BUCK2 refer to
the threshold of the error comparator. When the induc-
tor is in continuous conduction, BUCK2 output voltage
has a DC regulation level higher than the trip level by
50% of the ripple. In discontinuous conduction
(SKP2/SDN = high, light-loaded), BUCK2 output volt-
age has a DC regulation level higher than the error-
comparator threshold by approximately 1.5% due to
slope compensation.
Note that BUCK1 automatically enters forced-PWM
mode during all output voltage transitions and stays in
forced-PWM mode until the transition is completed and
for 32 clock cycles thereafter. The reason for that is the
forced-PWM operation provides current sinking capa-
bility required during output-voltage transitions.
Linear-Regulator Controller
The linear-regulator controller of the MAX1816/MAX1994
is an analog gain block with an open-drain N-channel
output. It drives an external PNP pass transistor with a
220base-to-emitter resistor (Figure 1). The controller
is guaranteed to provide at least 20mA sink current. The
linear regulator is typically used to provide a
1.2V/500mA VID logic supply. The controller is designed
to be stable with an output capacitor of 10µF or more.
The output voltage can be adjusted with a resistive volt-
age-divider between the linear regulator output and
analog ground with the center tap connected to LINFB.
The set point of LINFB is 1.0V. The regulator is enabled
when LIN/SDN is high. As soon as LINFB is in regula-
tion, the open-drain power-good output LINGOOD goes
high after a 1ms (min) delay. When the output goes out
of regulation or LIN/SDN goes low, LINGOOD is forced
low within approximately 10µs.
The 1ms (min) LINGOOD delay is necessary to allow
the PLLs in the CPU to power up and stabilize before
turning on the main regulator. The delay time is com-
puted based on 1024 RTIME clock cycles. As such, the
delay varies based on the RTIME period.
MOSFET Gate Drivers (DH_, DL_)
The DH_ and DL_ drivers are optimized for driving mod-
erate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in the notebook CPU environment, where a large
VIN -V
OUT_ differential exists. Two adaptive dead-time
circuits monitor the DH_ and DL_ outputs and prevent
the opposite side FET from turning on until DL_ or DH_ is
fully off. There must be a low-resistance, low-inductance
path from the DL_ and DH_ drivers to the MOSFET gates
for the adaptive dead-time circuits to work properly.
Otherwise, the sense circuitry in the MAX1816/MAX1994
interprets the MOSFET gate as off while there is actual-
ly still charge left on the gate. Use very short, wide traces
measuring 10 to 20 squares (50 mils to 100 mils wide if
the MOSFET is 1in from the MAX1816/MAX1994).
The internal pulldown transistor that drives DL_ low is
robust, with a very low pulldown resistance. For DL1,
this resistance is 0.35(typ), while the resistance for
DL2 is slightly higher at 0.7(typ). This helps prevent
DL_ from being pulled up during the fast rise-time of
the inductor node, due to capacitive coupling from the
drain to the gate of the low-side synchronous-rectifier
MOSFET. However, for high-current applications, some
combinations of high- and low-side FETs can cause
excessive gate-drain coupling, which can lead to effi-
ciency-killing, EMI-producing shoot-through currents.
This is often remedied by adding a resistor in series
with BST_, which increases the turn-on time of the high-
side FET without degrading the turn-off time (Figure 8).
LX_
+5V
VBATT
5TYP
DH_
BST_
MAX1816
MAX1994
Figure 8. Reducing the Switching-Node Rise Time
INDUCTOR CURRENT
ILOAD = IPEAK/2
ON-TIME0 TIME
IPEAK
L
VBATT - VOUT
i
t=
Figure 7. Pulse-Skipping/Discontinuous Crossover Point
[MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
32 ______________________________________________________________________________________
Shutdown Control (SKP1/
SSDDNN
,
SKP2/
SSDDNN
, and LIN/
SSDDNN
)
If BUCK2 is used, always start BUCK2 before starting
BUCK1. When SKP1/SDN goes below 0.5V, BUCK1
enters low-power shutdown mode. PGOOD goes low
immediately. The output voltage ramps down to zero in
25mV steps at the clock rate set by RTIME. Thirty-two
clocks after the DAC reaches the zero setting, DL1 is
forced to VDD, and DH1 is forced low. When SKP1/SDN
goes above 1.4V or floats, the DAC target is evaluated
and switching begins. The slew-rate controller ramps
up from zero in 25mV steps to the selected DAC code
value. There is no traditional soft-start (variable current-
limit) circuitry, so full output current is available immedi-
ately. Floating SKP1/SDN causes BUCK1 to operate in
low-noise forced-PWM mode. Forcing SKP1/SDN
above 2.8V enables skip mode operation.
When SKP2/SDN goes below 0.5V, BUCK2 enters shut-
down mode. In shutdown mode, DL2 is forced to VDD if
overvoltage protection is enabled. If OVPSET is con-
nected to VCC, overvoltage protection is disabled and
DL2 is forced low in shutdown mode.
When LIN/SDN goes below 0.8V, the linear regulator of
the MAX1816/MAX1994 enters shutdown mode. In
shutdown mode, LINBSE is forced to a high-impedance
state preventing sufficient drive to the external PNP
pass transistor in the regulator. LINGOOD is forced low
within 10µs (typ) when LIN/SDN goes low. Forcing
LIN/SDN above 2.4V turns on the linear regulator.
Power-On Reset
Power-on reset (POR) occurs when VCC rises above
approximately 2V, resetting the fault latch and preparing
the MAX1816/MAX1994 for operation. VCC undervoltage
lockout (UVLO) circuitry inhibits switching, forces
PGOOD low, and forces the DL1 gate driver high (to
enforce output overvoltage protection). The DL2 gate
driver is also forced high if OVP is enabled. When VCC
rises above 4.25V, the DAC inputs are sampled and the
output voltage begins to slew to the DAC setting. For
automatic startup, the battery voltage should be present
before VCC. If the MAX1816/MAX1994 attempt to bring
the output into regulation without the battery voltage
present, the fault latch will trip. Toggling any of the shut-
down control pins resets the fault latch.
Power Valid Outputs
(PGOOD and LINGOOD)
PGOOD is an open-drain power-good output. Table 4
describes the behavior of PGOOD with respect to the
logic inputs. Window comparators on FBS and OUT2
(FB2) control the PGOOD output. If BUCK1 and BUCK2
are in regulation then PGOOD is high, except during
power-up and power-down.
The PGOOD output goes low if FBS or OUT2 (FB2) is
outside a window of ±10% about the nominal set point
(see the DAC Inputs and Internal Multiplexers and
Adjusting BUCK2 Output Voltage sections).
PGOOD is forced low when SKP1/SDN is low. If
SKP2/SDN is low, then OUT2 (FB2) does not affect
PGOOD. Normally, PGOOD is forced high during all
VID transitions, and stays high for 4 clock periods after
the DAC count is equalized. If BUCK2 goes out of regu-
lation during these conditions, then PGOOD goes low
as a consequence. A pullup resistor on PGOOD caus-
es additional finite shutdown current.
The following conditions must all be met for PGOOD to
go high:
VCC must be above UVLO.
SKP1/SDN must be greater than 1.4V or unconnected.
The output of BUCK1 must be within a window of
±10% about the nominal set point.
PGOOD is forced high during DAC code transitions
of BUCK1. The blanking period persists for N+4
RTIME clock cycles. Blanking does not occur during
power-up and power-down.
If SKP2/SDN is not low, then OUT2 (FB2) must be
within a window of ±10% about the nominal set point.
When enabled, a fault on OUT2 overrides the blank-
ing on BUCK1.
LINGOOD is an open-drain power-good output for the
linear regulator. LINGOOD goes high at least 1ms after
the internal comparator signals that the output is in reg-
ulation. In normal operation, if the internal comparator
signals that the circuit is out of regulation, LINGOOD
goes low within approximately 10µs (typ). If LIN/SDN
goes low, LINGOOD is immediately forced low.
Note that all three regulators are forced off when a fault is
detected. DL_ are forced high, DH_ are forced low, and
the linear regulator is turned off. (See the Output
Overvoltage Protection, Output Undervoltage Protection,
UVLO, and Thermal Fault Protection sections).
DAC Inputs and Internal
Multiplexers (SUS)
The MAX1816/MAX1994 have a unique internal VID input
multiplexer (mux) that can select one of two different VID
DAC code settings for different processor states. When
the logic level at SUS is low, the mux selects the VID DAC
code settings from the D0D4 inputs (Table 5). Do not
leave D0D4 floatinguse 100kpullup resistors if the
inputs float. When SUS is high, the suspend mode mux
selects the VID DAC code settings from the S0/S1 input
decoder. The outputs of the decoder are determined by
[VIAXIIVI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________ 33
Table 4. BUCK1 and BUCK2 Operating Mode Truth Table
OVP SKP1/SDN SKP2/SDN DL1 DL2 MODE PGOOD
X GND VCC HIGH Switching BUCK2 LOW
Enabled VCC GND Switching HIGH BUCK1 Monitor BUCK1 only
Disabled VCC GND Switching LOW BUCK1 Monitor BUCK1 only
Enabled GND GND HIGH HIGH Shutdown LOW
Disabled GND GND HIGH LOW Shutdown LOW
XV
CC VCC Switching Switching Both in skip mode Monitor both
Enabled >10.8V GND Switching HIGH BUCK1 no-fault test mode Monitor BUCK1 only
Disabled >10.8V GND Switching LOW BUCK1 no-fault test mode Monitor BUCK1 only
X >10.8V VCC Switching Switching No-fault test mode Monitor both
X >10.8V Float Switching
Switching in
forced PWM
mode
No-fault test mode Monitor both
Enabled Float GND
Switching in
forced PWM
mode
HIGH BUCK1 in forced PWM
mode Monitor BUCK1 only
Disabled Float GND
Switching in
forced PWM
mode
LOW BUCK1 in forced PWM
mode Monitor BUCK1 only
X Float VCC
Switching in
forced PWM
mode
Switching
BUCK1 in forced PWM
mode, BUCK2 in skip
mode
Monitor both
X Float Float
Switching in
forced PWM
mode
Switching in
forced PWM
mode
BUCK1 and BUCK2 in
forced PWM Mode Monitor both
X GND Float HIGH
Switching in
forced PWM
mode
BUCK1 off, BUCK in
forced PWM mode LOW
XV
CC Float Switching
Switching in
forced PWM
mode
BUCK1 in skip mode,
BUVK2 in forced PWM
mode
Monitor both
Enabled VCC or
float
VCC or
float HIGH HIGH OVP and UVP faults LOW
Disabled VCC or
float
VCC or
float HIGH HIGH UVP faults only LOW
X = Dont care.
inputs S0 and S1, which are four-level digital inputs
(Table 6). All code transitions (even those asking for the
exact same code) activate the slew-rate controller. In
other words, up-going or down-going transitions from one
code to another, soft-start and soft-stop are all handled in
the same way.
BUCK1 Output-Voltage Offset Control
(SUS, PERF,
DDPPSSLLPP,,
and OFS_)
The MAX1816/MAX1994 support three independent off-
sets to the voltage-positioned load line. The offsets are
adjusted using resistive voltage-dividers at the
OFS0OFS2 inputs (see Figure 10). For inputs from 0 to
0.8V, a negative offset is added to the output that is
[VIAXIIVI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
34 ______________________________________________________________________________________
equal to 1/8th the voltage appearing at the selected
OFS input (VOUT = -0.125 ×VOFS_). For inputs from
1.2V to 2V, a positive offset is added to the output that
is equal to 1/8th the difference between the reference
voltage and the voltage appearing at the selected OFS
input (VOUT = 0.125 ×(VREF - VOFS_)). With this
scheme, both positive and negative offsets can be
achieved with a single voltage-divider. The piecewise
linear transfer function is shown in Figure 9.
The regions of the transfer function below zero, above
2.0V, and between 0.8V and 1.2V are undefined. OFS
inputs are disallowed in these regions, and the respec-
tive effects on the output are not specified.
The offset control inputs are selected using a combina-
tion of the three logic inputs (SUS, PERF, and DPSLP),
which also define the operating mode for the
MAX1816/MAX1994. Table 7 details which OFS input is
selected based on these control inputs.
BUCK1 Output-Voltage Transition Timing
The MAX1816/MAX1994 are designed to perform out-
put voltage transitions in a controlled manner, automati-
cally minimizing input surge currents. This feature
allows the regulator to perform nearly ideal transitions,
guaranteeing just-in-time arrival at the new output volt-
age level with the lowest possible peak currents for a
given output capacitance.
Modern mobile CPUs operate at multiple clock frequen-
cies that require multiple VID settings. It is common
when transitioning from one clock frequency to another
for the CPU to go into a low-power state before chang-
ing the output voltage and clock frequency. The change
must be accomplished within a fixed time intervaloften
less than 100µs.
Table 6. Output Voltage vs. Suspend
Mode DAC Codes
S1 S0 VOUT (V)
MAX1816/MAX1994
GND GND 1.075
GND REF 1.050
GND OPEN 1.025
GND VCC 1.000
REF GND 0.975
REF REF 0.950
REF OPEN 0.925
REF VCC 0.900
OPEN GND 0.875
OPEN REF 0.850
OPEN OPEN 0.825
OPEN VCC 0.800
VCC GND 0.775
VCC REF 0.750
VCC OPEN 0.725
VCC VCC 0.700
Table 5. Output Voltage vs. DAC Codes
D4 D3 D2 D1 D0 VOUT (V)
MAX1816
VOUT (V)
MAX1994
0 0 0 0 0 1.750 2.000
0 0 0 0 1 1.700 1.950
0 0 0 1 0 1.650 1.900
0 0 0 1 1 1.600 1.850
0 0 1 0 0 1.550 1.800
0 0 1 0 1 1.500 1.750
0 0 1 1 0 1.450 1.700
0 0 1 1 1 1.400 1.650
0 1 0 0 0 1.350 1.600
0 1 0 0 1 1.300 1.550
0 1 0 1 0 1.250 1.500
0 1 0 1 1 1.200 1.450
0 1 1 0 0 1.150 1.400
0 1 1 0 1 1.100 1.350
0 1 1 1 0 1.050 1.300
0 1 1 1 1 1.000 No CPU
1 0 0 0 0 0.975 1.275
1 0 0 0 1 0.950 1.250
1 0 0 1 0 0.925 1.225
1 0 0 1 1 0.900 1.200
1 0 1 0 0 0.875 1.175
1 0 1 0 1 0.850 1.150
1 0 1 1 0 0.825 1.125
1 0 1 1 1 0.800 1.100
1 1 0 0 0 0.775 1.075
1 1 0 0 1 0.750 1.050
1 1 0 1 0 0.725 1.025
1 1 0 1 1 0.700 1.000
1 1 1 0 0 0.675 0.975
1 1 1 0 1 0.650 0.950
1 1 1 1 0 0.625 0.925
1 1 1 1 1 0.600 No CPU
[MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________ 35
At the beginning of an output voltage transition, the regu-
lator is placed in forced-PWM mode and the PGOOD
output is high. If there is a fault on BUCK2 during this
period, PGOOD goes low. The output voltage follows the
internal DAC code, which changes in 25mV increments
until it reaches the programmed VID code. The regulator
remains in forced-PWM mode for 32 clock cycles after
the transition to ensure that the output settles properly.
The PGOOD output is forced high for 4 clock cycles after
the transition also to allow the output to settle. The slew-
rate clock frequency (set by the RTIME resistor) must be
set fast enough to ensure that the longest transition is
completed within the allotted time interval.
The output voltage transition is performed in 25mV steps,
preceded by a 4µs delay and followed by one additional
clock period. The total time for a transition depends on
RTIME, the voltage difference, and the accuracy of the
MAX1816/MAX1994s slew-rate clock, and is not depen-
dent on the total output capacitance. The greater the out-
put capacitance, the higher the surge current required
for the transition. The MAX1816/MAX1994 automatically
control the current to the minimum level required to com-
plete the transition in the calculated time. As long as the
surge current is less than the current limit set by ILIM1,
the transition time is given by:
where fSLEW = 252kHz ×143k/ RTIME, VOLD is the
original DAC setting, and VNEW is the new DAC setting.
See Time Frequency Accuracy in the Electrical
Characteristics table for fSLEW accuracy. The practical
range of RTIME is 68kto 680k, corresponding to
1.9µs to 19µs per 25mV step. Although the DAC takes
discrete 25mV steps, the output filter makes the transi-
tions relatively smooth. The average inductor current
required to make an output voltage transition is:
IL COUT 25mV fSLEW
The slew-rate controller also performs a soft-start and
soft-stop function. The soft-start function works by
counting up from zero, in order to minimize turn-on
surge currents. The soft-stop executes this process in
reverse, eliminating the negative output voltages and
the need for an external Schottky output clamp diode
that would otherwise be required if DL1 were simply
forced high.
Setting BUCK2 Output Voltage
BUCK2s Dual Modeoperation allows the selection of
common voltages without requiring external compo-
nents (Figure 1). In fixed mode, connect FB2 to AGND
for 2.5V output, or connect FB2 to VCC for 1.8V output.
In adjustable mode, the output voltage can be adjusted
from 1.0V to 5.5V using a resistive voltage-divider from
the BUCK2 output to AGND with the center tap con-
nected to FB2 (Figure 11). The equation for adjusting
the output voltage is:
where VFB2 is 1.0V.
VVR
R
OUT FB22
11
2
=+
ts
f
VV
mV
SLEW SLEW
OLD NEW
≤µ+ +
41125
Figure 9. Offset-Control Transfer Function
-0.15
-0.05
-0.10
0.05
0
0.10
0.15
UNDEFINED
0 1.00.5 0.8 1.2 1.5 2.0
OFS_ INPUT VOLTAGE (V)
OUTPUT OFFSET VOLTAGE (V)
Figure 10. Simplified Offset-Control Circuits
REF OR VOUT1 REF OR VOUT1
OR
OFS0
OFS1
OFS1
OFS0
OFS1
OFS2
Dual Mode is a trademark of Maxim Integrated Products, Inc.
[MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
36 ______________________________________________________________________________________
Output Overvoltage Protection
Output overvoltage protection (OVP) is available on
BUCK1, BUCK2, and the linear regulator. The LINFB
input is always monitored for overvoltage. The FBS and
OUT2 inputs are only monitored for overvoltages when
OVP is enabled. When any output exceeds the desired
OVP threshold, the fault latch is set and the regulator is
turned off. In the fault mode, DL1 and DL2 are forced
high, DH1 and DH2 are forced low, and the linear regu-
lator is turned off. For BUCK1 and BUCK2, if the condi-
tion that caused the overvoltage (such as a shorted
high-side MOSFET) persists, the battery fuse will blow.
DL1 is also kept high continuously when VCC UVLO is
active, as well as in shutdown mode (Table 4). The
device remains in the fault mode until VCC is cycled, or
either SKP_/SDN or LIN/SDN is toggled. The triggering
of the reset condition occurs on the rising edge of the
SKP_/SDN or LIN/SDN signals.
For BUCK1, the default OVP threshold is 2V for the
MAX1816 and 2.25V for the MAX1994. For BUCK2, the
OVP threshold is 115% of the nominal voltage for OUT2
(FB2 if external feedback is used for BUCK2). The over-
voltage detection level for FBS can be adjusted through
an external resistive voltage-divider. Connecting OVPSET
to a voltage between 1.0V and 2.0V sets the OVP thresh-
old for FBS. For the MAX1816, the fault latch is set when
VFBS > VOVPSET. For the MAX1994, the fault latch is set
when VFBS > 1.125 VOVPSET. The OVP threshold on
OUT2 is not adjustable and remains at the default value
of 115%. Connecting OVPSET to VCC disables OVP for
BUCK1 and BUCK2. The operation of the linear regulator
is not affected by OVPSET. Overvoltage protection can
be disabled using the NO FAULT test mode (see the NO
FAULT Test Mode section).
Output Undervoltage Protection
The output undervoltage protection (UVP) is available on
BUCK1, BUCK2, and the linear regulator. The protection
is similar to foldback current limiting, but employs a timer
rather than a variable current limit. If the output voltage is
under 70% of the nominal value for BUCK1 and BUCK2,
and under 90% for the linear regulator (see the Electrical
Characteristics table for the respective UVP thresholds),
the fault latch is set. In the fault mode, DL1 and DL2 are
forced high, DH1 and DH2 are forced low, and the linear
regulator is turned off. The controller does not restart until
VCC power is cycled, or either SKP_/SDN or LIN/SDN is
toggled. The triggering of the reset condition occurs on
the rising edge of the SKP_/SDN or LIN/SDN signals.
Table 7. Offset Selection Truth Table
INPUTS ACTIVE OFS INPUTS
MODE SUS PERF DPSLP OFS2 OFS1 OFS0
Battery Sleep 0 0 0 1 0 0
Battery 0 0 1 0 1 0
Performance Sleep 0 1 0 0 0 1
Performance 0 1 1 0 0 0
Suspend 1 0 0 0 0 0
Suspend 1 0 1 0 0 0
Suspend 1 1 0 0 0 0
Suspend 1 1 1 0 0 0
0 = Logic low or input not selected.
1 = Logic high or input selected.
DL2
AGND
OUT2
CS2
DH2
FB2
VBATT
VOUT
R1
R2
MAX1816
MAX1994
PGND
Figure 11. Adjusting BUCK2 Output Voltage with a Resistive
Voltage-Divider
[MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________ 37
To allow startup, UVP is ignored during the undervoltage
blanking time (the first 256 cycles of the slew rate after
startup for BUCK1, the first 4096 cycles for BUCK2 and
the first 512 cycles for the linear regulator). UVP can be
disabled using the NO FAULT test mode (see the NO
FAULT Test Mode section).
UVLO
The MAX1816/MAX1994 provide input undervoltage lock-
out (UVLO) protection. If the VCC voltage drops low
enough to trip the UVLO comparator, it is assumed that
there is not enough supply voltage to make valid deci-
sions. In order to protect the output from overvoltage
faults, DL1 and DL2 are forced high if OVP is enabled,
DH_ is forced low, and the linear regulator is turned off. If
OVP is disabled, DL1 is forced high, DL2 is forced low,
DH_ is forced low, and the linear regulator is turned off.
For BUCK1 (and also for BUCK2 if OVP is enabled), this
condition rapidly forces the outputs to zero since the
slew-rate controller is not active. The fault results in large
negative inductor currents and possibly small negative
output voltages. If VCC is likely to drop in this fashion, the
outputs can be clamped with Schottky diodes to PGND to
reduce the negative excursions.
Thermal Fault Protection
The MAX1816/MAX1994 feature a thermal fault-protec-
tion circuit. When the junction temperature rises above
+160°C, a thermal sensor sets the fault latch, which
pulls DL_ high, DH_ low, and turns off the linear regula-
tor. The device remains in fault mode until the junction
temperature cools by 15°C, and either VCC power is
cycled, or SKP_/SDN or LIN/SDN is toggled.
NO FAULT Test Mode
The over/undervoltage protection features can compli-
cate the process of debugging prototype breadboards
since there are (at most) a few milliseconds in which to
determine what went wrong. Therefore, a test mode is
provided to disable the OVP, UVP, and thermal shut-
down features, and clear the fault latch if it has been
set. Test mode applies to BUCK1, BUCK2, and the lin-
ear regulator. In the test mode, BUCK1 operates as if
SKP1/SDN was high (skip mode). Set the voltage on
SKP1/SDN between 10.8V to 13.2V to enable the NO
FAULT test mode.
BUCK1/BUCK2
Design Procedure
Firmly establish the input voltage range and maximum
load current for BUCK1 and BUCK2 before choosing a
switching frequency and inductor operating point (rip-
ple-current ratio). The primary design trade-off lies in
choosing a good switching frequency and inductor
operating point, and the following four factors dictate
the rest of the design:
1) Input Voltage Range. The maximum value
(VIN(MAX)) must accommodate the worst-case high
AC adapter voltage. The minimum value (VIN(MIN))
must account for the lowest battery voltage after
drops due to connectors, fuses, and battery selec-
tor switches. If there is a choice, lower input volt-
ages result in better efficiency.
2) Maximum Load Current. There are two values to
consider. The peak load current (ILOAD(MAX)) deter-
mines the instantaneous component stresses and
filtering requirements, and thus drives output
capacitor selection, inductor saturation rating, and
the design of the current-limit circuit. The continu-
ous load current (ILOAD) determines the thermal
stresses and thus drives the selection of input
capacitors, MOSFETs, and other critical heat-con-
tributing components. Modern notebook CPUs gen-
erally exhibit ILOAD = ILOAD(MAX) 80%.
3) Switching Frequency. This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage, due to MOSFET switching losses that
are proportional to frequency and VIN. The optimum
frequency is also a moving target, due to rapid
improvements in MOSFET technology that are mak-
ing higher frequencies more practical.
4) Inductor Operating Point. This choice provides
tradeoffs between size and efficiency. Low inductor
values cause large ripple currents, resulting in the
smallest size, but poor efficiency and high output
noise. The minimum practical inductor value is one
that causes the circuit to operate at the edge of criti-
cal conduction (where the inductor current just
touches zero with every cycle at maximum load).
Inductor values lower than this grant no further size-
reduction benefit. The MAX1816/MAX1994s pulse-
skipping algorithm initiates skip mode at the critical
conduction point. So, the inductor operating point
also determines the load current value at which
PFM/PWM switchover occurs. The optimum point is
usually found between 20% and 50% ripple current.
[MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
38 ______________________________________________________________________________________
5) Inductor Ripple Current. The inductor ripple cur-
rent also impacts transient response performance,
especially at low VIN - VOUT differentials. Low induc-
tor values allow the inductor current to slew faster,
replenishing charge removed from the output filter
capacitors by a sudden load step. The amount of
output sag is also a function of the maximum duty
factor, which can be calculated from the on-time
and minimum off-time:
where tOFF(MIN) is the minimum off-time (see the
Electrical Characteristics table) and K is from Table 3.
Inductor Selection
The switching frequency and operating point (% ripple
current or LIR) determine the inductor value as follows:
Example: ILOAD(MAX) = 19A, VIN = 7V, VOUT = 1.25V,
fSW = 300kHz, 30% ripple current or LIR = 0.30:
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered iron
is inexpensive and can work well at 200kHz. The core
must be large enough not to saturate at the peak induc-
tor current (IPEAK):
Setting the Current Limit for BUCK1
Connect ILIM1 to VCC for a default 50mV (CS1+ to CS1-)
current-limit threshold. For an adjustable threshold, con-
nect a resistive voltage-divider from REF to GND, with
ILIM1 connected to the center tap. The current-limit
threshold is precisely 1/10th of the voltage at ILIM1. When
adjusting the current limit, use 1% tolerance resistors for
the divider and a 10µA divider current to prevent a signifi-
cant increase of errors in the current-limit threshold.
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The val-
ley of the inductor current occurs at ILOAD(MAX) minus
half of the ripple current; therefore:
The current-sense resistor value (R1 in Figure 1) is cal-
culated according to the worst-case (minimum) current-
limit threshold voltage (see the Electrical Characteristics
table) and the valley current-limit threshold ILIMIT(MIN)
described above:
where 0.8 is a factor for the worst-case low current-limit
threshold.
To protect against component damage during short-cir-
cuit conditions, use the calculated value of RSENSE to
size the MOSFET switches and specify inductor satura-
tion-current ratings according to the worst-case high
current-limit threshold:
where 1.2 is a factor for worst-case high current-limit
threshold.
Low-inductance resistors, such as surface-mount metal
film, are recommended.
Setting the Current Limit for BUCK2
Connect ILIM2 to VCC for a default 50mV CS2 to GND
current-limit threshold. For an adjustable threshold,
connect a resistive voltage-divider from REF to GND,
with ILIM2 connected to the center tap. The current-
limit threshold is precisely 1/10th of the voltage at
ILIM2. When adjusting the current limit, use 1% toler-
ance resistors for the divider and a 10µA divider cur-
rent to prevent a significant increase of errors in the
current-limit threshold.
ImV
RLIR
Fixed Mode
IV
RLIR
Adjustable Mode
PEAK MAX SENSE
PEAK MAX ILIM
SENSE
()
()
.()
()
..
()
()
=××+
=×× ×+
50 1 2 1
01 12 1
1
RmV
IFixed Mode
RV
IAdjustable Mode
SENSE LIMIT MIN
SENSE ILIM
LIMIT MIN
=×
=××
50 0 8
01 08
1
.()
..
()
()
()
II LIR
LIMIT MIN LOAD MAX() ( )
12
II LIR
PEAK LOAD MAX
+
()
12
LVV V
V kHz A H=×
×××
125 7 125
7 300 0 30 19 060
.(.)
..
LVVV
V f LIR I
OUT IN OUT
IN SW LOAD MAX
=×
×××
()
()
V
II LK
V
Vt
CV K
VV
Vt
SAG
LOAD LOAD OUT
IN OFF MIN
OUT OUT IN OUT
IN OFF MIN
=
×× +
×××
() ()
()
12
2
2
|L|M\T(M\N) 5,7mfl OUT VOUT [MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________ 39
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The val-
ley of the inductor current occurs at ILOAD(MAX) minus
half of the ripple current; therefore:
where ILIMIT(MIN) equals the minimum current-limit
threshold voltage divided by the current-sense resistor.
The sense resistor (R2 in Figure 1) determines the achiev-
able current-limit accuracy. There is a trade-off between
current-limit accuracy and sense-resistor power dissipa-
tion. Most applications employ a current-sense voltage of
50mV to 100mV. Choose a sense resistor so that:
where 0.8 is a factor for worst-case low current-limit
threshold.
Extremely cost-sensitive applications that do not require
high-accuracy current sensing can use the on-resis-
tance of the low-side MOSFET switch in place of the
sense resistor by connecting CS2 to LX2. Use the worst-
case maximum value for RDS(ON) from the MOSFET
data sheet taking into account the rise in RDS(ON) with
temperature. A good general rule is to allow 0.5% addi-
tional resistance for each °C temperature rise.
Assume the current-sense resistor in the application cir-
cuit in Figure 1 is removed and CS2 is directly tied to
LX2. The Q4 maximum RDS(ON) = 3.8mat TJ= +25°C
and 5.7mat TJ= +125°C.
The minimum current-limit threshold is:
and the required valley current limit is:
ILIMIT(MIN) > 7A (1 - 0.30/2) = 5.95A
since 7A is greater than the required 5.95A, the circuit
can deliver the 7A full-load current.
Output Capacitor Selection
(BUCK1 and BUCK2)
The output filter capacitor must have low enough effec-
tive series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements. Also, the capacitance
value must be high enough to absorb the inductor ener-
gy going from a full-load to no-load condition without
tripping the OVP circuit.
In CPU core voltage regulators and other applications
where the output is subject to violent load transients,
the output capacitors size typically depends on how
much ESR is needed to prevent the output from dipping
too low under a load transient. Ignoring the sag due to
finite capacitance:
In non-CPU applications, the output capacitors size
often depends on how much ESR is needed to maintain
an acceptable level of output-voltage ripple:
The actual microfarad capacitance value required often
relates to the physical size needed to achieve low ESR,
as well as to the chemistry of the capacitor technology.
Thus, the capacitor is usually selected by ESR and volt-
age rating rather than by capacitance value (this is true
of tantalums, OSCONs, and other electrolytics).
When using low-capacity filter capacitors such as
ceramic or polymer types, capacitor size is usually deter-
mined by the capacity needed to prevent VSAG and
VSOAR from causing problems during load transients.
Generally, once enough capacitance is added to meet
the overshoot requirement, undershoot at the rising load
edge is no longer a problem.
The amount of overshoot due to stored inductor energy
can be calculated as:
where IPEAK is the peak inductor current.
VLI
CV
SOAR PEAK
OUT OUT
=×
××
2
2
RV
LIR I
ESR PP
LOAD MAX
×
()
RV
I
ESR DIP
LOAD MAX
()
ImV
mA
LIMIT MIN()
..
.
=×× =
500 01 08
57 7
RmV
I
Fixed Mode
RV
I
Adjustable Mode
SENSE
LIMIT MIN
SENSE ILIM
LIMIT MIN
=×
=××
50 0 8
01 08
2
. ( )
..
( )
()
()
II LIR
LIMIT MIN LOAD MAX() ( )
12
redu [MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
40 ______________________________________________________________________________________
BUCK1 Stability Considerations
BUCK1 is fundamentally different from previous Quick-
PWM controllers in two respects: it uses a current-sense
amplifier to obtain the current feedback signal (ramp),
and it uses differential remote sense to compensate for
voltage drops along the high-current path. The regulator
adds the differential remote-sense signal to the current-
feedback signal to correct the output voltage. As long
as the amplitude of the resulting signal is greater than
1% of the output voltage, the regulator remains stable.
Stability can be determined by comparing the zero
formed with the current-sense feedback network to the
switching frequency.
The boundary condition of stability is given by the fol-
lowing expression:
where COUT1 is the local output capacitance (Figure 1),
CREMOTE is the remote output capacitance, RLOCAL is
the ESR of the local capacitors, RREMOTE is the ESR of
the remote capacitors, and RDROOP is the effective
voltage-positioning resistance, which is determined by
the voltage-positioning gain AVPS and current-sense
resistor RSENSE:
RDROOP = AVPS x RSENSE
Like previous Quick-PWM controllers, larger values of
ESR and sense resistance increase stability. The volt-
age-positioning gain AVPS effectively increases the
sense resistance, which further enhances stability.
The RC time constants of the local and remote capaci-
tors affect the stability criteria. These two time con-
stants are defined as follows:
τLOCAL = (RDROOP + RLOCAL + RPCB_TRACE) x COUT1
τREMOTE = (RDROOP + RREMOTE) x CREMOTE
where RPCB_TRACE is the PC board trace resistance
shown in Figure 1.
When the local capacitance time constant is either
much greater or much smaller than that of the remote
capacitance, the stability criteria is:
In applications where these two time constants are
approximately equal, the criteria for stable operation
reduces to:
The standard application circuit (Figure 1) operating at
300kHz easily achieves stable operation because the
time constant of the local capacitors is much greater
than that of the remote capacitors.
In this example, COUT1 = 990µF, RLOCAL = 3.3m,
CREMOTE = 10µF, RREMOTE = 5m, and RDROOP = 2 x
1m= 2m:
When voltage positioning is not used (AVPS = 0) and the
ESR of the output capacitors alone cannot meet the sta-
bility requirement, the current feedback signal must be
generated from a different source. The current ramp sig-
nal at CS1+ and the output voltage must be summed at
the FBS input. For stable operation, a 3.3µF feed-for-
ward capacitor is added from the CS1+ input to FBS
and a 10resistor is inserted from the remote load to
FBS forming an RC filter (Figure 12). The cutoff frequen-
cy of the RC filter should be approximately an order of
magnitude lower than the regulators switching frequen-
cy to prevent sluggish transient response. To avoid
input-bias current-induced offset errors, the resistor
should be less than 20.
2 990 10 3 3
990 5 10 1
2 300
532 167
mFFm
Fm F kHz
ss
ΩΩ
×+
()
+
×+×
×
µµ
µµ
µµ
.
. .
RRC fand
RR C f
DROOP LOCAL OUT SW
DROOP REMOTE REMOTE SW
+
()
×≥
×
+
()
×≥
×
1
1
2
1
2
RCC R
CR C f
DROOP OUT REMOTE LOCAL
OUT REMOTE REMOTE SW
×+
()
×
1
1
1
2
fRCC
RCR C
Z
DROOP OUT REMOTE
LOCAL OUT REMOTE REMOTE
××+
()
+
×+ ×
1
21
1
π
ff
ZSW
π
[5‘an THEMO [MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________ 41
For nonvoltage-positioned applications using a feed-
forward circuit, the RC time constants of the local and
remote capacitors are defined as:
τLOCAL = (RSENSE + RLOCAL) x COUT1
τREMOTE = (RSENSE + RREMOTE + RPCB_TRACE)
x CREMOTE
The new stability criteria for nonvoltage-positioned
applications using feed forward becomes:
for τLOCAL much greater or much smaller than
τREMOTE, and
when τLOCAL and τREMOTE are approximately equal.
If the voltage-positioning gain in the standard applica-
tion circuit (Figure 1) is set to zero and the feed-forward
compensation circuit shown in Figure 12 is used, stable
operation can still be easily achieved.
In this example, COUT1 = 990µF, RLOCAL = 3.3m,
CREMOTE = 10µF, RREMOTE = 5m, RSENSE = 1m,
and RPCB_TRACE = 2m, and the local time constant is
much greater than the remote time constant.
Therefore:
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and fast-feed-
back loop instability. Double-pulsing occurs due to
noise on the output or because the ESR is so low that
there is not enough voltage ramp in the output-voltage
signal. This fools the error comparator into triggering
a new cycle immediately after the 400ns minimum off-
time period has expired. Double-pulsing is more annoy-
ing than harmful, resulting in nothing worse than
increased output ripple. However, it can indicate the
possible presence of loop instability, which is caused
by insufficient current feedback signal.
Loop instability can result in oscillations at the output
after line or load perturbations that can trip the overvolt-
age protection latch or cause the output voltage to fall
below the tolerance limit. The easiest method for check-
ing stability is to apply a very fast zero-to-max load
transient and carefully observe the output-voltage rip-
ple envelope for overshoot and ringing. It can help to
simultaneously monitor the inductor current with an AC
current probe. Do not allow more than one cycle of
ringing after the initial step-response under/overshoot.
BUCK2 Stability Considerations
The stability criterion for BUCK2 is the same as previous
Quick-PWM controllers like the MAX1714. Stability is
determined by comparing the value of the ESR zero to
the switching frequency. The point of stability is given by
the following expression:
For good phase margin, it is recommended to increase
the equivalent RC time constant by a factor of two. The
standard application circuit (Figure 1) operating at
390kHz with COUT = 330µF and RESR = 10m, easily
meets this requirement.
ff
where f RC
ESR SW
ESR ESR OUT
=××
π
π
1
2
1 990 10 3 3
990 5 10 1
2 300
432 167
mFFm
Fm F kHz
ss
ΩΩ
×+
()
+
×+×
×
µµ
µµ
µµ
.
. .
RR C fand
RR C f
SENSE LOCAL OUT SW
SENSE REMOTE REMOTE SW
+
()
×≥
×
+
()
×≥
×
1
1
2
1
2
RCC R
CR C f
SENSE OUT REMOTE LOCAL
OUT REMOTE REMOTE SW
×+
()
×
1
1
1
2
Figure 12. Output Feed Forward for Nonvoltage-Positioned
Applications
COUT
RSENSE
3.3µF
10
PC BOARD TRACE
RESISTANCE
REMOTE
LOAD
CS1+
CS1-
FBS
GDS
PC BOARD TRACE
RESISTANCE
'GATE [MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
42 ______________________________________________________________________________________
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents
defined by the following equation:
The RMS input currents for BUCK1 and BUCK2 can be
calculated using the above equation. Use the sum
of these two currents as the total RMS current. Note
that this is a very conservative estimation because the
two regulators are never in phase 100% of the time.
The actual RMS current is always lower than the
calculated value.
For most applications, nontantalum chemistries (ceramic
or OSCON) are preferred due to their resilience to
inrush surge currents typical of systems with a switch
or a connector in series with the battery. If the
MAX1816/MAX1994 operate as the second stage of a
two-stage power conversion system, tantalum input
capacitors are acceptable. In either configuration,
choose an input capacitor that exhibits less than +10°C
temperature rise at the RMS input current for optimal
circuit longevity.
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
(>12A) when using high-voltage (>20V) AC adapters.
Low-current applications usually require less attention.
The high-side MOSFET (Q1 in Figure1) must be able to
dissipate the resistive losses plus the switching losses
at both VIN(MIN) and VIN(MAX). Calculate both of these
sums. Ideally, the losses at VIN(MIN) should be roughly
equal to the losses at VIN(MAX), with lower losses in
between. If the losses at VIN(MIN) are significantly high-
er than the losses at VIN(MAX), consider increasing the
size of Q1. Conversely, if the losses at VIN(MAX) are sig-
nificantly higher than the losses at VIN(MIN), consider
reducing the size of Q1. If VIN does not vary over a
wide range, the minimum power dissipation occurs
where the resistive losses equal the switching losses.
Choose a low-side MOSFET (Q2) that has the lowest
possible RDS(ON), comes in a moderate-sized package
(i.e., two or more 8-pin SOs, DPAKs, or D2PAKs), and is
reasonably priced. Ensure that the MAX1816/MAX1994
DL_ gate driver can drive Q2; in other words, check that
the dV/dt caused by Q1 turning on does not pull up the
gate of Q2 due to drain-to-gate capacitance, causing
cross-conduction problems. Switching losses are not an
issue for the low-side MOSFET, since it is a zero-voltage
switched device when used in the buck topology.
MOSFET Power Dissipation
The high-side MOSFET conduction power dissipation
due to on-state channel resistance is:
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the RDS(ON) required to stay within package
power-dissipation limits often constrains how small the
MOSFET can be.
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
CV2fSW switching-loss equation. If the high-side MOSFET
chosen for adequate RDS(ON) at low battery voltages
becomes extraordinarily hot when subjected to VIN(MAX),
reconsider the MOSFET selection.
Calculating the power dissipation in Q1 due to switch-
ing losses is difficult since it must allow for difficult
quantifying factors that influence the turn-on and turn-
off times. These factors include the internal gate resis-
tance, gate charge, threshold voltage, source induct-
ance, and PC board layout characteristics. The follow-
ing switching-loss calculation provides only a very
rough estimate and is no substitute for breadboard
evaluation and thermal measurements:
where CRSS is the reverse transfer capacitance of Q1
and IGATE is the peak gate-drive source/sink current
(1.5A typ for BUCK1, 0.75A typ for BUCK2).
For the low-side MOSFET (Q2), the worst-case power
dissipation always occurs at maximum battery voltage:
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than ILOAD(MAX)
but are not quite high enough to exceed the current limit
and cause the fault latch to trip. To protect against this
possibility, overdesign the circuit to tolerate:
ILOAD =I
LIMIT(HIGH ) + (LIR/2) ILOAD(MAX)
PD Q V
VIR
OUT
IN MAX LOAD DS ON
()
() ()
21 22
=
××
PD Q Switching CV fI
I
RSS IN MAX SW LOAD
GATE
(_ ) ()
1
2
=×××
PD Q Conduction V
VIR
OUT
IN LOAD DS ON
(_ ) ()
121
=× ×
II VVV
V
RMS LOAD OUT IN OUT
IN
=()
[MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________ 43
where ILIMIT(HIGH) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation.
The MOSFETs must have a good-sized heat sink to
handle the overload power dissipation. If short-circuit
protection without overload protection is enough, a
normal ILOAD value can be used for calculating compo-
nent stresses.
Choose a Shottky diode (D1) having a forward voltage
low enough to prevent the Q2 MOSFET body diode
from turning on during the dead time. As a general rule,
a diode having a DC current rating equal to 1/3 of the
load current is sufficient. This diode is optional and can
be removed if efficiency is not critical.
Linear Regulator
Design Procedure
Output Voltage Selection
Adjust the linear regulators output voltage by connect-
ing a resistive voltage-divider from VLIN to AGND with
the center tap connected to LINFB (Figure 1). Select R9
in the range of 10kto 100k. Calculate R8 with the
following equation:
R8 = R9 [(VLIN / 1.00V) - 1]
Pass Transistor Selection
The PNP pass transistor must meet specifications for
current gain (hFE), input capacitance, emitter-collector
saturation voltage, and power dissipation. The
transistors current gain limits the guaranteed maximum
output current to:
where IDRV is the minimum base-drive current, and REB
is the pullup resistor connected between the transis-
tors emitter and base. Furthermore, the transistors cur-
rent gain increases the linear regulators DC loop gain
(see the Linear Regulator Stability Requirements sec-
tion), so excessive gain destabilizes the output.
Therefore, transistors with current gain over 300A/A at
the maximum output current are not recommended.
The transistors input capacitance and input resistance
also create a second pole, which could be low enough
to make the output unstable when heavily loaded.
The transistors saturation voltage at the maximum out-
put current determines the minimum input-to-output
voltage differential that the linear regulator supports.
Alternatively, the packages power dissipation could
limit the usable maximum input-to-output voltage differ-
ential. The maximum power dissipation capability of the
transistors package and mounting must exceed the
actual power dissipation in the device.
The power dissipation equals the maximum load current
times the maximum input-to-output voltage differential:
P = ILOAD(MAX) x(V
LDOIN - VLIN) = ILOAD(MAX) xV
CE
Linear Regulator Stability Requirements
The MAX1816/MAX1994 linear-regulator controller uses
an internal transconductance amplifier to drive an
external pass transistor. The transconductance amplifi-
er, the pass transistor, the emitter-base resistor, and
the output capacitor determine the loop stability. If the
output capacitor and pass transistor are not properly
selected, the linear regulator is unstable.
The transconductance amplifier regulates the output
voltage by controlling the pass transistors base cur-
rent. Since the output voltage is a function of the load
current and load resistance, the total DC loop gain is
approximately:
where VTis 26mV at room temperature, IBIAS is the cur-
rent though the emitter-base resistor (REB), and VREF =
1.0V. This bias resistor is typically 220, providing
approximately 3.2mA of bias current.
The output capacitor and the load resistance create the
dominant pole in the system. However, the pass tran-
sistors input capacitance creates a second pole in the
system. Additionally, the output capacitors ESR gener-
ates a zero. To achieve stable operation, use the follow-
ing equations to verify that the linear regulator is
properly compensated:
1) First, determine the dominant pole set by the linear
regulators output capacitor and the load resistor:
The unity gain crossover of the linear regulator is:
fCROSSOVER =A
V(LDO)fPOLE(CLDO)
2) Next, determine the second pole set by the emitter-
base capacitance (including the transistors input
capacitance), the transistors input resistance, and
the emitter-base pullup resistor:
fCR
I
CV
POLE CLDO
LDO LOAD
LOAD MAX
LDO LDO
() ()
==
1
22ππ
AV
V
Ih
I
V LDO REF
T
BIAS FE
LOAD
() .=
+
155
II
V
Rh
LOAD MAX DRV EB
EB FE MIN() ()
=
[MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
44 ______________________________________________________________________________________
3) A third pole is set by the linear regulators feedback
resistance and the capacitance between LINFB
and GND, including the stray capacitance:
4) If the second and third poles occur well after unity
gain crossover, the linear regulator remains stable:
fPOLE(CEB) > 2fPOLE(CLDO)AV(LDO)
However, if the ESR zero occurs before the unity gain
crossover, cancel the zero with the feedback pole by
changing circuit components such that:
For most applications where ceramic capacitors are
used, the ESR zero always occurs after the crossover.
Output Capacitor Selection
Typically, more output capacitance provides the best
performance, since this also reduces the output voltage
drop immediately after a load transient. Connect at
least a 10µF capacitor between the linear regulators
output and ground, as close to the external pass tran-
sistor as possible. Depending on the selected pass
transistor, larger capacitor values may be required
for stability (see the Linear Regulator Stability
Requirements section). Furthermore, the output capaci-
tors ESR affects stability. Use output capacitors with an
ESR less than 200mto ensure stability and optimum
transient response. Once the minimum capacitor value
for stability is determined, verify that the linear regula-
tors output does not contain excessive noise. Although
adequate for stability, small capacitor values can pro-
vide too much bandwidth, making the linear regulator
sensitive to noise. Larger capacitor values reduce the
bandwidth, thereby reducing the regulators noise sen-
sitivity.
Applications Information
Voltage Positioning
Powering new mobile processors requires new tech-
niques to reduce cost, size, and power dissipation.
Voltage positioning reduces the total number of output
capacitors to meet a given transient response require-
ment. Setting the no-load output voltage slightly higher
allows a larger step down when the output current sud-
denly increases, and regulating at the lower output volt-
age under load allows a larger step up when the output
current suddenly decreases. Allowing a larger step size
means that the output capacitance can be reduced
and the capacitors ESR can be increased.
Adding a series output resistor positions the full-load
output voltage below the actual DAC programmed volt-
age. Connect FB directly to the inductor side of the
voltage-positioning resistor (R1, 1m). The other side
of the voltage-positioning resistor should be connected
directly to the output filter capacitor with a short, wide
PC board trace. With the gain pin floating (GAIN = 2), a
20A full-load current causes a 40mV drop in the output.
This 40mV is a -3.2% droop.
An additional benefit of voltage positioning is reduced
power consumption at high load currents. Because the
output voltage is lower under load, the CPU draws less
current. The result is lower power dissipation in the
CPU, although some extra power is dissipated in R1.
For a nominal 1.25V, 20A output, reducing the output
voltage by 3.2% gives an output voltage of 1.21V and
an output current of 19.4A. Given these values, CPU
power consumption is reduced from 25W to 23.5W. The
additional power consumption of R1 is:
1m(19.4A)2= 0.38W
And the overall power savings is as follows:
25W - (23.5W + 0.38W) = 1.12W
In effect, 1.5W of CPU dissipation is saved, and the
power supply dissipates some of the power savings,
but both the net savings and the transfer of dissipation
away from the hot CPU are beneficial.
High-Current Master-Slave Applications
The MAX1816/MAX1994 can be used in high-current
applications using additional slave regulators. Figure 2
illustrates a 40A master-slave application using this
technique. The MAX1994 is placed in forced PWM
mode to simplify operation with the slave. Refer to the
MAX1980 data sheet for a detailed description of the
master-slave architecture and how to configure correctly
the slave circuit.
Dropout Performance
The output voltage adjustment range for continuous-
conduction operation is restricted by the nonadjustable
500ns (max) minimum off-time one-shot (375ns max at
550kHz and 1000kHz). For best dropout performance,
use the slower (200kHz) on-time settings.
fCR
POLE FB LDO ESR
()
1
2π
fCRR
POLE FB FB
() (||)
=1
289π
fCR R
RI Vh
CRVh
POLE CEB EB EB IN
EB LOAD T FE
EB EB T FE
() (||)
==
+
1
22ππ
[MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________ 45
When working with low-input voltages, the duty-factor limit
must be calculated using worst-case values for on- and
off-times. Manufacturing tolerances and internal propaga-
tion delays introduce an error to the TON K factor. This
error is greater at higher frequencies (Table 3).
Also, keep in mind that transient response performance
of buck regulators operated close to dropout is poor,
and bulk output capacitance must often be added (see
the VSAG equation in the Design Procedure section).
The absolute point of dropout is when the inductor cur-
rent ramps down during the minimum off-time (IDOWN)
as much as it ramps up during the on-time (IUP). The
ratio h = IUP/IDOWN is an indicator of ability to slew
the inductor current higher in response to increased
load, and must always be greater than 1. As h
approaches 1, the absolute minimum dropout point, the
inductor current is less able to increase during each
switching cycle and VSAG greatly increases, unless
additional output capacitance is used.
A reasonable minimum value for h is 1.5, but this can
be adjusted up or down to allow trade-offs between
VSAG, output capacitance, and minimum operating volt-
age. For a given value of h, the minimum operating volt-
age can be calculated as:
where VDROP1 and VDROP2 are the parasitic voltage
drops in the discharge and charge paths, respectively
(see the On-Time One-Shot (TON) section), TOFF(MIN)
is from the Electrical Characteristics table, and K is
taken from Table 3. The absolute minimum input volt-
age is calculated with h = 1.
If the calculated VIN(MIN) is greater than the required
minimum input voltage, then operating frequency must
be reduced or output capacitance added to obtain
an acceptable VSAG. If operation near dropout is
anticipated, calculate VSAG to be sure of adequate
transient response.
Dropout Design Example
VOUT = 1.2V
fSW = 300kHz
K = 3.3µs, worst-case K = 2.97µs
TOFF(MIN) = 500ns
VDROP1 = VDROP2 = 100mV
h = 1.5
Calculate again with h = 1 gives the absolute limit of
dropout:
Since 1.56V is less than the lower limit of the input volt-
age range (2V), the practical minimum input voltage
with reasonable output capacitance would be 2V.
One-Stage (Battery Input) vs.
Two-Stage (5V Input) Conversion
The MAX1816/MAX1994 can be used with a direct bat-
tery connection (one stage) or can obtain power from a
regulated 5V supply (two stage). Each approach has
advantages, and careful consideration should go into
the selection of the final design.
The one-stage approach offers smaller total inductor
size and fewer capacitors overall due to the reduced
demands on the 5V supply. The transient response of
the single stage is better due to the ability to ramp up
the inductor current faster. The total efficiency of a sin-
gle stage is better than the two-stage approach.
The two-stage approach allows flexible placement due
to smaller circuit size and reduced local power dissipa-
tion. The power supply can be placed closer to the
CPU for better regulation and lower I2R losses from PC
board traces. Although the two-stage design has worse
transient response than the single stage, this can be
offset by the use of a voltage-positioned converter.
Ceramic Output Capacitor Applications
Ceramic capacitors have advantages and disadvan-
tages. They have ultra-low ESR and are noncom-
bustible, relatively small, and nonpolarized. They are
also expensive and brittle, and their ultra-low ESR char-
acteristic can result in excessively high ESR zero fre-
quencies (affecting stability in nonvoltage-positioned
circuits). In addition, their relatively low capacitance
value can cause output overshoot when going abruptly
from full-load to no-load conditions, unless the inductor
value can be made small (high switching frequency), or
there are some bulk tantalum or electrolytic capacitors
in parallel to absorb the stored energy in the inductor.
In some cases, there may be no room for electrolytic
capacitors, creating a need for a DC-DC design that
uses nothing but ceramic capacitors.
VVV
s
s
VV V
IN MIN()
(. . )
.
.
...=+
µ×
µ
+=
12 01
105 1
297
01 01 156
VVV
s
s
VV V
IN MIN()
(. . )
..
.
...=+
µ×
µ
+=
12 01
105 15
297
01 01 174
VVV
Th
K
VV
IN MIN OUT DROP
OFF MIN
DROP DROP()
()
()
=+
×
+−
121
1
[MAXI/III
MAX1816/MAX1994
The MAX1816/MAX1994 can take full advantage of the
small size and low ESR of ceramic output capacitors in
a voltage-positioned circuit. The addition of the posi-
tioning resistor increases the ripple at FB, lowering the
effective ESR zero frequency of the ceramic output
capacitor.
Output overshoot (VSOAR) determines the minimum
output capacitance requirement (see the Output
Capacitor Selection section). Often the switching fre-
quency is increased to 550kHz or 1000kHz, and the
inductor value is reduced to minimize the energy trans-
ferred from inductor to capacitor during load-step
recovery. The efficiency penalty for operating at
550kHz is about 2% to 3% and about 5% at 1000kHz
when compared to the 300kHz voltage-positioned cir-
cuit, primarily due to the high-side MOSFET switching
losses.
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 13). Refer to the MAX1816/MAX1994 EV kit data
sheet for a specific layout example.
If possible, mount all of the power components on the
top side of the board with their ground terminals flush
against one another. Follow these guidelines for good
PC board layout:
1) Isolate the power components on the top side from
the sensitive analog components on the bottom
side with a ground shield. Use a separate PGND
plane under the BUCK1 and BUCK2 sides (called
PGND1 and PGND2). Avoid the introduction of AC
currents into the PGND1 and PGND2 ground
planes.
2) Use a star ground connection on the power plane
to minimize the crosstalk between BUCK1 and
BUCK2.
3) Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation.
4) Connect all analog grounds to a separate solid
copper plane, which connects to the AGND pin of
the MAX1816/MAX1994. This includes the VCC
bypass capacitor, REF bypass capacitor, compen-
sation components, the TIME resistor, as well as
any other resistive dividers.
5) Tie AGND and PGND together close to the IC. Do
not connect them together anywhere else. Carefully
follow the grounding instructions in the Layout
Procedure.
6) In high-current master-slave applications, the mas-
ter controller should have a separate analog
ground. Return the appropriate noise-sensitive
components to this plane. Since the reference in
the master is sometimes connected to the slave, it
may be necessary to couple the analog ground in
the master to the analog ground in the slave to pre-
vent ground offsets. A low value (10) resistor is
sufficient to link the two grounds.
7) Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PC boards (2oz vs. 1oz) can enhance full
load efficiency by 1% or more. Correctly routing PC
board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single milliohm of excess trace resistance
causes a measurable efficiency penalty.
8) Keep the high-current gate-driver traces (DL_, DH_,
LX_, and BST_) short and wide to minimize trace
resistance and inductance. This is essential for
high-power MOSFETs that require low-impedance
gate drivers to avoid shoot-through currents.
9) CS1+, CS1-, CS2, and AGND connections for cur-
rent limiting must be made using Kelvin-sense con-
nections to guarantee the current-limit accuracy.
Kelvin connections to LX2 and AGND must also be
made if the synchronous rectifier RDS(ON) of
BUCK2 is used for current limiting. With 8-pin SO
MOSFETs, this is best done by routing power to the
MOSFETs from the outside using the top copper
layer, while connecting GND and LX inside (under-
neath) the 8-pin SO package.
10) When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
11) Route high-speed switching nodes away from sen-
sitive analog areas (CC, REF, ILIM_). Make all pin-
strap control input connections (SKP_/SDN, ILIM_,
etc.) to analog ground or VCC rather than power
ground or VDD.
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
46 ______________________________________________________________________________________
[MAXI/III
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________ 47
Layout Procedure
1) Place the power components first, with ground ter-
minals adjacent (low-side MOSFET sources, CIN_,
COUT_, D1/D2 anodes). If possible, make all these
connections on the top layer with wide, copper-
filled areas.
2) Mount the controller IC adjacent to the low-side MOS-
FET, preferably on the backside in order to keep LX_,
PGND_, and the DL_ drive lines short and wide. The
DL_ gate traces must be short and wide, measuring
10 to 20 squares (50 mils to 100 mils wide if the
MOSFET is 1in from the controller IC).
3) Group the gate-drive components (BST_ diodes
and capacitors, VDD bypass capacitor) together
near the controller IC.
4) Make the MAX1816/MAX1994 controllers ground
connections as shown in Figure 13. This diagram
can be viewed as having three separate ground
planes: input/output ground, where all the high-
power components go; the power ground plane,
where the PGND pin and VDD bypass capacitors
go; and an analog ground plane where sensitive
analog components go. The analog ground plane
and power ground plane must meet only at a single
point close to the IC. These two planes are then
connected to the high-power output ground with a
short connection from PGND to the source of the
low-side MOSFET (the middle of the star ground).
This point must also be very close to the output
capacitor ground terminal.
5) Connect the output power planes (VCORE and sys-
tem ground planes) directly to the output filter
capacitor positive and negative terminals with multi-
ple vias. Place the entire DC-DC converter circuit
as close to the CPU as is practical.
Chip Information
TRANSISTOR COUNT: 13,313
Figure 13. Power-Stage PC Board Layout Example
POWER GROUND
POWER GROUND
INPUT (V+)
BOTTOM LAYER
TOP LAYER
L1
L2
COUT1
COUT1
COUT1
COUT1
COUT2 COUT2
CIN CIN CIN CIN CIN CIN
VOUT2
VOUT1
POWER GROUND
VIA TO POWER GROUND
ANALOG
GROUND
MAX1816
MAX1994
LX1 LX2
LX1 LX2
VDD CAP
VCC CAP
REF CAP
amen A A —g— 4r m,\ I— — Kim“ ‘I’ '— m._.....A w l I uuuu uuuu “5'“ ; . -—'2- . C; l 3 j c; j c j c | E: + 7 [II 7 + , . c ,/ 3‘ E 4 :1 E | _ \9; . = I T' x |_ I mnnn nnnnl‘j —r_ .L _- W mm A sum: PM ME — EH— EI_J I imam W {Irswlkwu IH H _L I—L-mw/Pm Wm ll/l A X I [VI \ H7 [VIAXIIVI
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
48 ______________________________________________________________________________________
32, 44, 48L QFN .EPS
PROPRIETARY INFORMATION
APPROVAL
TITLE:
DOCUMENT CONTROL NO.
21-0144
PACKAGE OUTLINE
32, 44, 48L QFN THIN, 7x7x0.8 mm
1
A
REV.
2
e
L
e
L
A1 A
A2
E/2
E
D/2
D
DETAIL A
D2/2
D2
b
L
k
E2/2
E2
(NE-1) X e
(ND-1) X e
e
C
L
C
L
C
L
C
L
k
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
cumum. m5. usmpuwm 5.2 a 19"“ «am m ms MW...“ 225?: pm asz «Lm «va7 «Lm mm _ L55 ”a as us an m _ swam Mm. m. m. mm. mm. MAX. MIN. mm. m m NOM. mm mm _ 1.55 m ”5 .55 m, ”5 mm A n.1n 5.75 m run .115 m n.7n 0.75 m n.7u m m “5714-5551557.“ an 420 m m 0.30 “a . M :1 nm mas I: am m (.1 Hz 5.55 n am 5.55 mm . 555 5.60 5.75 m m mwmu A; m nzr. w as; 020513. on REF. 5 ms am 0.35 m m 0.39 m n25 0.3:: m m 0.30 a m m m m 7.00 m m 7.0a m nu mu 1.“: 5 on m mu om 71.757 7.1!: m mu m 5.» ma 7.1a . 0.55550 0.50550 mm amuse. kozs--ozs--n25--a.zs.. L MS 5.55 p.55 0A5 [5.55 0.95 m m m m us us u a: u a u m u 12 m u: n a 1: NOTES: mumsmmo a: romcm comm yo 5»: Vitsu-WN. m mumslws ARE w mmumns. mus ARK m mans. u \s m: mm. Nuuazn or mwws. m: minim p1 mama mu mama museums cowamoN 5m coniu m JESD 954 svv—mz. arms or mmm n mamas»: m: ovnom. aur mm a: LOCATED mm m: zen: \chArED. m: mlm n IDENnFIER m a: man A new m2 mm) mmRE, DWENSIUN n wpuzs m mmwzm mwnw. AND \s MEASURED 35mm 0.25 mm AND 0.30 mm mm mm». TIP. ND mu NE REFEW m m: NUMBER ur mmlrws on men a mu 5 SIDE nzspzcwm. r» a» M»: DEPoPuumuN .5 5555.555 m . mumlm 5.55m. ‘ oomrwvrv mm m .55 W55.) 5m 5m 5N5 .5 m .5 m: mm. [VI A ,( I [VI DRAWING CDNFGRMS m 4am: anzu REVIS‘OM c. .3!" wmvwz sum. Nur :xczzn mu mm. \ \l/ MAXIM
MAX1816/MAX1994
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 49
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
PROPRIETARY INFORMATION
DOCUMENT CONTROL NO.APPROVAL
TITLE:
A
REV.
2
2
EXPOSED PAD VARIATIONS
21-0144
PACKAGE OUTLINE
32, 44, 48L QFN THIN, 7x7x0.8 mm
COMMON DIMENSIONS
** NOTE: T4877-1 IS A CUSTOM 48L PKG. WITH 4 LEADS DEPOPULATED.
TOTAL NUMBER OF LEADS ARE 44.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)

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