653 Series Datasheet by CTS-Frequency Controls

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©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
DOC# 008-0367-0 Rev. E Page 1 of 10
Model 653
Very Low Jitter LVPECL or LVDS Clock
Features
Ceramic Surface Mount Package
Very Low Phase Jitter Performance, 500fs Maximum
Fundamental or 3rd Overtone Crystal Design
Frequency Range 10 320MHz *
+2.5V or +3.3V Operation [+1.8V LVDS only]
Output Enable Standard
Tape and Reel Packaging, EIA-418
Applications
SerDes
Storage Area Networking
Broadband Access
SONET/SDH/DWDM
PON
Ethernet/GbE/SyncE
Fiber Channel
Test and Measurement
Description
CTS Model 653 is a low cost, high performance clock oscillator supporting differential LVPECL or LVDS outputs.
Employing the latest IC technology, M653 has excellent stability and very low jitter/phase noise performance.
Ordering Information
Model
653
Code Code Code
P 6 M
L 5 2
E 4 3
V 3
2
Code Code Code
A T
C
I
G
Notes:
1]
2]
3]
4]
This product is specified for use only in standard commercial applications. Supplier disclaims all express and implied warranties and liability in connection with any use of this
product in any non-commercial applications or in any application that may expose the product to conditions that are outside of the tolerances provided in its specification.
I
3
T
Output
Type
Frequency Code
[MHz]
Frequency
Stability
Temperature
Range
+1.8Vdc
4
Contact your local CTS Representative or CTS Customer Service for availability.
-40°C to +85°C
Temp. Range
Not all performance combinations and frequencies may be available.
LVPECL - Pin 2 Enable
±30ppm
LVDS - Pin 2 Enable
Output
Stability
Voltage
LVPECL - Pin 1 Enable
±20ppm
2
Supply
Voltage
Packaging
P
XXX or XXXX
3
Packing
Product Frequency Code
1
-10°C to +60°C
1k pcs./reel
±50ppm
Frequency
+3.3Vdc
-20°C to +70°C
LVDS - Pin 1 Enable
±25ppm
+2.5Vdc
-40°C to +105°C
3
±100ppm
Part Dimensions:
5.0 × 3.2 × 1.2mm • 62.00mg
Standard Frequencies
- 25.00MHz - 125.00MHz - 187.50MHz
- 50.00MHz - 150.00MHz - 200.00MHz
- 74.1758MHz - 155.52MHz - 212.50MHz
- 74.25MHz - 156.25MHz - 250.00MHz
- 100.00MHz - 161.1328MHz - 312.50MHz
* See Page 9 for additional developed frequencies.
Check with factory for availability of frequencies not listed.
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©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 653
Very Low Jitter LVPECL or LVDS Clock
DOC# 008-0367-0 Rev. E Page 2 of 10
Electrical Specifications
Operating Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
Maximum Supply Voltage
V
CC
--0.5 -5.0 V
1.710 1.8 1.890
2.375 2.5 2.625
3.135 3.3 3.465
Supply Current
LVPECL -55 88
LVDS -45 66
LVDS V
CC
= +1.8 @ Maximum Load - 7 20
-20
+70
-40
+85
-40
+105
Storage Temperature
T
STG
--40 -+125 °C
Frequency Stability
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
Frequency Range
LVPECL
LVDS
LVDS V
CC
= +1.8V
Frequency Stability
[Note 2]
Δf/f
O
-±ppm
Aging Δf/f
25
First Year @ +25°C, nominal V
CC
-3 -3ppm
Output Parameters
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
Output Type - - -
Output Load
R
L
Terminated to V
CC
- 2.0V -50 -Ohms
V
OH
V
CC
- 1.025 - V
CC
- 0.880
V
OL
V
CC
- 1.810 - V
CC
- 1.620
V
OH
V
CC
- 1.085 - V
CC
- 0.880
V
OL
V
CC
- 1.830 - V
CC
- 1.555
Output Duty Cycle SYM @ V
CC
- 1.3V 45 -55 %
Rise and Fall Time T
R
, T
F
@ 20%/80% Levels, R
L
= 50 Ohms -0.3 0.7 ns
Output Type - - -
Output Load
R
L
Between Outputs -100 -Ohms
V
OH
-1.43 1.60
V
OL
0.90 1.10 -
Output Duty Cycle SYM @ 1.25V 45 -55 %
Differential Output Voltage V
OD
R
L
= 100 Ohms 247 330 454 mV
Offset Voltage V
OS
LVDS Load 1.125 1.25 1.375 V
Rise and Fall Time T
R
, T
F
@ 20%/80% Levels, R
L
= 100 Ohms -0.4 0.7 ns
V
CC
= +2.5V or +3.3V
LVDS
Output Voltage Levels
LVDS Load
V
Output Voltage Levels
PECL Load, -20°C to +70°C
V
PECL Load, -40°C to +85°C
V
-
+25
°C
LVPECL
10 - 320
MHz
20 - 220
20, 25, 30, 50 or 100
2.] Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 1st year aging.
±5%
V
I
CC
V
CC
= +2.5V or +3.3V @ Maximum Load
10 - 320
Supply Voltage
[Note 1]
1.] LVDS output only for +1.8V option.
mA
Operating Temperature
V
CC
f
O
T
A
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©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 653
Very Low Jitter LVPECL or LVDS Clock
DOC# 008-0367-0 Rev. E Page 3 of 10
Electrical Specifications
Enable Truth Table
Pin 1 or Pin 2
Pin 4 & Pin 5
Logic1
Output
Open
Output
Logic0
High Imp.
Test Circuit
LVPECL LVDS
Output Waveform
LVPECL or LVDS
Output Parameters
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
Start Up Time TSApplication of VCC - 2 5 ms
Enable Function [Standby]
Enable Input Voltage
VIH Pin 1 or 2 Logic '1', Output Enabled 0.7VCC - - V
Disable Input Voltage VIL Pin 1 or 2 Logic '0', Output Disabled - - 0.3VCC V
Disable Time TPLZ Pin 1 or 2 Logic '0', Output Disabled - - 200 ns
Enable Time TPLZ Pin 1 or 2 Logic '1', Output Enabled - - 2 ms
40MHz - 320MHz, Bandwidth 12kHz to 20MHz -300 500 fs
10MHz - 39.999MHz, Bandwidth 12kHz to 5MHz -500 <1 ps
Phase Jitter, RMS
tjrms
(maxi mm W: u§7smu aa
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 653
Very Low Jitter LVPECL or LVDS Clock
DOC# 008-0367-0 Rev. E Page 4 of 10
Electrical Specifications
Performance Data
Phase Noise [typical]
25MHz, LVPECL, VCC = +3.3V, TA = +25°C
100MHz, LVPECL, VCC = +3.3V, TA = +25°C
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©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 653
Very Low Jitter LVPECL or LVDS Clock
DOC# 008-0367-0 Rev. E Page 5 of 10
Electrical Specifications
Performance Data
Phase Noise [typical]
312.50MHz, LVPECL, VCC = +3.3V, TA = +25°C
155.52MHz, LVDS, VCC = +3.3V, TA = +25°C
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©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 653
Very Low Jitter LVPECL or LVDS Clock
DOC# 008-0367-0 Rev. E Page 6 of 10
Electrical Specifications
Performance Data
Phase Noise [typical]
156.25MHz, LVDS, VCC = +1.8V, TA = +25°C
Phase Noise Tabulated
Typical, VCC = +3.3V, TA = +25°C
PARAMETER SYMBOL CONDITIONS TYP UNIT PARAMETER SYMBOL CONDITIONS TYP UNIT
LVPECL @ 25.00MHz LVPECL @ 100.00MHz
Phase Noise Single Side Band Phase Noise Single Side Band
@ 10Hz -82.16 @ 10Hz -65.65
@ 100Hz -113.77 @ 100Hz -100.19
@ 1kHz -139.77 @ 1kHz -131.02
@ 10kHz -156.60 @ 10kHz -145.49
@ 100kHz -161.45 @ 100kHz -150.36
@ 1MHz -161.31 @ 1MHz -151.37
@ 5MHz -159.28 @ 5MHz -152.11
Phase Jitter, RMS tjrms Integration Bandwidth 12kHz - 5MHz 192.78 fs Phase Jitter, RMS tjrms Integration Bandwidth 12kHz - 20MHz 132.20 fs
PARAMETER SYMBOL CONDITIONS TYP UNIT
LVPECL @ 312.20MHz
Phase Noise Single Side Band
@ 10Hz -65.93
@ 100Hz -95.92
@ 1kHz -128.25
@ 10kHz -130.51
@ 100kHz -142.82
@ 1MHz -142.84
@ 10MHz -143.80
Phase Jitter, RMS tjrms Integration Bandwidth 12kHz - 20MHz 208.52 fs
-
dBc/Hz
-
dBc/Hz
-
dBc/Hz
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©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 653
Very Low Jitter LVPECL or LVDS Clock
DOC# 008-0367-0 Rev. E Page 7 of 10
Electrical Specifications
Performance Data
Phase Noise Tabulated
Typical, VCC = +3.3V, TA = +25°C Typical, VCC = +1.8V, TA = +25°C
PARAMETER SYMBOL CONDITIONS TYP UNIT PARAMETER SYMBOL CONDITIONS TYP UNIT
LVDS @ 155.52MHz LVDS @ 156.25MHz
Phase Noise Single Side Band Phase Noise Single Side Band
@ 10Hz -69.89 @ 10Hz -74.81
@ 100Hz -103.42 @ 100Hz -102.03
@ 1kHz -130.99 @ 1kHz -126.12
@ 10kHz -142.69 @ 10kHz -141.97
@ 100kHz -144.46 @ 100kHz -148.38
@ 1MHz -144.49 @ 1MHz -154.15
@ 20MHz -145.13 @ 20MHz -156.93
Phase Jitter, RMS tjrms Integration Bandwidth 12kHz - 20MHz 383.70 fs Phase Jitter, RMS tjrms Integration Bandwidth 12kHz - 20MHz 102.31 fs
-
dBc/Hz
-
dBc/Hz
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©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 653
Very Low Jitter LVPECL or LVDS Clock
DOC# 008-0367-0 Rev. E Page 8 of 10
Mechanical Specifications
Package Drawing Marking Information
Recommended Pad Layout Notes
Pin Assignments
Pin
Symbol
Function
1
EOH or N.C.
Enable [std] or No Connect
2
N.C. or EOH
No Connect or Enable [opt]
3
GND
Circuit & Package Ground
4
Output
RF Output
5
Output
Complimentary RF Output
6
VCC
Supply Voltage
Table I - Date Code
2001 2005 2009 2013 2017 A B C D E F G H J K L M
2002 2006 2010 2014 2018 N P Q R S T U V W X Y Z
2003 2007 2011 2015 2019 a b c d e f g h j k l m
2004 2008 2012 2016 2020 n p q r s t u v w x y z
NOV
DEC
YEAR
MAY
JUN
JUL
AUG
SEP
OCT
MONTH
JAN
FEB
MAR
APR
1. ** - Manufacturing Site Code.
2. D Date Code. See Table I for codes.
3. O Output Type; P or E = LVPECL, L or V = LVDS.
3. ST Frequency Stability/Temperature Code.
[Refer to Ordering Information]
4. V Voltage Code; 3 = 3.3V, 2 = 2.5V, M = 1.8V.
5. xxxx Frequency Code.
3-digits, frequencies below 100MHz
4-digits, frequencies 100MHz or greater
[See document 016-1454-0, Frequency Code Tables.]
1. JEDEC termination code (e4). Barrier-plating is
nickel [Ni] with gold [Au] flash plate.
2. Reflow conditions per JEDEC J-STD-020; +260°C
maximum, 20 seconds.
3. MSL = 1.
CTS**D
653OSTV
● xxxx
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©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 653
Very Low Jitter LVPECL or LVDS Clock
DOC# 008-0367-0 Rev. E Page 9 of 10
Packaging - Tape and Reel
Tape Drawing
Reel Drawing
Notes
1. Device quantity is 3k pieces maximum per 180mm reel.
2. Complete CTS part number, frequency value and date code information must appear on reel and carton labels.
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©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 653
Very Low Jitter LVPECL or LVDS Clock
DOC# 008-0367-0 Rev. E Page 10 of 10
Addendum
Additional Developed Frequencies MHz
Frequency Codes for Cover Page Table MHz
FREQUENCY
FREQUENCY
CODE
FREQUENCY
FREQUENCY
CODE
FREQUENCY
FREQUENCY
CODE
FREQUENCY
FREQUENCY
CODE
10.000000 100 153.600000 1536
19.440000 194 156.253906 156A
27.000000 270 167.372800 167A
40.000000 400 173.370800 1733
44.736000 447 175.000000 1750
80.000000 800 178.500000 1785
120.000000 1200 180.000000 1800
133.000000 1330 184.320000 1843
148.351600 148A 225.000000 2250
148.500000 1485
FREQUENCY
FREQUENCY
CODE
FREQUENCY
FREQUENCY
CODE
FREQUENCY
FREQUENCY
CODE
FREQUENCY
FREQUENCY
CODE
25.000000 250 100.000000 1000 156.250000 1562 212.500000 2125
50.000000 500 125.000000 1250 161.132800 1611 250.000000 2500
74.175800 74A 150.000000 1500 187.500000 1875 312.500000 3125
74.250000 742 155.520000 1555 200.000000 2000

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