LT3045-1 Datasheet by Analog Devices Inc.

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LT3045-1
1
30451fa
For more information www.linear.com/LT3045-1
TYPICAL APPLICATION
FEATURES DESCRIPTION
20V, 500mA, Ultralow Noise,
Ultrahigh PSRR Linear Regulator with VIOC Control
The LT
®
3045-1 is a high performance low dropout linear
regulator featuring LTCs ultralow noise and ultrahigh PSRR
architecture for powering noise sensitive applications. De-
signed as a precision current reference followed by a high
performance voltage buffer, the LT3045-1 can be easily
paralleled to further reduce noise, increase output current
and spread heat on the PCB. In addition to the LT3045
feature set, the LT3045-1 incorporates a VIOC tracking
function to control an upstream switching converter to
maintain a constant voltage across the LT3045-1 and
hence minimize power dissipation.
The device supplies 500mA at a typical 260mV dropout
voltage. Operating quiescent current is nominally 2.3mA
and drops to <<1µA in shutdown. The LT3045-1’s wide
output voltage range (0V to 15V) while maintaining unity-
gain operation provides virtually constant output noise,
PSRR, bandwidth and load regulation, independent of the
programmed output voltage. Additionally, the regulator
features programmable current limit, fast start-up capa-
bility and programmable power good to indicate output
voltage regulation.
The LT3045-1 is stable with a minimum 10µF ceramic
output capacitor. Built-in protection includes reverse-
battery protection, reverse-current protection, internal
current limit with foldback and thermal limit with hysteresis.
The LT3045-1 is available in thermally enhanced 12-Lead
MSOP and 3mm × 3mm DFN packages.
Noise Spectral Density
APPLICATIONS
n Ultralow RMS Noise: 0.8µVRMS (10Hz to 100kHz)
n Ultralow Spot Noise: 2nV/√Hz at 10kHz
n Ultrahigh PSRR: 76dB at 1MHz
n Output Current: 500mA
n Wide Input Voltage Range: 1.8V to 20V
n Single Capacitor Improves Noise and PSRR
n 100µA SET Pin Current: ±1% Initial Accuracy
n VIOC Pin Controls Upstream Regulator to Minimize
Power Dissipation
n Single Resistor Programs Output Voltage
n Programmable Current Limit
n Low Dropout Voltage: 260mV
n Output Voltage Range: 0V to 15V
n Programmable Power Good
n Fast Start-Up Capability
n Precision Enable/UVLO
n Parallelable for Lower Noise and Higher Current
n Internal Current Limit with Foldback
n Minimum Output Capacitor: 10µF Ceramic
n Reverse-Battery and Reverse-Current Protection
n 12-Lead MSOP and 3mm × 3mm DFN Packages
n RF Power Supplies: PLLs, VCOs, Mixers, LNAs, PAs
n Very Low Noise Instrumentation
n High Speed/High Precision Data Converters
n Medical Applications: Imaging, Diagnostics
n Post-Regulator for Switching Supplies L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Analog
Devices, Inc. Patents pending. All other trademarks are the property of their respective owners.
LDO
IN
= 4.3V
LDO
OUT
= 3.3V
I
LOAD
= 500mA
LDO
OUT
LDO
Noise Floor
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
0.01
0.1
1
10
100
1000
NOISE (µV/√
Hz
)
30451 TA01b
+
100µA
IN
EN/UV
PGFB
VIOC
GND
OUT
LT3045-1
ILIM PG 10µF
47µF
VIN
12V
4.7µF
VOUT: VARIABLE
IOUT(MAX)
: 500mA
30451 TA01a
249Ω
SET
OUTS
LT8608
BST
SW
PG
FB
IN
EN/UV
TR/SS
MODE
RT
INTVCC 7.68k
40.2k
2.2µH
2.21k
GND
10nF
1µF
0.22µF
f
SW = 1MHz
L: XFL4020-222MEC
VLDOIN – VLDOUT = 1V
LT3045— 1 TOP vwEw TOP VIEW
LT3045-1
2
30451fa
For more information www.linear.com/LT3045-1
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
IN Pin Voltage .........................................................±22V
VIOC Pin Voltage (Note 10) ..............................0.3V, 4V
EN/UV Pin Voltage ..................................................±22V
IN-to-EN/UV Differential..........................................±22V
PG Pin Voltage (Note 10) ...............................0.3V, 22V
ILIM Pin Voltage (Note 10) ............................... 0.3V, 1V
PGFB Pin Voltage (Note 10) ...........................0.3V, 22V
SET Pin Voltage (Note 10) .............................. 0.3V, 16V
SET Pin Current (Note 7) .................................... ±20mA
OUTS Pin Voltage (Note 10) ........................... 0.3V, 16V
OUTS Pin Current (Note 7) ................................. ±20mA
(Note 1)
TOP VIEW
DD PACKAGE
12-LEAD (3mm
×
3mm) PLASTIC DFN
12
11
8
9
10
4
5
3
2
1OUT
OUT
OUTS
GND
SET
PGFB
IN
IN
VIOC
EN/UV
PG
ILIM 67
13
GND
TJMAX = 150°C, θJA = 34°C/W, θJC = 5.5°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
1
2
3
4
5
6
IN
IN
VIOC
EN/UV
PG
ILIM
12
11
10
9
8
7
OUT
OUT
OUTS
GND
SET
PGFB
TOP VIEW
MSE PACKAGE
12-LEAD PLASTIC MSOP
13
GND
TJMAX = 150°C, θJA = 33°C/W, θJC = 8°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3045EDD-1#PBF LT3045EDD-1#TRPBF LHBR 12-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LT3045IDD-1#PBF LT3045IDD-1#TRPBF LHBR 12-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LT3045EMSE-1#PBF LT3045EMSE-1#TRPBF 30451 12-Lead Plastic MSOP –40°C to 125°C
LT3045IMSE-1#PBF LT3045IMSE-1#TRPBF 30451 12-Lead Plastic MSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
LT3045 Options
PART NUMBER VIOC FUNCTION
LT3045-1 Yes
LT3045 No
OUT Pin Voltage (Note 10) .............................0.3V, 16V
OUT-to-OUTS Differential (Note 14) ....................... ±1.2V
IN-to-OUT Differential .............................................±22V
IN-to-OUTS Differential ........................................... ±22V
Output Short-Circuit Duration .......................... Indefinite
Operating Junction Temperature Range (Note 9)
E-Grade, I-Grade ............................... 40°C to 125°C
Storage Temperature Range .................. 65°C to 150°C
Lead Temperature (Soldering, 10 Sec)
MSE Package ................................................... 300°C
http://www.linear.com/product/LT3045-1#orderinfo
LT3045— 1
LT3045-1
3
30451fa
For more information www.linear.com/LT3045-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Voltage Range l2 20 V
Minimum IN Pin Voltage
(Note 2)
ILOAD = 500mA, VIN UVLO Rising
VIN UVLO Hysteresis
l1.78
75
2 V
mV
Output Voltage Range VIN > VOUT l0 15 V
SET Pin Current (ISET) VIN = 2V, ILOAD = 1mA, VOUT = 1.3V
2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 500mA (Note 3)
l
99
98
100
100
101
102
µA
µA
Fast Start-Up Set Pin
Current
VPGFB = 289mV, VIN = 2.8V, VSET = 1.3V 2 mA
Output Offset Voltage
VOS (VOUT – VSET)
(Note 4)
VIN = 2V, ILOAD = 1mA, VOUT = 1.3V
2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 500mA (Note 3)
l
–1
–2
1
2
mV
mV
Line Regulation: ∆ISET
Line Regulation: ∆VOS
VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V
VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V (Note 4)
l
l
0.5
0.5
±2
±3
nA/V
µV/V
Load Regulation: ∆ISET
Load Regulation: ∆VOS
ILOAD = 1mA to 500mA, VIN = 2V, VOUT = 1.3V
ILOAD = 1mA to 500mA, VIN = 2V, VOUT = 1.3V (Note 4)
l
3
0.1
0.5
nA
mV
Change in ISET with VSET
Change in VOS with VSET
Change in ISET with VSET
Change in VOS with VSET
VSET = 1.3V to 15V, VIN = 20V, ILOAD = 1mA
VSET = 1.3V to 15V, VIN = 20V, ILOAD = 1mA (Note 4)
VSET = 0V to 1.3V, VIN = 20V, ILOAD = 1mA
VSET = 0V to 1.3V, VIN = 20V, ILOAD = 1mA (Note 4)
l
l
l
l
30
0.03
150
0.3
400
0.6
600
2
nA
mV
nA
mV
Dropout Voltage
(Note 5)
ILOAD = 1mA, 50mA
l
220 275
330
mV
mV
ILOAD = 300mA
l
220 280
350
mV
mV
ILOAD = 500mA
l
260 350
450
mV
mV
GND Pin Current
VIN = VOUT(NOMINAL)
(Note 6)
ILOAD = 10µA
ILOAD = 1mA
ILOAD = 50mA
ILOAD = 100mA
ILOAD = 500mA
l
l
l
l
2.2
2.4
3.5
4.3
15
4
5.5
7
25
mA
mA
mA
mA
mA
Output Noise Spectral
Density (Notes 4, 8)
ILOAD = 500mA, Frequency = 10Hz, COUT = 10µF, CSET = 0.47µF, VOUT = 3.3V
ILOAD = 500mA, Frequency = 10Hz, COUT = 10µF, CSET = 4.7µF, 1.3V ≤ VOUT ≤ 15V
ILOAD = 500mA, Frequency = 10kHz, COUT = 10µF, CSET = 0.47µF, 1.3V ≤ VOUT ≤ 15V
ILOAD = 500mA, Frequency = 10kHz, COUT = 10µF, CSET = 0.47µF, 0V ≤ VOUT < 1.3V
500
70
2
5
nV/Hz
nV/Hz
nV/Hz
nV/Hz
Output RMS Noise
(Notes 4, 8)
ILOAD = 500mA, BW = 10Hz to 100kHz, COUT = 10µF, CSET = 0.47µF, VOUT = 3.3V
ILOAD = 500mA, BW = 10Hz to 100kHz, COUT = 10µF, CSET = 4.7µF, 1.3V ≤ VOUT ≤ 15V
ILOAD = 500mA, BW = 10Hz to 100kHz, COUT = 10µF, CSET = 4.7µF, 0V ≤ VOUT < 1.3V
2.5
0.8
1.8
µVRMS
µVRMS
µVRMS
Reference Current RMS
Output Noise (Notes 4, 8)
BW = 10Hz to 100kHz 6 nARMS
Ripple Rejection
1.3V ≤ VOUT ≤ 15V
VIN – VOUT = 2V (Avg)
(Notes 4, 8)
VRIPPLE = 500mVP-P, fRIPPLE = 120Hz, ILOAD = 500mA, COUT = 10µF, CSET = 4.7µF
VRIPPLE = 150mVP-P, fRIPPLE = 10kHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
VRIPPLE = 150mVP-P, fRIPPLE = 100kHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
VRIPPLE = 150mVP-P, fRIPPLE = 1MHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
VRIPPLE = 80mVP-P, fRIPPLE = 10MHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
117
90
77
76
53
dB
dB
dB
dB
dB
Ripple Rejection
0V ≤ VOUT < 1.3V
VIN – VOUT = 2V (Avg)
(Notes 4, 8)
VRIPPLE = 500mVP-P, fRIPPLE = 120Hz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
VRIPPLE = 50mVP-P, fRIPPLE = 10kHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
VRIPPLE = 50mVP-P, fRIPPLE = 100kHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
VRIPPLE = 50mVP-P, fRIPPLE = 1MHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
VRIPPLE = 50mVP-P, fRIPPLE = 10MHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
104
85
72
64
54
dB
dB
dB
dB
dB
EN/UV Pin Threshold EN/UV Trip Point Rising (Turn-On), VIN = 2V l1.18 1.24 1.32 V
EN/UV Pin Hysteresis EN/UV Trip Point Hysteresis, VIN = 2V 130 mV
LT3045— 1
LT3045-1
4
30451fa
For more information www.linear.com/LT3045-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER CONDITIONS MIN TYP MAX UNITS
EN/UV Pin Current VEN/UV = 0V, VIN = 20V
VEN/UV = 1.24V, VIN = 20V
VEN/UV = 20V, VIN = 0V
l
l
0.03
8
±1
15
µA
µA
µA
Quiescent Current in
Shutdown (VEN/UV = 0V)
VIN = 6V
l
0.3 1
10
µA
µA
Internal Current Limit
(Note 12)
VIN = 2V, VOUT = 0V
VIN = 12V, VOUT = 0V
VIN = 20V, VOUT = 0V
l
l
570
230
710
700
330
850
430
mA
mA
mA
Programmable
Current Limit
Programming Scale Factor: 2V < VIN < 20V (Note 11)
VIN = 2V, VOUT = 0V, RILIM = 300Ω
VIN = 2V, VOUT = 0V, RILIM = 1.5kΩ
l
l
450
90
150
500
100
550
110
mA • kΩ
mA
mA
PGFB Trip Point PGFB Trip Point Rising l291 300 309 mV
PGFB Hysteresis PGFB Trip Point Hysteresis 7 mV
PGFB Pin Current VIN = 2V, VPGFB = 300mV 25 nA
PG Output Low Voltage IPG = 100µA l30 100 mV
PG Leakage Current VPG = 20V l1 µA
Reverse Input Current VIN = –20V, VEN/UV = 0V, VOUT = 0V, VSET = 0V l100 µA
Reverse Output Current VIN = 0, VOUT = 5V, SET = Open 14 25 µA
Minimum Load Required
(Note 13)
VOUT < 1V l10 µA
Thermal Shutdown TJ Rising
Hysteresis
165
8
°C
°C
Start-Up Time VOUT(NOM) = 5V, ILOAD = 500mA, CSET = 0.47µF, VIN = 6V, VPGFB = 6V
VOUT(NOM) = 5V, ILOAD = 500mA, CSET = 4.7µF, VIN = 6V, VPGFB = 6V
VOUT(NOM) = 5V, ILOAD = 500mA, CSET = 4.7µF, VIN = 6V, RPG1 = 50kΩ,
RPG2 = 700kΩ (with Fast Start-Up to 90% of VOUT)
55
550
10
ms
ms
ms
Thermal Regulation 10ms Pulse –0.01 %/W
Input-to-Output
Differential Voltage
Control (VIOC) (Note 15)
VIOC Amplifier Gain 1 V/V
VIOC Pin Voltage Range: VOUT>VVIOC + 0.5V l1 4 V
VIOC Pin Voltage: VOUT≤ 1.5V, VIN=2.5V 1 V
VIOC Pin Source Current l200 µA
VIOC Pin Sink Current: VIN ≥ 2.5V l15 µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The EN/UV pin threshold must be met to ensure device operation.
Note 3: Maximum junction temperature limits operating conditions. The
regulated output voltage specification does not apply for all possible
combinations of input voltage and output current, especially due to the
internal current limit foldback which starts to decrease current limit at
VIN VOUT > 12V. If operating at maximum output current, limit the input
voltage range. If operating at the maximum input voltage, limit the output
current range.
Note 4: OUTS ties directly to OUT.
Note 5: Dropout voltage is the minimum input-to-output differential
voltage needed to maintain regulation at a specified output current. The
dropout voltage is measured when output is 1% out of regulation. This
definition results in a higher dropout voltage compared to hard dropout
which is measured when VIN = VOUT(NOMINAL). For lower output voltages,
below 1.5V, dropout voltage is limited by the minimum input voltage
specification. Please consult the Typical Performance Characteristics
for curves of dropout voltage as a function of output load current and
temperature measured in a typical application circuit.
LT3045— 1
LT3045-1
5
30451fa
For more information www.linear.com/LT3045-1
ELECTRICAL CHARACTERISTICS
Note 6: GND pin current is tested with VIN = VOUT(NOMINAL) and a current
source load. Therefore, the device is tested while operating in dropout. This
is the worst-case GND pin current. GND pin current decreases at higher
input voltages. Note that GND pin current does not include SET pin or ILIM
pin current but Quiescent current does include them.
Note 7: SET and OUTS pins are clamped using diodes and two 25Ω series
resistors. For less than 5ms transients, this clamp circuitry can carry
more than the rated current. Refer to Applications Information for more
information.
Note 8: Adding a capacitor across the SET pin resistor decreases output
voltage noise. Adding this capacitor bypasses the SET pin resistor’s
thermal noise as well as the reference current’s noise. The output noise
then equals the error amplifier noise. Use of a SET pin bypass capacitor
also increases start-up time.
Note 9: The LT3045-1 is tested and specified under pulsed load conditions
such that TJ TA. The LT3045-1E is 100% tested at 25°C and performance
is guaranteed from 0°C to 125°C. Specifications over the –40°C to 125°C
operating temperature range are assured by design, characterization, and
correlation with statistical process controls. The LT3045-1I is guaranteed
over the full –40°C to 125°C operating temperature range. High junction
temperatures degrade operating lifetimes. Operating lifetime is derated at
junction temperatures greater than 125°C.
Note 10: Parasitic diodes exist internally between the VIOC, ILIM, PG,
PGFB, SET, OUTS, and OUT pins and the GND pin. Do not drive these pins
more than 0.3V below the GND pin during a fault condition. These pins
must remain at a voltage more positive than GND during normal operation.
Note 11: The current limit programming scale factor is specified while the
internal backup current limit is not active. Note that the internal current
limit has foldback protection for VIN VOUT differentials greater than 12V.
Note 12: The internal back-up current limit circuitry incorporates foldback
protection that decreases current limit for VIN VOUT > 12V. Some level of
output current is provided at all VIN VOUT differential voltages. Consult the
Typical Performance Characteristics graph for current limit vs VIN VOUT.
Note 13: For output voltages less than 1V, the LT3045-1 requires a 10µA
minimum load current for stability.
Note 14: Maximum OUT-to-OUTS differential is guaranteed by design.
Note 15: The VIOC buffer outputs a voltage equal to VIN – VOUT or
VIN–1.5V (for VOUT≤1.5V). See Block Diagram and Applications
Information for further information. The VIOC pin’s source current should
be set between 10µA and 200µA.
LT3045— 1 TuTu T999 T995 gmna T992 T999 999 995 994 992 995 SET PIN CURRENT 775 759 725 u 25 59 75 T99 T25 T50 TEMPERATURE ("0) , D N = 3250 72 ’T u T 2 TuTu T999 T995 gmna ETun2 KTuna 999 995 994 992 995 RE SET PIN CU u V05 DTSTRIBUTTON (mVT DuTPUT VOLTAGE (V) T5 3 45 5 T5 9Tu512135T5 99 n OFFSETVOLTAGE (mVT T T 729 u : N = 3250 EB WU ‘0‘ I02 ng DTSTRTBUTTON TVA) V ——— T5u°c T25°c — 25°C ’55°C 2 4 5 8 “1‘2 ‘4 TNPUT VOLTAGE (V) T6 I8 20 T5 3 45 5 75 9 T9512T35T5 DUTPUT VOLTAGE (V) OFFSET VOLTAGE (RM 20 T5 T0 95 OFFSETVOLTAGE (NM 20 T5 llsErmA) n 775 750 725 n 25 50 75 T00 T25 T59 TEMPERATURE 1°C) ‘L’ TWA — — T59°C VuUT’ I W —— T25°C — 25°C . ’55°C 2 4 5 8 T0 T2 I4 mPuT VOLTAGE (V) T6 T9 20 VW 25V mAtufiUUmA 3V ISET ’75 ’SU ’25 U 25 50 75 “JD T25 I50 TEMPERATURE ("0) ,
LT3045-1
6
30451fa
For more information www.linear.com/LT3045-1
SET Pin Current Offset Voltage (VOUT – VSET) Load Regulation
I
L
= 1mA
V
IN
= 20V
150°C
125°C
25°C
–55°C
OUTPUT VOLTAGE (V)
0
1.5
3
4.5
6
7.5
9
10.5
12
13.5
15
99.0
99.2
99.4
99.6
99.8
100.0
100.2
100.4
100.6
100.8
101.0
SET PIN CURRENT (µA)
30451 G07
I
L
= 1mA
V
IN
= 20V
150°C
125°C
25°C
–55°C
OUTPUT VOLTAGE (V)
0
1.5
3
4.5
6
7.5
9
10.5
12
13.5
15
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
OFFSET VOLTAGE (mV)
30451 G08
V
IN
= 2.5V
∆I
L
= 1mA to 500mA
V
OUT
= 1.3V
V
OS
I
SET
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
2
4
6
8
10
12
14
16
18
20
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
∆I
SET
(nA)
∆ V
OS
(mV)
30451 G09
TYPICAL PERFORMANCE CHARACTERISTICS
Offset Voltage SET Pin Current Offset Voltage (VOUT – VSET)
SET Pin Current SET Pin Current Offset Voltage (VOUT – VSET)
TJ = 25°C, unless otherwise noted.
V
IN
= 2V
I
L
= 1mA
V
OUT
= 1.3V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
99.0
99.2
99.4
99.6
99.8
100.0
100.2
100.4
100.6
100.8
101.0
SET PIN CURRENT (µA)
30451 G01
N = 3250
I
SET
DISTRIBUTION (µA)
98
99
100
101
102
30451 G02
V
IN
= 2V
I
L
= 1mA
V
OUT
= 1.3V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
OFFSET VOLTAGE (mV)
30451 G03
N = 3250
V
OS
DISTRIBUTION (mV)
–2
–1
0
1
2
30451 G04
I
L
= 1mA
V
OUT
= 1.3V
150°C
125°C
25°C
–55°C
INPUT VOLTAGE (V)
0
2
4
6
8
10
12
14
16
18
20
99.0
99.2
99.4
99.6
99.8
100.0
100.2
100.4
100.6
100.8
101.0
SET PIN CURRENT (µA)
30451 G05
I
L
= 1mA
V
OUT
= 1.3V
150°C
125°C
25°C
–55°C
INPUT VOLTAGE (V)
0
2
4
6
8
10
12
14
16
18
20
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
OFFSET VOLTAGE (mV)
30451 G06
vw = 2v VENTUV VTN 3 5 IL ; TWA ng: 13x OUIESCENT CURRENT (mil) n5 U ’75 ’50 ’25 U 25 50 75 WU T25 I50 TEMPERATURE (we) 150°C I25“C CUIESCENT CURRENT (mA) n5 — 25"C v 755% a O T 2 3 4 5 OUTPUT VOLTAGE (V) 20 TE TL : 51mm Tl = SUUmA 6ND PIN CURRENT (mA) TL : IflflmA TLzlmA ’75 ’50 ’25 U 25 50 75 T00 T25 T50 TEMPERATURECC) E DROPOUTVOLTACE TEMPERATURE (”0) 500 450 Ann 350 am? 250 200 T 150 um 50 n n 50 THE 150 200 25m 300 350 Ann 450 sun OUTPUT CURRENT (MA) n 50 THE T50 200 250 300 35a Ann 450 sun OUTPUT CURRENT (MA) 0 775 ’50 725 n 25 50 75 Too T25 TED T50°C T25°C — 25°C . ’55°C LT3045— 1 VENTUV’VTN TL : IflUA ng = as M: Rm: IflUA CUIESCENT CURRENT (mA) U 2 4 E 8 ID ‘2 T4 TNPUT VOLTAGE (V) I5 T8 20 sun 450 34% TL=4UUTHA 5 35a ‘ sun TL: SUDmA 250 mu T50 mm 50 DROPOUTVOLTACE n ’75 ’50 ’25 U 25 5D 75 I00 ‘25 T50 TEMPERATURE m ng = 33 2k GNU FIN CURRENT (mA) R = 33032 Rl=3 U U T 2 3 4 5 5 7 8 S TU WPUT VOLTAGE (V) 7
LT3045-1
7
30451fa
For more information www.linear.com/LT3045-1
TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Current Typical Dropout Voltage Dropout Voltage
Quiescent Current Quiescent Current Quiescent Current
TJ = 25°C, unless otherwise noted.
V
IN
= 2V
V
EN/UV
= V
IN
I
L
= 10µA
R
SET
= 13k
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
QUIESCENT CURRENT (mA)
30451 G10
V
EN/UV
= 0V
V
IN
= 20V
V
IN
= 2V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
5
10
15
20
25
30
35
40
45
50
QUIESCENT CURRENT (µA)
30451 G11
V
EN/UV
= V
IN
I
L
= 10µA
R
SET
= 33.2kΩ
I
VIOC
= 10µA
INPUT VOLTAGE (V)
0
2
4
6
8
10
12
14
16
18
20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
QUIESCENT CURRENT (mA)
30451 G12
V
IN
= 6V
V
EN/UV
= VIN
I
L
= 10µA
150°C
125°C
25°C
–55°C
OUTPUT VOLTAGE (V)
0
2
4
1
3
5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
QUIESCENT CURRENT (mA)
30451 G13
R
SET
= 33.2k
150°C
125°C
25°C
–55°C
OUTPUT CURRENT (mA)
0
50
100
150
200
250
300
350
400
450
500
0
50
100
150
200
250
300
350
400
450
500
DROPOUT VOLTAGE (mV)
30451 G14
R
SET
= 33.2k
I
L
= 500mA
I
L
= 400mA
I
L
= 1mA
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
50
100
150
200
250
300
350
400
450
500
DROPOUT VOLTAGE (mV)
30451 G15
GND Pin Current GND Pin Current GND Pin Current
V
IN
= 5V
R
SET
= 33.2k
I
L
= 500mA
I
L
= 300mA
I
L
= 100mA
I
L
= 1mA
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
2
4
6
8
10
12
14
16
18
20
GND PIN CURRENT (mA)
30451 G16
V
IN
= 4.3V
R
SET
= 33.2k
150°C
125°C
25°C
–55°C
OUTPUT CURRENT (mA)
0
50
100
150
200
250
300
350
400
450
500
0
2
4
6
8
10
12
14
16
18
20
22
GND PIN CURRENT (mA)
30451 G17
R
SET
= 33.2k
R
L
= 6.6Ω
R
L
= 11Ω
R
L
= 33Ω
R
L
= 330Ω
R
L
= 3.3kΩ
INPUT VOLTAGE (V)
0
1
2
3
4
5
6
7
8
9
10
0
2
4
6
8
10
12
14
16
18
GND PIN CURRENT (mA)
30451 G18
LT3045— 1 21m 175 150 125 11m 1175 INPUT UVLU THRESHOLD (V) 1150 1125 — RISWG uVLo — FALLING UVLD u 775 7511 725 u 25 5D 75 mm 125150 TEMPERATURE1°CJ 55 511 45 $411 g 35 gm E 25 E; 211 E ‘ 5 z — — 150°C 10 — 125°C — 25°C “5 - ’55“C n u 2 a 5 31111214151820 ENABLEPWVOLTAGELV) a: V1N=2V 150°C 125°C — 25°C 2 \ ’55°C 302 V ~ E I 5 E E \ E 01 \ a 4a 71a ’16 714712 4D ‘8 is 74 72 u ENABLE P1N VOLTAGE (V) 132 1311 125 124 122 TURN-0N THRESHOLD (v1 1211 118 775 ’50 725 n 25 511 75 10012515n TEMPERATURE 1°C) EM/UV PIN CURRENTM) u 2 4 5 8 1111214 ENABLE PW VOLTAGE (V) 15 1a 20 man an m Tun Hun 5% Ann sun mm mm CURRENT LIMITunA) —VW=25V — VW=12V n ’75 ’50 ’25 U 25 50 75 100 125150 TEMPERATURECC) $1411 95 80 e5 5o 775 75U 725 u 25 5o 75 100 125150 TEMPERATUPE1°CJ EM/UV PIN CURRENT (UM {‘11 150°C “‘0 — 125°C — 25°C - ’55°C 711m ’ZU’IB’VE’M’IZ’TU ,3 75 74 72 u ENABLE PW VOLTAGE (V) 51m 51m 41m 31m 21m CURRENT LIMIT (711A) 1110 n 775 ’50 725 n 25 511 75 10012515n TEMPERATURE 1°C)
LT3045-1
8
30451fa
For more information www.linear.com/LT3045-1
TYPICAL PERFORMANCE CHARACTERISTICS
EN/UV Pin Current EN/UV Pin Current Negative Enable Pin Current
Minimum Input Voltage EN/UV Turn-On Threshold EN/UV Pin Hysteresis
TJ = 25°C, unless otherwise noted.
RISING UVLO
FALLING UVLO
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
INPUT UVLO THRESHOLD (V)
30451 G19
V
IN
= 2V
V
IN
= 10V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
1.18
1.20
1.22
1.24
1.26
1.28
1.30
1.32
TURN-ON THRESHOLD (V)
30451 G20
V
IN
= 2V
V
IN
= 10V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
50
65
80
95
110
125
140
155
170
185
200
EN/UV PIN HYSTERESIS (mV)
30451 G21
V
IN
= 20V
150°C
125°C
25°C
–55°C
ENABLE PIN VOLTAGE (V)
0
2
4
6
8
10
12
14
16
18
20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
EN/UV PIN CURRENT (µA)
30451 G22
V
IN
= 20V
V
IN
= 2V
ENABLE PIN VOLTAGE (V)
0
2
4
6
8
10
12
14
16
18
20
0
1
2
3
4
5
6
7
8
9
10
EN/UV PIN CURRENT (µA)
30451 G23
V
IN
= 2V
150°C
125°C
25°C
–55°C
ENABLE PIN VOLTAGE (V)
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
EN/UV PIN CURRENT (µA)
30451 G24
Input Pin Current Internal Current Limit Internal Current Limit
V
IN
= 2V
150°C
125°C
25°C
–55°C
ENABLE PIN VOLTAGE (V)
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
0
0
0.1
0.2
0.3
INPUT CURRENT (µA)
30451 G25
R
ILIM
= 0Ω
V
OUT
= 0V
V
IN
= 2.5V
V
IN
= 12V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
100
200
300
400
500
600
700
800
900
1000
CURRENT LIMIT (mA)
30451 G26
V
IN
= 20V
R
ILIM
= 0Ω
V
OUT
= 0V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
100
200
300
400
500
600
CURRENT LIMIT (mA)
30451 G27
LT3045— 1 CURRENT LIMIT (mA) ILIM PIN CURRENTMT mun am am Tun Hun sun Ann sun 2m mu 0 0 Tune so 800 700 600 500 400 300 200 mu 150°C I25“C — 25m v 755m 245 a CURRENTLIMIT (mm In T2 T4 T5 T8 20 WPUT’TO’OUTPUT DTFFERENTTAL (v) u u 50 Too T50 200 25a sun 350 400 45m 500 OUTPUT CURRENT (mA) VTN : 2v vpm = new TpG : TuuuA ’75 ’50 ’25 U TEMPERATURE m an mm 25 50 75 um T25 T50 7000 200 RTLTm=SUUsI sun vaupuv T80 800 760 700 EMU 600 t 720 E 500 4 H10 E 400 g 80 m 300 a so 200 4D — VW = 2 5v Tuu _ VWZW 20 U U ’75 ’53 ’25 U 25 5D 75 WU I25 ‘50 ’75 ’50 ’25 U 25 5D 75 WE I25 750 TEMPERATURE ("m TEMPERATURE (an) F 3“] E 308 VW 2V 306 E s 304 g 302 § 5 I 300 E 4 298 E 3 296 5 u 2 294 292 ‘ 290 D ’75 ’53 ’25 U 25 5D 75 WU I25 ‘50 ’75 ’50 ’25 U 25 5D 75 THU ‘25 T50 TEMPERATURE ("m TEMPERATURE (as) > mu an an vpg vw=25v VPGF Um : zvnmv an 25 vsna av 7U 20 an A / \\ E / 50 : 15 40 E EU I 0 2D 05 TD 0 U ’75 ’50 ’25 D 25 5D 75 I00 ‘25 T50 ’75 ’53 ’25 U 25 5D 75 WU I25 ‘50 TEMPERATURE m TEMPERATURE ("m 9
LT3045-1
9
30451fa
For more information www.linear.com/LT3045-1
TYPICAL PERFORMANCE CHARACTERISTICS
ILIM Pin Current PGFB Rising Threshold PGFB Hysteresis
Internal Current Limit Programmable Current Limit Programmable Current Limit
TJ = 25°C, unless otherwise noted.
R
ILIM
= 0Ω
150°C
125°C
25°C
–55°C
INPUT-TO-OUTPUT DIFFERENTIAL (V)
0
2
4
6
8
10
12
14
16
18
20
0
100
200
300
400
500
600
700
800
900
1000
CURRENT LIMIT (mA)
30451 G28
R
ILIM
= 300Ω
V
OUT
= 0V
V
IN
= 2.5V
V
IN
= 12V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
100
200
300
400
500
600
700
800
900
1000
CURRENT LIMIT (mA)
30451 G29
R
ILIM
= 1.5k
V
OUT
= 0V
V
IN
= 2.5V
V
IN
= 12V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
20
40
60
80
100
120
140
160
180
200
CURRENT LIMIT (mA)
30451 G30
V
ILIM
= 0V
R
SET
= 13k
2.5V
IN
5V
IN
10V
IN
OUTPUT CURRENT (mA)
0
50
100
150
200
250
300
350
400
450
500
0
100
200
300
400
500
600
700
800
900
1000
ILIM PIN CURRENT (uA)
30451 G31
V
IN
= 2V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
290
292
294
296
298
300
302
304
306
308
310
PGFB RISING THRESHOLD (mV)
30451 G32
V
IN
= 2V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
1
2
3
4
5
6
7
8
PGFB HYSTERESIS (mV)
30451 G33
PG Output Low Voltage PG Pin Leakage Current
ISET During Start-Up with Fast
Start-Up Enabled
V
IN
= 2V
V
PGFB
= 290mV
I
PG
= 100µA
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
5
10
15
20
25
30
35
40
45
50
V
PG
(mV)
30451 G34
V
PG
= 2V
V
PGFB
= 310mV
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
10
20
30
40
50
60
70
80
90
100
I
PG
(nA)
30451 G35
V
IN
= 2.5V
V
PGFB
= 290mV
V
SET
= 1.3V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
0.5
1.0
1.5
2.0
2.5
3.0
I
SET
(mA)
30451 G36
LT3045— 1 :5 ‘2 v 7 vpm=2anmv Vw=5 name so VsEr=‘3V / w ng=332k __‘2§550 e v v >5mV A — u A our 53 / 25 // E ,5“ E, 5 / / A / a / E 2“ g 5 4 : i 5 3 E w 5 5 E a S 4 S we E E 2 o D n5 2 ‘ u u u u 2 4 e s m ‘2 M I5 m 2n 0 5 m ‘5 2a 775 an 725 u 25 50 75 mm 125 my vwrmrvsn DIFFERENT‘AL (w ,, vum 7 ng (mV) , TEMPERATURE (an) a 120 wzu — swam — Cnur= wur no —- CSEI=U4NAF nu —- Cnm=22uf um mu 6 an an a an a an E m E 70 E $ m an a so an 50 an 40 Cuurlfluf 30 c U umr an * sn= u 20 \L=5UUmA 20 |L=SDDmA 4 5 e 7 a a mu ‘2 w: M ‘5 10 mu m Wk mnk mm mm m we w Ink wax IM wM ouwmvomsnw , > anquchwz) FREDUENCHHZ) mm 120 we no so ‘2“ 1 .2 um 30 mm \ an 7a a ,> a an 2: an E an :_ E m E 50 5 5 E m m an a w an — \LzmflmA 5" 3U —— ‘ngnnm vw=5v an 20 — mflkHz Irmm 4n — \LzlflflmA ngzaulx — Vaurz‘av __ 5mm ngzsnw - ‘Lzmm cm mur an — UGV<>
LT3045-1
10
30451fa
For more information www.linear.com/LT3045-1
TYPICAL PERFORMANCE CHARACTERISTICS
VOUT Forced Above VOUT(NOMINAL) Power Supply Ripple Rejection Power Supply Ripple Rejection
ISET During Start-Up with Fast
Start-Up Enabled
Output Overshoot Recovery
Current Sink
Output Overshoot Recovery
Current Sink
TJ = 25°C, unless otherwise noted.
V
PGFB
= 290mV
V
SET
= 1.3V
V
IN
-TO-V
SET
DIFFERENTIAL (V)
0
2
4
6
8
10
12
14
16
18
20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
I
SET
(mA)
30451 G37
V
IN
= 5V
R
SET
= 33.2k
150°C
125°C
25°C
–55°C
V
OUT
– V
SET
(mV)
0
5
10
15
20
0
2
4
6
8
10
12
OUTPUT SINK CURRENT (mA)
30451 G38
V
IN
= 5V
R
SET
= 33.2k
V
OUT
– V
SET
> 5mV
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
1
2
3
4
5
6
7
OUTPUT SINK CURRENT (mA)
30451 G39
V
IN
= 5V
R
SET
= 33.2k
OUTPUT VOLTAGE (V)
4
5
6
7
8
9
10
11
12
13
14
15
0
2
4
6
8
CURRENT (mA)
30451 G40
IIN WHEN VEN = 0V
IOUT WHEN VEN = 0V
IIN WHEN VEN = VIN
IOUT WHEN VEN = VIN
V
IN
= 5V
R
SET
= 30.1k
C
OUT
= 10µF
I
L
= 500mA
C
SET
= 4.7µF
C
SET
= 0.47µF
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
20
30
40
50
60
70
80
90
100
110
120
PSRR (dB)
30451 G41
V
IN
= 5V
R
SET
= 30.1k
C
SET
= 0.47µF
I
L
= 500mA
C
OUT
= 10µF
C
OUT
= 22µF
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
20
30
40
50
60
70
80
90
100
110
120
PSRR (dB)
30451 G42
Power Supply Ripple Rejection
Power Supply Ripple Rejection
as a Function of Error Amplifier
Input Pair Power Supply Ripple Rejection
V
IN
= 5V
R
SET
= 30.1k
C
OUT
= 10µF
C
SET
= 0.47µF
I
L
= 500mA
I
L
= 300mA
I
L
= 100mA
I
L
= 50mA
I
L
= 1mA
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
20
40
60
80
100
120
140
PSRR (dB)
30451 G43
V
IN
= V
OUT
+ 2V
I
L
= 500mA
C
OUT
= 10µF
C
SET
= 0.47µF
V
OUT
≥ 1.3V
0.6V < V
OUT
< 1.3V
V
OUT
≤ 0.6V
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
20
30
40
50
60
70
80
90
100
110
120
PSRR (dB)
30451 G44
I
L
= 500mA
R
SET
= 30.1k
C
OUT
= 10µF
C
SET
= 0.47µF
100kHz
500kHz
1MHz
2MHz
INPUT–TO–OUTPUT DIFFERENTIAL (V)
0
1
2
3
4
5
0
10
20
30
40
50
60
70
80
90
100
PSRR (dB)
30451 G45
LT3045— 1 2 a 2n T8 T3 V‘N’VU%L;2V an 5 ‘w E 3‘ 5 3 g Tum; = 5mm: 3 Tum) = 5uumA E T a >) >1V 4 fl ‘ 2 W $ ‘ 2 5 a a z T n z z T u S S S E u s E E as g u 5 g g as 3 u a E 3 no u 2 02 n n u n somuT5uzuuzsnauuasnanmsusnn um m T To mu 0 T5 3 45 5 75 a man 135m LOAD CURRENT (mA) sET Pm CAPACTTANCE (UE) DuTPUT VOLTAGE w) man man man Iflfl t WU 2 I00 , z, a % E % E In E H] CDUT‘WUF E In S S S E E, E D ‘ vwzsv D T o ‘ nsg 32k ouwzzur ng 332x CnUr=WF CsET 7UP CsEr=47uF m TMD=5uumA m \mwzfiflflmA m swam W Iflfl Ik Wk mflk WM IBM ‘0 WU Wk Iflk Wok IM WM W Iflfl Wk Wk mflk ‘M WM FREQUENCV (Hz) mmugmcv m2, FREQUENCV um mun — vsz av — newvma av _ VWSDEV OUTPUT g mu > WWW g m szSV 2 R5g=332k OUTPUT s COUT=|0UF Tr E ICSUSEUIQJ : z m D ‘ vW=vao2v ‘ W | unmA Hus/UN ” zuus/mv our VW=5V m ESE NF RSET=332k H] mm Tk Wk mnk TM mM £2332ng ”WHEN“ ("U LOAD sTEP : IflmA To 5uumA ‘I‘I
LT3045-1
11
30451fa
For more information www.linear.com/LT3045-1
TYPICAL PERFORMANCE CHARACTERISTICS
Integrated RMS Output Noise
(10Hz to 100kHz)
Noise Spectral Density
Integrated RMS Output Noise
(10Hz to 100kHz)
Noise Spectral Density
Integrated RMS Output Noise
(10Hz to 100kHz)
Noise Spectral Density
TJ = 25°C, unless otherwise noted.
V
IN
= 5V
R
SET
= 33.2k
C
OUT
= 10µF
C
SET
= 4.7µF
LOAD CURRENT (mA)
0
50
100
150
200
250
300
350
400
450
500
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
RMS OUTPUT NOISE (µV
RMS
)
30451 G46
V
IN
= 5V
C
OUT
= 10µF
R
SET
= 33.2k
I
LOAD
= 500mA
SET PIN CAPACITANCE (µF)
0.01
0.1
1
10
100
0
1
2
3
4
5
6
7
8
9
RMS OUTPUT NOISE (µV
RMS
)
30451 G47
V
IN
= V
OUT
+ 2V
C
OUT
= 10µF
C
SET
= 4.7µF
I
LOAD
= 500mA
OUTPUT VOLTAGE (V)
0
1.5
3
4.5
6
7.5
9
10.5
12
13.5
15
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
RMS OUTPUT NOISE (µV
RMS
)
30451 G48
V
IN
= 5V
R
SET
= 33.2k
C
OUT
= 10µF
I
LOAD
= 500mA
C
SET
= 0.047µF
C
SET
= 0.47µF
C
SET
= 1µF
C
SET
= 4.7µF
C
SET
= 22µF
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
0.1
1
10
100
1000
OUTPUT NOISE (nV/√Hz)
30451 G49
V
IN
= 5V
R
SET
= 33.2k
C
SET
= 4.7µF
I
LOAD
= 500mA
C
OUT
= 10µF
C
OUT
= 22µF
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
0.1
1
10
100
1000
OUTPUT NOISE (nV/√Hz)
30451 G50
V
IN
= 5V
R
SET
= 33.2k
C
SET
= 4.7µF
C
OUT
= 10µF
I
L
= 500mA
I
L
= 300mA
I
L
= 100mA
I
L
= 10mA
I
L
= 1mA
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
0.1
1
10
100
1000
OUTPUT NOISE (nV/√Hz)
30451 G51
Noise Spectral Density as
a Function of Error Amplifier
Input Pair Output Noise: 10Hz to 100kHz Load Transient Response
V
IN
= V
OUT
+ 2V
I
L
= 500mA
C
OUT
= 10µF
C
SET
= 4.7µF
V
OUT
≥ 1.3V
0.6V < V
OUT
< 1.3V
V
OUT
≤ 0.6V
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
0.1
1
10
100
1000
OUTPUT NOISE (nV/√Hz)
30451 G52
V
IN
= 5V
R
SET
= 33.2k
C
OUT
= 10µF
C
SET
= 4.7µF
I
L
= 500mA
1ms/DIV
V/DIV
30451 G53
V
IN
= 5V
R
SET
= 33.2k
C
OUT
= 10µF
C
SET
= 0.47µF
LOAD STEP = 10mA TO 500mA
20µs/DIV
OUTPUT
CURRENT
500mA/DIV
OUTPUT
VOLTAGE
20mV/DIV
30451 G54
LT3045— I EUUmV/DIV INPUT VOLTAGE OUTPUT WITH WP“ EAsT STAR'HJP 2mm OUTPUT VOLTAGE PULSE EN/UV OUTPUT OUTPUT WITHOUT VOLTAGE FAST STARTrUP memv swmv "m” mums/DIV W “ Earns/DIV "W" Vw :4 5v To 5v vW = IN TO 5v [Isa 33 2k Om = v cm: TUUE Rsn C5g=u INF CaUT = ‘qu IL: 500mA 05g = OATUF KL :5 5:1 I I0 I I0 I 08 I 08 I 06 I 06 A I 04 A I 04 a a g 102 a ‘02 S S g I 00 g I 00 a 098 a 098 9 9 > Ose > Ose 094 094 __: [7‘32 [792 — [7‘30 [790 *75 *50 *25 U 25 5D 75 IUD I25 I50 0 25 50 75 I00 I25 I50 I75 200 TEMPERATURE (as) was SOURCE CURRENT (LIA) *20 I I0 *I8 I 08 -45 I 06 < fill="" a="" i="" 04="" g="" 42="" g="" 102="" k="" s="" 3="" 4o="" a="" mu="" x=""> E *8 g [798 g ,5 S 096 s _ _ O 775 ,50 725 O 12 25 5O 75 I00 I25 I53 TEMPERATURE (”0) O94 __ O92 — USU u 50 I00 I53 2OO 250 BED 350 400 45O 500 OUTPUT LOAD CURRENT (mA)
LT3045-1
12
30451fa
For more information www.linear.com/LT3045-1
TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up Time with and
without Fast Start-Up Circuitry for
Large CSET
Input Supply Ramp-Up and
Ramp-Down
Line Transient Response
TJ = 25°C, unless otherwise noted.
V
IN
= 4.5V TO 5V
R
SET
= 33.2k
C
OUT
= 10µF
C
SET
= 0.47µF
I
L
= 500mA
5µs/DIV
INPUT
VOLTAGE
500mV/DIV
OUTPUT
VOLTAGE
1mV/DIV
30451 G55
V
IN
= 5V
R
SET
= 33.2k
C
OUT
= 10µF
C
SET
= 4.7µF
R
L
= 6.6Ω
500mV/DIV
2V/DIV
OUTPUT WITH
FAST START–UP
(SET AT 90%)
OUTPUT WITHOUT
FAST START–UP
PULSE EN/UV
100ms/DIV
30451 G56
INPUT VOLTAGE
OUTPUT VOLTAGE
V
IN
= 0V TO 5V
V
EN/UV
= V
IN
R
SET
= 33.2k
C
OUT
= 10µF
C
SET
= 0.47µF
R
L
= 6.6Ω
50ms/DIV
2V/DIV
30451 G57
VIOC Voltage
VIOC Voltage
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0.90
0.92
0.94
0.96
0.98
1.00
1.02
1.04
1.06
1.08
1.10
VIOC VOLTAGE (V)
30451 G58
VIN = 4.3V
VOUT = 3.3V
IVIOC = 100µA
IOUT = 1mA
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
VIOC SINK CURRENT (µA)
30451 G60
VIN = 4.3V
VOUT = 3.3V
VVIOC = 2V
IOUT = 1mA
VIOC SOURCE CURRENT (µA)
0
25
50
75
100
125
150
175
200
0.90
0.92
0.94
0.96
0.98
1.00
1.02
1.04
1.06
1.08
1.10
VIOC VOLTAGE (V)
30451 G59
150°C
125°C
25°C
–55°C
VIN = 4.3V
VOUT = 3.3V
IOUT = 1mA
OUTPUT LOAD CURRENT (mA)
0
50
100
150
200
250
300
350
400
450
500
0.90
0.92
0.94
0.96
0.98
1.00
1.02
1.04
1.06
1.08
1.10
VIOC VOLTAGE (V)
30451 G61
150°C
125°C
25°C
–55°C
VIN = 4.3V
VOUT = 3.3V
IVIOC = 100µA
VIOC Voltage
VIOC Sink Current
LT3045— 1 13
LT3045-1
13
30451fa
For more information www.linear.com/LT3045-1
PIN FUNCTIONS
IN (Pins 1, 2): Input. These pins supply power to the
regulator. The LT3045-1 requires a bypass capacitor at the
IN pin. In general, a battery’s output impedance rises with
frequency, so include a bypass capacitor in battery-powered
applications. While a 4.7µF input bypass capacitor gener-
ally suffices, applications with large load transients may
require higher input capacitance to prevent input supply
droop. Consult the Applications Information section on the
proper use of an input capacitor and its effect on circuit
performance, in particular PSRR. The LT3045-1 withstands
reverse voltages on IN with respect to GND, OUTS and OUT.
In the case of a reversed input, which occurs if a battery
is plugged-in backwards, the LT3045-1 acts as if a diode
is in series with its input. Hence, no reverse-current flows
into the LT3045-1 and no negative voltage appears at the
load. The device protects itself and the load.
VIOC (Pin 3): Voltage for Input-to-Output Control. The
LT3045-1 incorporates a tracking function to control the
switching pre-regulator powering the LT3045-1. The VIOC
pin is the output of this tracking function that drives the pre-
regulator’s feedback (FB) pin to maintain the LT3045-1s
input voltage at VOUT + VVIOC. This function minimizes
power dissipation while maintaining PSRR performance.
See Applications Information section for details.
EN/UV (Pin 4): Enable/UVLO. Pulling the LT3045-1’s EN/
UV pin low places the part in shutdown. Quiescent current
in shutdown drops to less than 1µA and the output volt-
age turns off. Alternatively, the EN/UV pin can set an input
supply undervoltage lockout (UVLO) threshold using a
resistor divider between IN, EN/UV and GND. The LT3045-1
typically turns on when the EN/UV voltage exceeds 1.24V
on its rising edge, with a 130mV hysteresis on its falling
edge. The EN/UV pin can be driven above the input voltage
and maintain proper functionality. If unused, tie EN/UV to
IN. Do not float the EN/UV pin.
PG (Pin 5): Power Good. PG is an open-collector flag that
indicates output voltage regulation. PG pulls low if PGFB
is below 300mV. If the power good functionality is not
needed, float the PG pin. A parasitic substrate diode exists
between PG and GND pins of the LT3045-1; do not drive
PG more than 0.3V below GND during normal operation
or during a fault condition.
ILIM (Pin 6): Current Limit Programming Pin. Connecting a
resistor between ILIM and GND programs the current limit.
For best accuracy, Kelvin connect this resistor directly to
the LT3045-1’s GND pin. The programming scale factor
is nominally 150mA•kΩ. The ILIM pin sources current
proportional (1:500) to output current; therefore, it also
serves as a current monitoring pin with a 0V to 300mV
range. If the programmable current limit functionality is
not needed, tie ILIM to GND. A parasitic substrate diode
exists between ILIM and GND pins of the LT3045-1; do
not drive ILIM more than 0.3V below GND during normal
operation or during a fault condition.
PGFB (Pin 7): Power Good Feedback. The PG pin pulls
high if PGFB increases beyond 300mV on its rising edge,
with 7mV hysteresis on its falling edge. Connecting an
external resistor divider between OUT, PGFB and GND
sets the programmable power good threshold with the
following transfer function: 0.3V (1 + RPG2/RPG1). As
discussed in the Applications Information section, PGFB
also activates the fast start-up circuitry. Tie PGFB to IN
if power good and fast start-up functionalities are not
needed, and if reverse input protection is additionally
required, tie the anode of a 1N4148 diode to IN and its
cathode to PGFB. See the Typical Applications section for
details. A parasitic substrate diode exists between PGFB
and GND pins of the LT3045-1; do not drive PGFB more
than 0.3V below GND during normal operation or during
a fault condition.
SET (Pin 8): SET. This pin is the inverting input of the er-
ror amplifier and the regulation set-point for the LT3045-
1. SET sources a precision 100µA current that flows
through an external resistor connected between SET and
GND. The LT3045-1’s output voltage is determined by
VSET = ISET RSET. Output voltage range is from zero to
15V. Adding a capacitor from SET to GND improves noise,
PSRR and transient response at the expense of increased
start-up time. For optimum load regulation, Kelvin con-
nect the ground side of the SET pin resistor directly to
the load. A parasitic substrate diode exists between SET
and GND pins of the LT3045-1; do not drive SET more
than 0.3V below GND during normal operation or during
a fault condition.
LT3045— 1 14
LT3045-1
14
30451fa
For more information www.linear.com/LT3045-1
PIN FUNCTIONS
GND (Pin 9, Exposed Pad Pin 13): Ground. The exposed
backside is an electrical connection to GND. To ensure
proper electrical and thermal performance, solder the
exposed backside to the PCB ground and tie it directly
to the GND pin.
OUTS (Pin 10): Output Sense. This pin is the noninvert-
ing input to the error amplifier. For optimal transient
performance and load regulation, Kelvin connect OUTS
directly to the output capacitor and the load. Also, tie the
GND connections of the output capacitor and the SET pin
capacitor directly together. A parasitic substrate diode
exists between OUTS and GND pins of the LT3045-1; do
not drive OUTS more than 0.3V below GND during normal
operation or during a fault condition.
OUT (Pins 11, 12): Output. These pins supply power to the
load. For stability, use a minimum 10µF output capacitor
with an ESR below 20mΩ and an ESL below 2nH. Large
load transients require larger output capacitance to limit
peak voltage transients. Refer to the Applications Informa-
tion section for more information on output capacitance. A
parasitic substrate diode exists between OUT and GND pins
of the LT3045-1; do not drive OUT more than 0.3V below
GND during normal operation or during a fault condition.
LT3045— 1 Erma I: I 15
LT3045-1
15
30451fa
For more information www.linear.com/LT3045-1
BLOCK DIAGRAM
V
+
OUTPUT OVERSHOOT
RECOVERY
ERROR
AMPLIFIER
INTERNAL CURRENT
LIMIT
PROGRAMMABLE
CURRENT LIMIT
QC QP
OUT
COUT
CIN
VIN
RL
VOUT
1.5V
100µA
2mA
V
+
300mV
215Ω
QPWR
+
DRIVER
+
+
V
+
300mV
ILIM
RILIM
+
IN
1, 2
THERMAL
SHDN
CURRENT
REFERENCE
FAST START-UP
INPUT
UVLO
SET-TO-OUTS
PROTECTION
CLAMP
INPUT UVLO
CURRENT LIMIT
THERMAL SHDN
DROPOUT
RSET
RPG
RPG2
RPG1
CSET
FAST START-UP
DISABLE LOGIC
OUTS
30451 BD
SETPGPGFB
EN/UV VIOC
GND
V
+
300mV
V
+
1.24V
PROGRAMMABLE
POWER GOOD
+
ENABLE
COMPARATOR
INPUT-TO-
OUTPUT
CONTROL
BIAS
+
– –
AV = 1
1.5V
+
4 3
7 5 9, 13 8 10 6
11, 12
LT3045— 1 16
LT3045-1
16
30451fa
For more information www.linear.com/LT3045-1
APPLICATIONS INFORMATION
The LT3045-1 is a high performance low dropout linear
regulator featuring LTCs ultralow noise (2nV/√Hz at
10kHz) and ultrahigh PSRR (76dB at 1MHz) architecture
for powering noise sensitive applications. Designed as a
precision current source followed by a high performance
rail-to-rail voltage buffer, the LT3045-1 can be easily paral-
leled to further reduce noise, increase output current and
spread heat on the PCB. The device additionally features
programmable current limit, fast start-up capability and
programmable power good.
The LT3045-1 is easy to use and incorporates all of the
protection features expected in high performance regula-
tors. Included are short-circuit protection, safe operating
area protection, reverse-battery protection, reverse-current
protection, and thermal shutdown with hysteresis.
In addition to the LT3045 feature set, the LT3045-1 incor-
porates a VIOC tracking function to control an upstream
switching converter to maintain a constant voltage across
the LT3045-1 and hence minimize power dissipation.
Output Voltage
The LT3045-1 incorporates a precision 100µA current
source flowing out of the SET pin, which also ties to the
error amplifier’s inverting input. Figure1 illustrates that
connecting a resistor from SET to ground generates a refer-
ence voltage for the error amplifier. This reference voltage
is simply the product of the SET pin current and the SET
pin resistor
. The error amplifier’s unity-gain configuration
produces a low impedance version of this voltage on its
noninverting input, i.e. the OUTS pin, which is externally
tied to the OUT pin.
Figure1. Basic Adjustable Regulator
The LT3045-1’s rail-to-rail error amplifier and current
reference allows for a wide output voltage range from 0V
(using a 0Ω resistor) to VIN minus dropout — up to 15V.
A PNP-based input pair is active for 0V to 0.6V output
and an NPN-based input pair is active for output volt-
ages greater than 1.3V, with a smooth transition between
the two input pairs from 0.6V to 1.3V output. While the
NPN-based input pair is designed to offer the best overall
performance, refer to the Electrical Characteristics Table for
details on offset voltage, SET pin current, output noise and
PSRR variation with the error amp input pair. Table 1 lists
many common output voltages and their corresponding
1% RSET resistors.
Table 1. 1% Resistor for Common Output Voltages
VOUT (V) RSET (kΩ)
2.5 24.9
3.3 33.2
5 49.9
12 121
15 150
The benefit of using a current reference compared with a
voltage reference as used in conventional regulators is that
the regulator always operates in unity gain configuration,
independent of the programmed output voltage. This al-
lows the LT3045-1 to have loop gain, frequency response
and bandwidth independent of the output voltage. As a
result, noise, PSRR and transient performance do not
change with output voltage. Moreover, since none of the
error amp gain is needed to amplify the SET pin voltage
to a higher output voltage, output load regulation is more
tightly specified in the hundreds of microvolts range and
not as a fixed percentage of the output voltage.
Since the zero TC current source is highly accurate, the
SET pin resistor can become the limiting factor in achiev-
ing high accuracy. Hence, it should be a precision resistor.
Additionally, any leakage paths to or from the SET pin
create errors in the output voltage. If necessary, use high
quality insulation (e.g., Teflon, Kel-F); moreover, clean-
ing of all insulating surfaces to remove fluxes and other
residues may be required. High humidity environments
may require a surface coating at the SET pin to provide
a moisture barrier
.
+
100µA
IN
EN/UV
PGFB
VIOC GND
OUT
LT3045-1
ILIM PG
10µF
4.7µF
V
IN
5V ±5%
0.47µF
V
OUT,
3.3V
I
OUT(MAX)
, 500mA
30451 F01
33.2k
SET
OUTS
LT3045— 1 DEMO BOARD Vam Inmowxxl mm 17
LT3045-1
17
30451fa
For more information www.linear.com/LT3045-1
APPLICATIONS INFORMATION
Minimize board leakage by encircling the SET pin with a
guard ring operated at a potential close to itself — ideally
tied to the OUT pin. Guarding both sides of the circuit
board is recommended. Bulk leakage reduction depends
on the guard ring width. Leakages of 100nA into or out of
the SET pin creates a 0.1% error in the reference voltage.
Leakages of this magnitude, coupled with other sources
of leakage, can cause significant errors in the output volt-
age, especially over wide operating temperature range.
Figure2 illustrates a typical guard ring layout technique.
Figure2. DFN Guard Ring Layout
Figure3, minimize the effects of PCB trace and solder
inductance by tying the OUTS pin directly to COUT and
the GND side of CSET directly to the GND side of COUT,
as well as keep the GND sides of CIN and COUT reasonably
close. Refer to the LT3045-1 demo board manual for more
information on the recommended layout that meets these
requirements. While the LT3045-1 is robust enough not
to oscillate if the recommended layout is not followed,
depending on the actual layout, phase/gain margin, noise
and PSRR performance may degrade.
Stability and Output Capacitance
The LT3045-1 requires an output capacitor for stability.
Given its high bandwidth, LTC recommends low ESR and
ESL ceramic capacitors. A minimum 10µF output capaci-
tance with an ESR below 20mΩ and an ESL below 2nH is
required for stability.
Given the high PSRR and low noise performance attained
using a single 10µF ceramic output capacitor, larger values
of output capacitor only marginally improves the perfor-
mance because the regulator bandwidth decreases with
increasing output capacitance hence, there is little to
be gained by using larger than the minimum 10µF output
capacitor. Nonetheless, larger values of output capacitance
do decrease peak output deviations during a load transient.
Note that bypass capacitors used to decouple individual
components powered by the LT3045-1 increase the ef-
fective output capacitance.
Figure3. COUT and CSET Connections for Best Performance
30451 F02
OUT
SET
12
11
8
9
10
4
5
3
2
1
67
13
Since the SET pin is a high impedance node, unwanted
signals may couple into the SET pin and cause erratic
behavior. This is most noticeable when operating with a
minimum output capacitor at heavy load currents. By-
passing the SET pin with a small capacitance to ground
resolves this issue — 10nF is sufficient.
For applications requiring higher accuracy or an adjust-
able output voltage, the SET pin may be actively driven
by an external voltage source capable of sinking 100µA.
Connecting a precision voltage reference to the SET pin
eliminates any errors present in the output voltage due
to the reference current and SET pin resistor tolerances.
Output Sensing and Stability
The LT3045-1’s OUTS pin provides a Kelvin sense con-
nection to the output. The SET pin resistor’s GND side
provides a Kelvin sense connection to the loads GND side.
Additionally, for ultrahigh PSRR, the LT3045-1 bandwidth
is made quite high (~1MHz), making it very close to a
typical 10µF (1206 case size) ceramic output capacitor’s
self-resonance frequency (~1.6MHz). Therefore, it is very
important to avoid adding extra impedance (ESR and
ESL) outside the feedback loop. To that end, as shown in
C
OUT
R
SET
C
SET
C
IN
OUT
IN
SET
VIOC
LT3045-1
DEMO BOARD
PCB LAYOUT
ILLUSTRATES
4-TERMINAL
CONNECTION
TO COUT
100µA
OUTS
PG
ILIM
30451 F03
GND
PGFB
EN/UV
V
OUT
I
OUT(MAX)
: 500mA
V
IN
LT3045— 1 v \ XSR 20 :3 3:; 2. $35 xsfi \ vsv / Au :3 3:; 2. $35 :3 m3; 2. $35 18
LT3045-1
18
30451fa
For more information www.linear.com/LT3045-1
APPLICATIONS INFORMATION
Give extra consideration to the type of ceramic capacitors
used. They are manufactured with a variety of dielectrics,
each with different behavior across temperature and applied
voltage. The most common dielectrics used are specified
with EIA temperature characteristic codes of Z5U, Y5V,
X5R and X7R. The Z5U and Y5V dielectrics are good for
providing high capacitance in the small packages, but they
tend to have stronger voltage and temperature coefficients
as shown in Figure4 and Figure5. When used with a 5V
regulator, a 16V 10µF Y5V capacitor can exhibit an effective
value as low as 1µF to 2µF for the DC bias voltage applied
over the operating temperature range.
X5R and X7R dielectrics result in more stable character-
istics and are thus more suitable for LT3045-1. The X7R
dielectric has better stability across temperature, while the
X5R is less expensive and is available in higher values.
Nonetheless, care must still be exercised when using
X5R and X7R capacitors. The X5R and X7R codes only
specify operating temperature range and the maximum
capacitance change over temperature. While capacitance
change due to DC bias for X5R and X7R is better than
Y5V and Z5U dielectrics, it can still be significant enough
to drop capacitance below sufficient levels. As shown in
Figure6, capacitor DC bias characteristics tend to improve
as component case size increases, but verification of
expected capacitance at the operating voltage is highly
recommended. Due to its good voltage coefficient in small
case sizes, LTC recommends using Murata’s GJ8 series
ceramic capacitors.
High Vibration Environments
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress upon
it, similar to how a piezoelectric microphone works. For a
ceramic capacitor, this stress can be induced by mechanical
vibrations within the system or due to thermal transients.
LT3045-1 applications in high vibration environments
have three distinct piezoelectric noise generators: ceramic
output, input, and SET pin capacitors. However, due to
LT3045-1’s very low output impedance over a wide fre-
quency range, negligible output noise is generated using
Figure4. Ceramic Capacitor DC Bias Characteristics
Figure5. Ceramic Capacitor Temperature Characteristics
Figure6. Capacitor Voltage Coefficient for Different Case Sizes
DC BIAS VOLTAGE (V)
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
0
–100
CHANGE IN VALUE (%)
–80
642 810 12
30451 F04
14
0
20
–60
–40
X5R
Y5V
–20
16
TEMPERATURE (°C)
–50
–100
CHANGE IN VALUE (%)
–80
250–25 50 75 100
30451 F05
0
20
40
–60
–40 Y5V
–20
125
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
X5R
DC BIAS (V)
1
–100
CHANGE IN VALUE (%)
–80
–60
–40
–20
0
20
5 10 15 20
30451 F06
25
GRM SERIES, 0805, 1.45mm THICK
GRM SERIES, 1206, 1.8mm THICK
GRM SERIES, 1210, 2.2mm THICK
GJ8 SERIES, 1206, 1.9mm THICK
MURATA: 25V,10%,
X7R/X5R, 10µF CERAMIC
LT3045— 1 19
LT3045-1
19
30451fa
For more information www.linear.com/LT3045-1
APPLICATIONS INFORMATION
a ceramic output capacitor. Similarly, due to LT3045-1’s
ultrahigh PSRR, negligible output noise is generated
using a ceramic input capacitor. Nonetheless, given the
high SET pin impedance, any piezoelectric response
from a ceramic SET pin capacitor generates significant
output noise – peak-to-peak excursions of hundreds of
µVs. However, due to the SET pin capacitor’s high ESR
and ESL tolerance, any non-piezoelectrically responsive
(tantalum, electrolytic, or film) capacitor can be used at
the SET pin – although electrolytic capacitors tend to
have high 1/f noise. In any case, use of a surface mount
capacitor is highly recommended.
Stability and Input Capacitance
The LT3045-1 is stable with a minimum 4.7µF IN pin capaci-
tor. LTC recommends using low ESR ceramic capacitors.
In cases where long wires connect the power supply to
the LT3045-1’s input and ground terminals, the use of low
value input capacitors combined with a large load current
can result in instability. The resonant LC tank circuit formed
by the wire inductance and the input capacitor is the cause
and not because of LT3045-1’s instability.
The self-inductance, or isolated inductance, of a wire
is directly proportional to its length. The wire diameter,
however, has less influence on its self-inductance. For
example, the self-inductance of a 2-AWG isolated wire
with a diameter of 0.26" is about half the inductance of a
30-AWG wire with a diameter of 0.01". One foot of 30-AWG
wire has 465nH of self-inductance.
Several methods exist to reduce a wire’s self-inductance.
One method divides the current flowing towards the
LT3045-1 between two parallel conductors. In this case,
placing the wires further apart reduces the inductance; up
to a 50% reduction when placed only a few inches apart.
Splitting the wires connect two equal inductors in parallel.
However, when placed in close proximity to each other,
their mutual inductance adds to the overall self inductance
of the wires — therefore a 50% reduction is not possible
in such cases. The second and more effective technique
to reduce the overall inductance is to place the forward
and return current conductors (the input and ground
wires) in close proximity. Two 30-AWG wires separated
by 0.02" reduce the overall inductance to about one-fifth
of a single wire.
If a battery mounted in close proximity powers the LT3045-
1, a 4.7µF input capacitor suffices for stability. However,
if a distantly located supply powers the LT3045-1, use a
larger value input capacitor. Use a rough guideline of 1µF
(in addition to the 4.7µF minimum) per 6" of wire length.
The minimum input capacitance needed to stabilize the
application also varies with the output capacitance as
well as the load current. Placing additional capacitance
on the LT3045-1’s output helps. However, this requires
significantly more capacitance compared to additional input
bypassing. Series resistance between the supply and the
LT3045-1 input also helps stabilize the application; as little
as 0.1Ω to 0.5Ω suffices. This impedance dampens the
LC tank circuit at the expense of dropout voltage. A better
alternative is to use a higher ESR tantalum or electrolytic
capacitor at the LT3045-1 input in parallel with a 4.7µF
ceramic capacitor.
PSRR and Input Capacitance
For applications utilizing the LT3045-1 for post-regulating
switching converters, placing a capacitor directly at the
LT3045-1 input results in AC current (at the switching
frequency) to flow near the LT3045-1. This relatively high-
frequency switching current generates a magnetic field
that couples to the LT3045-1 output, thereby degrading its
effective PSRR. While highly dependent on the PCB, the
switching pre-regulator, the input capacitance, amongst
other factors, the PSRR degradation can be easily over
30dB at 1MHz. This degradation is present even if the
LT3045-1 is de-soldered from the board, because it ef-
fectively degrades the PSRR of the PC board itself. While
negligible for conventional low PSRR LDOs, LT3045-1’s
ultrahigh PSRR requires careful attention to higher order
parasitics in order to extract the full performance offered
by the regulator.
To mitigate the flow of high-frequency switching current
near the LT3045-1, the LT3045-1 input capacitor can be
entirely removed -- as long as the switching converters
output capacitor is located more than an inch away from
the LT3045-1. Magnetic coupling rapidly decreases with
increasing distance. Nonetheless, if the switching pre-
LT3045— 1
LT3045-1
20
30451fa
For more information www.linear.com/LT3045-1
APPLICATIONS INFORMATION
regulator is placed too far away (conservatively more
than a couple inches) from the LT3045-1, with no input
capacitor present, as with any regulator, the LT3045-1
input will oscillate at the parasitic LC resonance frequency.
Besides, it is generally a very common (and a preferred)
practice to bypass regulator input with some capacitance.
So this option is fairly limited in its scope and not the most
palatable solution.
To that end, LTC recommends using the LT3045-1 demo
board layout for achieving the best possible PSRR perfor-
mance. The LT3045-1 demo board layout utilizes magnetic
field cancellation techniques to prevent PSRR degradation
caused by this high-frequency current flowwhile utilizing
the input capacitor.
Filtering High Frequency Spikes
For applications where the LT3045-1 is used to post-
regulate a switching converter, its high PSRR effectively
suppresses any noise present at the switchers switching
frequency typically 100kHz to 4MHz. However, the very
high frequency (hundreds of MHz) “spikes” beyond the
LT3045-1’s bandwidth — associated with the switcher’s
power switch transition times will almost directly pass
through the LT3045-1. While the output capacitor is partly
intended to absorb these spikes, its ESL will limit its ability
at these frequencies. A ferrite bead or even the inductance
associated with a short (e.g. 0.5”) PCB trace between the
switcher’s output and the LT3045-1’s input can serve as
an LC-filter to suppress these very high frequency spikes.
Output Noise
The LT3045-1 offers many advantages with respect to
noise performance. Traditional linear regulators have
several sources of noise. The most critical noise sources
for a traditional regulator are its voltage reference, error
amplifier, noise from the resistor divider network used for
setting output voltage and the noise gain created by this
resistor divider. Many low noise regulators pin out their
voltage reference to allow for noise reduction by bypassing
the reference voltage.
Unlike most linear regulators, the LT3045-1 does not use
a voltage reference; instead, it uses a 100µA current refer-
ence. The current reference operates with typical noise
current level of 20pA/√Hz (6nARMS over a 10Hz to 100kHz
bandwidth). The resultant voltage noise equals the current
noise multiplied by the resistor value, which in turn is RMS
summed with the error amplifiers noise and the resistor’s
own noise of 4kTR whereby k = Boltzmanns constant
1.38 • 10–23J/K and T is the absolute temperature.
One problem that conventional linear regulators face is
that the resistor divider setting the output voltage gains up
the reference noise. In contrast, the LT3045-1’s unity-gain
follower architecture presents no gain from the SET pin
to the output. Therefore, if a capacitor bypasses the SET
pin resistor, then the output noise is independent of the
programmed output voltage. The resultant output noise
is then set just by the error amplifier’s noise — typically
2nV/√Hz from 10kHz to 1MHz and 0.8µVRMS in a 10Hz
to 100kHz bandwidth using a 4.7µF SET pin capacitor.
Paralleling multiple LT3045-1s further reduces noise by
N, for N parallel regulators.
Refer to the Typical Performance Characteristics section
for noise spectral density and RMS integrated noise over
various load currents and SET pin capacitances.
Set Pin (Bypass) Capacitance: Noise, PSRR, Transient
Response and Soft-Start
In addition to reducing output noise, using a SET pin bypass
capacitor also improves PSRR and transient performance.
Note that any bypass capacitor leakage deteriorates the
LT3045-1s DC regulation. Capacitor leakage of even 100nA
is a 0.1% DC error. Therefore, LTC recommends the use
of a good quality low leakage ceramic capacitor.
Using a SET pin bypass capacitor also soft-starts the output
and limits inrush current. The RC time constant, formed
by the SET pin resistor and capacitor, controls soft-start
time. Ramp-up rate from 0 to 90% of nominal VOUT is:
tSS ≈ 2.3 • RSET • CSET (Fast Start-Up Disabled)
Fast Start-Up
For ultralow noise applications that require low 1/f noise
(i.e. at frequencies below 100Hz), a larger value SET pin
capacitor is required, up to 22µF. While this would normally
significantly increase the regulator’s start-up time, the
LT3045— 1 150mA'k RENZ RPGZ 21
LT3045-1
21
30451fa
For more information www.linear.com/LT3045-1
APPLICATIONS INFORMATION
LT3045-1 incorporates fast start-up circuitry that increases
the SET pin current to about 2mA during start-up.
As shown in the Block Diagram, the 2mA current source
remains engaged while PGFB is below 300mV, unless the
regulator is in current limit, dropout, thermal shutdown
or input voltage is below minimum VIN.
If fast start-up capability is not used, tie PGFB to IN or to
OUT for output voltages above 300mV. Note that doing
so also disables power good functionality.
ENABLE/UVLO
The EN/UV pin is used to put the regulator into a micro-
power shutdown state. The LT3045-1 has an accurate
1.24V turn-on threshold on the EN/UV pin with 130mV
of hysteresis. This threshold can be used in conjunction
with a resistor divider from the input supply to define an
accurate undervoltage lockout (UVLO) threshold for the
regulator. The EN/UV pin current (IEN) at the threshold from
the Electrical Characteristics table needs to be considered
when calculating the resistor divider network:
VIN(UVLO) =1.24V • 1+REN2
REN1
+IEN REN2
The EN/UV pin current (IEN) can be ignored if REN1 is less
than 100k. If unused, tie EN/UV pin to IN.
Programmable Power Good
As illustrated in the Block Diagram, power good thresh-
old is user programmable using the ratio of two external
resistors, RPG2 and RPG1:
VOUT(PG_ THRESHOLD) =0.3V • 1+RPG2
RPG1
+IPGFB RPG2
If the PGFB pin increases above 300mV, the open-collector
PG pin de-asserts and becomes high impedance. The
power good comparator has 7mV hysteresis and 5µs of
deglitching. The PGFB pin current (IPGFB) from the Electrical
Characteristics table must be considered when determining
the resistor divider network. The PGFB pin current (IPGFB)
can be ignored if RPG1 is less than 30k. If power good
functionality is not used, float the PG pin. Please note that
programmable power good and fast start-up capabilities
are disabled for output voltages below 300mV.
Externally Programmable Current Limit
The ILIM pins current limit threshold is 300mV. Connecting
a resistor from ILIM to GND sets the maximum current
flowing out of the ILIM pin, which in turn programs the
LT3045-1s current limit. With a 150mA kΩ programming
scale factor, the current limit can be calculated as follows:
Current Limit =
150mA k
Ω
RILIM
For example, a 1kΩ resistor programs the current limit
to 150mA and a 2kΩ resistor programs the current limit
to 75mA. For good accuracy, Kelvin connect this resistor
to the LT3045-1’s GND pin.
In cases where IN-to-OUT differential is greater than 12V,
the LT3045-1’s foldback circuitry decreases the internal
current limit. As a result, internal current limit may over-
ride the externally programmed current limit level to keep
the LT3045-1 within its safe-operating-area (SOA). See
the Internal Current Limit vs Input-to-Output Differential
graph in the Typical Performance Characteristics section.
As shown in the Block Diagram, the ILIM pin sources current
proportional (1:500) to output current; therefore, it also
serves as a current monitoring pin with a 0V to 300mV
range. If external current limit or current monitoring is
not used, tie ILIM to GND.
Output Overshoot Recovery
During a load step from full load to no load (or light
load), the output voltage overshoots before the regulator
responds to turn the power transistor OFF. Given that there
is no load (or very light load) present at the output, it takes
a long time to discharge the output capacitor.
As illustrated in the Block Diagram, the LT3045-1 incor-
porates an overshoot recovery circuitry that turns on a
current sink to discharge the output capacitor in the event
OUTS is higher than SET. This current is typically about
4mA. No load recovery is disabled for input voltages less
than 2.5V or output voltages less than 1.5V.
LT3045- 1 22
LT3045-1
22
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For more information www.linear.com/LT3045-1
APPLICATIONS INFORMATION
If OUTS is externally held above SET, the current sink
turns ON in an attempt to restore OUTS to its programmed
voltage. The current sink remains ON until the external
circuitry releases OUTS.
Direct Paralleling for Higher Current
Higher output current is obtained by paralleling multiple
LT3045-1s. Tie all SET pins together and all IN pins together.
Connect the OUT pins together using small pieces of PCB
trace (used as a ballast resistor) to equalize currents in
the LT3045-1s. PCB trace resistance in milliohms/inch is
shown in Table 2.
Table 2. PC Board Trace Resistance
WEIGHT (oz) 10mil WIDTH 20mil WIDTH
1 54.3 27.1
2 27.1 13.6
Trace resistance is measured in mΩ/in.
The small worst-case offset of 2mV for each paralleled
LT3045-1 minimizes the required ballast resistor value.
Figure7 illustrates that two LT3045-1s, each using a 20mΩ
PCB trace ballast resistor, provide better than 20% accurate
output current sharing at full load. The two 20mΩ external
resistors only add 10mV of output regulation drop with a
1A maximum current. With a 3.3V output, this only adds
0.3% to the regulation accuracy. As has been discussed
previously, tie the OUTS pin directly to the output capacitor.
More than two LT3045-1s can also be paralleled for even
higher output current and lower output noise. Paralleling
multiple LT3045-1s is also useful for distributing heat on
the PCB. For applications with high input-to-output voltage
differential, an input series resistor or resistor in parallel
with the LT3045-1 can also be used to spread heat.
PCB Layout Considerations
Given the LT3045-1s high bandwidth and ultrahigh
PSRR, careful PCB layout must be employed to achieve
full device performance. Figure8 shows a recommended
layout that delivers full performance of the regulator.
Refer to the LT3045-1’s DC2593A demo board manual
for further details.
Figure7. Parallel Devices
Figure8. Recommended DFN Layout
+
100µA
IN
EN/UV
PGFB
GND
OUT
LT3045-1
ILIM PG 10µF
20mΩ
VOUT
3.3V
I
OUT(MAX)
1A
30451 F07
16.5k
SET
OUTS
+
100µA
IN
EN/UV
PGFB
GND
OUT
LT3045-1
VIOC
VIOC ILIM PG 10µF
20mΩ
10µF
VIN
5V ±5%
SET
OUTS
0.47µF
LT3045— 1 23
LT3045-1
23
30451fa
For more information www.linear.com/LT3045-1
High Efficiency Linear Regulator: Voltage Input-to-
Output Control (VIOC)
The VIOC pin is used to control an upstream switching
converter (e.g. buck, boost, buck-boost, etc) to maintain
a constant voltage across the LT3045-1, regardless of
the LDOs output voltage. This maximizes efficiency
while maintaining PSRR performance. The VIOC pin is
the output of a fast unity-gain amplifier that measures
the difference between IN and OUT or 1.5V, whichever is
higher. As shown in Figure9, the VIOC feature is simple
to use. Just tie the VIOC pin to the upstream switching
converter’s feedback (FB) pin, and this will regulate the
LT3045-1’s input-to-output differential to the switching
converter’s feedback voltage. When paralleling multiple
LT3045-1s, tie the VIOC pin of one of the LT3045-1 to the
upstream switching converter’s feedback pin and float the
remaining VIOC pins.
While the VIOC buffer is inside the switching converter’s
feedback loop, given the VIOC buffer’s high bandwidth,
the switching converters frequency compensation doesnt
need to be adjusted. Phase delay through the VIOC buffer
is typically less than 2° for frequencies as high as 100kHz;
hence, within the switching converters bandwidth (usually
much less than 100kHz), the VIOC buffer will be transpar-
ent and just act like an ideal wire.
For example, for a switching converter with less than
100kHz bandwidth and a phase margin of 50°, using the
VIOC buffer, the phase margin will degrade by at most 2°.
Hence, the phase margin for the switching converter (using
the VIOC pin) will be at least 48°. Given the VIOC buffer is
inside the switching converter’s feedback loop, the total
capacitance on the VIOC pin is required to be below 20pF.
As shown in Figure10, the input-to-output differential
voltage is easily programmable to support different ap-
APPLICATIONS INFORMATION
Figure9. VIOC Basic Operation
LT3045-1
VLDOOUT
: VARIABLE
IOUT(MAX): 500mA
30451 F09
+
IN
EN/UV
PGFB
GND
OUT
VIOC
ILIM PG
10µF
V
IN
SET
OUTS
R1
UPSTREAM
DC/DC
CONVERTER
SWIN
FB
0.47µF
1×
VLDOIN
VFBSWITCHER
Figure10. Programming Input-to-Output Differential
LT3045-1
VOUT: VARIABLE
IOUT(MAX): 500
mA
30451 F10
+
IN
EN/UV
PGFB
GND
OUT
VIOC
ILIM PG
10µF
V
IN
SET
OUTS
R3
R1
R2
UPSTREAM
DC/DC
CONVERTER
SWIN
FB
0.47µF
1×
LT3045— 1 R1 R2 R1 R1 R2 R3 R1
LT3045-1
24
30451fa
For more information www.linear.com/LT3045-1
APPLICATIONS INFORMATION
plication needs (PSRR vs. power dissipation) using the
following equation:
VLDOIN – VLDOOUT =VVIOC =VFBSWITCHER
R1
+
R2
R1
Furthermore, in the event the LT3045-1 SET pin opens up,
the LT3045-1 input voltage can rise up to the switcher’s
input voltage, and thus potentially violate the LT3045-1’s
absolute maximum rating. To prevent this, the maximum
LT3045-1 input voltage can be set using a resistor (R3)
between the VIOC and IN pins of the regulator such that:
V(MAX)LDOIN =VFBSWITCHER
R1
+
R2
+
R3
R1
+ISINK R3
Moreover, the VIOC pin is capable of sourcing 200µA
and sinking 15µA of current. To mitigate the effect of the
sink current on the maximum LDO input voltage (shown
above), choose R1 such that the resistor divider typically
runs at least 100µA.
For VOUT > 1.5V, VIN = VOUT + VVIOC. The VIOC pin volt-
age (and hence the input-to-output differential) can be
programmed anywhere between a minimum of 1V and
a maximum of 4V or VOUT – 0.5V (for VOUT > 1.5V),
whichever is lower. For applications where the feedback
pin of the switching regulator is below 1V, use resistors
R1 and R2 to make sure the VIOC pin is within the afore-
mentioned range. Note that the VIOC pin voltage cannot
be programmed below the upstream switching converters
feedback pin. For VOUT≤1.5V, the VIOC programming
range is 1V ±5%. If VIOC is set to be outside this range,
then the LT3045-1 input voltage will rise to the maximum
value set using R3. If VIOC functionality is not used, float
the VIOC pin.
Given the maximum VIOC programming voltage is de-
pendent on VOUT, care must be taken in setting the VIOC
voltage. For instance, if VIOC is set to 1V, the LDO’s IN-
to-OUT differential will be regulated to 1V for VOUT > 1.5V.
Similarly, if VIOC is set to 2V, the regulator’s IN-to-OUT
differential will be regulated to 2V for VOUT > 2.5V (i.e.
VVIOC + 0.5V). However, if the output voltage is below
2.5V, for this example, then the LDO will not be able to
drive its VIOC pin to the right level of 2V. As a result, the
upstream pre-regulator’s output will rise, thereby caus-
ing the LT3045-1 input voltage to rise to the maximum
voltage set using R3. Hence, for protection under various
fault conditions, the use of R3 to set the maximum VIN
voltage (below 20V) is required.
Typical VIOC Application
Figure11 shows a typical VIOC application used to post-
regulate the output of the LT8608 buck converter. The VIOC
voltage is set at 1V with the maximum LDO input voltage
set to 16.5V. Figure12 shows the LDO’s input and output
voltage when pulsing the LT3045-1’s EN/UV pin, and as
Figure11. Typical LT3045-1 Post-Regulating Application
+
100µA
IN
EN/UV
PGFB
VIOC
GND
OUT
LT3045-1
ILIM PG 10µF
47µF
VIN
20V
4.7µF
VOUT: VARIABLE
IOUT(MAX): 500mA
30451 F11
249Ω
140k
SET
OUTS
LT8608
BST
SW
PG
FB
IN
EN/UV
TR/SS
MODE
RT
INTVCC 7.68k
40.2k
2.2µH
2.21k
GND
10nF
F
0.22µF
fSW = 1MHz
L: XFL4020-222MEC
VLDOIN – VLDOUT = 1V
VMAXLDOIN = 16.5V
LT3045— 1 \ k ng = 33 M) km = Him/Mo mm n: mm W Ink wok FREUUENCV (Hz) wmw f ”V' — Vsn — mow — LDDDUT Ims/mv "m" V5Er=3VT04V k: 51mm — VsEr — Loom — wow 5vxmv \r—— ”V 2vnmv — VENyW — LDOW — mow av av wxmv SUUms/DW ““5 ”Z ‘L; mm Ems/UN 1st m ngpzszm RL: sen Vw Lmsua =2W mm mm ‘LuAn=5UUmA nmA Q SDDmA/DW f, m > Innmwuw ‘ N g ‘ E snmwuw . " New In — woman) — Loom — Luonmac) — LDDW mm — NmseHuuv zanus/mv um VM mM 25
LT3045-1
25
30451fa
For more information www.linear.com/LT3045-1
APPLICATIONS INFORMATION
can be seen, when the LDO is disabled, the LDO input volt-
age goes to the maximum input voltage set by the resistor
divider on the VIOC pin. Figure13 shows the load step
response of the LT8608 using the VIOC buffer. Figure14
shows the LDO’s input and output voltage response to
stepping the set pin from 3V to 4V. Figure15 shows the
LDO’s output and input voltage while ramping the SET
pin from 0V to 10V, and as can be seen, the LT8608’s
output voltage tracks the LT3045’s output voltage when
it is greater than 1.5V. Lastly, Figure16 shows the noise
spectral density at the LT3045-1 input and output.
Figure12. LT3045-1 EN/UV Pulse
V
EN/UV
LDO
IN
LDO
OUT
R
SET
= 33.2kΩ
R
L
= 6.6Ω
V
IN LT8608
= 20V
500ms/DIV
0V
1V/DIV
5V/DIV
0V
30451 F12
Figure13. Load Step Response Using the VIOC Buffer
I
LOAD
LDO
IN
(ac)
LDO
OUT
(ac)
R
SET
= 33.2kΩ
I
LOAD
= 10mA to 500mA
200µs/DIV
0mA
500mA/DIV
100mV/DIV
50mV/DIV
30451 F13
Figure14. Stepping VSET from 3V to 4V (and Back to 3V)
V
SET
LDO
IN
LDO
OUT
V
SET
= 3V TO 4V
I
L
= 500mA
1ms/DIV
0V
1V/DIV
30451 F14
VSET AND LDOOUT ARE OVERLAID
Figure15. Ramping VSET from 0V to 10V (and Back to 0V)
V
SET
LDO
OUT
LDO
IN
I
L
= 500mA
5ms/DIV
2V/DIV
0V
30451 F15
VSET AND LDOOUT ARE OVERLAID
Figure16. LT3045-1’s Input and Output Noise Spectral Density
LDO
IN
= 4.3V
LDO
OUT
= 3.3V
I
LOAD
= 500mA
LDO
OUT
LDO
IN
Noise Floor
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
0.01
0.1
1
10
100
1000
NOISE (µV/√
Hz
)
30451 F16
LT3045— 1
LT3045-1
26
30451fa
For more information www.linear.com/LT3045-1
Thermal Considerations
The LT3045-1 has internal power and thermal limiting
circuits that protect the device under overload conditions.
The thermal shutdown temperature is nominally 165°C
with about 8°C of hysteresis. For continuous normal
load conditions, do not exceed the maximum junction
temperature (125°C for E- and I-grades). It is important to
consider all sources of thermal resistance from junction to
ambient. This includes junction-to-case, case-to-heat sink
interface, heat sink resistance or circuit board-to-ambient
as the application dictates. Additionally, consider all heat
sources in close proximity to the LT3045-1.
The undersides of the DFN and MSOP packages have
exposed metal from the lead frame to the die attachment.
Both packages allow heat to directly transfer from the die
junction to the PCB metal to limit maximum operating
junction temperature. The dual-in-line pin arrangement
allows metal to extend beyond the ends of the package
on the topside (component side) of the PCB.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PCB and its
copper traces. Copper board stiffeners and plated through-
holes can also be used to spread the heat generated by
the regulator.
Tables 3 and 4 list thermal resistance as a function of copper
area on a fixed board size. All measurements were taken
in still air on a 4 layer FR-4 board with 1oz solid internal
planes and 2oz top/bottom planes with a total board thick-
ness of 1.6mm. The four layers were electrically isolated
with no thermal vias present. PCB layers, copper weight,
board layout and thermal vias affect the resultant thermal
resistance. For more information on thermal resistance
and high thermal conductivity test boards, refer to JEDEC
standard JESD51, notably JESD51-7 and JESD51-12.
Achieving low thermal resistance necessitates attention
to detail and careful PCB layout.
Table 3. Measured Thermal Resistance for DFN Package
COPPER AREA
BOARD AREA
THERMAL
RESISTANCETOP SIDE* BOTTOM SIDE
2500mm22500mm22500mm234°C/W
1000mm22500mm22500mm234°C/W
225mm22500mm22500mm235°C/W
100mm22500mm22500mm236°C/W
*Device is mounted on topside
Table 4. Measured Thermal Resistance for MSOP Package
COPPER AREA
BOARD AREA
THERMAL
RESISTANCETOP SIDE* BOTTOM SIDE
2500mm22500mm22500mm233°C/W
1000mm22500mm22500mm233°C/W
225mm22500mm22500mm234°C/W
100mm22500mm22500mm235°C/W
*Device is mounted on topside
Calculating Junction Temperature
Example: Given an output voltage of 3.3V and input voltage
of 5V ± 5%, output current range from 1mA to 500mA,
and a maximum ambient temperature of 85°C, what is the
maximum junction temperature?
The LT3045-1’s power dissipation is:
IOUT(MAX) • (VIN(MAX) – VOUT) + IGND • VIN(MAX)
where:
IOUT(MAX) = 500mA
VIN(MAX) = 5.25V
IGND (at IOUT = 500mA and VIN = 5.25V) = 12.5mA
thus:
PDISS = 0.5A • (5.25V – 3.3V) + 12.5mA • 5.25V = 1W
Using a DFN package, the thermal resistance is in the
range of 34°C/W to 36°C/W depending on the copper area.
Therefore, the junction temperature rise above ambient
approximately equals:
1W • 35°C/W = 35°C
APPLICATIONS INFORMATION
LT3045— 1 27
LT3045-1
27
30451fa
For more information www.linear.com/LT3045-1
APPLICATIONS INFORMATION
The maximum junction temperature equals the maxi-
mum ambient temperature plus the maximum junction
temperature rise above ambient:
TJMAX = 85°C + 35°C = 120°C
Overload Recovery
Like many IC power regulators, the LT3045-1 incorporates
safe-operating-area (SOA) protection. The SOA protection
activates at input-to-output differential voltages greater
than 12V. The SOA protection decreases the current limit
as the input-to-output differential increases and keeps
the power transistor inside a safe operating region for all
values of input-to-output voltages up to the LT3045-1’s
absolute maximum ratings. The LT3045-1 provides some
level of output current for all values of input-to-output dif-
ferentials. Refer to the Current Limit curves in the Typical
Performance Characteristics section. When power is first
applied and input voltage rises, the output follows the input
and keeps the input-to-output differential low to allow the
regulator to supply large output current and start-up into
high current loads.
Due to current limit foldback, however, at high input volt-
ages a problem can occur if the output voltage is low and
the load current is high. Such situations occur after the
removal of a short-circuit or if the EN/UV pin is pulled high
after the input voltage has already turned ON. The load
line in such cases intersects the output current profile at
two points. The regulator now has two stable operating
points. With this double intersection, the input power
supply may need to be cycled down to zero and brought
back up again to make the output recover. Other linear
regulators with foldback current limit protection (such as
the LT1965 and LT1963A) also exhibit this phenomenon,
so it is not unique to the LT3045-1.
Protection Features
The LT3045-1 incorporates several protection features for
battery-powered applications. Precision current limit and
thermal overload protection protect the LT3045-1 against
overload and fault conditions at the device’s output. For
normal operation, do not allow the junction temperature
to exceed 125°C (E-grade, I-grade).
To protect the LT3045-1’s low noise error amplifier, the
SET-to-OUTS protection clamp limits the maximum voltage
between SET and OUTS with a maximum DC current of
20mA through the clamp. So for applications where SET
is actively driven by a voltage source, the voltage source
must be current limited to 20mA or less. Moreover, to limit
the transient current flowing through these clamps during
a transient fault condition, limit the maximum value of the
SET pin capacitor (CSET) to 22µF.
The LT3045-1 also incorporates reverse input protection
whereby the IN pin withstands reverse voltages of up to
–20V without causing any input current flow and without
developing negative voltages at the OUT pin. The regulator
protects both itself and the load against batteries that are
plugged-in backwards.
In circuits where a backup battery is required, several
different input/output conditions can occur. The output
voltage may be held up while the input is either pulled to
GND, pulled to some intermediate voltage, or left open-
circuit. In all of these cases, the reverse-current protection
circuitry prevents current flow from output to the input.
Nonetheless, due to the OUTS-to-SET clamp, unless the
SET pin is floating, current can flow to GND through the
SET pin resistor as well as up to 15mA to GND through
the output overshoot recovery circuitry. This current flow
through the output overshoot recovery circuitry can be
significantly reduced by placing a Schottky diode between
OUTS and SET pins, with its anode at the OUTS pin.
LT3045— 1 LTSflASrl Rum , R1 + RLUAD m Vnunmm ‘5V Rum) GMD OUTPUT CURRENT NmsE = 0 8w A? “SH
LT3045-1
28
30451fa
For more information www.linear.com/LT3045-1
TYPICAL APPLICATIONS
12VIN to 3.3VOUT with 0.8µVRMS Integrated Noise
100µA
IN
EN/UV
PG
GND
OUT
LT3045-1
VIOC ILIM PGFB
453k
10µF
4.7µF
VIN
12V ±5%
200k
4.7µF
VOUT
3.3V
IOUT
200mA
49.9k
30451 TA02
33.2k
SET
OUTS
+
750Ω
Low Noise CC/CV Lab Power Supply Ultralow Noise Current Source for RF Biasing Applications
10µF
4.7µF
OUT
IN
SET
LT3045-1
100µA
OUTS
PGFB
ILIM
GND
PG
EN/UV
30451 TA04
+
4.7µF
OUTPUT CURRENT NOISE = 0.8µVRMS/ROUT
INCREASE R1 (AND RSET) TO REDUCE CURRENT NOISE
RSET
2k
R
LOAD
V
OUT(MAX)
: 15V
R
OUT
= R
1
+ R
LOAD
R1
VIN
1.8V TO 20V
VIOC
10µF
0.47µF
4.7µF
RSET
R
IOUT
V
IN
OUT
IN
SET
LT3045-1
V
OUT
100µA
OUTS
PGFB
ILIM
GND
PG
EN/UV
30451 TA03
+
VOUT(MAX) =100μARSET
IOUT(MAX) =150mA kΩ
RIOUT
VIOC
Vw 4v 1mm 3 av Tumor; LT3045— 1 WM 3 3v @1an 500qu LTaaAsrw LTaaAsrw Vw 5 5v m zuv um I 29
LT3045-1
29
30451fa
For more information www.linear.com/LT3045-1
TYPICAL APPLICATIONS
Programming Undervoltage Lockout
10µF
33.2k
0.47µF
REN2
110k
REN1
49.9k
4.7µF
V
IN
4V Turn-ON
3.4V Turn-OFF
OUT
IN
SET
LT3045-1
V
OUT
3.3V
I
OUT(MAX)
500mA
100µA
OUTS
EN/UV
ILIM
GND
PG
PGFB
30451 TA05
+
VIN(UVLO)RISING =1.24V 1+110k
49.9k
VIOC
Ratiometric Tracking
10µF
0.1µF
10µF
33.2k
10µF
0.1µF
16.9k
V
IN
5.5V TO 20V
V
OUT
3.3V
MIN LOAD 200µA
OUT
IN
SET
LT3045-1
V
OUT
5V
100µA
OUTS
ILIM
GND
30451 TA06
+
PGFB
PG
EN/UV
OUT
IN
SET
LT3045-1
100µA
OUTS
ILIM
GND
+
PGFB
PG
EN/UV
VIOC
VIOC
LT3045— 1 4 M vum = 5V ‘uunMAXL 500qu L 2 5] [(066556 a 4.5 um 6ND ILIM IMF 165k I N=NUMBER ornEmesw PARALLEL R n M :LsnmA-m/LLLWR D-N n R 7 R c :R y-SflD/N
LT3045-1
30
30451fa
For more information www.linear.com/LT3045-1
TYPICAL APPLICATIONS
Paralleling Multiple Devices Using ILIM (Current Monitor) to Cancel Ballast Resistor Drop
Ultralow 1/f Noise Reference Buffer
10µF
4.7µF
4.7µF
OUT
IN
SET
LT3045-1
V
OUT
= 5V
I
OUT(MAX)
500mA
100µA
OUTS
ILIM
GND
LTC6655-5
30451 TA07
+
1,2
3,4,5
6,7
10µF
49.9k
1k
VIN
6V ±5%
PGFB
PG
EN/UV
VIOC
10µF
N = NUMBER OF DEVICES IN PARALLEL
RCDC = CABLE (BALLAST RESISTOR) DROP CANCELLATION RESISTOR
RILIM = CURRENT LIMIT PROGRAMMING RESISTOR
RBALLAST = BALLAST RESISTOR
ILIM = OUTPUT CURRENT LIMIT
10µF
20mΩ
F
10µF
OUT
IN
SET
LT3045-1
100µA
100µA
OUTS
PGFB
ILIM
GND
PG
EN/UV
IN
PGFB
PG
EN/UV
+
16.5k
RILIM
28
RCDC
RILIM = 150mA kΩ/ILIM RCDC N
= 287Ω (FOR 500mA ILIM PER REGULATOR)
RCDC = RBALLAST 500/N
= 5Ω
VOUT = 3.3V
IOUT(MAX) = 1A
287Ω
20mΩ
+
30451 TA08
OUT
LT3045-1
OUTS
SET
ILIM
GND
VIN
5V ±5%
VIOC VIOC
m mum GNU PGFB é IDfluA Ell/LIV . PGFB PG LT3045— 1 mmw w 1mm 6% . Ell/LIV PGFB PG SH 31
LT3045-1
31
30451fa
For more information www.linear.com/LT3045-1
TYPICAL APPLICATIONS
Paralleling Multiple LT3045-1s for 2A Output Current
10µF
10µF
20mΩ
4.7µF
OUT
IN
SET
LT3045-1
100µA
100µA
OUTS
PGFB
ILIM
GND
PG
EN/UV
IN
PGFB
PG
EN/UV
+
8.25k
20mΩ
+
30451 TA09
OUT
LT3045-1
OUTS
SET
ILIM
GND
10µF
10µF
20mΩ
22µF
OUT
IN
SET
LT3045-1
100µA
100µA
OUTS
PGFB
GND
PG
EN/UV
IN
PGFB
PG
EN/UV
+
453k
200k
49.9k
VOUT = 3.3V
IOUT(MAX) = 2A
DROPOUT = 300mV
20mΩ
+
OUT
LT3045-1
OUTS
SET
ILIM
ILIM
GND
OUTPUT NOISE =
0.8µV
RMS
4
=0.4µVRMS
VIN
5V ±5%
VIOC
VIOC
VIOC
VIOC
LT3045— 1 mm NOISE 20W 51‘qu TO IflflkHz) Tfisgflfia name: mu umsmv umsmv VW . moan PERFECT wrwns 7 , 5‘13“; _L Anna znnnv saw 3 g 2563 ‘UUUNV 42.5"V 200K LTSflASrl wma
LT3045-1
32
30451fa
For more information www.linear.com/LT3045-1
TYPICAL APPLICATIONS
Low Noise Wheatstone Bridge Power Supply
10µF
33.2k
4.7µF
200k
453k
49.9k
4.7µF
R2
R1
R3
+
R4
V
IN
5V ±5%
OUT
IN
SET
LT3045-1
30451 TA10
V
OUT
: 3.3V AND I
OUT(MAX)
: 500mA
100µA
OUTS
PGFB
ILIM
GND
PG
EN/UV
RESISTOR
TOLERANCE
BRIDGE PSRR
NOISE AT VBRIDGE
USING LT1763
1%
5%
40dB
26dB
8nVRMS
42.5nVRMS
PERFECT
MATCHING
INFINITE
NOISE AT VBRIDGE
USING LT3045-1
200nVRMS
1000nVRMS
LT1763 NOISE: 20µVRMS (10Hz TO 100kHz)
LT3045-1 NOISE: 0.8µVRMS (10Hz TO 100kHz)
VBRIDGE
+
VIOC
PGFB Disabled without Reverse Input Protection PGFB Disabled with Reverse Input Protection
RSET
10µF
0.47µF
4.7µF
V
IN
OUT
IN
SET
LT3045-1
V
OUT
100µA
OUTS
ILIM
GND
+
30451 TA11
PGFB
PG
EN/UV
VIOC
0.47µF
10µF
1N4148
4.7µF
RSET
V
IN
OUT
IN
SET
V
OUT
100µA
OUTS
PGFB
ILIM
GND
PG
EN/UV
30451 TA12
+
LT3045-1
VIOC
DD Package i ,,,L,,, w ‘0 w L 4 L 17%? N ‘ 2 3 4 5 6 LT3045— 1 33
LT3045-1
33
30451fa
For more information www.linear.com/LT3045-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT3045-1#packaging for the most recent package drawings.
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
0.75 ±0.05
R = 0.115
TYP
16
127
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD12) DFN 0106 REV A
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.23 ±0.05
0.25 ±0.05
2.25 REF
2.38 ±0.05
1.65 ±0.05
2.10 ±0.05
0.70 ±0.05
3.50
±0.05
PACKAGE
OUTLINE
PIN 1 NOTCH
R = 0.20 OR
0.25 × 45°
CHAMFER
2.38 ±0.10
2.25 REF
0.45 BSC
0.45 BSC
DD Package
12-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1725 Rev A)
LT3045— 1 MSE Package
LT3045-1
34
30451fa
For more information www.linear.com/LT3045-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT3045-1#packaging for the most recent package drawings.
MSOP (MSE12) 0213 REV G
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.22 –0.38
(.009 – .015)
TYP
0.86
(.034)
REF
0.650
(.0256)
BSC
12
12 11 10 9 8 7
7
DETAIL “B”
16
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
RECOMMENDED SOLDER PAD LAYOUT
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
2.845 ±0.102
(.112 ±.004)
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102
(.065 ±.004)
0.1016 ±0.0508
(.004 ±.002)
1 2 3 4 5 6
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.406 ±0.076
(.016 ±.003)
REF
4.90 ±0.152
(.193 ±.006)
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.12 REF
0.35
REF
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
0.42 ±0.038
(.0165
±.0015)
TYP
0.65
(.0256)
BSC
MSE Package
12-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev G)
LT3045— 1 35
LT3045-1
35
30451fa
For more information www.linear.com/LT3045-1
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 09/17 Modified Typical Application circuit.
Modified conditions for 3 VIOC curves: IOUT = 1mA.
Modified Figure 11.
1
12
23
LT3045— 1 36 L7me \ E§NGL%%
LT3045-1
36
30451fa
For more information www.linear.com/LT3045-1
LT 0917 REV A • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2017
www.linear.com/LT3045-1
RELATED PARTS
TYPICAL APPLICATION
+
100µA
IN
EN/UV
PGFB
GND
OUT
LT3045-1
ILIM PG 10µF
20mΩ
VOUT
: VARIABLE
IOUT(MAX): 1A
30451 TA13
SET
OUTS
+
100µA
IN
EN/UV
PGFB
GND
OUT
LT3045-1
VIOC
VIOC ILIM PG 10µF
20mΩ
V
IN
SET
OUTS
0.47µF
R3
R1
R2
UPSTREAM
DC/DC CONVERTER
SWIN
FB
Parallel Devices
PART NUMBER DESCRIPTION COMMENTS
LT1761 100mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20µVRMS, VIN = 1.8V to 20V,
TSOT-23 Package
LT1763 500mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20μVRMS, VIN = 1.8V to 20V,
4mm × 3mm DFN and SO-8 Packages
LT3042 200mA, Ultralow Noise and Ultrahigh PSRR LDO 0.8μVRMS Noise and 79dB PSRR at 1MHz, VIN = 1.8V to 20V, 350mV
Dropout Voltage, Programmable Current Limit and Power Good,
3mm × 3mm DFN and MSOP Packages
LT3045 500mA, Ultralow Noise and Ultrahigh PSRR LDO 0.8μVRMS Noise and 76dB PSRR at 1MHz, VIN = 1.8V to 20V, 260mV
Dropout Voltage, Programmable Current Limit and Power Good,
3mm × 3mm DFN and MSOP Packages
LT3065 500mA Low Noise LDO with Soft-Start 300mV Dropout Voltage, Low Noise: 25μVRMS, VIN = 1.8V to 45V,
3mm × 3mm DFN and MSOP Packages
LT3080 1.1A, Parallelable, Low Noise, Low Dropout Linear Regulator 300mV Dropout Voltage (2-Supply Operation), Low Noise: 40μVRMS,
VIN: 1.2V to 36V, VOUT: 0V to 35.7V, Current-Based Reference with
1-Resistor VOUT Set; Directly Parallelable (No Op Amp Required),
Stable with Ceramic Capacitors; TO-220, DD-Pak, SOT-223, MSOP
and 3mm × 3mm DFN-8 Packages; LT3080-1 Version Has Integrated
Internal Ballast Resistor
LT3085 500mA, Parallelable, Low Noise, Low Dropout Linear
Regulator
275mV Dropout (2-Supply Operation), Low Noise: 40μVRMS, VIN: 1.2V
to 36V, VOUT: 0V to 35.7V, Current-Based Reference with 1-Resistor
VOUT Set, Directly Parallelable (No Op Amp Required), Stable with
Ceramic Capacitors; MS8E and 2mm × 3mm DFN-6 Packages

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