8T49N524I Datasheet by Renesas Electronics America Inc

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IDT8T49N524NLGI REVISION A JANUARY 23, 2014 1 ©2014 Integrated Device Technology, Inc.
DATA SHEET
Programmable FemtoClock® NG LVPECL/LVDS
Dual 4-Output Fractional Clock Generator
IDT8T49N524I
General Description
The IDT8T49N524I is an eight output programmable any-rate dual
clock generator with selectable LVDS or LVPECL outputs. Both clock
generators use Fractional Output Dividers to be able to generate out-
put frequencies that are independent of each other and independent
of the input frequency. Output frequencies for both clock generators
are generated from a single crystal or reference clock.
Clock Generator A supports three different factory-programmed
default frequencies that can be selected from using only the FSEL
control pins. Alternatively any desired output frequency can be
programmed over the I2C serial port. The chosen output frequency is
then driven out the QA0 to QA3 outputs.
Clock Generator B supports a single factory-programmed default
frequency. It can also be programmed for any output frequency via
the serial port. The output frequency is driven out the QB0 to QB3
outputs.
Some examples of frequency configurations that can be achieved
are shown in Table 5A. Please consult IDT for programming software
that can be used to determine the required settings for any desired
configuration.
Excellent phase noise performance is achieved with IDT’s fourth
Generation FemtoClock® NG PLL technology, which delivers
sub-0.5ps RMS phase jitter in the integer divide mode.
Features
Fourth Generation FemtoClock® NG PLL technology
Eight outputs selectable as LVPECL or LVDS
Input selectable: fundamental mode crystal or clock reference
Supports fundamental mode crystals from 10MHz - 40MHz
CLK, nCLK input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
Input frequencies from 5MHz up to 800MHz
Two independent output frequencies can be generated
Output frequencies independent of each other and of input
Output frequencies from 15.234MHz - 645MHz, and
975MHz - 1290MHz, (See Table 5D for details)
RMS phase jitter at 125MHz (12kHz - 20MHz): 0.282ps (typical)
RMS phase jitter at 156.25MHz (12kHz - 20MHz):
0.278ps (typical)
Full 2.5V or 3.3V power supply
I2C programming interface
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
VCC / VCCA / VCCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V (LVPECL only)
2.5V / 2.5V / 2.5V
Pin Assignment
12345678910
31
32
33
34
35
36
37
38
39
40
20
19
18
17
16
15
14
13
12
11
30292827 26 25 24 2322 21
V
EE_B
SCLK
SDATA
V
EE
VCCA
LOCK
VEE
VCC
CLK_SEL
V
EE_A
FSEL1
VCC
XTAL_IN
VEE
ADDR_SEL
FSEL0
nCLK
CLK
V
EE
XTAL_OUT
QA0
nQA0
QA1
nQA1
VCCO_A
QA2
nQA2
QA3
nQA3
V
EE_A
QB0
nQB0
V
CCO_B
QB2
nQB2
QB3
V
EE_B
nQB3
nQB1
QB1
IDT8T49N524I
40 Lead VFQFN
6mm x 6mm x 0.925mm
4.65mm x 4.65mm EPad
NL Package
Top View
ANINT,1[5:D] ANFRACJU Deleclur . Charge Pump Femmclack®NG vco +N|N1,2[5:n] +M|NT [8:1] +NFHACJ|1
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 2 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Block Diagram
Pulldown
PU/PD
LOCK
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
CLK SEL
XTAL_IN
XTAL_OUT
CLK
nCLK
FSEL0
FSEL1
SCLK
SDATA
ADDR_SEL
Xtal
Osc
FemtoClock®NG
VCO
Divider,
Output Type
&
Output
Enable
Selection
÷P[1:0]
0
1
OUTPUT ENABLE
OUTPUT STYLE
8
Phase
Detector
+
Charge
Pump
Pulldown
Pulldown
Pulldown
Pullup
Pullup
Pulldown
÷MINT [8:1] ÷2
÷NINT_2[5:0]
÷NFRAC_2[15:0]
÷2
÷NINT_1[5:0]
÷NFRAC_1[15:0]
÷2
÷2
1
0
x2
0
1
1
0
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 3 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Pin Description & Characteristics
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 2 QA0, nQA0 Output Clock generator A differential output pair. LVPECL or LVDS interface levels.
3, 4 QA1, nQA1 Output Clock generator A differential output pair. LVPECL or LVDS interface levels.
5V
CCO_A Power Clock generator A output supply pin.
6, 7 QA2, nQA2 Output Clock generator A differential output pair. LVPECL or LVDS interface levels.
8, 9 QA3, nQA3 Output Clock generator A differential output pair. LVPECL or LVDS interface levels.
10, 13, 18,
21, 31, 34,
37, 40
VEE Power Negative supply pins.
11,
12
XTAL_IN
XTAL_OUT Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
14 CLK Input Pulldown Non-inverting differential clock input.
15 nCLK Input Pullup/
Pulldown Inverting differential clock input. Internal resistor bias to VCC/2.
16,
20
FSEL0,
FSEL1 Input Pulldown Frequency select pins. See Table 4A for frequency selection.
LVCMOS/LVTTL interface levels.
17 ADDR_SEL Input Pulldown I2C Address select pin. LVCMOS/LVTTL interface levels.
19, 38 VCC Power Core supply pins.
22, 23 nQB3, QB3 Output Clock generator B differential output pair. LVPECL or LVDS interface levels.
24, 25 nQB2, QB2 Output Clock generator B differential output pair. LVPECL or LVDS interface levels.
26 VCCO_B Power Clock generator B output supply pin.
27, 28 nQB1, QB1 Output Clock generator B differential output pair. LVPECL or LVDS interface levels.
29, 30 nQB0, QB0 Output Clock generator B differential output pair. LVPECL or LVDS interface levels.
32 SCLK Input Pullup I2C Clock Input. LVCMOS/LVTTL interface levels.
33 SDATA Input/Output Pullup I2C Data Input. Input: LVCMOS/LVTTL interface levels. Output: Open
Drain.
35 VCCA Power Analog supply pin.
36 LOCK Output PLL Lock Indicator.
39 CLK_SEL Input Pulldown
Input source control pin. LVCMOS/LVTTL interface levels.
0 = Crystal is input source (default)
1 = CLK, nCLK input reference clock is input source
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 3.5 pF
RPULLDOWN Input Pulldown Resistor 51 k
RPULLUP Input Pullup Resistor 51 k
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 4 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Register Map
Table 3. I2C Register Map
Register
Binary
Register
Address
Register Bit
D7 D6 D5 D4 D3 D2 D1 D0
0 00000 MINT0[7] MINT0[6] MINT0[5] MINT0[4] MINT0[3] MINT0[2] MINT0[1] MINT0[0]
1 00001 MINT1[7] MINT1[6] MINT1[5] MINT1[4] MINT1[3] MINT1[2] MINT1[1] MINT1[0]
2 00010 MINT2[7] MINT2[6] MINT2[5] MINT2[4] MINT2[3] MINT2[2] MINT2[1] MINT2[0]
3 00011 reserved reserved reserved reserved reserved reserved reserved reserved
4 00100 unused unused NINTB[5] NINTB[4] NINTB[3] NINTB[2] NINTB[1] NINTB[0]
5 00101 unused unused unused unused unused unused DIVB_BYPASS DIVB_INT
6 00110 NFRACB[7] NFRACB[6] NFRACB[5] NFRACB[4] NFRACB[3] NFRACB[2] NFRACB[1] NFRACB[0]
7 00111 NFRACB[15] NFRACB[14] NFRACB[13] NFRACB[12] NFRACB[11] NFRACB[10] NFRACB[9] NFRACB[8]
8 01000 NINTA_0[5] NINTA_0[4] NINTA_0[3] NINTA_0[2] NINTA_0[1] NINTA_0[0] CP0[1] CP0[0]
9 01001 NINTA_1[5] NINTA_1[4] NINTA_1[3] NINTA_1[2] NINTA_1[1] NINTA_1[0] CP1[1] CP1[0]
10 01010 NINTA_2[5] NINTA_2[4] NINTA_2[3] NINTA_2[2] NINTA_2[1] NINTA_2[0] CP2[1] CP2[0]
11 01011 reserved reserved reserved reserved reserved reserved reserved reserved
12 01100 OE_QB3 OE_QB2 OE_QB1 OE_QB0 OE_QA3 OE_QA2 OE_QA1 OE_QA0
13 01101 unused unused unused unused LVDS_SEL PLL_BYPASS P[1] P[0]
14 01110 1 1
DOUBLER_
ENABLE unused unused unused DIVA_BYPASS DIVA_INT
15 01111 unused unused 111111
16 10000 NFRACA_0[15] NFRACA_0[14] NFRACA_0[13] NFRACA_0[12] NFRACA_0[11] NFRACA_0[10] NFRACA_0[9] NFRACA_0[8]
17 10001 NFRACA_1[15] NFRACA_1[14] NFRACA_1[13] NFRACA_1[12] NFRACA_1[11] NFRACA_1[10] NFRACA_1[9] NFRACA_1[8]
18 10010 NFRACA_2[15] NFRACA_2[14] NFRACA_2[13] NFRACA_2[12] NFRACA_2[11] NFRACA_2[10] NFRACA_2[9] NFRACA_2[8]
19 10011 reserved reserved reserved reserved reserved reserved reserved reserved
20 10100 NFRACA_0[7] NFRACA_0[6] NFRACA_0[5] NFRACA_0[4] NFRACA_0[3] NFRACA_0[2] NFRACA_0[1] NFRACA_0[0]
21 10101 NFRACA_1[7] NFRACA_1[6] NFRACA_1[5] NFRACA_1[4] NFRACA_1[3] NFRACA_1[2] NFRACA_1[1] NFRACA_1[0]
22 10110 NFRACA_2[7] NFRACA_2[6] NFRACA_2[5] NFRACA_2[4] NFRACA_2[3] NFRACA_2[2] NFRACA_2[1] NFRACA_2[0]
23 10111 reserved reserved reserved reserved reserved reserved reserved reserved
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 5 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Function Tables
Table 4A. Frequency Select Table
Table 4B. I2C Register Function Descriptions
FSEL1 FSEL0
Pre-scaler
Ratio
Feedback
Divider Ratio QAn Operation QBn Operation
0 (default) 0 (default) P MINT0 NINTA_0 NFRACA_0 NINTB NFRACB
0 1 P MINT1 NINTA_1 NFRACA_1 NINTB NFRACB
1 0 P MINT2 NINTA_2 NFRACA_2 NINTB NFRACB
11 Reserved
Bits Name Function
MINTn[7:0] Integer Feedback Divider Register n
(n = 0...2)
Sets the integer feedback divider value. See Table 5B for the feedback
divider coding.
P[1:0] Input Divider Register Sets the PLL input divider. The divider value has the range of 1, 2, 4 and
8. See Table 5C for the divider coding.
NINTA_n[5:0] Output Divider A - Integer Portion n
(n = 0...2)
Sets the integer portion of the output divider A. See Table 5D for the
output divider coding.
NFRACA_n[15:0] Output Divider A - Fractional Portion
(n = 0...2)
Sets the fractional portion of the output divider A. See Table 5D for the
output divider coding.
NINTB[5:0] Output Divider B - Integer Portion Sets the integer portion of the output divider B. See Table 5D for the
output divider coding.
NFRACB[15:0] Output Divider B - Fractional Portion Sets the fractional portion of the output divider B. See Table 5D for the
output divider coding.
CPn[1:0] PLL Bandwidth n (n = 0...2) Sets the FemtoClock® NG PLL Charge Pump current to support the
selected operating frequency. See Table 5E.
OE_Qxx Output Enable
Sets the desired output to Active or High impedance.
0 = Output is high-impedance (default)
1 = Output is active.
LVDS_SEL Output Style
Selects differential output style
0 = LVPECL (default)
1 = LVDS
PLL_BYPASS PLL Bypass
Bypasses PLL. Input to phase detector is routed through output dividers
A and B to the output fanout buffers. Dividers should be programmed for
integer divide operation (DIVA_INT = DIVB_INT = 0) for proper operation.
DOUBLER_
ENABLE Input Doubler
Enables the input frequency doubler.
0 = Input frequency presented directly to PLL
1 = Input frequency doubled before PLL (default)
DIVA_BYPASS Bypass Output Divider A Bypasses output divider A. QAn output frequency is VCO/2.
DIVB_BYPASS Bypass Output Divider B Bypasses output divider B. QBn output frequency is VCO/2.
DIVA_INT Divider A Integer Mode Disables fractional portion of divider A. Setting this bit will provide better
phase noise performance in cases where the fractional portion is 0.
DIVB_INT Divider B Integer Mode Disables fractional portion of divider B. Setting this bit will provide better
phase noise performance in cases where the fractional portion is 0.
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 6 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Frequency Configuration
The IDT8T49N524I is capable of being loaded with up to three
different frequency configurations. Use of the FSEL[1:0] inputs allows
a user to select from any of those three configurations at any time.
The three frequency configurations may be pre-loaded at the factory
or can be setup at any time over the I2C serial port. Table 5A shows
a number of example configurations.
It is recommended to use the IDT8T49N524I Configuration SW to
generate the desired configurations for the device.
Table 5A. Frequency Configuration Examples
Output Frequencies
(MHz)
Input or Crystal
Frequency (MHz)
Input Divider
P
Effective Feedback
Divider Ratio M
VCO Frequency
(MHz) fVCO
Effective Output
Divider Ratio N
62.5 25 1 100 2500 40
78.125 25 1 100 2500 32
100 25 1 96 2400 24
106.25 25 1 102 2550 24
125 25 1 100 2500 20
133.333 25 1 96 2400 18
150 25 1 96 2400 16
156.25 25 1 100 2500 16
166.666 25 1 80 2000 12
187.5 25 1 90 2250 12
200 25 1 96 2400 12
212.5 25 1 102 2550 12
250 25 1 100 2500 10
300 25 1 96 2400 8
312.5 25 1 100 2500 8
375 25 1 90 2250 6
400 25 1 96 2400 6
625 25 1 100 2500 4
1250 25 1 100 2500 2
30.72 25 1 88 2200 71.6145833333
61.44 25 1 88 2200 35.8072916667
76.8 25 1 88 2200 28.6458333333
122.88 25 1 88 2200 17.9153094463
148.5 25 1 88 2200 14.8148148148
153.6 25 1 88 2200 14.3229166667
155.52 25 1 88 2200 14.1460905350
159.375 25 1 88 2200 13.8039215686
160 25 1 88 2200 13.75
161.1328125 25 1 88 2200 13.6533333333
164.355 25 1 88 2200 13.3856590916
166.6285 25 1 88 2200 13.2030234924
184.32 25 1 88 2200 11.9357638889
311.04 25 1 88 2200 7.0730452675
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 7 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Table 5B. Feedback Divider MINTn Coding Table 5C. Input Pre-scaler (P) Coding
Table 5D. Output Divider NINTx and NFRACx Coding
NOTE: When operating in Integer-mode, set NFRACx = 0, DIVA_INT = 1, and NINTx to desired output frequency configurations.
NOTE 1: When operating in fractional-mode, output frequency is limited to 322.5MHz. NFRACx must be set to 0 if NINTx = 000010 or 000011.
NOTE 2: The output divider is bypassed to generate frequencies in this range on the output. Set DIVx_INT and DIVx_BYPASS bits for the
desired output divider (A or B) for a ÷2 operation on that output bank.
Table 5E. Charge Pump CPn[1:0] Settings
NOTE: FemtoClock® NG PLL stability is only guaranteed over the feedback divider ranges listed in Table 5B.
Register Bit
Feedback Divide Ratio MMINTn[7:0]
000000xx Do Not Use
0000100 8
0000101 10
0000110 12
0000111 14
00001000 thru 11111111 16 thru 510
Register Bit
Input Pre-scaler Divide Ratio PP1 P0
00 1
01 2
10 4
11 8
Frequency Divider N
Output Frequency Register Bit
fMIN (MHz) fMAX (MHz) NINTx[5:0]
Do Not Use 00000x
2 975 1290 xxxxxx (NOTE 2)
4 487.5 645 000010
6 325 430 000011
8 – 9.99999999 (NOTE 1) 195 322.5 000100
N – N +1.99999999 1950/ (N + 1.99999999) 2580 / N ...
126 - 127.99999999 15.234 20.476 111111
Register Bit
Feedback Divider
(M) Value Range
CPn[1] CPn[0] Minimum Maximum
001648
0 1 49 100
1 0 101 192
1 1 193 510
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 8 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Power-up Default Configuration Description
The IDT8T49N524I supports a variety of options such as different
output styles, number of programmed default frequencies, output en-
able and operating temperature range. The device options and de-
fault frequencies must be specified at the time of order and are
programmed by IDT prior to shipment. The document, Programma-
ble FemtoClock® NG Product Ordering Guide specifies the available
order codes.
Other order codes with respective programmed frequencies are
available from IDT upon request. After power-up changes to the
output frequencies, and state of outputs, active or high impedance,
are controlled by FSEL[1:0] or the I2C interface.
Serial Interface Configuration Description
The IDT8T49N524I has an I2C-compatible configuration interface to
access any of the internal registers (Table 3) for frequency and PLL
parameter programming. The IDT8T49N524I acts as a slave device
on the I2C bus and has the address 0b110111x, where x is set by the
value on ADDR_SEL input. (See Tables 6A & 6B). The interface
accepts byte-oriented block write and block read operations. An
address byte (P) specifies the register address (Table 3) as the byte
position of the first register to write or read. Data bytes (registers) are
accessed in sequential order from the lowest to the highest byte
(most significant bit first, see Table 6C, 6D). Read and write block
transfers can be stopped after any complete byte transfer. It is
recommended to terminate the I2C read or write transfer after
accessing byte #23 by sending a stop command.
For full electrical I2C compliance, it is recommended to use external
pull-up resistors for SDATA and SCLK. The internal pull-up resistors
have a size of 50K typical.
Table 6A. I2C Device Slave Address ADDR_SEL = 0 (default)
Table 6B. I2C Device Slave Address ADDR_SEL = 1
Table 6C. Block Write Operation
Table 6D. Block Read Operation
1101110R/W
1101111R/W
Bit 1 2:8 9 10 11:18 19 20:27 28 29-36 37 ... ... ...
Description START Slave Address W (0) ACK Address Byte P ACK Data
Byte (P) ACK
Data
Byte
(P+1)
ACK
Data
Byte
...
ACK STOP
Length (bits) 1711818181811
Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39-46 47 ... ... ...
Description START Slave
Address
W
(0)
A
C
K
Address
byte P
A
C
K
Repeated
START
Slave
address
R
(1)
A
C
K
Data Byte
(P)
A
C
K
Data Byte
(P+1)
A
C
K
Data Byte
...
A
C
K
STOP
Length (bits) 1 711811 7118181811
ce, 0 32 4“ 455“ 50“
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 9 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
DC Electrical Characteristics
Table 7A. LVPECL Power Supply DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C
Table 7B. LVPECL Power Supply DC Characteristics, VCC = VCCO_A = VCCO_B = 2.5V±5%, VEE = 0V, TA = -40°C to 85°C
Item Rating
Supply Voltages, VCC, VCCA, VCCO_A, VCCO_B 3.6V
Inputs, VI
XTAL_IN
Other Input
0V to 2V
-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
Outputs, IO (LVDS)
Continuous Current
Surge Current
Outputs, IO (LVCMOS)
Continuous Current (LOCK)
Continuous Current (SDATA)
Surge Current (all)
50mA
100mA
10mA
15mA
12mA
10mA
22mA
Package Thermal Impedance, JA 32.4C/W (0 mps)
Storage Temperature, TSTG -65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Core Supply Voltage 3.135 3.3 3.465 V
VCCA Analog Supply Voltage VCC – 0.18 3.3 VCC V
VCCO_A, VCCO_B Output Supply Voltage 3.135 3.3 3.465 V
IEE Power Supply Current 264 300 mA
ICCA Analog Supply Current 15 18 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Core Supply Voltage 2.375 2.5 2.625 V
VCCA Analog Supply Voltage VCC – 0.17 2.5 VCC V
VCCO_A, VCCO_B Output Supply Voltage 2.375 2.5 2.625 V
IEE Power Supply Current 256 290 mA
ICCA Analog Supply Current 14 17 mA
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 10 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Table 7C. LVPECL Power Supply DC Characteristics,
VCC = 3.3V±5%, VCCO_A = VCCO_B = 2.5V±5%, VEE = 0V, TA = -40°C to 85°C
Table 7D. LVDS Power Supply DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V±5%, TA = -40°C to 85°C
Table 7E. LVDS Power Supply DC Characteristics, VCC = VCCO_A = VCCO_B = 2.5V±5%, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Core Supply Voltage 3.135 3.3 3.465 V
VCCA Analog Supply Voltage VCC – 0.18 3.3 VCC V
VCCO_A, VCCO_B Output Supply Voltage 2.375 2.5 2.625 V
IEE Power Supply Current 264 300 mA
ICCA Analog Supply Current 15 18 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Core Supply Voltage 3.135 3.3 3.465 V
VCCA Analog Supply Voltage VCC – 0.18 3.3 VCC V
VCCO_A, VCCO_B Output Supply Voltage 3.135 3.3 3.465 V
ICC Power Supply Current 188 212 mA
ICCA Analog Supply Current 15 18 mA
ICCO_A + ICCO_B Output Supply Current 148 167 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Core Supply Voltage 2.375 2.5 2.625 V
VCCA Analog Supply Voltage VCC – 0.17 2.5 VCC V
VCCO_A, VCCO_B Output Supply Voltage 2.375 2.5 2.625 V
ICC Power Supply Current 177 200 mA
ICCA Analog Supply Current 14 17 mA
ICCO_A + ICCO_B Output Supply Current 147 166 mA
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 11 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Table 7F. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Table 7G. Differential DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
NOTE 1: VIL should not be less then -0.3V.
NOTE 2: Common mode input voltage is at the crosspoint.
Table 7H. LVPECL DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C
NOTE: VCCO_X denotes VCCO_A and VCCO_B.
NOTE 1: Outputs terminated with 50 to VCCO_X – 2V.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage VCC = 3.3V 2 VCC + 0.3 V
VCC = 2.5V 1.7 VCC + 0.3 V
VIL Input Low Voltage VCC = 3.3V -0.3 0.8 V
VCC = 2.5V -0.3 0.7 V
IIH
Input
High Current
SCLK,
SDATA VCC = VIN = 3.465V or 2.625V 5 µA
FSEL[1:0],
CLK_SEL,
ADDR_SEL
VCC = VIN = 3.465V or 2.625V 150 µA
IIL
Input
Low Current
SCLK,
SDATA VCC = 3.465V or 2.625V, VIN = 0V -150 µA
FSEL[1:0],
CLK_SEL,
ADDR_SEL
VCC = 3.465V or 2.625V, VIN = 0V -5 µA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
IIH
Input
High Current CLK, nCLK VCC = VIN = 3.465V or 2.625V 150 µA
IIL
Input
Low Current
nCLK VCC = 3.465V or 2.625V, VIN = 0V -150 µA
CLK VCC = 3.465V or 2.625V, VIN = 0V -5 µA
VPP
Peak-to-Peak Voltage:
NOTE 1 0.15 1.3 V
VCMR
Common Mode Input
Voltage; NOTE 1, NOTE 2 VEE + 0.5 VDD – 0.85 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH Output High Voltage; NOTE 1 VCCO_X – 1.1 VCCO_X – 0.75 V
VOL Output Low Voltage; NOTE 1 VCCO_X – 2.0 VCCO_X – 1.6 V
VSWING
Peak-to-Peak Output Voltage
Swing 0.6 1.0 V
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 12 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Table 7I. LVPECL DC Characteristics, VCC = VCCO_A = VCCO_B = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
NOTE: VCCO_X denotes VCCO_A and VCCO_B
NOTE 1: Outputs terminated with 50 to VCCO_X – 2V.
Table 7J. LVPECL DC Characteristics, VCC = 3.3V±5%, VCCO_A = VCCO_B = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
NOTE: VCCO_X denotes VCCO_A and VCCO_B
NOTE 1: Outputs termination with 50 to VCCO_X – 2V.
Table 7K. LVDS DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C
Table 7L. LVDS DC Characteristics, VCC = VCCO_A = VCCO_B = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Table 8. Crystal Characteristics
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH Output High Voltage; NOTE 1 VCCO_X – 1.2 VCCO_X – 0.75 V
VOL Output Low Voltage; NOTE 1 VCCO_X – 2.0 VCCO_X – 1.6 V
VSWING
Peak-to-Peak Output Voltage
Swing 0.5 1.0 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH Output High Voltage; NOTE 1 VCCO_X – 1.2 VCCO_X – 0.75 V
VOL Output Low Voltage; NOTE 1 VCCO_X – 2.0 VCCO_X – 1.5 V
VSWING
Peak-to-Peak Output Voltage
Swing 0.5 1.0 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD Differential Output Voltage 247 454 mV
VOD VOD Magnitude Change 50 mV
VOS Output Low Voltage; 1.15 1.375 V
VOS VOS Magnitude Change 50 mV
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD Differential Output Voltage 247 454 mV
VOD VOD Magnitude Change 50 mV
VOS Output Low Voltage; 1.15 1.375 V
VOS VOS Magnitude Change 50 mV
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 10 40 MHz
Equivalent Series Resistance (ESR) 50
Load Capacitance (CL) 12 18 pF
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 13 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
AC Electrical Characteristics
Table 9. AC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ± 5% or 2.5V ± 5% VEE = 0V, TA = -40°C to 85°
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All Integer mode characterizations done using 25MHz, 12pf resonant Crystal.
NOTE: Output dividers using even integer divide ratios.
NOTE 1: Please refer to Phase Noise Plots.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: Refer to fLOCK in Parameter Measurement Information.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fDIFF_IN Differential Input Frequency 5 800 MHz
fPFD
Phase / Frequency Detector
Frequency 5100MHz
fVCO VCO Frequency 1950 2580 MHz
tjit(Ø) RMS Phase Jitter, Random;
NOTE 1
100MHz, Integration Range:
12kHz – 20MHz 0.303 0.405 ps
125MHz, Integration Range:
12kHz – 20MHz 0.282 0.383 ps
156.25MHz, Integration Range:
12kHz – 20MHz 0.278 0.371 ps
212.5MHz, Integration Range:
12kHz – 20MHz 0.341 0.734 ps
tsk(b) Bank Skew;
NOTE 2, 3
LVPECL Outputs LVDS_SEL = 0 40 ps
LVDS Outputs LVDS_SEL = 1
tLOCK PLL Lock Time; NOTE 4 25 ms
tR / tF
Output
Rise/Fall Time
LVPECL Outputs 20% - 80%, LVDS_SEL = 0 100 400 ps
LVDS Outputs 20% - 80%, LVDS_SEL = 1 100 400 ps
odc Output Duty
Cycle
LVPECL N 45 55 %
LVDS
LVPECL N > 3 40 60 %
LVDS
tSSetup Time SDATA to SCLK 5 ns
tHHold Time SDATA from
SCLK 5ns
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IDT8T49N524NLGI REVISION A JANUARY 23, 2014 14 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Typical Phase Noise at 125MHz
Noise Power (dBc / Hz)
Offset Frequency (Hz)
125MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.282ps (typical)
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IDT8T49N524NLGI REVISION A JANUARY 23, 2014 15 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Parameter Measurement Information
3.3V Core/3.3V LVPECL Output Load Test Circuit
3.3V Core/2.5V LVPECL Output Load Test Circuit
2.5V Core/2.5V LVDS Output Load Test Circuit
2.5V Core/2.5V LVPECL Output Load Test Circuit
3.3V Core/3.3V LVDS Output Load Test Circuit
Differential Input Levels
2V
-1.3V+0.165V
VCCA
2V
VCC,
VCCO_X
SCOPE
Qx
nQx
VEE
VCC
2.8V±0.04V
-0.5V±0.125V
VCCA
2V
2.8V±0.04V
VCCO_X
SCOPE
Qx
nQx
2.5V±5%
POWER SUPPLY
+–
Float GND
VCC,
VCCA
VCCO_X
VCC,
2V
-0.5V±0.125V
VCCA
2V
VCCO_X
3.3V ±5%
VCCA
VCC,
VCCO_X
VCC
VEE
CLK
nCLK
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IDT8T49N524NLGI REVISION A JANUARY 23, 2014 16 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Parameter Measurement Information, continued
RMS Phase Jitter
LVDS Output Rise/Fall Time
Output Skew
PLL Lock Time
LVPECL Output Rise/Fall Time
Differential Output Duty Cycle/Output Pulse Width/Period
20%
80% 80%
20%
tRtF
VOD
nQx
Qx
Qx
Qy
nQx
nQy
nQx
Qx
nQx
Qx
DC Inpm
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 17 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Parameter Measurement Information, continued
Offset Voltage Setup Differential Output Voltage Setup
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 18 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
XTAL_IN to ground.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
It is recommended that CLK, nCLK be left unconnected in frequency
synthesizer mode.
LVCMOS Control Pins
All control pins have internal pullup or pulldown resistors; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Outputs:
LVPECL Outputs
All unused LVPECL output pairs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating there should be no trace
attached.
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 19 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1= VCC/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1in the center of the input voltage swing. For
example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2
value should be adjusted to set V1 at 1.25V. The values below are for
when both the single ended swing and VCC are at the same voltage.
This configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the input will at-
tenuate the signal in half. This can be done in one of two ways. First,
R3 and R4 in parallel should equal the transmission line impedance.
For most 50 applications, R3 and R4 can be 100. The values of
the resistors can be increased to reduce the loading for slower and
weaker LVCMOS driver. When using single-ended signaling, the
noise rejection benefits of differential signaling are reduced. Even
though the differential input can handle full rail LVCMOS signaling, it
is recommended that the amplitude be reduced. The datasheet spec-
ifies a lower differential amplitude, however this only applies to differ-
ential signals. For single-ended applications, the swing can be larger,
however VIL cannot be less than -0.3V and VIH cannot be more than
VCC + 0.3V. Though some of the recommended components might
not be used, the pads should be placed in the layout. They can be uti-
lized for debugging purposes. The datasheet specifications are char-
acterized and guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
Receiv er
+
-R4
100
R3
100
RS Zo = 50 Ohm
Ro
Driver
VCC
VCC
R2
1K
R1
1K
C1
0.1uF
Ro + Rs = Zo
V1
VC C VC C
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 20 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by one
side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 2A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be in-
creased to reduce the loading for a slower and weaker LVCMOS driv-
er. Figure 2B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and guar-
anteed by using a quartz crystal as the input.
Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface
Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface
VCC XTAL_OUT
XTAL_IN
R1
100
R2
100
Zo = 50 ohmsRs
Ro
Zo = Ro + Rs
C1
.1uf
LVCMOS Driver
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IDT8T49N524NLGI REVISION A JANUARY 23, 2014 21 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
3.3V Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 3A to 3E show interface examples
for the CLK/nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. Please consult
with the vendor of the driver component to confirm the driver
termination requirements. For example, in Figure 3A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
Figure 3A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 3C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 3E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 3B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 3D. CLK/nCLK Input Driven by a
3.3V LVDS Driver
R1
50Ω
R2
50Ω
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
nCLK
3.3V
LVHSTL
IDT
LVHSTL Driver
Differential
Input
3
.
3V
C
L
K
n
C
L
K
3
.
3V
3
.
3V
LVPE
CL
Differential
In
p
u
t
H
CSL
*R
3
*
R4
C
L
K
n
C
L
K
3
.
3V
3
.
3V
Diff
e
r
e
nti
a
l
In
p
u
t
CLK
nCLK
Differential
Input
LVPECL
3.3V
Zo = 50Ω
Zo = 50Ω
3.3V
R1
50Ω
R2
50Ω
R2
50Ω
3.3V
R1
100Ω
LVDS
CLK
nCLK
3.3V
Receiver
Zo = 50Ω
Zo = 50Ω
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IDT8T49N524NLGI REVISION A JANUARY 23, 2014 22 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
2.5V Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 4A to 4E show interface examples
for the CLK/nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. Please consult
with the vendor of the driver component to confirm the driver
termination requirements. For example, in Figure 4A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
Figure 4A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 4C. CLK/nCLK Input Driven by a
2.5V LVPECL Driver
Figure 4E. CLK/nCLK Input Driven by a
2.5V LVDS Driver
Figure 4B. CLK/nCLK Input Driven by a
2.5V LVPECL Driver
Figure 4D. CLK/nCLK Input Driven by a
2.5V HCSL Driver
R1
50
R2
50
1.
8V
Zo
=
50
Zo
=
50
C
L
K
nC
L
K
2
.
5V
L
VH
S
T
L
I
DT
O
pen Emitte
r
L
VH
S
TL Driv
er
Differential
I
nput
R3
250
R4
250
R1
6
2.
5
R2
6
2.
5
2
.
5V
Zo
=
50
Zo
=
50
C
L
K
nC
L
K
2
.
5V
2
.
5V
L
VPE
CL
Differential
I
nput
2
.
5V
R1
1
00
L
VD
S
C
L
K
nC
L
K
2
.
5V
Differential
I
nput
Zo
=
50
Zo
=
50
C
L
K
nC
L
K
D
i
ffe
r
e
nti
a
l
I
nput
L
VPE
CL
2
.
5V
Zo
=
50
Zo
=
50
2
.
5V
R1
50
R2
50
R3
1
8
HCSL
*
R
3
33
*R4
33
C
L
K
nC
L
K
2
.
5V
2
.
5V
Zo
=
50
Zo
=
50
D
i
ffe
r
e
nti
a
l
I
nput
R1
50
R2
50
*O
ptional
R
3
a
n
d
R4
ca
n
be
0
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 23 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
LVDS Driver Termination
For a general LVDS interface, the recommended value for the termi-
nation impedance (ZT) is between 90 and 132. The actual value
should be selected to match the differential impedance (Z0) of your
transmission line. A typical point-to-point LVDS design uses a 100
parallel resistor at the receiver and a 100 differential transmis-
sion-line environment. In order to avoid any transmission-line reflec-
tion issues, the components should be surface mounted and must be
placed as close to the receiver as possible. IDT offers a full line of
LVDS compliant devices with two types of output structures: current
source and voltage source. The standard termination schematic as
shown in Figure 5A can be used with either type of output structure.
Figure 5B, which can also be used with both output types, is an op-
tional termination with center tap capacitance to help filter common
mode noise. The capacitor value should be approximately 50pF. If us-
ing a non-standard termination, it is recommended to contact IDT
and confirm if the output structure is current source or voltage source
type. In addition, since these outputs are LVDS compatible, the input
receiver’s amplitude and common-mode input range should be veri-
fied for compatibility with the output.
LVDS Termination
LVDS
Driver
LVDS
Driver
LVDS
Receiver
LVDS
Receiver
ZT
C
ZO ZT
ZO ZT
ZT
2
ZT
2
Figure 5A. Standard Termination
Figure 5B. Optional Termination
33V LVFECL Inpm
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 24 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recom-
mended only as guidelines.
The differential outputs are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating resis-
tors (DC current path to ground) or current sources must be used for
functionality. These outputs are designed to drive 50 transmission
lines. Matched impedance techniques should be used to maximize
operating frequency and minimize signal distortion. Figures 6A and
6B show two different layouts which are recommended only as guide-
lines. Other suitable clock layouts may exist and it would be recom-
mended that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process variations.
Figure 6A. 3.3V LVPECL Output Termination Figure 6B. 3.3V LVPECL Output Termination
R1
84
R2
84
3.3V
R3
125
R4
125
Zo = 50
Zo = 50
LVPECL Input
3.3V
3.3V
+
_
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 25 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Termination for 2.5V LVPECL Outputs
Figure 7A and Figure 7B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to VCCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground
level. The R3 in Figure 7B can be eliminated and the termination is
shown in Figure 7C.
Figure 7A. 2.5V LVPECL Driver Termination Example
Figure 7C. 2.5V LVPECL Driver Termination Example
Figure 7B. 2.5V LVPECL Driver Termination Example
2.5V LVPECL Driver
V
CCO
= 2.5V
2.5V
2.5V
50
50
R1
250
R3
250
R2
62.5
R4
62.5
+
2.5V LVPECL Driver
V
CCO
= 2.5V
2.5V
50
50
R1
50
R2
50
+
2.5V LVPECL Driver
VCCO = 2.5V
2.5V
50
50
R1
50
R2
50
R3
18
+
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IDT8T49N524NLGI REVISION A JANUARY 23, 2014 26 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 8. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the ther-
mal/electrical performance. Sufficient clearance should be designed
on the PCB between the outer edges of the land pattern and the inner
edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a sol-
der joint, thermal vias are necessary to effectively conduct from the
surface of the PCB to the ground plane(s). The land pattern must be
connected to ground through these vias. The vias act as “heat pipes”.
The number of vias (i.e. “heat pipes”) are application specific and de-
pendent upon the package power dissipation as well as electrical
conductivity requirements. Thus, thermal and electrical analysis
and/or testing are recommended to determine the minimum number
needed. Maximum thermal and electrical performance is achieved
when an array of vias is incorporated in the land pattern. It is recom-
mended to use as many vias connected to ground as possible. It is
also recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/slug
and the thermal land. Precautions should be taken to eliminate any
solder voids between the exposed heat slug and the land pattern.
Note: These recommendations are to be used as a guideline only.
For further information, please refer to the Application Note on the
Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance
Lead frame Base Package, Amkor Technology.
Figure 8. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
SOLDERSOLDER PINPIN EXPOSED HEAT SLUG
PIN PAD PIN PADGROUND PLANE LAND PATTERN
(GROUND PAD)
THERMAL VIA
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 27 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Schematic Layout
Figure 9 (next page) shows an example IDT8T49N524I application
schematic that focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set. In this example, the input reference is LVDS and the outputs have
all been configured for LVPECL.
In this example a 12pF parallel resonant Fox FX325BS 25MHz
crystal is used with load caps C1 = C2 = 10pF. The load caps are
recommended for frequency accuracy, but these may be adjusted for
different board layouts. Crystals with different load capacities may be
used, but the load capacitors will have to be changed accordingly. If
different crystal types are used, please consult IDT for
recommendations.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The IDT8T49N524I provides
separate power supplies to isolate any high switching noise from
coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1µF capacitor in each power pin filter and the resistor of the VDDA
power filters should be placed on the device side of the PCB and the
other components can be placed on the opposite side.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequency. This
low-pass filter starts to attenuate noise at approximately 10kHz. If a
specific frequency noise component with high amplitude interference
is known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if required,
additional filtering be added. Additionally general design practice for
power plane voltage stability suggests adding bulk capacitances in
the general area of all devices.
W |J|| W? 77 ‘H1i”*5’14 % ”pt-HIM IIHH 6%; 1. «wet
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 28 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Figure 9. IDT8T49N524I Application Schematic
R9
180
R8
18 0
U1
SCLK
32 SDA TA
33
VEE
40
VCCA 35
VE E
34
VCC 38
CLK_SEL
39
LO C K 36
VE E
37
QA0 1
nQA0 2
nQA1 4
QA1 3
VC C O_A 5
QA2 6
nQA2 7
VEE
10
QA3 8
nQA3 9
VEE
21
FSEL1
20
nCLK
15
CLK
14
VCC 19
VE E
18
XTAL _O U T
12
XTAL _I N
11
AD D _S EL
17
FSEL0
16
VE E
13
QB0 30
nQB0 29
QB1 28
nQB1 27
VEE
31
QB2 25
nQB2 24
VC C O_B 26
QB3 23
nQB3 22
ePAD
41
QA1
nQA1
nQA2
QA2
nQA3
QA3
nQB0
QB0
nQB1
QB1
nQB2
QB2
nQB3
LVDS Driv er
Zo = 50 Ohm
Zo = 50 Ohm
R3
10 0 QB3
VCCA
VC C
C9
0.1uF
3.3V
C10
10uF
FB 1
BLM18BB221SN1
12
R4 10
C6
10uF
C20
0.1uF
VCCO
C22
0. 1 u F
VC C O
LO C K
VC C
C13
0. 1 u F
VC C A
C14
0. 1 u F
X1
1
3
2 4
25 MHz
(12pf)
XTAL_ IN
C1
10pF C2
10pF
XTAL _O U T
Fox FX325BS Crystal
C11
0. 1 u F
Place each 0.1uF bypass cap
directly ad jacent to its
correspondi ng VCC, VCCA,
VCCO_A or V CCO_B pin.
VC C
VC C
To Logic
Inp ut
pin s
VC C
RU2
Not Install
RU1
1K
RD2
1K
To L og i c
Inp ut
pin s
RD1
Not Install
Logic Control Input Examples
Set Logic
Input to '1' Set Logic
Input to '0'
VCCO
C23
0.1uF
3.3V
C24
10uF
FB2
B LM18B B221SN1
1 2
+3. 3V PE C L R ec eiv er
+
-
nQA0
R6
50
R7
50
Zo = 50 Ohm
Zo = 50 Ohm
R5
50
3.3V
SDA TA
SCLK
R1
4.7K R2
4. 7 K
CLK_SEL
ADD_SEL
FS EL1
FS EL0
50
50
CML Receiver
IN
IN
Zo = 50 Ohm
Zo = 50 Ohm
Optional 3. 3v PECL AC Termination
for PECL swing compliant 2.5V CML Receiver
C12
0.1u
C15
0.1u
2.5V
QA0
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 29 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
LVPECL Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8T49N524I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the IDT8T49N524I is the sum of the core power plus the power dissipated due to loading.
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 300mA = 1039.5mW
Power (outputs)MAX = 31.6mW/Loaded Output pair
If all outputs are loaded, the total power is 8 * 31.6mW = 252.8mW
Total Power_MAX (3.465V, with all outputs switching) = 1039.5mW + 252.8mW = 1292.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 27.9°C/W per Table 10 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.292W * 27.9°C/W = 121.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 10. Thermal Resistance JA for 40 Lead VFQFN, Forced Convection
NOTE 1: JA simulation is performed with 4-layers, 8in. x 8in. PCB.
NOTE 2: JEDEC Standard requires air flow.
JA by Velocity
Meters per Second 012
Multi-Layer PCB; NOTE 1 27.9°C/W 21.6°C/W 19.1°C/W
Multi-Layer PCB, JEDEC Standard NOTE 2 25.7°C/W 23.4°C/W
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 30 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
LVPECL output driver circuit and termination are shown in Figure 10.
Figure 10. LVPECL Driver Circuit and Termination
To calculate power dissipation per output pair due to loading, use the following equations which assume a 50 load, and a termination voltage
of VCCO – 2V.
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.75V
(VCCO_MAX – VOH_MAX) = 0.75V
For logic low, VOUT = VOL_MAX = VCCO_MAX 1.6V
(VCCO_MAX – VOL_MAX) = 1.6V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.75V)/50] * 0.75V = 18.75mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.6V)/50] * 1.6V = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 31.6mW
VOUT
VCCO
VCCO
- 2V
Q1
RL
50Ω
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 31 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
LVDS Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8T49N524I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the IDT8T49N524I is the sum of the core power plus the analog power plus the power dissipated due to the load.
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
Power (core)MAX = VCC_MAX * (ICC_MAX + ICCA_MAX) = 3.465V * (212mA + 18mA) = 796.95mW
Power (outputs)MAX = VCCO_MAX * ICCO_MAX = 3.465V * 167mA = 578.66mW
Total Power_MAX = 796.95mW + 578.66mW = 1375.61mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 27.9°C/W per Table 11 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.376W * 27.9°C/W = 123.40°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 11. Thermal Resistance JA for 40 Lead VFQFN, Forced Convection
NOTE 1: JA simulation is performed with 4-layers, 8in. x 8in. PCB.
NOTE 2: JEDEC Standard requires air flow.
JA by Velocity
Meters per Second 012
Multi-Layer PCB; NOTE 1 27.9°C/W 21.6°C/W 19.1°C/W
Multi-Layer PCB, JEDEC Standard NOTE 2 25.7°C/W 23.4°C/W
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 32 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Reliability Information
Table 12. JA vs. Air Flow Table for a 40 Lead VFQFN
NOTE 1: JA simulation is performed with 4-layers, 8in. x 8in. PCB.
NOTE 2: JEDEC Standard requires air flow.
Transistor Count
The transistor count for IDT8T49N524I is: 35,322
JA by Velocity
Meters per Second 012
Multi-Layer PCB; NOTE 1 27.9°C/W 21.6°C/W 19.1°C/W
Multi-Layer PCB, JEDEC Standard NOTE 2 25.7°C/W 23.4°C/W
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IDT8T49N524NLGI REVISION A JANUARY 23, 2014 33 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
40 Lead VFQFN Package Outline and Package Dimensions
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IDT8T49N524NLGI REVISION A JANUARY 23, 2014 34 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
40 Lead VFQFN Package Outline and Package Dimensions, continued
40 Lead VFQFN, D2/E2 EPAD Dimensions: 4.65mm x 4.65mm
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 35 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Ordering Information
Table 13. Ordering Information
NOTE: For the specific -ddd order codes, refer to Programmable FemtoClock® NG Product Ordering Guide document.
Part/Order Number Marking Package Shipping Packaging Temperature
8T49N524-dddNLGI IDT8T49N524-dddNLGI “Lead-Free” 40 Lead VFQFN Tray -40C to 85C
8T49N524-dddNLGI8 IDT8T49N524-dddNLGI “Lead-Free” 40 Lead VFQFN Tape & Reel -40C to 85C
IDT8T49N524NLGI REVISION A JANUARY 23, 2014 36 ©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Revision History Sheet
Rev Table Page Description of Change Date
A In footer, corrected year of date from 2012 to 2013. 4/2/2013
AT5D
T9
1
12
18
32
33
Features: Changed ‘Output frequencies from 15.5MHz - 650MHz, and 975MHz -
1300MHz’ to ‘Output frequencies from 15.234MHz - 645MHz, and 975MHz - 1290MHz,
(See Table 5D for details)’
Changed fMAX column: 1300 to 1290; 650 to 645; 433.33333 to 430; 2600 to 2580;
20.635 to 20.476; NOTE 1: 325MHz to 322.5MHz.
fVCO: 1910MHz Min to 1950MHz Min; 2500MHz Max to 2580MHz Max
2nd paragraph: 18pF to 12pF
Updated Applications schematic to include Fox crystal
7/10/2013
A
T13
8, 35
40
Changed name of the IDT8T49N00xI Programmable FemtoClock® NG Product Ordering
Information document to Programmable FemtoClock® Ordering Product Information
Deleted quantity from Tape & Reel, Deleted Lead Free note.
8/21/2013
A
T13
1
8
35
Changed title to Programmable FemtoClock® NG LVPECL/LVDS Dual 4-Output
Fractional Clock Generator.
Changed text from ‘Programmable FemtoClock® Ordering Product Information’ to
Programmable FemtoClock® NG Product Ordering Guide’.
Changed Note from ‘Programmable FemtoClock® Ordering Product Information’ to
Programmable FemtoClock® NG Product Ordering Guide’.
9/26/13
A 2 Block diagram - corrected FSELx pin names. 1/23/14
‘DID'IZ www.lDT.com
IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product
features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in
customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of mer-
chantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or
safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners.
Copyright 2014. All rights reserved.
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