ADE9078 Datasheet by Analog Devices Inc.

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ANALOG DEVICES formance, Polyphase Energy Metering AFE ADE9078 Documenl Feedback Moat hulda IRQD lRQl
High Performance, Polyphase
Energy Metering AFE
Data Sheet
ADE9078
Rev. 0 Document Feedback
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Technical Support www.analog.com
FEATURES
7 high performance analog-to-digital converters (ADCs)
101 dB signal-to-noise ratio (SNR)
10,000:1 dynamic range
Wide input range: ±1 V, 0.707 V rms full scale
Differential inputs
±25 ppm/°C maximum channel temperature drift (including
ADC, internal VREF, and PGA drift) enabling Class 0.2
meters with standard external components
Power quality measurements
Line frequency: 1 measurement per phase
Zero crossing detection, zero-crossing timeout
Phase angle measurements
Supports current transformers (CTs) and Rogowski coil
(di/dt) sensors
Multiple range phase/gain compensation for CTs
Digital integrator for Rogowski coils
Flexible waveform buffer
Able to resample waveform to ensure 64 points per line
cycle for ease of external harmonic analysis
Events can trigger waveform storage
Simplifies data collection for IEC 61000-4-7 harmonic analysis
Advanced metrology feature set
Total active power, volt-amperes reactive (VAR), volt-
amperes (VA), watthour, VAR-hour, and VA-hour
Fundamental VAR and VAR-hour
Current and voltage rms per phase (xIRMS, xVRMS)
Supports active energy standards: IEC 62053-21,
IEC 62053-22; EN50470-3; OIML R46, ANSI C12.20
Supports reactive energy standards: IEC 62053-23,
IEC 62053-4
High speed communication port
10 MHz serial peripheral interface (SPI)
APPLICATIONS
Polyphase meters
Power quality monitoring
Protective device
GENERAL DESCRIPTION
The ADE90781 is a highly accurate, fully integrated energy
metering device. Interfacing with both current transformer
(CT) and Rogowski coil sensors, the ADE9078 enables users to
develop a 3-phase metrology platform, which achieves high
performance for Class 1 up to Class 0.2 meters.
FUNCTIONAL BLOCK DIAGRAM
SINC4
AND
DECIMATION
LDO
1.25V
REFERENCE
CF1
TO CF4
IRQ0
IRQ1
SPI
ADE9078
PGA
ADC
PGA
ADC
PGA
ADC
PGA
ADC
PGA
ADC
PGA
ADC
PGA
ADC METROLOGY FEATURES
(PER PHASE)
IRMS, VRMS
ACTIVE POWER, VA
WATTHOUR, VA-Hr
WAVEFORM BUFFER
LINE FREQUENCY
ETC.
14331-001
Figure 1.
The ADE9078 integrates seven high performances ADCs and a
flexible DSP core. An integrated high end reference ensures low
drift over temperature with a combined drift of less than
±25 ppm/°C maximum per channel, each of which includes a
programmable gain amplifier (PGA) and ADC.
The ADE9078 offers an integrated flexible waveform buffer that
stores samples at a fixed data rate or a sampling rate that varies
based on line frequency to ensure 64 points per line cycle. These
two options make it easy to implement harmonic analysis in an
external processor according to IEC 61000-4-7.
Two power modes are provided to enable detection of meter
tampering: PSM2 uses a low power comparator to compare
current channels to a threshold and indicates whether it is
exceeded on the IRQ0 and IRQ1 outputs; PSM1 enables fast
measurement of current and voltage rms (xVRMS and xIRMS),
active power, and VA R during a tamper.
The ADE9078 allows advanced and highly accurate energy
measurements, enabling one platform to cover a wide range of
meters, through a combination of various high end metrology
features and superior analog performance.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329; 6,262,600; 7,489,526; 7,558,080. Other patents are pending.
ADE9078 Data Sheet
Rev. 0 | Page 2 of 107
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Timing Characteristics ................................................................ 7
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 12
Total Energy Linearity over Supply and Temperature ........... 12
Fundamental Energy Linearity with Fifth Harmonic over
Supply and Temperature ............................................................ 13
Total Energy Error over Frequency .......................................... 14
RMS Linearity over Temperature and RMS Error over
Frequency .................................................................................... 15
Energy Linearity Repeatability ................................................. 16
Total Energy and RMS Linearity with Integrator On ............ 17
Total Energy Error over Frequency with Integrator On ....... 18
Test Circuit ...................................................................................... 19
Terminology .................................................................................... 20
Theory Of Operation ..................................................................... 22
ADC ............................................................................................. 22
Crystal Oscillator/External Clock ............................................ 24
Power Management .................................................................... 25
Measurements (Normal Mode) ................................................ 27
Measurements (PSM1) .............................................................. 45
Measurements (PSM2) .............................................................. 54
Key Features .................................................................................... 55
Flexible Waveform Buffer with Resampling ........................... 55
Multipoint Phase/Gain Calibration ......................................... 55
RMS of Sum of Instantaneous Currents Measurement ......... 55
Tamper Modes ............................................................................ 55
Power Factor................................................................................ 55
Zero-Crossing Timeout Detection ........................................... 55
Line Period Measurement ......................................................... 55
Angle Measurement ................................................................... 55
Phase Sequence Error Detection .............................................. 55
Quick Start ....................................................................................... 56
Applications Information .............................................................. 57
Non-Blondel Compliant Meters ............................................... 58
Applying the ADE9078 to a 4-Wire Wye Service ...................... 58
Applying the ADE9078 to a 3-Wire Delta Service ................. 59
Applying the ADE9078 to a Non-Blondel Compliant, 4-Wire
Wye Service ................................................................................. 60
Applying the ADE9078 to a Non-Blondel Compliant, 4-Wire
Delta Service ............................................................................... 60
Service Type Summary .............................................................. 60
Accessing On-Chip Data ............................................................... 62
SPI Protocol Overview .............................................................. 62
SPI Write ...................................................................................... 63
SPI Read ....................................................................................... 63
SPI Burst Read ............................................................................ 63
SPI Protocol CRC ....................................................................... 64
Additional Communication Verification Registers ............... 64
CRC of Configuration Registers............................................... 65
Configuration Lock .................................................................... 65
Waveform Buffer ............................................................................ 66
Fixed Data Rate Waveforms ...................................................... 67
Fixed Data Rate Waveforms Filling and Trigger-Based Modes .. 68
Resampled Waveforms .............................................................. 70
Configuring the Waveform Buffer ........................................... 70
Burst Read Waveform Buffer Samples from SPI .................... 71
Interrupts/Events ............................................................................ 74
Interrupts (IRQ0 and IRQ1) ..................................................... 74
EVENT ........................................................................................ 74
Status Bits in Additional Registers ........................................... 74
Troubleshooting .............................................................................. 75
SPI Does Not Work .................................................................... 75
PSM2_CFG Register Value Is Not Retained When Going
from PSM2 or PSM3 to PSM0 .................................................. 75
Register Information ...................................................................... 76
Register Details ........................................................................... 88
Outline Dimensions ..................................................................... 107
Ordering Guide ........................................................................ 107
Data Sheet ADE9078
Rev. 0 | Page 3 of 107
REVISION HISTORY
8/2016—Revision 0: Initial Version
Table L
ADE9078 Data Sheet
Rev. 0 | Page 4 of 107
SPECIFICATIONS
VDD = 2.7 V to 3.63 V, GND = AGND = DGND = 0 V, on-chip reference, CLKIN = 12.288 MHz crystal (XTAL), TMIN to TMAX = −40°C to
+85°C for minimum and maximum specifications, TA = 25°C (typical) for typical specifications.
Table 1.1
Parameter Min Typ Max Unit Test Conditions/Comments
ACCURACY
Measurement error per phase
Total Active Energy 0.1 % Over a dynamic range of 5000 to 1, 10 sec
accumulation; gain compensation only
0.2 % Over a dynamic range of 10,000 to 1, 20 sec
accumulation; gain compensation only
Total Reactive Energy 0.1 % Over a dynamic range of 5000 to 1, 10 sec
accumulation; gain compensation only
0.2 % Over a dynamic range of 10,000 to 1, 20 sec
accumulation; gain compensation only
Total Apparent Energy 0.1 % Over a dynamic range of 1000 to 1, 2 sec
accumulation
0.5
%
Over a dynamic range of 5000 to 1, 10 sec
accumulation
Fundamental Reactive 0.1 % Over a dynamic range of 5000 to 1, 2 sec
accumulation
0.2 % Over a dynamic range of 10,000 to 1,
20 sec accumulation
IRMS, VRMS 0.1 % Over a dynamic range of 1000 to 1
0.5 % Over a dynamic range of 5000 to 1
Active Power, VAR 0.2 % Over a dynamic range of 5000 to 1, 1 sec
accumulation
Power Factor (PF) ±0.001 Over a dynamic range of 5000 to 1
64-Point per Line Cycle
Resampled Data
0.1
%
An FFT is performed to receive the magni-
tude response; this error is the worst case
error in the fundamental magnitude caused
by resampling algorithm distortion; input
signal is 50 Hz fundamental on voltage
channel and fundamental with ninth har-
monic at half of full scale on current channel
0.3 % An FFT is performed to receive the magni-
tude response; this error is the magnitude
error of ninth harmonic caused by the
resampling algorithm distortion input signal
is 50 Hz fundamental with ninth harmonic
at half of full scale on current channel
72 dB Amplitude of highest spur; input signal is
50 Hz fundamental and ninth harmonic
at half of full scale on the current channel
3 % An FFT is performed to receive the magni-
tude response; this error is the magnitude
error of 31st harmonic caused by resampling
algorithm distortion; input signal is 50 Hz
fundamental with 31st harmonic at half of
full scale on the current channel
38 dB Amplitude of highest spur; input signal is
50 Hz fundamental and 31st harmonic at
half of full scale on the current channel
Line Period Measurement 0.001 Hz Resolution at 50 Hz
Current to Current, Voltage to
Voltage, and Voltage to
Current Angle Measurement
0.036 Degrees Resolution at 50 Hz; voltage and current
at 1/10th of full scale
PSM1 IRMS 0.2 % Accuracy achieved 40 ms after entering
PSM1 mode at 600:1
Data Sheet ADE9078
Rev. 0 | Page 5 of 107
Parameter Min Typ Max Unit Test Conditions/Comments
PSM1 Active Power 0.2 % Accuracy achieved 40 ms after entering
PSM1 mode at 600:1
PSM2 Peak Current Detection 5 % Accuracy of current detection threshold,
achieved 120 ms after entering PSM2 mode
at 660:1
ADC See the ADC section
PGA Gain Settings (GAIN) 1, 2, or 4 V/V PGA gain setting is referred to as GAIN
Differential Input Voltage Range
(VxP − VxN, IxP − IxN)
−1/GAIN +1/GAIN V 0.707 V rms; when VREF = 1.25 V, this
voltage corresponds to 53 million codes
Maximum Operating Voltage on
Analog Input Pins (VxP, VxN,
IxP, and IxN)
−0.6 0.6 V Voltage on the pin with respect to
ground (GND = AGND = DGND =
REFGND), VREF = 1.25 V
Signal-to-Noise Ratio (SNR)2 VIN = full scale/gain; see the Terminology
section
PGA = 1 101 dB 4 kSPS sinc4 + infinite impulse response
(IIR) low-pass filter (LPF) output
97 dB 16 kSPS sinc4 output
PGA = 4 97 dB 4 kSPS sinc4 + IIR LPF output
94 dB 16 kSPS sinc4 output
Total Harmonic Distortion (THD)2 See the Terminology section
PGA = 1 −106 dB 4 kSPS sinc4 + IIR LPF output
−106 dB 16 kSPS sinc4 output
PGA = 4 −115 dB 4 kSPS sinc4 + IIR LPF output
−112 dB 16 kSPS sinc4 output
Signal-to-Noise and Distortion
Ratio (SINAD)2
See the Terminology section
PGA = 1 100 dB 4 kSPS sinc4 + IIR LPF output
96 dB 16 kSPS sinc4 output
PGA = 4 96 dB 4 kSPS sinc4 + IIR LPF output
93 dB 16 kSPS sinc4 output
Spurious-Free Dynamic Range
(SFDR)2
See the Terminology section
PGA = 1 110 dB 4 kSPS sinc4 + IIR LPF output
Output Pass Band (−0.1 dB) See the Terminology section
Sinc4 Outputs 0.672 kHz 16 kSPS sinc4 output
Sinc4 + IIR LPF Outputs 0.672 kHz 4 kSPS output
Output Bandwidth (−3 dB)2 See the Terminology section
Sinc4 Outputs 3.6325 kHz 16 kSPS sinc4 output
Sinc4 + IIR LPF Outputs 1.6 kHz 4 kSPS output
Crosstalk2 −120 dB
See the Terminology section, at 50 Hz
and 60 Hz
AC Power Supply Rejection
Ratio (AC PSRR)2
−120 dB
See the Terminology section, at 50 Hz
and 60 Hz
AC Common-Mode Rejection
Ratio (AC CMRR)2
−115 dB At 100 Hz and 120 Hz
Gain Error ±0.3 ±1 % See the Terminology section
Gain Drift2 ±3 ppm/°C See the Terminology section
Offset ±0.36 ±3.8 mV See the Terminology section
Offset Drift2 0 ±6 μV/°C See the Terminology section
ADE9078 Data Sheet
Rev. 0 | Page 6 of 107
Parameter Min Typ Max Unit Test Conditions/Comments
Channel Drift (PGA, ADC,
Internal Voltage Reference)
±7 ±25 ppm/°C PGA = 1, internal VREF
±7 ±25 ppm/°C PGA = 2, internal VREF
±7 ±25 ppm/°C PGA = 4, internal VREF
Differential Input Impedance (DC) 330 366 See the Terminology section, PGA = 1
160 180 PGA = 2
80 90 PGA = 4
INTERNAL VOLTAGE REFERENCE Nominal 1.25 V ±1 mV
Voltage Reference 1.250 V TA = 25°C, REF pin
Temperature Coefficient2 ±5 ±20 ppm/°C TA = −40°C to +85°C
EXTERNAL VOLTAGE REFERENCE
External Voltage Reference Input
Voltage (REF)
1.2, 1.25 V
REFGND must be tied to GND, AGND, and
DGND; 1.25 V external reference is preferred;
the full-scale values mentioned in this data
sheet are for a voltage reference of 1.25 V
Average Reference Current 120 μA/V
CRYSTAL OSCILLATOR CLKIN = 12.288 MHz ± 30 ppm (see the
Crystal Oscillator/External Clock section)
Input Clock Frequency 12.165 12.288 12.411 MHz
Internal Capacitance on CLKIN
and CLKOUT
4 pF
Internal Feedback Resistance
Between CLKIN and CLKOUT
2.5
Transconductance (gm) 9 mA/V
EXTERNAL CLOCK INPUT
Input Clock Frequency 12.165 12.288 12.411 MHz
Duty Cycle2 45:55 50:50 55:45 %
CLKIN Logic Inputs 3.3 V tolerant
Input Voltage
High, VINH 1.2 V VDD = 2.7 V to 3.63 V
Low, VINL 0.5 V VDD = 2.7 V to 3.63 V
LOGIC INPUTS
PM0, PM1, RESET, MOSI, SCLK,
and SS
Input Voltage
High, VINH 2.4 V VDD = 2.7 V to 3.63 V
Low, VINL 0.8 V VDD = 2.7 V to 3.63 V
Input Current, IIN 15 μA VIN = 0 V
Internal Capacitance, CIN 10 pF
LOGIC OUTPUTS
MISO, IRQ0, and IRQ1 V
DD = 2.97 V to 3.63 V
Output Voltage
High, VOH 2.4 V ISOURCE = 4 mA
Low, VOL 0.8 V ISINK = 4 mA
Internal Capacitance, CIN 10 pF
CF1, CF2, CF3, and CF4 VDD = 2.97 V to 3.63 V
Output Voltage
High, VOH 2.4 V ISOURCE = 8 mA
Low, VOL 0.8 V ISINK = 8 mA
Internal Capacitance, CIN 10 pF
Data Sheet ADE9078
Rev. 0 | Page 7 of 107
Parameter Min Typ Max Unit Test Conditions/Comments
LOGIC OUTPUTS
MISO, IRQ0, and IRQ1 V
DD = 2.7 V
Output Voltage
High, VOH 2.4 V ISOURCE = 1 mA
Low, VOL 0.8 V ISINK = 4 mA
CF1, CF2, CF3, and CF4 VDD = 2.7 V
Output Voltage
High, VOH 2.4 V ISOURCE = 3 mA
Low, VOL 0.8 V ISINK = 8 mA
LOW DROPOUT REGULATORS (LDOs)
AVDD 1.9 V See the Power-On Sequence section
DVDD 1.7 V
POWER SUPPLY For specified performance
VDD 2.7 3.3 3.63 V
Supply Current (VDD) VDD = 3.63 V
Power Save Mode 0 (PSM0) 10 12 mA Normal mode, seven ADCs enabled
9.5 11 mA
Normal mode, seven ADCs enabled, total
reactive power computation disabled
10.5 12 mA
Normal mode, seven ADCs enabled,
waveform buffer enabled
10 11.6 mA Normal mode, six ADCs enabled
Power Save Mode 1 (PSM1) 9 10.6 mA Fast rms, active power, and total reactive
power measurement within 30 ms for
tamper detection
Power Save Mode 2 (PSM2) 115 200 μA Compares current to threshold, AVDD = 0 V,
DVDD = 0 V
Power Save Mode 3 (PSM3) 50 200 nA Idle, AVDD = 0 V, DVDD = 0 V
1 Throughout this data sheet, multifunction pins, such as CF3/ZX, are referred to either by the entire pin name or by a single function of the pin, for example, CF3, when
only that function is relevant.
2 Tested during device characterization.
TIMING CHARACTERISTICS
Table 2.
Parameter Symbol Min Typ Max Unit
SS to SCLK Edge tSS 10 ns
SCLK Frequency 10 MHz
SCLK Low Pulse Width tSL 40 ns
SCLK High Pulse Width tSH 40 ns
Data Output Valid After SCLK Edge tDAV 40 ns
Data Input Setup Time Before SCLK Edge tDSU 10 ns
Data Input Hold Time After SCLK Edge tDHD 10 ns
Data Output Fall Time tDF 10 ns
Data Output Rise Time tDR 10 ns
SCLK Fall Time tSF 10 ns
SCLK Rise Time tSR 10 ns
MISO Disable After SS Rising Edge tDIS 100 ns
SS High After SCLK Edge tSFS 0 ns
1 "— 1: it— ‘FL 31; LL a; H
ADE9078 Data Sheet
Rev. 0 | Page 8 of 107
MSB LSB
LSB IN
INTERMEDIATE BITS
INTERMEDIATE BITS
t
SFS
t
DIS
t
SS
t
SL
t
DF
t
SH
t
DHD
t
DAV
t
DSU
t
SR
t
SF
t
DR
MSB IN
MOSI
MISO
SCLK
SS
14331-002
Figure 2. SPI Interface Timing
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Data Sheet ADE9078
Rev. 0 | Page 9 of 107
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to GND 0.3 V to +3.96 V
Analog Input Voltage to GND,
IAP, IAN, IBP, IBN, ICP, ICN, VAP, VAN
VBP, VBN, VCP, VCN
1.9 V to +2 V
Reference Input Voltage to REFGND 0.3 V to +2 V
Digital Input Voltage to GND 0.3 V to VDD + 0.3 V
Digital Output Voltage to GND 0.3 V to VDD + 0.3 V
Operating Temperature
Industrial Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec)1 260°C
ESD
Human Body Model
2
4 kV
Machine Model3 200 V
Field Induced Charged Device Model
(FICDM) 4
1.25 kV
1 Analog Devices recommends that reflow profiles used in soldering RoHS
compliant devices conform to J-STD-020D.1 from JEDEC. Refer to JEDEC for
the latest revision of this standard.
2 Applicable standard: ANSI/ESDA/JEDEC JS-001-2014.
3 Applicable standard: JESD22-A115-A (ESD machine model standard of
JEDEC).
4 Applicable Standard JESD22-C101F (ESD FICDM standard of JEDEC).
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment.
Careful attention to PCB thermal design is required.
Table 4. Thermal Resistance
Package Type
θ
JA
θ
JC
Unit
CP-40-71 27.14 3.13 °C/W
1 Test Condition 1: The junction to air measurement uses a 2S2P JEDEC test board
with 4 × 4 standard JEDEC vias. The junction to case measurement uses a 1S0P
JEDEC test board with 4 × 4 standard JEDEC vias. See JEDEC standard JESD51-2.
ESD CAUTION
Ex .9. Eu to xNEu E‘ main xAUm E: as. % men DGND DDOMT mo Pm
ADE9078 Data Sheet
Rev. 0 | Page 10 of 107
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1PULL_HIGH
2DGND
3DVDDOUT
4PM0
5
PM1
6
RESET
7IAP
8IAN
9IBP
10IBN
23 VCN
24 VCP
25 AVDDOUT
26 AGND
27 VDD
28 GND
29 CLKIN
30 CLKOUT
22 VBP
21 VBN
11
ICP
12
ICN
13
INP
15
REFGND
17
NC1
16
REF
18
NC2
19
VAN
20
VAP
14
INN
33 CF1
34 CF2
35 CF3/ZX
36 CF4/EVENT/DREADY
37 SCLK
38 MISO
39 MOSI
40 SS
32 IRQ1
31 IRQ0
ADE9078
TOP VIEW
(Not to Scale)
14331-003
NOTES
1. IT IS RECOMMENDED TO TIE THE
NC1 AND NC2 PINS TO GROUND.
2. EXPOSED PAD. CREATE A SIMILAR PAD ON THE
PRINTED CIRCUIT BOARD (PCB) UNDER THE
EXPOSED PAD. SOLDER THE EXPOSED PAD TO THE
PAD ON THE PCB TO CONFER MECHANICAL STRENGTH
TO THE PACKAGE AND CONNECT ALL GROUNDS
(GND, AGND, DGND, AND REFGND) TOGETHER AT
THIS POINT.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 PULL_HIGH Pull High. Tie this pin to VDD.
2 DGND Digital Ground. This pin provides the ground reference for the digital circuitry in the ADE9078. Because
the digital return currents in the ADE9078 are small, it is acceptable to connect this pin to the analog
ground plane of the whole system. Connect all grounds (GND, AGND, DGND, and REFGND) together at one
point.
3 DVDDOUT 1.8 V Output of the Digital Low Dropout Regulator (LDO). Decouple this pin with a 0.1 μF ceramic
capacitor in parallel with a ceramic 4.7 μF capacitor.
4 PM0 Power Mode Pin 0. PM0, combined with PM1, defines the power mode. For normal operation, PM0 and
PM1 must be grounded (see the Power Modes section).
5 PM1 Power Mode Pin 1. PM1 combined with PM0, defines the power mode. For normal operation, PM0 and
PM1 must be grounded (see the Power Modes section).
6 RESET Reset Input, Active Low. This pin must stay low for at least 1 μs to trigger a hardware reset.
7, 8 IAP, IAN Analog Inputs, Channel IA. The IAP (positive) and IAN (negative) inputs are fully differential voltage
inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.
9, 10 IBP, IBN Analog Inputs, Channel IB. The IBP (positive) and IBN (negative) inputs are fully differential voltage
inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.
11, 12 ICP, ICN Analog Inputs, Channel IC. The ICP (positive) and ICN (negative) inputs are fully differential voltage
inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.
13, 14 INP, INN Analog Inputs, Channel IN. The INP (positive) and INN (negative) inputs are fully differential voltage
inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.
15 REFGND Ground Reference, Internal Voltage Reference. Connect all grounds (GND, AGND, DGND, and REFGND)
together at one point.
16 REF Voltage Reference. The REF pin provides access to the on-chip voltage reference. The on-chip reference
has a nominal value of 1.25 V. An external reference of 1.2 V to 1.25 V can also be connected at this pin. In
either case, decouple REF to REFGND with 0.1 μF ceramic capacitor in parallel with a ceramic 4.7 μF capacitor.
After reset, the on-chip reference is enabled. To use the internal voltage reference with external circuits, a
buffer is required. The full-scale values mentioned in this data sheet are for a voltage reference of 1.25 V.
17 NC1 No Connection. It is recommended to tie this pin to ground.
18 NC2 No Connection. It is recommended to tie this pin to ground.
i <3 i="" a/event="">
Data Sheet ADE9078
Rev. 0 | Page 11 of 107
Pin No. Mnemonic Description
19, 20 VAN, VAP Analog Inputs, Channel VA. The VAP (positive) and VAN (negative) inputs are fully differential voltage
inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.
21, 22 VBN, VBP Analog Inputs, Channel VB. The VBP (positive) and VBN (negative) inputs are fully differential voltage
inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.
23, 24
VCN, VCP
Analog Inputs, Channel VC. The VCP (positive) and VCN (negative) inputs are fully differential voltage
inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.
25 AVDDOUT 1.9 V Output of the Analog Low Dropout Regulator (LDO). Decouple AVDDOUT with a 0.1 µF ceramic
capacitor in parallel with a ceramic 4.7 µF capacitor. Do not connect external active circuitry to this pin.
26 AGND Analog Ground Reference. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point.
27 VDD Supply Voltage. The VDD pin provides the supply voltage. Decouple VDD to GND with a ceramic 0.1 µF
capacitor in parallel with a ceramic 10 µF capacitor.
28 GND Supply Ground Reference. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point.
29 CLKIN Crystal/Clock Input. Connect a crystal across CLKIN and CLKOUT to provide a clock source. See the Crystal
Selection section for details on choosing a suitable crystal. Alternatively, an external clock can be
provided at this logic input.
30
CLKOUT
Crystal Output. Connect a crystal across CLKIN and CLKOUT to provide a clock source. When using CLKOUT
to drive external circuits, connect an external buffer. When using an external clock on CLKIN, leave
CLKOUT unconnected.
31 IRQ0 Interrupt Request Output. This pin is an active low logic output. See the Interrupts/Events section for
information about events that trigger interrupts.
32 IRQ1 Interrupt Request Output. This pin is an active low logic output. See the Interrupts/Events section for
information about events that trigger interrupts.
33 CF1 Calibration Frequency (CF) Logic Output 1. The CF1, CF2, CF3, and CF4 outputs provide power
information based on the CFxSEL bits in the CFMODE register. Use these outputs for operational and
calibration purposes. Scale the full-scale output frequency by writing to the CFxDEN registers (see the
Digital to Frequency ConversionCFx Output section).
34 CF2 CF Logic Output 2. This pin indicates CF2.
35 CF3/ZX CF Logic Output 3/Zero Crossing. This pin indicates CF3 or zero crossing.
36 CF4/EVENT/DREADY CF Logic Output 4/Event Pin/Data Ready. This pin indicates CF4, events, or when new data is ready.
37 SCLK Serial Clock Input for the SPI Port. All serial data transfers synchronize to this clock (see the Accessing
On-Chip Data section). The SCLK pin has a Schmitt trigger input for use with a clock source that has a
slow edge transition time, for example, optoisolator outputs.
38 MISO Data Output for the SPI Port.
39 MOSI Data Input for the SPI Port.
40 SS Slave Select for the SPI Port.
EP Exposed Pad. Create a similar pad on the printed circuit board (PCB) under the exposed pad. Solder the
exposed pad to the pad on the PCB to confer mechanical strength to the package and connect all
grounds (GND, AGND, DGND, and REFGND) together at this point.
i=3: as 9,5 05 5E“ 3; 3mm“ 3.. 55: \,- m ,4. as 11.3 4).: 4; 5 0,5 3.. 55: SE“ 5 :35;
ADE9078 Data Sheet
Rev. 0 | Page 12 of 107
TYPICAL PERFORMANCE CHARACTERISTICS
TOTAL ENERGY LINEARITY OVER SUPPLY AND TEMPERATURE
Sinusoidal voltage with an amplitude of 50% of full scale and a frequency of 50 Hz; sinusoidal current with variable amplitudes from
100% of full scale down to 0.005% or 0.02% of full scale and with a frequency of 50 Hz; integrator off.
–0.5
–0.3
–0.1
0
0.1
0.3
0.5
0.001 0.01 0.1 110 100
ERROR (%)
PERCENTAGE OF FULL-SCALE CURRENT (%)
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
14331-103
Figure 4. Total Active Energy Error as a Percentage of Reading over
Temperature, PF = 1
0.001 0.01 0.1 110 100
ERROR (%)
PERCENTAGE OF FULL-SCALE CURRENT (%)
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
14331-104
Figure 5. Total Reactive Energy Error as a Percentage of Reading over
Temperature, PF = 0
–0.5
–0.3
–0.1
0
0.1
0.3
0.5
0.01 0.1 110 100
ERROR (%)
PERCENTAGE OF FULL-SCALE CURRENT (%)
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
14331-105
Figure 6. Total Apparent Energy Error as a Percentage of Reading over
Temperature, PF = 1
–0.5
–0.3
–0.1
0.1
0
0.3
0.5
0.001 0.01 0.1 110 100
ERROR (%)
PERCENTAGE OF FULL-SCALE CURRENT (%)
T
A
= 25°C
2.7V
2.97V
3.3V
3.63V
14331-106
Figure 7. Total Active Energy Error as a Percentage of Reading over Supply
Voltage, PF = 1, TA = 25°C
–0.5
–0.3
–0.1
0
0.1
0.3
0.5
0.001 0.01 0.1 110 100
ERROR (%)
PERCENTAGE OF FULL-SCALE CURRENT (%)
T
A
= 25°C
2.7V
2.97V
3.3V
3.63V
14331-107
Figure 8. Total Reactive Energy Error as a Percentage of Reading over Supply
Voltage, PF = 0, TA = 25°
–0.5
–0.3
–0.1
0
0.1
0.3
0.5
0.01 0.1 110 100
ERROR (%)
PERCENTAGE OF FULL-SCALE CURRENT (%)
T
A
= 25°C
2.7V
2.97V
3.3V
3.63V
14331-108
Figure 9. Total Apparent Energy Error as a Percentage of Reading over
Supply Voltage, PF = 1, TA = 25°
=5! 0,5 3; «SE :85;
Data Sheet ADE9078
Rev. 0 | Page 13 of 107
FUNDAMENTAL ENERGY LINEARITY WITH FIFTH HARMONIC OVER SUPPLY AND TEMPERATURE
Fundamental voltage component in phase with fifth harmonic; current with a 50 Hz component that has variable amplitudes from 100%
of full scale down to 0.005% of full scale and a fifth harmonic with a constant amplitude of 40% of fundamental; integrator off.
–0.5
–0.3
–0.1
0
0.1
0.3
0.5
0.001 0.01 0.1 110 100
ERROR (%)
PERCENTAGE OF FULL-SCALE CURRENT (%)
14331-109
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
Figure 10. Fundamental Reactive Energy Error as a Percentage of Reading
over Temperature, PF = 0
0.001 0.01 0.1 110 100
ERROR (%)
PERCENTAGE OF FULL-SCALE CURRENT (%)
–0.5
–0.3
–0.1
0
0.1
0.3
0.5 T
A
= 25°C
2.7V
2.97V
3.3V
3.63V
14331-110
Figure 11. Fundamental Reactive Energy Error as a Percentage of Reading
over Supply Voltage, PF = 0, TA = 25°
n10 nos 4. as 4110
ADE9078 Data Sheet
Rev. 0 | Page 14 of 107
TOTAL ENERGY ERROR OVER FREQUENCY
Sinusoidal voltage with a constant amplitude of 50% of full scale; sinusoidal current with a constant amplitude of 10% of full scale;
variable frequency between 45 Hz and 65 Hz; integrator off.
40 45 50 55 60 65 70
ERROR (%)
LINE FREQUENCY (Hz)
POWER FACTOR = 1
POWER FACTOR = 0.5
POWER FACTOR = –0.5
14331-111
Figure 12. Total Active Energy Error as a Percentage of Reading vs. Line
Frequency, PF = −0.5, +0.5, and +1
–0.10
–0.05
0
0.05
0.10
40 45 50 55 60 65 70
ERROR (%)
LINE FREQUENCY (Hz)
POWER FACTOR = 0
POWER FACTOR = 0.866
POWER FACTOR = –0.866
14331-112
Figure 13. Total Reactive Energy Error as a Percentage of Reading vs. Line
Frequency, PF = −0.866, 0, and +0.866
9.1 n 0.05 E93 ,9 as 4m: ms 3; momfi ma 0.05 7 onE 47.05 am 9,5 F :85;
Data Sheet ADE9078
Rev. 0 | Page 15 of 107
RMS LINEARITY OVER TEMPERATURE AND RMS ERROR OVER FREQUENCY
Sinusoidal current and voltage with variable amplitudes from 100% of full scale down to 0.02% of full scale using a frequency of 50 Hz;
variable frequency between 45 Hz and 65 Hz; sinusoidal current amplitude of 10% of full scale and voltage amplitude of 50% of full scale;
integrator off.
–0.5
–0.3
–0.1
0.1
0
0.3
0.5
0.01 0.1 110 100
ERROR (%)
PERCENTAGE OF FULL-SCALE CURRENT (%)
TA = –40°C
TA = +25°C
TA = +85°C
14331-113
Figure 14. Current RMS Error as a Percentage of Reading over Temperature
–0.5
–0.3
–0.1
0.1
0
0.3
0.5
0.01 0.1 110 100
ERROR (%)
PERCENTAGE OF FULL-SCALE CURRENT (%)
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
14331-114
Figure 15. Voltage RMS Error as a Percentage of Reading over Temperature
40 45 50 55 60 65 70
ERROR (%)
LINE FREQUENCY (Hz)
14331-115
Figure 16. Current RMS Error as a Percentage of Reading vs. Line Frequency
40 45 50 55 60 65 70
ERROR (%)
LINE FREQUENCY (Hz)
14331-116
Figure 17. Voltage RMS Error as a Percentage of Reading vs. Line Frequency
ms in. momfi as 3; 55: 9,5 3.; momfi
ADE9078 Data Sheet
Rev. 0 | Page 16 of 107
ENERGY LINEARITY REPEATABILITY
Sinusoidal voltage with an amplitude of 50% of full scale and a frequency of 50 Hz; sinusoidal current with variable amplitudes from
100% of full scale down to 0.005% of full scale and with a frequency of 50 Hz. For Figure 20, besides the fundamental component, the
voltage contained a fifth harmonic with a constant amplitude of 40% of fundamental, and the current contained a fifth harmonic with a
constant amplitude of 40% of fundamental. Integrator off. Measurements at 25°C repeated 30 times.
–0.5
–0.3
–0.1
0
0.1
0.3
0.5
0.001 0.01 0.1 110 100
ERROR (%)
PERCENTAGE OF FULL-SCALE CURRENT (%)
14331-117
Figure 18. Total Active Energy Error as a Percentage of Reading, PF = 1
(Standard Deviation σ = 0.03% at 0.01% of Full-Scale Current)
–0.5
–0.3
–0.1
0.1
0
0.3
0.5
0.001 0.01 0.1 110 100
ERROR (%)
PERCENTAGE OF FULL-SCALE CURRENT (%)
14331-118
Figure 19. Total Reactive Energy Error as a Percentage of Reading, PF = 0
(Standard Deviation σ = 0.04% at 0.01% of Full-Scale Current)
–0.5
–0.3
–0.1
0.1
0
0.3
0.5
0.001 0.01 0.1 110 100
ERROR (%)
PERCENTAGE OF FULL-SCALE CURRENT (%)
14331-119
Figure 20. Fundamental Reactive Energy Error as a Percentage of Reading,
PF = 0 (Standard Deviation σ = 0.04% at 0.01% of Full-Scale Current)
Data Sheet ADE9078
Rev. 0 | Page 17 of 107
TOTAL ENERGY AND RMS LINEARITY WITH INTEGRATOR ON
Sinusoidal voltage with an amplitude of 50% of full scale and a frequency of 50 Hz; gain of current channel set to 4; sinusoidal current
with variable amplitudes from 100% of full scale down to 0.05% or 0.1% of full scale and with a frequency of 50 Hz; full scale at gain of 4 = (full
scale at gain of 1)/4, high-pass corner frequency of 4.97 Hz.
–0.5
–0.3
–0.1
0.1
0
0.3
0.5
0.01 0.1 1 10 100
ERROR (%)
PERCENTAGE OF FULL-SCALE CURRENT (%)
POWER FACTOR = 1
POWER FACTOR = 0.5
POWER FACTOR = –0.5
14331-120
Figure 21. Total Active Energy Error, Gain = 4, Integrator On
–0.5
–0.3
–0.1
0.1
0
0.3
0.5
0.1 1 10 100
ERROR (%)
PERCENTAGE OF FULL-SCALE CURRENT (%)
14331-121
Figure 22. Total Reactive Energy Error, Gain = 4, Integrator On
–0.5
–0.3
–0.1
0.1
0
0.3
0.5
0.01 0.1 1 10 100
ERROR (%)
PERCENTAGE OF FULL-SCALE CURRENT (%)
POWER FACTOR = 0
POWER FACTOR = 0.866
POWER FACTOR = –0.866
14331-122
Figure 23. Total Apparent Energy Error, Gain = 4, Integrator On
–0.5
–0.3
–0.1
0.1
0.3
0.5
0.1 1 10 100
PERCENTAGE OF FULL-SCALE CURRENT (%)
ERROR (%)
14331-123
Figure 24. Total RMS Current Error, Gain = 4, Integrator On
ERROR w.) $£A as «4 4:4 45 ERRoR w.) a“ 9.5 In A“ 415
ADE9078 Data Sheet
Rev. 0 | Page 18 of 107
TOTAL ENERGY ERROR OVER FREQUENCY WITH INTEGRATOR ON
Sinusoidal voltage with a constant amplitude of 50% of full scale; gain of current channel set to 4; sinusoidal current with a constant
amplitude of 10% of full scale; variable frequency between 45 Hz and 65 Hz, gigh-pass corner frequency of 4.97 Hz.
POWER FACTOR = 0
POWER FACTOR = 0.5
POWER FACTOR = –0.5
40 45 50 55 60 65 70
ERROR (%)
LINE FREQUENCY (Hz)
14331-124
Figure 25. Total Active Energy Error as a Percentage of Reading vs. Line
Frequency, Gain = 4, Integrator On
40 45 50 55 60 65 70
ERROR (%)
LINE FREQUENCY (Hz)
POWER FACTOR = 0
POWER FACTOR = 0.866
POWER FACTOR = –0.866
14331-125
Figure 26. Total Reactive Energy Error as a Percentage of Reading vs. Line
Frequency, Gain = 4, Integrator On
Data Sheet ADE9078
Rev. 0 | Page 19 of 107
TEST CIRCUIT
SAME AS
CF2
PM0
0.22µF
4.7µF
MOSI
MISO
CF4/EVENT/DREADY
CF3/ZX
CF2
CF1
REF
IN/OUT
CLKOUT
CLKIN
PM1
RESET
IAP
IAN
IBP
IBN
ICP
ICN
INP
INN
VBN
VBP
4
22
5
6
7
8
9
10
11
12
13
14
21
40
39
38
36
35
34
33
32
31
16
30
29
ADE9078
25 27 3
AVDDOUT
VDD
DVDDOUT
215
DGND
AGND
0.22µF
4.7µF
0.1µF
4.7µF+
++
0.1µF
10µF +
SAME AS
IAP, IAN
SAME AS
IAP, IAN
22nF
1k
1k
1k
10k
1k22nF
3.3V
3.3
V
1µF
22nF
22nF
SS
IRQ1
IRQ0
3.3V
18pF
18pF
SAME AS
IAP, IAN
VAN
VAP
20
19
SAME AS
VAP, VAN
VCN
24
23
SAME AS
VAP, VAN VCP
SCLK
37
26 28
REFGND
GND
14331-127
Figure 27. Test Circuit
ADE9078 Data Sheet
Rev. 0 | Page 20 of 107
TERMINOLOGY
Differential Input Voltage Range and Maximum Operating
Voltage on VxP, VxN, IxP, and IxN Analog Input Pins
The differential input range describes the maximum difference
between the IxP and IxN or VxP and VxN pins. The maximum
operating voltage given in Table 1 describes the maximum
voltage that can be present on each pin, including any common-
mode voltage. Figure 28 illustrates the maximum input between
xP and xM, which is seen in the application when a current
transformer with center tapped burden resistor is used. Figure 29
illustrates the maximum input voltage range between xP and xN
when a pseudo differential input is applied, as is commonly
seen when sensing the line voltage.
+0.1V
0
+0.6V
–0.4V
0x0474 E650 =
+74,770,000
0xFB8B 19B0 =
–74,770,000
CHANNEL (x_PCF) WAVEFORM
DATA RANGE WITH x_GAIN = 1
xP INPUT PIN
xM INPUT PIN
+0.1V
+0.6V
–0.4V
14331-010
Figure 28. Maximum Input Signal with Differential Antiphase Input with
Common-Mode Voltage = 0.1 V Gain = 1
+0.1V
0
+0.6V
-0.4V
+0.1V
0x0474 E650 =
+74,770,000
0xFB8B 19B0 =
–74,770,000
CHANNEL (x_PCF) WAVEFORM
DATA RANGE WITH x_GAIN = 2
xP INPUT PIN
xM INPUT PIN
14331-011
Figure 29. Maximum Input Signal with Pseudo Differential Input with
Common-Mode Voltage = 0.1 V, Gain = 2 (x_GAIN = 2)
Crosstalk
Crosstalk is measured by grounding one channel and applying a
full-scale 50 Hz or 60 Hz signal on all the other channels. The
crosstalk is equal to the ratio between the grounded ADC output
value and its ADC full-scale output value. The ADC outputs are
acquired for 100 sec. Crosstalk is expressed in decibels.
Differential Input Impedance (DC)
The differential input impedance represents the impedance
between the pair IxP and IxN or VxP and VxN. It varies with
the PGA gain selection as indicated in Table 1.
ADC Offset
ADC offset is the difference between the average measured
ADC output code with both inputs connected to GND and the
ideal ADC output code of zero. ADC offset is expressed in
microvolts.
ADC Offset Drift over Temperature
The ADC offset drift is the change in offset over temperature.
It is measured at −40°C, +25°C, and +85°C. The offset drift over
temperature is computed as follows:


 

C25C85
C25C85
,
C25C40
C25C40
max OffsetOffset
OffsetOffset
Drift
Offset drift is expressed in μV/°C.
Gain Error
The gain error in the ADCs represents the difference between the
measured ADC output code (minus the offset) and the ideal
output code when an external voltage reference of 1.2 V is used (see
the Voltage Reference section). The difference is expressed as a
percentage of the ideal code. It represents the overall gain error
of one channel.
Gain Drift over Temperature
This temperature coefficient includes the temperature variation
of the ADC gain while using an external voltage reference of
1.2 V. It represents the overall temperature coefficient of one
current or voltage channel. With an external voltage reference
of 1.2 V in use, the ADC gain is measured at −40°C, +25°C, and
+85°C. Then the temperature coefficient is computed as follows:


 

C25C85C)25(
C25C85
,
C25C40C)25(
C25C40
max Gain
GainGain
Gain
GainGain
Drift
Gain drift is measured in ppm/°C.
Data Sheet ADE9078
Rev. 0 | Page 21 of 107
AC Power Supply Rejection (PSRR)
AC PSRR quantifies the measurement error as a percentage of
reading when the dc power supply is VNOM and modulated with
ac and the inputs are grounded. For the ac PSRR measurement,
20 sec of samples is captured with nominal supplies (3.3 V) and a
second set are captured with an additional ac signal (330 mV peak
at 50 Hz) introduced onto the supplies. Then, the PSRR is
expressed as PSRR = 20 log10(V2/V1).
Signal-to-Noise Ratio (SNR)
SNR is calculated by inputting a 50 Hz signal, and samples are
acquired for 2 sec. The amplitudes for each frequency up to the
bandwidth given in Table 1 as the ADC output bandwidth (−3 dB)
are calculated. To determine the SNR, the signal at 50 Hz is
compared to the sum of the power from all the other frequencies,
removing power from its harmonics. The value for SNR is
expressed in decibels.
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is calculated by inputting a 50 Hz signal, and samples
are acquired for 2 sec. The amplitudes for each frequency up to
the bandwidth given in Table 1 as the ADC output bandwidth
(−3 dB) are calculated. To determine the SINAD, the signal at
50 Hz is compared to the sum of the power from all the other
frequencies. The value for SINAD is expressed in decibels.
Total Harmonic Distortion (THD)
THD is calculated by inputting a 50 Hz signal, and samples are
acquired for over 2 sec. The amplitudes for each frequency up
to the bandwidth given in Table 1 as the ADC output
bandwidth (−3 dB) are calculated. To determine the THD, the
amplitudes of the 50 Hz harmonics up to the bandwidth are
root sum squared. The value for THD is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
SFDR is calculated by inputting a 50 Hz signal, and samples are
acquired for over 2 sec. The amplitudes for each frequency up
to the bandwidth given in Table 1 as the ADC output bandwidth
(−3 dB) are calculated. To determine the SFDR, the amplitude
of the largest signal that is not a harmonic of 50 Hz is recorded.
The value for SFDR is expressed in decibels.
ADC Output Pass Band
The ADC output pass band is the bandwidth within 0.1 dB,
resulting from the digital filtering in the sinc4 and sinc4 + IIR LPF.
ADC Output Bandwidth
The ADC output bandwidth is the bandwidth within −3 dB,
resulting from the digital filtering in the sinc4 and sinc4 + IIR LPF.
E15: M1
ADE9078 Data Sheet
Rev. 0 | Page 22 of 107
THEORY OF OPERATION
The ADE9078 integrates seven high performance ADCs and a
flexible DSP core. An integrated high end reference ensures low
drift over temperature with a combined drift of less than
±25 ppm/°C maximum for the whole channel including PGA
and ADC.
The ADE9078 is a highly accurate, fully integrated energy
metering device. Interfacing with both CT and Rogowski coil
sensors, the ADE9078 enables users to develop a 3-phase metrology
platform, which achieves high performance for Class 1 through
Class 0.2 meters. See the Measurements (Normal Mode) section
for more information.
Two power modes are provided to enable detection of meter
tampering: PSM2 uses a low power comparator to compare
current channels to a threshold and indicates whether it has
been exceeded on the IRQ0 and IRQ1 outputs; PSM1 enables
fast measurement of current and voltage rms (xVRMS, xIRMS),
active power, and VAR during a tamper. See the Measurements
(PSM1) section and Measurements (PSM2) section for more
information about how to use these modes.
ADC
Overview
The ADE9078 incorporates seven independent, second-order, Σ-Δ
ADCs that sample simultaneously. Each ADC is 24 bits and supports
fully differential and pseudo differential inputs that can go above
and below ground. The ADE9078 includes a low noise, low drift,
internal band gap reference. Set the EXT_REF bit in the CONFIG1
register if using an external voltage reference. Each ADC contains
a programmable gain amplifier, which allows a gain of 1, 2, or 4.
The ADCs incorporate proprietary dither techniques to prevent
idle tones at low input levels, extending the accuracy range.
Analog Input Configuration
There is no internal buffering on the device. The impedance of
the ADE9078 depends on the programmable gain selected (see
the Specifications table).
Fully Differential Inputs
The input signals on the IAP, IAN, IBP, IBN, ICP, ICN, VAP, VAN,
VBP, VBN, VCP, and VCN pins must not exceed 0.6 V relative
to AGND, the analog ground reference. The differential full-
scale input range of the ADCs is ±1 V peak (0.707 V rms), and
the maximum allowed common-mode voltage at the ADC pins
must not exceed ±0.1 V.
Figure 30 and Figure 31 show two common types of input
signals for an energy metering application. Figure 30 shows the
maximum input allowed with differential antiphase signals. A
current transformer with center tapped burden resistor generates
differential antiphase signals. Figure 31 shows the maximum
input signal with pseudo differential signals, similar to those
obtained when sensing the mains voltage signal through a
resistive divider or using a Rogowski coil current sensor.
The following conditions must be met for the input signals with
gain = 1:
|IAP, IAN, IBP, IBN, ICP, ICN, VAP, VAN, VBP, VBN, VCP,
and VCN| ≤ 0.6 V peak relative to AGND
|IxP − IxN| ≤ 1 V peak, |VxP − VxN| ≤ 1 V peak
+0.1V
0
+0.6V
–0.4V
0x0474 E650 =
NOTES
1. x_PCF IS THE INSTANTANEOUS WAVEFORM OBTAINED
AFTER GAIN AND PHASE COMPENSATION.
+74,770,000
0xFB8B 19B0 =
–74,770,000
CHANNEL (x_PCF) WAVEFORM
DATA RANGE WITH x_GAIN = 1
xP INPUT PIN
xM INPUT PIN
+0.1V
+0.6V
–0.4V
14331-012
Figure 30. Maximum Input Signal with Differential Antiphase Input with
Common-Mode Voltage = 0.1 V, Gain = 1
+0.1V
0
+0.6V
–0.4V
+0.1V
0x0474 E650 =
+74,770,000
xFB8B 19B0 =
–74,770,000
CHANNEL (x_PCF) WAVEFORM
DATA RANGE WITH x_GAIN = 2
xP INPUT PIN
xM INPUT PIN
14331-013
N
OTES
1
. x_PCF IS THE INSTANTANEOUS WAVEFORM OBTAINED
AFTER GAIN AND PHASE COMPENS ATION.
Figure 31. Maximum Input Signal with Pseudo Differential Input with
Common-Mode Voltage = 0.1 V, Gain = 2
Each ADC contains a programmable gain amplifier that allows
a gain of 1, 2, or 4. The ADC produces full-scale output codes with
an input of ±1 V. With a gain of 1, this full-scale input corresponds
to a differential antiphase input of 0.707 V rms, as shown in
Figure 30. At a gain of 2, full-scale output codes are produced
with an input of 0.353 V rms, as shown in Figure 31. At a gain
avg—n— a
Data Sheet ADE9078
Rev. 0 | Page 23 of 107
of 4, full-scale output codes are generated with a 0.1765 V rms
input signal. Note that the voltages on the xP and xN pins must
be within ±0.6 V as described in this section and Table 1.
Write the x_GAIN bits in the PGA_GAIN register to configure
the gain for each channel.
Interfacing to Current and Voltage Sensors
Figure 32 and Figure 34 show the typical circuits to connect to
current transformer and Rogowski coil current sensors. Figure 33
shows the typical interface circuit to measure the mains voltage.
The antialiasing filter corner is chosen to be around 7 kHz to
provide sufficient attenuation of out of band signals near the
modulator clock frequency. The same RC filter corner is used
on voltage channels, as well, to avoid phase errors between current
and voltage signals. Note that the Rogowski coil (that is, a di/dt
sensor) input network has a second-order antialiasing filter. The
integrator used in conjunction to the Rogowski coil has a
−20 dB/dec attenuation and an approximately −90° phase shift.
When combined with a di/dt sensor, the resulting magnitude
and phase response is a flat gain over the frequency band of
interest. However, the di/dt sensor has a 20 dB/dec gain associated
with it, and it generates significant high frequency noise. An
antialiasing filter of at least the second order is required to avoid
noise aliasing back in the band of interest when the ADC is
sampling. See Figure 34 for the recommended antialiasing filter.
1k
8.222nF
AGND
IxP
IxN
0.656V rms max
100A RMS MAX
10A RMS NOM
CT
I
8.2
1k
22nF
AGND
2500:1
14331-014
Figure 32. Application Circuit with a Current Transformer Current Sensor
1M
1k22nF
AGND
VxP
VxN
0.240V rms
240V rms
1k22nF
NEUTRAL
PHASE
AGND
14331-015
Figure 33. Application Circuit with Voltage Sensed Through Resistor Divider
1k
IxP
IxN
0.3535V rms
22nF22nF
100
1k
22nF
22nF
100
14331-016
Figure 34. Application Circuit with Rogowski Coil Current Sensor
Internal RF Immunity Filter
Energy metering applications require the meter to be immune to
external radio frequency fields of 30 V/m, from 80 MHz to 10 GHz,
according to IEC 61000-4-3. The ADE9078 has internal antialias-
ing filters to improve performance in testing because it is difficult
to filter these signals externally. The second-order, internal low-
pass filter has a corner frequency of 10 MHz. Note that external
antialias filters are required to attenuate frequencies above 7 kHz, as
shown in the Interfacing to Current and Voltage Sensors section.
Modes of Operation
Each ADC has two modes of operation: normal mode and
disabled mode.
In the normal mode, the ADCs turn on and sample continuously.
Use the CHNL_DIS register to disable the ADCs individually.
Four different power modes are available in the ADE9078 (see
the Power Modes section). All ADCs turn on during the PSM0
power mode. In the PSM1 power mode, all of the ADCs except for
the neutral current ADC are turned on. In PSM2 mode and
PSM3 mode, all ADCs are disabled and cannot be turned on.
Table 6. ADC Operation in PSMx Power Modes
PSMx Power Mode ADC Mode of Operation
PSM0 Normal (on)
PSM1 IA, IB, IC, VA, VB, VC: normal (on)
IN: disabled (always off)
PSM2 Disabled (always off)
PSM3 Disabled (always off)
Output Data Rates and Format
When a conversion is complete, the DREADY bit of the STATUS0
register is set to 1. If the CF4_CFG bits in the CONFIG1 register
are equal to 11, the CF4/EVENT/DREADY pin corresponds to
DREADY and pulses high to indicate when seven new ADC
results are ready. Note that the DREADY update rate depends
on the data selected in the WF_SRC bits in the WFB_CFG register.
For the ADE9078, the modulator sampling rate (MODCLK) is
fixed at 1.024 MHz (CLKIN/12 = 12.288 MHz/12). The output
data rate of the sinc4 filter is 16 kHz (SINC_ODR = MODCLK/64),
whereas the low-pass filter/decimator stage yields an output rate
four times slower than the sinc4 filter output rate (SINC_ODR).
Figure 35 shows the digital filtering, which takes the 1.024 MHz
ADC samples and creates waveform information at a decimated
rate of 16 kHz or 4 kHz.
ANALOG
INPUT
Σ- × 7
DIGITAL
MULTIBIT SINC4 IIR LPF/
DECIMATOR
DIGITAL
WAVEFORM
WAVEFORM
BUFFER
(×7 CHANNELS)
1.024MHz 16kHz 4kHz
14331-017
Figure 35. Datapath Following ADC Stage
“II! ‘ “”4 ‘
ADE9078 Data Sheet
Rev. 0 | Page 24 of 107
The output data rates are summarized in Table 7.
Table 7. Output Data Rates
Parameter Data Rate
CLKIN Frequency 12.288 MHz
ADC Modulator Clock, MODCLK 1.024 MHz
Sinc4, SINC_ODR 16 kHz
Low-Pass Filter 4 kHz
Bandwidth (Pass Band) 0.672 kHz
The ADC data in the waveform buffer is stored as 32-bit data by
shifting left by 4 bits and sign extending, as shown in Figure 36.
ADC_DATA[23:0] 0000SE
14331-136
Figure 36. Format for the ADC Data Stored in the Waveform Buffer,
x_SINC_DAT and x_LPF_DAT Registers
The expected output code from the sinc4 filter when input is at 1 V
peak is 4,190,000 decimal (d), which corresponds to a value of
67,110,000d in the waveform buffer. The expected output code
from the decimator filter when input is at 1 V peak is 4,660,000d,
which corresponds to a value of 74,520,000d in the waveform
buffer (see the Waveform Buffer section for more information).
Voltage Reference
The ADE9078 supports a 1.25 V internal reference. The
temperature drift of the reference voltage is ±5 ppm/°C typical,
±20 ppm/°C maximum. An external reference can be connected
between the REF and REFGND pins. Set the EXT_REF bit of
the CONFIG1 register when using an external voltage reference,
which disables the internal reference buffer.
CRYSTAL OSCILLATOR/EXTERNAL CLOCK
The ADE9078 contains a crystal oscillator. Alternatively, a digital
clock signal can be applied at the CLKIN pin of the ADE9078.
When a crystal is used as the clock source for the ADE9078,
attach the crystal and the ceramic capacitors, with capacitances
of CL1 and CL2, as shown in Figure 37. It is not recommended to
attach an external feedback resistor in parallel to the crystal.
When a digital clock signal is applied at the CLKIN pin, the
inverted output is available at the CLKOUT pin. This output is
not buffered internally and cannot drive any other external
devices directly. Note that CLKOUT is available in the PSM0
and PSM1 operating modes only.
P1 L1
CLKIN CLKOUT29 30
P2L2
1.75k2.5k
C
IN1
C
IN2
12.288MHz
14331-018
Figure 37. Crystal Application Circuit
Crystal Selection
The transconductance of the crystal oscillator circuit in the
ADE9078, gm, is provided in Table 1. It is recommended to have
three to five times more gm than the calculated gmCRITICAL for the
crystal.
The following equation shows how to calculate the gmCRITICAL for
the crystal from information given in the crystal data sheet:
gmCRITICAL = 4 × ESRMAX × 1000 × (2π × fCLK (Hz))2 × (C0 + CL)2
where:
gmCRITICAL is the minimum gain required to start the crystal in mA/V.
ESRMAX is the maximum electrical series resistance (ESR),
expressed in Ω.
fCLK (Hz) is 12.288 MHz, expressed in Hz as 12.288 × 106.
C0 is the maximum shunt capacitance, expressed in farads.
CL is the total load capacitance, expressed in farads.
Crystals with low ESR and smaller load capacitance have a
lower gmCRITICAL and are easier to drive.
The evaluation board of the ADE9078 uses a crystal manufactured
by Abracon (ABLS-12.288MHZ-L4Q-T), which has a maximum
ESR of 50 Ω, a load capacitance of 18 pF, and a maximum shunt
capacitance of 7 pF, which results in a gmCRITICAL of 0.75 mA/V, as
follows:
gmCRITICAL = 4 × ESRMAX × 1000 × (2π × fCLK (Hz))2 × (C0 + CL)2
gmCRITICAL = 4 × 50 × 1000 × (2π × 12.288 × 106)2 × (7 ×
10−120+ 18 × 10−12)2 = 0.75 mA/V
The gain of the crystal oscillator circuit in the ADE9078, the gm,
provided in Table 1 is more than 5 × gmCRITICAL; thus, there is
sufficient margin to start up this crystal.
Load Capacitor Calculation
Crystal manufacturers specify the combined load capacitance
across the crystal, CL. The capacitances in Figure 37 can be
described as follows:
CP1 and CP2 are the parasitic capacitances on the clock pins
formed due to PCB traces.
CIN1 and CIN2 are the internal capacitances of the CLKIN
and CLKOUT pins, respectively.
CL1 and CL2 are the selected load capacitors to reach the
correct combined CL for the crystal.
The internal pin capacitances, CIN1 and CIN2, are 4 pF each, as
given in Table 1. To find the values of CP1 and CP2, measure the
capacitance on each of the clock pins of the PCB, CLKIN, and
CLKOUT, respectively, with respect to the AGND pin. If the
measurement is performed after soldering the IC to the PCB,
subtract the 4 pF internal capacitance of the clock pins to
determine the actual value of parasitic capacitance on each of the
crystal pins.
nun whether the current Inputs are above mmhuld, check the IRQO and IRQI
Data Sheet ADE9078
Rev. 0 | Page 25 of 107
To select the appropriate capacitance value for the ceramic
capacitors, calculate CL1 and CL2, from the following expression:
CL = ((CL1 + CP1 + CIN1) × (CL2 + CP2 + CIN2))/( CL1 + CP1 +
CIN1 + CL2 + CP2 + CIN2) (1)
Select CL1 and CL2 such that the total capacitance on each clock
pins is equal:
CL1 + CP1 + CIN1 = CL2 + CP2 + CIN2 (2)
Using Equation 1 and Equation 2, the values of CL1 and CL2 can
be calculated.
Load Capacitor Calculation Example
If a crystal with load capacitance specification of 12 pF is selected,
and the measured parasitic capacitances from the PCB traces
are CP1 = CP2 = 2 pF, Equation 1 implies,
CL = ((CL1 + CP1 + CIN1) × (CL2 + CP2 + CIN2))/(CL1 + CP1 +
CIN1 + CL2 + CP2 + CIN2)
12 pF = ((CL1 + 2 pF + 4 pF) × (CL2 + 2 pF + 4 pF))/(CL1 +
2 pF + 4 pF + CL2 + 2 pF + 4 pF)
Assuming CL1 = CL2, to satisfy Equation 2,
12 pF = ((CL1 + 6 pF) × (CL1 + 6 pF))/(CL1 + 6 pF + CL1 + 6 pF)
12 pF = ((CL1 + 6 pF) × (CL1 + 6 pF))/(2 × (CL1 + 6 pF))
12 pF = (CL1 + 6 pF)/2
Thus, CL1 = CL2 = 18 pF.
Based on this example, 18 pF ceramic capacitors are selected for CL1
and CL2. The user must verify the customized values based on care-
ful investigations on multiple devices over the temperature range.
POWER MANAGEMENT
Power Modes
The ADE9078 offers four operating modes: PSM0, PSM1, PSM2,
and PSM3. The entry into the power modes is controlled by the
PM1 and PM0 pins. These pins are checked continuously to
determine which operating mode to enter. Table 8 shows the
PMx pin configurations for each power mode.
Most applications use PSM0 (normal mode). If the user wants
to put the ADE9078 into a low power reset state, use PSM3.
PSM1 and PSM2, in combination with PSM3, enable low power
tamper detection and measurement, which is required in some
regions. These operating modes enable the user to check for a
tamper condition while minimizing power consumption
because in tamper scenarios, a battery typically powers the
ADE9078.
The current peak detection mode, PSM2, checks if the input
currents are above a user set amplitude. The tamper
measurement mode, PSM1, allows the user to make key
measurements quickly for IRMS, VRMS, active power, and VA R
with a reduced power consumption compared to PSM0.
In the application, the host microcontroller creates a duty cycle
that puts the ADE9078 into PSM2, waits the required time to
receive a result indicated in Table 8, and then returns to PSM3.
This cycle continues once per minute until the tamper checking
cycle ends, which may be up to seven days in some applications. If a
tamper is detected in PSM2, PSM1 is entered and the key measure-
ments are made. After the time required for measurements has
elapsed, the host microcontroller reads the results via the SPI
interface and changes the PM1 and PM0 pins to put the device
back into PSM3. This cycle continues once per minute until the
tamper checking cycle ends, which may be up to seven days in
some applications. Figure 38 shows the functions available in
PSM2 and PSM1.
SINC4
AND
DECIMATION
AVDD
LDO
DVDD
LDO
SPI
1.25V
REFERENCE
TEMP
SENSOR
CF1
TO CF4
IRQ0
IRQ1
SPI
PM1
PM0
ADE9078
PGA
ADC
PGA
ADC
SAR
AVAILABLE IN PSM0
AVAILABLE IN PSM2
DISABLED IN PSM1
PGA
ADC
PGA
ADC
PGA
ADC
PGA
ADC
PGA
ADC
METROLOGY FEATURES
(PER PHASE)
IRMS, VRMS
ACTIVE POWER, VA
YX, ANGLE
WAVEFORM BUFFER
ENERGY/POWER/CF
ACCUMULATION
LINE FREQUENCY
ETC.
LOW
POWER
COMPARATOR
14331-019
Figure 38. Functions Available in PSM1 and PSM2
As indicated in Table 8, the SPI is not available in PSM2. To check
whether the current inputs are above the user configured tamper
threshold, check the IRQ0 and IRQ1 pins (see the Measurements
(PSM2) section for more information).
One register is retained during PSM2 and PSM3: PSM2_CFG, as
shown in Table 8. Note that if PSM0 or PSM1 is entered, PSM2_CFG
returns to it default value and must be rewritten before reentering
PSM2 (see the Measurements (Normal Mode) section,
Measurements (PSM1) section, and Measurements (PSM2)
section for details on functionality in PSM0, PSM1, and PSM2).
Table 8‘ Power Modes (PSMO, PSMI, PSMZ, and PSM3) information) thh 1‘ ONE int lRQl vnn mmw l 0.5ms V ‘0 sl'd IRQI
ADE9078 Data Sheet
Rev. 0 | Page 26 of 107
Table 8. Power Modes (PSM0, PSM1, PSM2, and PSM3)
PSMx
Power
Mode Description
PM1
Pin
PM0
Pin
Power
Consumption Functions Available
SPI
Available
Retained Registers
When Switching into
Power Mode
PSM0 Normal mode 0 0 10 mA All functions. Yes Not applicable
PSM1
Tamper
measurement
mode
0
1
9 mA
Active and reactive power, IRMS, VRMS, all
calculated using the PSM1 computation method.
ZX, period, and angle measurements are available.
The neutral current channel, waveform buffer, and
energy/power/CF accumulations are disabled.
Yes
Not applicable
PSM2
Current peak
detect mode
1
0
115 µA
Current peak detect.
No
PSM2_CFG
PSM3 Idle 1 1 50 nA None. No PSM2_CFG
Power-On Sequence
HOST CONFIGURES
IC VIA SPI AND THEN
WRITES RUN
REGISTER TO START
MEASUREMENTS
20ms0.5ms
0
VOLTAGE (V)
~26ms
ADE9078
RSTDONE
INTERRUPT
TRIGGERED
CRYSTAL
OSCILLATOR
STARTS
POR TIMER
TURNED ON
AVDD, DVDD
LDO TURNED
ON
POWER APPLIED
TO IC
IN PSM0, PSM1
14331-020
Figure 39. Power-On Sequence for PSM0 and PSM1
After power is applied to the VDD pin of the ADE9078, the
device checks the state of the PM0 and PM1 pins to check the
power supply mode (see the Power Modes section for more
information). If in PSM1 or PSM0 (PM1, PM0 = 00 or 01) and
if the RESET pin is high, the AVDD and DVDD LDOs turn on
after VDD reaches 2.4 V to 2.6 V. If t h e RESET pin is low, the
AVDD and DVDD LDOs are not turned on. Note that a clamp
limits the current used to charge the AVDD and DVDD LDOs
to approximately 17 mA per LDO. The power supply source must
be able to handle approximate charge current of 40 mA.
When AVDD and DVDD are both above 1.3 V to 1.5 V and
VDD is above 2.4 V to 2.6 V, a 20 ms timer is started to allow
additional time for the supplies to reach their normal potentials
(VDD between 2.7 V and 3.6 V, AVDD at 1.9 V, and DVDD at
1.7 V). After this timer has elapsed, the crystal oscillator starts.
The RSTDONE interrupt is triggered approximately 26 ms later,
bringing the IRQ1 pin low and setting the RSTDONE bit in the
STATUS1 register. This RSTDONE interrupt indicates to the
user that the ADE9078 has finished its power-up sequence.
Then, the user can configure the IC via the SPI (see the Quick
Start section for a list of important registers to configure). After
configuring the device, write the run register to start the DSP so
that it starts making measurements. Note that registers from
Address 0x000 through Address 0x0FF and Address 0x400
through Address 0x5FF are restored to their default values
during power-on. Registers from Address 0x200 through
Address 0x3FF are cleared within 500 µs from when the run
register value changes from 0x0000 to 0x0001. Also note that
the waveform buffer, Address 0x800 through Address 0xFFF, is
not cleared after reset.
In PSM2 and PSM3, the AVDD and DVDD LDOs are not
turned on. The RSTDONE interrupt does not occur and the SPI
port is not available (see the Power Modes section for more
information on these modes).
Brownout Detection
Power-on reset (POR) circuits monitor the VDD, AVDD, and
DVDD supplies. If AVDD or DVDD drop below a threshold
between 1.3 V and 1.5 V, or VDD drops below a threshold between
2.4 V and 2.6 V, the IC is held in reset. If the power-on sequence
begins again, the ADE9078 waits until AVDD and DVDD are
above 1.3 V to 1.5 V and VDD is above 2.4 V to 2.6 V to start
the 20 ms POR timer. A RSTDONE interrupt on the IRQ1 pin
indicates when the ADE9078 can be reinitialized via SPI.
.H.
Data Sheet ADE9078
Rev. 0 | Page 27 of 107
Reset
If the RESET pin goes low for 1 μs, the AVDD and DVDD LDOs
turn off. The power on sequence resumes from the point where
the AVDD and DVDD LDOs are turned on (see the Power-On
Sequence section for details). A software reset is initiated by
writing the SWRST bit in the CONFIG1 register, which resets
the digital logic and takes ~60 μs to complete.
For applications that require putting the ADE9078 into a low
power mode, it is recommended to use PSM3. In this mode, the
ADE9078 consumes approximately 2 μA, much lower than the
100 μA current consumption obtained when the ADE9078
RESET pin is held low (see Table 1 for the exact PSM3 current
consumption).
Changing to PSM2 or PSM3
The state of the PM1 and PM0 pins is continuously monitored.
If the power mode changes from PSM0 or PSM1 to PSM2 or
PSM3 (PM1, PM0 = 10 or 11) for 1 μs, the AVDD and DVDD
LDOs are turned off. When the power mode switches back to
PSM0 or PSM1, the power on sequence resumes from the point
where AVDD and DVDD LDOs are turned on (see the Power-
On Sequence section for details).
MEASUREMENTS (NORMAL MODE)
The ADE9078 offers per phase total IRMS and VRMS as well as
total active power, VAR, VA, and fundamental VAR powers. The
instantaneous low-pass filtered powers can be accumulated into
power or energy registers and are available in pulsed outputs,
CF1 through CF4.
Power quality information, such as zero-crossing detection, line
period, and angle measurements, is also available.
A waveform buffer stores samples directly from the ADC,
calculated resampled data, or processed current and voltage
samples.
The measurements described are available in PSM0, the normal
operating mode. A reduced set of features is available in PSM1
and PSM2 (see the Power Modes section for more details on
these operating modes).
SINC4
AND
DECIMATION
AVD D
LDO
DVDD
LDO
SPI
1.25V
REFERENCE
TEMP
SENSOR
CF1
TO CF4
IRQ0
IRQ1
SPI
PM1
PM0
ADE9078
PGA
ADC
PGA
ADC
SAR
AVAILABLE IN PSM0
AVAILABLE IN PSM2
DISABLED IN PSM1
PGA
ADC
PGA
ADC
PGA
ADC
PGA
ADC
PGA
ADC
METROLOGY FEATURES
(PER PHASE)
IRMS, VRMS
ACTIVE POWER, VA
YX, ANGLE
WAVEFORM BUFFER
ENERGY/POWER/CF
ACCUMULATION
LINE FREQUENCY
ETC.
LOW
POWER
COMPARATOR
14331-034
Figure 40. Features Available in Each Operating Mode
Current Channel
The current channel datapath for IA, IB, and IC is shown in
Figure 41. The current channel ADC waveforms can be sampled
at the sinc4 output in the xI_SINC_DAT registers at 16 kSPS, or
further decimated by an IIR low-pass filter in the xI_LPF_DAT
registers at 4 kSPS. Gain and phase compensation are applied,
creating the xI_PCF instantaneous current waveforms that update
at 4 kSPS. The xI_PCF waveforms are used for total active power,
VAR , IRM S , VA , a nd f u n d am e nt a l VA R ca lcu lat io ns . T h e xI _ P C F
value is also monitored in the current peak detection circuit. The
rms of the sum of instantaneous currents measurement uses the
AI_PCF, BI_PCF, and CI_PCF current channel waveforms to
calculate the neutral current or ro calculate the net vector current
sum including the neutral current measurement, NI_PCF (see
the Neutral Current RMS, RMS of Sum of Instantaneous Currents
section for more information). Finally, the angle measurements
indicate the time between the current channel zero crossing and
the voltage channel zero crossing on the same phase or current
channels on the other phases, updating at 512 kSPS in the
ANGLx_x registers.
The neutral current channel, Channel IN, offers a neutral
current sum rms and is used in an rms of instantaneous current
measurement, as shown in Figure 42. For more information
about these calculations, see the Neutral Current RMS, RMS of
Sum of Instantaneous Currents section. Channel IN offers a
gain calibration (NIGAIN) and a phase calibration (NPHCAL).
The digital integrator on Channel IN is enabled by setting the
ININTEN bit in the CONFIG0 register. Note that the Channel IN
neutral current modulator is turned off in PSM1.
ADEson “PC; ’mvzmu » Burrs! —A mv / —> .—/ v m‘w M I F” J {- mum v x « \ .01 av av W W av 4v El ADEQWB ~ch; L Wm -wAvEFom mm M5 :| w r“ °—| l—‘/ v mm“ H I F" - J PM W I v \ \ \ uv av w V ..v W W ,.v V VECYOR mm: was mum cumm :Im amuuwom
ADE9078 Data Sheet
Rev. 0 | Page 28 of 107
RESAMPLED WAVEFORM
DATA RANGE
IN
IN
ANALOG INPUT RANGE
PHASE
COMP
INTEGRATOR
WF_SRC
0xFBFF FB90 =
–67,110,000
0x0471 15C0 =
+74,520,000
0x0474 E650 =
+74,770,000
RESAMPLING
ADC_
REDIRECT
MUX
TOTAL ACTIVE AND
REACTIVE POWER
CALCULATION
ZX DETECTION
FUNDAMENTAL
REACTIVE POWER
CALCULATION
TOTAL CURRENT RMS
VA P O W E R
CALCULATIONS
CURRENTPEAK
DETECTION
NOT AVAILABLE IN ADE9078 PSM1
NOTE: ACC MODE.ICONSEL ONLY AFFECTS IB CHANNEL CALCULATION
CURRENT CHANNE L (IA, IB, IC)
CURRENT CHANNE L (xI_PCF)
DATA RANGE
SINC4 + IIR LPF (xI_LPF_DAT)
DATA RANGE
SINC4 OUTPUT (xI_SINC_D AT)
DATA RANGE
ICONSEL*
0x0400 0470 =
+67,110,000
ZX_SRC_SEL
INTENHPFDIS
xIGAINxxIGAIN
0x46B4 =
+18,100
0xB94C =
–18,100
0xFB8B 19B0 =
–74,770,000
0xFB8E EA40 =
–74,520,000
14331-035
16 kSPS
4 kSPS
4 kSPS
Figure 41. Current Channel Datapath
IN
IN
ANALOG INPUT RANGE
PHASE
COMP
INTEGRATOR
WF_SRC
RESAMPLING
ADC_
REDIRECT
MUX
NOT AVAILABLE IN ADE9078 PSM1
NEUTRAL CURRENT CHANNEL (IN)
ININT_EN
NIGAIN NIPHCAL
RESAMPLED WAVEFORM
DATA RANGE
0xFBFF FB90 =
–67,110,000
0x0471 15C0 =
+74,520,000
0x0474 E650 =
+74,770,000
CURRENT CHANNE L (xI_PCF)
DATA RANGE
SINC4 + IIR LPF (xI_LPF_DAT)
DATA RANGE
SINC4 OUTPUT (xI_SINC_D AT)
DATA RANGE
0x0400 0470 =
+67,110,000
0x46B4 =
+18,100
0xB94C =
–18,100
0xFB8B 19B0 =
–74,770,000
0xFB8E EA40 =
–74,520,000
14331-036
16kSPS
4kSPS
4kSPS
Figure 42. Neutral Current Channel Datapath
IA MODULATOR V I IA DIGITAL DATAPATH m"
Data Sheet ADE9078
Rev. 0 | Page 29 of 107
Current Channel Measurement Update Rates
Table 9 indicates the registers that hold current channel
measurements and the rate at which they update.
Table 9. Current Channel Measurement Update Rates
Register Name Description
Update
Rate
(kSPS)
AI_SINC_DAT IA sinc4 filter output 16
BI_SINC_DAT IB sinc4 filter output 16
CI_SINC_DAT IC sinc4 filter output 16
NI_SINC_DAT IN sinc4 filter output 16
AI_LPF__DAT IA sinc4 + IIR low-pass filter
output and decimation
4
BI_LPF__DAT IB sinc4 + IIR low-pass filter
output and decimation
4
CI_LPF__DAT IC sinc4 + IIR low-pass filter
output and decimation
4
NI_LPF__DAT IN sinc4 + IIR low-pass filter
output and decimation
4
AI_PCF Instantaneous current on IA 4
BI_PCF Instantaneous current on IB 4
CI_PCF Instantaneous current on IC 4
NI_PCF Instantaneous current on IN 4
AIRMS Filtered based total rms of IA 4
BIRMS Filtered based total rms of IB 4
CIRMS Filtered based total rms of IC 4
NIRMS Filtered based total rms of IN 4
ISUMRMS Filtered rms of sum of
instantaneous currents
(AI_PCF + BI_PCF +
CI_PCF ± NI_PCF) (see the
Neutral Current RMS, RMS of
Sum of Instantaneous
Currents section)
4
IPEAK Peak current channel
sample (see the Peak
Detection section)
4
ANGLx_x Voltage to current or
current to current phase
angle (see the Angle
Measurement section)
CLKIN/24 =
512
ADC_REDIRECT Multiplexer
The ADE9078 provides a multiplexer that allows any ADC
output to be redirected to any digital processing datapath.
By default, each modulator is mapped to its corresponding
datapath. For example, the IAP and IAN pins go into the IA
modulator, which is mapped to the IxA digital processing
datapath. Write to the ADC_REDIRECT register to change the
ADC to digital channel mapping.
The redirection can be useful to simplify PCB layout,
depending on if the ADE9078 is on the top or bottom of the
PCB by redirecting the IA ADC output to the IC digital datapath
and the IC ADC output to the IA digital datapath. To achieve
this configuration, write IA_DIN = 010 and IC_DIN = 000 in
the ADC_REDIRECT register.
Alternatively, the VA voltage channel output can be used for all
three datapaths by writing VB_DIN = 100 and VC_DIN = 100
in the ADC_REDIRECT register.
The neutral current channel does not offer a zero-crossing
output or angle measurements. To calibrate the phase of the
neutral current NI_PCF signal, direct the neutral current ADC
output to Phase B digital current channel and check how its
angle corresponds to Phase A by writing IA_DIN = 111.
REFERENCE
Σ-Δ
MODULATOR
V
IN
IA_DIN[2:0]
AI_SINC_DAT AI_LPF_DAT
IA_MOD
011
IB_MOD
IC_MOD
IN_MOD
VA_MOD
VB_MOD
VC_MOD
IA_MOD
000
001
010
100
101
110
111
14331-037
Figure 43. ADC_REDIRECT Modulator to Digital Datapath Multiplexing
Current Channel Gain, xIGAIN
There are many sources of gain error in an energy metering
system. The current sensor, including current transformer burden
resistors, may have some error. There is device to device gain
error in the ADE9078 device itself and the voltage reference
may have some variation (see Table 1 for the device
specifications).
The ADE9078 provides a current gain calibration register so
that each metering device has the same current channel scaling.
The current channel gain varies with xIGAIN as shown in the
following equation:
GAINHPF
xIGAIN
GainChannelCurrent _
2
1
27
×
+=
Use the following equation to calculate the xIGAIN value for a
given current channel gain:
xIGAIN = round((Current Channel Gain − 1) × 227)
where round() is a function to round to the nearest integer.
The current channel gain can be positive or negative.
For example, to increase the gain of the current channel up by
10% to 1.1,
xIGAIN = round((1.1 − 1) × 227) = 13,421,773 =
0x00CC CCCD
To decrease the gain by 10% to 0.9:
xIGAIN = round((0.9 − 1) × 227) = −13,421,773 =
0xFF33 3333
Mnsununz ma) was: (am Table 10. HPF Comer Gain with 50 Hz Input Signal ,um
ADE9078 Data Sheet
Rev. 0 | Page 30 of 107
It is also possible to use the current channel gain register to
change the sign of the current channel, which may be useful if
the current sensor was installed backwards. To compensate for
this situation, use current channel gain = −1.
xIGAIN = round((−1 − 1) × 227) = −268,435,456 =
0xF000 0000
If the multipoint gain and phase feature is used, it is
recommended to use the xIGAIN for the main correction,
performed at the nominal current for the meter (see the
Multipoint Gain and Phase Calibration section for more
information).
Note that for a given phase,
|Current Channel Gain × Voltage Channel Gain ×
Power Gain| ≤ 3.75
IB Calculation Using ICONSEL
Write the ICONSEL bit in the ACCMODE register to calculate
IB = −IA IC. This setting can help save the cost of a current
transformer in some 3-wire delta configurations. See the Applying
the ADE9078 to a 3-Wire Delta Service section for more
information.
High-Pass Filter
A high-pass filter is provided to remove dc offsets for accurate
rms and energy measurements.
The ADE9078 high-pass filter on the current and voltage channels
is enabled by default. It can be disabled by writing the DISPHPF bit
in the CONFIG0 register = 1.
It is recommended to leave the high-pass filter enabled to achieve
the metering performance listed in the specifications in Table 1.
For some applications, it is desirable to increase the high-pass
filter corner, such as to improve performance when a Rogowski
coil current sensor is used.
The high-pass filter corner is selectable using the HPF_CRN bits in
the CONFIG2 register.
Table 10. HPF Corner Gain with 50 Hz Input Signal
HPF_
CRN
f−3 dB
(Hz)
HPF_
GAIN
Settling Time
to 1% for DC
Step (sec)
Settling Time
to 0.1% for DC
Step (sec)
0 38.7 0.80 0.0178 0.0268
1 19.6 0.94 0.0363 0.0544
2 9.90 0.99 0.0731 0.1097
3
4.97
1.00
0.1468
0.2202
4
2.49
1.00
0.2942
0.4412
5 1.25 1.00 0.5889 0.8833
6 (default) 0.625 1.00 1.1784 1.7675
7 0.313 1.00 2.3573 3.5359
Digital Integrator
A digital integrator is included to allow easy interfacing to di/dt
current sensors, also known as Rogowski coils. The di/dt sensor
output increases 20 dB/decade over the frequency range. To
compensate for this increased output, the digital integrator applies
20 dB/decade gain with a phase shift of approximately −9.
A second-order antialiasing filter is required to avoid noise
aliasing back in the band of interest when the ADC is sampling.
To enable the digital integrator on the IA, IB, and IC channels,
set the INTEN bit in the CONFIG0 register. To enable the digital
integrator on the neutral current, IN channel, set the ININTEN bit
in the CONFIG0 register.
Figure 44 through Figure 47 show the magnitude and phase
response of the ADE9078 digital integrator with the
recommended DICOEFF value of 0xFFFFE000.
MAGNITUDE (dB)
FREQUENCY (Hz)
–150
0.1 110 100 1k
–100
–50
0
50
14331-038
Figure 44. Digital Integrator Magnitude Response, DICOEFF = 0xFFFFE000
PHASE (dB)
FREQUENCY (Hz)
0400 800 1200 1600 2000
14331-039
Figure 45. Digital Integrator Phase Response, DICOEFF = 0xFFFFE000
MAGNVTUDE um I 49 as 49 9A .5935 pus: may its as 4997 : nun nu SE <0> «nun v av - 4 DELAYV av on: SAMPLE
Data Sheet ADE9078
Rev. 0 | Page 31 of 107
MAGNITUDE (dB)
FREQUENCY
(Hz)
40 45 50 60 6555 70 8075 85 90
14331-040
Figure 46. Digital Integrator Magnitude Response from 40 Hz to 90 Hz,
DICOEFF = 0xFFFFE000
PHASE (dB)
FREQUENCY (Hz)
40 45 50 60 6555 70 8075 85 90
14331-141
Figure 47. Digital Integrator Phase Response from 40 Hz to 90 Hz, DICOEFF =
0xFFFFE000
The recommended DICOEFF value is 0xFFFFE000.
Phase Compensation
The ADE9078 phase compensation uses a digital filter to
achieve a phase adjustment of ±0.001°. This high resolution
improves the total active energy and reactive energy
performance at low power factors.
The phase calibration range is 15° to +4.5° at 50 Hz.
To achieve this phase compensation, the voltage channel is
delayed by one 4 kSPS sample, 4.5° at 50 Hz.
°×= 360
DSP
LINE
f
f
DelayChannelVoltage
°=
°
×= 5.
4360
4000
50
DelayChannelVoltage
The current channel is then delayed by a digital filter, according
to the value programmed into the xPHCALx register. The resulting
phase correction depends on the value in the xPHCALx register.
The following equation gives the phase correction between the
input current and voltage after the combined voltage and
current delays. In the following formula, phase correction is
positive to correct a current that lags the voltage, and phase
correction is negative to correct a situation where the current leads
the voltage, such as occurs with a current transformer:
××+
××
+×
=
ω
ω
ω
ω
cos21
sin2
arctan
cos2
sin
arctan(Degrees)
27
27
27
xPHCALx
xPHCALx
xPHCALx
CorrectionPhase
where ω = 2π × fLINE/fDSP.
Calculate the xPHCALx register value can from the desired
phase correction according to the following equation:
( )
( )
27
2
2sin
sinsin ×
+
=xPHALx
ϕω
ωωϕ
For example, if fLINE = 50 Hz, fDSP = 4 kHz, and the current leads
the voltage by 0.1°, the phase correction = −0.1°. Write
xPHCALx = 0xFFE9 7889 to correct for this phase difference.
ω = 2π × 50/4000 = 0.07854
( )
()
()
( )
( )
7889
9
xFFE0
471,
476
,1
2
1.
0
07854.
02
sin
07854.
0sin07854
.01
.0
sin
27
==
×
×
+
=RADIANS
RADIANS
xPHALx
DELAY V BY
ONE SAMPLE
4.5° AT 50Hz
INPUT
VOLTAGE
OUTPUT
VOLTAGE
DELAY I
BY UP TO
19.
INPUT
CURRENT
CURRENT
TRANSFORMER
SENSOR:
CURRENT LEADS
VOLTAGE
OUTPUT
CURRENT
I LEADS V BY UP TO 15°
PHASE COMPENSATION = –15°
ADE9078
14331-041
Figure 48. Phase Compensation Example for Current Transformer, Where the
Current Leads the Voltage
ADE9078
DELAY V BY
ONE SAMPLE
4.5
°
AT 50Hz
INPUT
VOLTAGE
OUTPUT
VOLTAGE
DELAY I
BY
INPUT
CURRENT
CURRENT LAGS
VOLTAGE
OUTPUT
CURRENT
I LAGS V BY UP TO 4.5
°
PHASE CORRECTION = +4.5
°
14331-042
Figure 49. Phase Compensation Example Where Current Lags Voltage
‘‘‘‘‘‘
ADE9078 Data Sheet
Rev. 0 | Page 32 of 107
Using the equations in the Phase Compensation section, it can
be seen that at 60 Hz, the voltage channel delay is 5.4°, as follows:
°
=
°
×= 4.
5
360
4000
60
(Degrees)Delay
Channel
Voltage
This calculation leads to a phase calibration range of −15° to
+5.4° at 60 Hz.
Note that this phase compensation is equivalent to a delay or
advance in time. As the line frequency varies, the applied phase
compensation varies as well according to the phase correction
equation.
Multipoint Gain and Phase Calibration
The ADE9078 allows the current channel gain and phase
compensation to vary as a function of the calculated input
current rms amplitude in xIRMS, which is useful to correct for
the nonlinearities of current transformer sensors to achieve
very high meter accuracy, for example in Class 0.2 meters.
Multipoint Gain and Phase
The current channel gain, xIGAIN, is applied regardless of the
xIRMS input signal level. This gain compensates for the
nominal gain error of the current channel, including the current
transformer and burden resistors. If multipoint gain and phase
compensation is enabled, an additional current gain value is
applied based on the xIRMS value to compensate for the
current transformer gain shift over input signal amplitude. The
current channel datapath is shown in Figure 51.
If multipoint gain and phase compensation is enabled, with
MTEN = 1 in the CONFIG0 register, an additional gain factor,
xIGAIN0 through xIGAIN4, is applied based on the xIRMS
current rms amplitude and the MTTHR_Lx and MTTHR_Hx
register values, as shown in Figure 50.
The applied current channel phase compensation varies based
on the xIRMS input signal level as well if multipoint gain and
phase compensation is enabled.
GAIN,
PHASE
CORRECTION
MTTHR_L1 ,
MTTHR_H0
MTTHR_H4 =
FULL SCALE
MTTHR_L0
= 0
REGION0 REGION1 REGION2 REGION3 REGION4
MTTHR_L2,
MTTHR_H1
MTTHR_L3,
MTTHR_H2
MTTHR_L4,
MTTHR_H3
xIGAIN4
xPHCAL4
xIGAIN3
xPHCAL3
xIGAIN2
xPHCAL2
xIGAIN1
xPHCAL1
xIGAIN0
xPHCAL0
XXXX
X
14331-043
Figure 50. Multipoint Gain and Phase Calibration
The MTTHR_Lx and MTTHR_Hx registers set up the regions
in which to apply each set of corrections, allowing hysteresis.
The decision of which coefficients to apply is done according to
the following rules:
If xIRMS >MTTHR_H[current_region]
If current_region 3
Current_region++;
Else If xIRMS < MTTHR_L[current_region]
If current_region 1
current_region--;
xIGAIN = xIGAIN[current_region];
xPHCAL = xPHCAL[current_region];
xMTREGION = current_region;
For example, if AIRMS goes above MTTHR_H2, the gain and
phase correction is set to AIGAIN3 and APHCAL3,
respectively. Then, if AIRMS goes below MTTHR_L3, the gain
and phase correction is set to AIGAIN2 and APHCAL2.
For proper operation, the value of the registers must be
increasing such that MTTHR_L0 < MTTHR_L1 <
MTTHR_H0 < MTTHR_L2 < MTTHR_H1 < MTTHR_L3 <
MTTHR_H2 < MTTHR_L4 < MTTHR_H3 < MTTHR_H4.
The following example configuration uses two regions, such
that Region 0 is used from 0 A to 20A and Region 1 is used
from 22 A to full scale:
MTTHR_L0 = 0
MTTHR_L1 = 0x95 9AC1 (20 A for this meter)
MTTHR_H0 = 0xA4 90A2 (22 A for this meter)
MTTHR_L2 = 0x7FFFFFFFE (maximum positive
threshold − 1)
MTTHR_H1 = 0x7FFFFFFFF (maximum positive
threshold)
The xMTREGION registers indicate the current region for each
phase and correspondingly, which xIGAINx and xPHCALx
coefficients are being applied.
Multipoint phase and gain calibration is disabled by default. To
enable it, set the MTEN bit in the CONFIG0 register.
Single-Point Gain and Phase
When multipoint gain and phase calibration is disabled, single-
point gain and phase calibration is allowed.
In this case, the xIGAIN register is applied. No additional current
channel gain is applied based on the xIRMS amplitude.
When multipoint gain and phase calibration is disabled, the
xPHCAL0 phase compensation is always applied regardless of
the xIRMS value.
ammo: V n Monummi E nv @ av @ W @ zxnzvzc-nom
Data Sheet ADE9078
Rev. 0 | Page 33 of 107
HPF
IN
IN
+1V
ANALOG INPUT RANGE
0V
–1V
ADE9078
PHASE
COMP
CURRENT RMS
(xIRMS)
INTEGRATOR
IB = –IA–IC
ADC_
REDIRECT
MUX
TOTAL ACTIVE AND
REACTIVE POWER
CALCULATION
FUNDAMENTAL
REACTIVE POWER
CALCULATION
CURRENT PEAK
DETECTION
TOTAL VA
POWER
CALCULATION
NOT AVAILABLE IN ADE9078 PSM1
NOTE: ACC MODE.ICONSEL ONLY AFFECTS IB CHANNEL CALCULATION
CURRENT CHANNEL (IA, IB, IC)
ICONSEL*
INTENHPFDIS
xIGAINx
xIGAIN
MTEN
IF MTEN = 1,
xIGAINx, PHASE COMP CHANGES BASED ON
xIRMS, MTTHR_Lx AND MTTHR_Hx
0: xIGAINx = xIGAIN0; PHASE COMP = xPHCAL0
1: xIGAINx = xIGAIN1; PHASE COMP = xPHCAL1
2: xIGAINx = xIGAIN2; PHASE COMP = xPHCAL2
3: xIGAINx = xIGAIN3; PHASE COMP = xPHCAL3
4: xIGAINx = xIGAIN4; PHASE COMP = xPHCAL4
xIRMS
xI_PCF
0xFBFF FB90 =
–67,110,000
SINC4 OUTPUT (xI_SINC_D AT)
DATA RANGE
0x0400 0470 =
+67,110,000
0x0471 15C0 =
+74,520,000
SINC4 + IIR LPF (xI_LPF_DAT)
DATA RANGE
0xFB8E EA40 =
–74,520,000
0x0474 E650 =
+74,770,000
CURRENT CHANNE L (xI_PCF)
DATA RANGE
0xFB8B 19B0 =
–74,770,000
14331-044
Figure 51. Current Channel with Multi-Point Gain and Phase Correction
14331-085
xVGAIN
HPF
VOLTAGE PEAK
DETECTION
REFERENCE
Σ-
MODULATOR
VP
V
IN
V
IN
+1V
ANALOG INPUT RANGE
0V
–1V
VN
ADE9078 VOLTAGE CHANNEL
SINC4 LPF 4:1
WF_SRC
WF_CAP_SEL
HPFDIS
xV_PCF
ADC_
REDIRECT
MUX
TOTAL ACTIVE AND
REACTIVE POWER
CALCULATION
ZX_SRC_SEL ZX DETECTION
TOTAL VOLTAGE RMS
VA POWER
CALCULATIONS
FUNDAMENTAL
REACTIVE POWER
CALCULATIONS
NOTE: CONSEL SUPPORTS SEVERAL 3-WIRE AND 4-WIRE HARDWARE CONFIGURATIONS
100
VA = VA VB;
VB = VA VC;
VC = VC VB;
VB = VA
VB = –VA – VC
VB = VA VC
011
010
001
000
RESAMPLED WAVEFORM
DATA RANGE
0V 0V0V
0xFBFF_FB90 =
–67,110,000
0x0471_15C0 =
+74,520,000
0x0474_E650 =
+74,770,000
0V
VOLTAGE CHANNE L (xV_PCF)
DATA RANGE
SINC4 + IIR LPF (xV_LPF_DAT)
DATA RANGE
SINC4 OUTPUT (xV_SINC_DAT)
DATA RANGE
0x0400_0470 =
+67,110,000
0x46B4 =
+18,100
0xB94C =
–18,100
0xFB8B_19B0 =
–74,770,000
0xFB8E_EA40 =
–74,520,000
16 kSPS
4 kSPS
WAVEFORM
BUFFER
RESAMPLING
VCONSEL*
4 kSPS
NOT AVAILABLE IN ADE9078 PSM1
Figure 52. Voltage Channel Datapath
Table 11. Volmg: Channel Measurement Update Rates
ADE9078 Data Sheet
Rev. 0 | Page 34 of 107
Table 11. Voltage Channel Measurement Update Rates
Register Name Description Update Rate
AV_SINC_DAT VA sinc4 filter output 16 kSPS
BV_SINC_DAT VB sinc4 filter output 16 kSPS
CV_SINC_DAT
VC sinc4 filter output
16 kSPS
AV_LPF_DAT VA sinc4 + IIR low-pass filter and decimator output fDSP = 4 kSPS
BV_LPF_DAT VB sinc4 + IIR low-pass filter and decimator output fDSP = 4 kSPS
CV_LPF_DAT VC sinc4 + IIR low-pass filter and decimator output fDSP = 4 kSPS
AV_PCF Instantaneous voltage on VA fDSP = 4 kSPS
BV_PCF Instantaneous voltage on VB fDSP = 4 kSPS
CV_PCF Instantaneous voltage on VC fDSP = 4 kSPS
AVRMS Filtered based total rms of VA fDSP = 4 kSPS
BVRMS Filtered based total rms of VB fDSP = 4 kSPS
CVRMS Filtered based total rms of VC fDSP = 4 kSPS
VPEAK Peak current channel sample (see the Peak Detection section) fDSP = 4 kSPS
APERIOD Line period measurement on VA fDSP = 4 kSPS
BPERIOD Line period measurement on VB fDSP = 4 kSPS
CPERIOD
Line period measurement on VB
f
DSP
= 4 kSPS
COM_PERIOD Line period measurement on combined signal from VA, VB, VC (see the Combined Voltage Zero Crossing
section)
fDSP = 4 kSPS
ANGLx_x Voltage to current or current to current phase angle (see the Angle Measurement section) CLKIN/24 = 512 kSPS
Voltage Channel
The voltage channel datapath is shown in Figure 52. The voltage
channel ADC waveforms can be sampled at the sinc4 output, in
the xV_SINC_DAT registers, at 16 kSPS or further decimated
by an IIR low-pass filter, in xV_LPF_DAT registers at fDSP =
4 kSPS. Gain and phase compensation are applied, creating the
xV_PCF instantaneous voltage waveforms that update at fDSP =
4 kSPS. The xV_PCF waveforms are used for total active power,
VA R , I R MS , VA , and fundamental VAR calculations. The
xV_PCF value is also monitored in the voltage peak detection
circuit. Finally, angle measurements indicate the time between
the voltage channel zero crossing and the current channel zero
crossing on the same phase or voltage channels on the other
phases, updating at CLKIN/24 = 512 kSPS in the ANGLx_x
registers. The line period measurement xPERIOD indicates the line
period, as described in the Line Period Calculation section.
Voltage Channel Measurements
Table 11 indicates the registers that hold voltage channel
measurements and the rate at which they update.
Voltage Channel Gain
Use the xVGAIN registers to calibrate the voltage channel of
each phase. The xVGAIN register has the same scaling as the
xIGAIN register.
GAINHPF
xIGAIN
GainChannelVoltage _
2
1
27
×
+
=
See the Current Channel Gain, xIGAIN section for more
information about the gain scaling and how it is affected by the
high-pass filter corner (HPF_CRN) selection.
Note that for a given phase,
|Current Channel Gain × Voltage Channel Gain ×
Power Gain| ≤ 3.75
Energy Measurements Overview
Figure 53 shows how AI_PCF and AV_PCF calculate per phase
rms and power and how the calculated rms and power are
accumulated into the AWATTHR and AWATT_ACC registers
and the CFx pulse outputs.
Per Phase Energy Measurements Update Rate
Instantaneous power measurements, including as xWATT,
xVAR, xVA, xFVAR, update at a rate of fDSP = 4 kSPS.
These measurements are accumulated into power measurements in
xWATT_ACC register that update at a user defined interval
ranging from 500 µs to 2 sec, depending on the selection in the
PWR_TIME register.
Energy measurements update every 4 kSPS by default and can
store up to 211 sec of accumulation at full scale. Alternatively, these
registers can be set into a different accumulation mode where
they update after a user defined number of line cycles or
samples.
The power factor measurements update every 4096/4 kSPS =
1.024 sec.
Data Sheet ADE9078
Rev. 0 | Page 35 of 107
AI_PCF
AV_PC F
PER PHASE
RMS AND
POWER
CALCULATION
AWATTHR
AVARHR
AFVARHR
AVAHR
PER PHASE
ENERGY
ACCUMULATION
AWATT_ACC
AVAR_ACC
AFVAR_ACC
AVA_ACC
CF1 PULSE OUTPUT
CF2 PULSE OUTPUT
CF3 PULSE OUTPUT
CF4 PULSE OUTPUT
ENERGY TO
FREQUENCY
AWATT
AVAR
AFVAR
AIRMS
AVRM S
AVA
ADE9078
PER PHASE
POWER
ACCUMULATION
14331-045
Figure 53. Per Phase Power and Energy Calculations from xI_PCF and xV_PCF Waveforms
Table 12. Active Power Related Register Update Rate
Register Name Description Update Rate
AWATT Low-pass filtered total active power on Phase A 4 kSPS
BWATT Low-pass filtered total active power on Phase B 4 kSPS
CWATT Low-pass filtered total active power on Phase C 4 kSPS
AWATT_ACC Accumulated total active power on Phase A After the PWR_TIME 4 kSPS samples, from 500 μs to 2.048 sec
BWATT_ACC Accumulated total active power on Phase B After the PWR_TIME 4 kSPS samples, from 500 μs to 2.048 sec
CWATT_ACC Accumulated total active power on Phase C After the PWR_TIME 4 kSPS samples, from 500 μs to 2.048 sec
AWATTHR Accumulated total active energy on Phase A According to the settings in EP_CFG and EP_TIME; holds up to
211 sec of energy at full scale
BWATTHR Accumulated total active energy on Phase B According to the settings in EP_CFG and EP_TIME; holds up to
211 sec of energy at full scale
CWATTHR Accumulated total active energy on Phase C According to the settings in EP_CFG and EP_TIME; holds up to
211 sec of energy at full scale
APF Phase A Power Factor (see the Power Factor section) Every 1.024 sec
BPF Phase A Power Factor (see the Power Factor section) Every 1.024 sec
CPF Phase A Power Factor (see the Power Factor section) Every 1.024 sec
Juneau a inwtmon LPF? 42am.
ADE9078 Data Sheet
Rev. 0 | Page 36 of 107
Power-Based and Filter-Based RMS Measurement
Algorithms
Filter-Based Total RMS
The ADE9078 offers current and voltage rms measurements,
which are calculated by squaring the input signal, low-pass
filtering, and then taking the square root of the result, as shown
in Figure 54.
x
2
2
15
xRMSOS
xRMS
52,866,837
xV_PCF OR xI_PCF
VOLTAGE OR CURRENT
CHANNEL WAVEFORM
14331-046
Figure 54. Filter Based RMS
The low-pass filter, LPF2, extracts the rms value, attenuating
harmonics of a 50 Hz or 60 Hz fundamental by at least 64 dB so
that at full scale, the variation in the calculated rms value is very
small, ±0.064% error. Note that the rms reading variation
increases as the input signal becomes smaller because the noise
in the measurement increases.
The filter based rms measurement is typically within 0.5% error
over a 5000:1 dynamic range and within 0.1% error over a 1000:1
dynamic range. Refer to the specifications in Table 1 to understand
what performance to expect from this measurement.
Note that the xRMS register does not read 0 with the xP and xN
inputs shorted together.
The filter based rms has a bandwidth of 1.6 kHz, as given in
Table 1.
The rms calculations, one for each channel, AIRMS, BIRMS,
CIRMS, NIRMS, AVRMS, BVRMS, and CVRMS, are updated
every 4 kSPS. The ISUMRMS calculation uses the same method
to calculate ISUMRMS, where ISUM = IA + IB + IC ± IN, and also
updates at 4 kSPS (see the Neutral Current RMS, RMS of Sum of
Instantaneous Currents section for more information).
The xRMS value at full scale is 52,866,837d. Table 13 shows the
rms settling time to 99% of full scale for a 50 Hz signal.
Table 13. RMS Settling Time
Configuration RMS Settling Time, FS = 99% (sec)
Integrator On, HPF On, and
LPF2 On
1.09
Integrator Off, HPF On, and
LPF2 On
0.96
For high performance at small input signals, below 1000:1, it is
recommended to calibrate the offset of this measurement using
the xRMSOS registers. The offset must be calibrated at the smallest
input signal that requires good performance—do not calibrate
this measurement with zero input signal.
The following equation indicates how the xRMSOS register
value modifies the result in the xRMS register:
xRMSOSxRMS0xRMS 152 2
where xRMS0 is the initial xRMS register value before offset
calibration.
At 1000:1, the expected xRMS0 = 52,866,837/1000 =
52,866.837. Then, one bit in the xRMSOS register changes
xRMS by (52,867.147 − 52,866.837)/52,866.837 = 0.0006%.
147.867,5212
1000
52,866,837 15
2
xRMS
Neutral Current RMS, RMS of Sum of Instantaneous
Currents
The ADE9078 calculates the neutral current rms from a neutral
current sensor input into the INP and INN pins, and stores the
result in the NIRMS register. A NIRMSOS register allows offset
calibration of this measurement. The scaling is the same as for
the other xIRMS and xIRMSOS registers (see the Filter-Based
Total RMS section for more information).
The ADE9078 also calculates the rms of ISUM = IA + IB + IC ± IN
and stores the result in ISUMRMS. An ISUMRMSOS register
allows offset calibration of this measurement. The scaling is the
same as for the other xIRMS and xIRMSOS registers (see the
Filter-Based Total RMS section for more information).
If a neutral current sensor is not used, write 0 to the
ISUM_CFG bits in the CONFIG0 register, and then ISUMRMS
approximates the neutral current from the sum of IA, IB, and IC.
If the measured neutral current, NI_PCF, deviates from the sum
of AI_PCF + BI_PCF + CI_PCF current channel waveforms,
there may be a fault in the system.
To determine how big the mismatch is between the measured
neutral current and the measured Channel A, Channel B, and
Channel C currents, select ISUM_CFG[1:0] to 01 or 10 based
on the direction of the neutral current with respect to the other
current channel waveforms.
Table 14. ISUM Configuration Options
ISUM_CFG[1:0] ISUM Calculation
00, 11 ISUM = AI_PCF + BI_PCF + CI_PCF
01 ISUM = AI_PCF + BI_PCF + CI_PCF + NI_PCF
10 ISUM = AI_PCF + BI_PCF + CI_PCF − NI_PCF
ISUMRMS has the same scaling as xIRMS. Note that if AI_PCF,
BI_PCF, and CI_PCF are all at full scale and in phase with each
other, with ISUM_CFG = 00 or 11, ISUMRMS is 3 × 52,866,837d =
158,600,511d. If AI_PCF, BI_PCF, CI_PCF, and NI_PCF are all
Data Sheet ADE9078
Rev. 0 | Page 37 of 107
at full scale and in phase with each other, with the ISUM_CFG = 01
then ISUMRMS is 4 × 52,866,837d = 211,467,348d.
To receive an indication if ISUMRMS exceeds a threshold,
configure ISUMLVL. The MISMTCH bit in STATUS0 and
associated interrupt indicate if there is a change in the
relationship between ISUMRMS and ISUMLVL.
Calculate the desired value of ISUMLVL according to the
following equation:
=X
SCALEFULLxIRMS
ISUMLVL __
where:
xIRMS_FULL_SCALE is the nominal xIRMS value with full-
scale inputs, 52,866,837.
X is the desired current level to indicate a MISMTCH error. For
example, set the ISUMLVL to warn about a rms of sum of
instantaneous currents greater than 10,000:1 from full scale, X =
10,000.
Total Active Power
Total active power is commonly used for billing purposes. It
includes power on the fundamental and on the harmonics.
Figure 55 shows how the low-pass filtered total active power on
Phase A is calculated. First, the AI_PCF and AV_PCF waveforms
are multiplied together. Then, the result is low-pass filtered,
unless DISAPLPF = 1. Finally, the APGAIN is applied to perform
a gain correction and the AWATTOS value is applied to correct
the active power offset.
APGAIN AWATTOS
AWATT
LPF2
DISAPLPF
AI_PCF
AV_PCF
ENERGY/
POWER/
CF ACCUMULATION
14331-047
Figure 55. Total Active Power (AWATT) Calculation
Figure 56 shows the relationship between the I and V input
signals and the instantaneous active power and low-pass filtered
active power, assuming that I and V are at full scale with just the
fundamental present and a power factor of 1.
If DISAPLPF = 1, AWAT T r e f l ects the instantaneous active
power and if it is 0, AWATT reflects the low-pass filtered active
power in Figure 56, assuming that APGAIN = 0 and
AWAT T OS = 0.
–0.062%
+0.062%
LOW-PASS FILTERED
ACTIVE POWER
20,823,646
0
INSTANTANEOUS
ACTIVE POWER
I, V FUNDAMENTAL
INPUT SIGNAL
14331-048
Figure 56. Instantaneous Active Power and Low-Pass Filtered Active Power at
a Power Factor of 1
The low-pass filter, LPF2, extracts the total active power,
attenuating harmonics of a 50 Hz or 60 Hz fundamental by
64 dB so that at full scale, the variation in the low-pass filtered
active power is very small, ±0.062%.
The resulting AWATT signal has an update rate of 4 kSPS and a
bandwidth of 1.6 kHz, as given in Table 1.
Phase B and Phase C have similar datapaths to those described
for AWATT to calculate BWATT and CWATT, with individual
gain and phase coefficients, BPGAIN and BWATTOS, and
CPGAIN, and CWATTOS.
The xPGAIN register has the same scaling as the xIGAIN
register (see the equations in the Current Channel Gain,
xIGAIN section).
Note that for a given phase,
|Current Channel Gain × Voltage Channel Gain ×
Power Gain| ≤ 3.75
xWATTOS has the same scaling as xWATT. To understand how
xWAT T O S affects the xWATT value, use the following
equation:
=
X
SCALEFULLxWATT
xWATTOS __
1
where:
xWATT_FULL_SCALE is the nominal xWATT value with full-
scale inputs, 20,823,646. Note that xVAR and VA have the same
scaling, so the same equation can be used for all three offsets.
X is the smallest power level to calibrate. For example, to
calibrate the energy at 10,000 from full scale, X = 10,000.
%05.0
000,10
20,823,646
1=
=xWATTOS
ADE9078 Data Sheet
Rev. 0 | Page 38 of 107
Then, each bit in the xWATTOS register can correct an error of
0.05% at 10,000:1. Note that in most applications, the total
active power performance with small inputs is sufficient with
xWATTOS at zero.
Table 15 shows the settling times for total active power for a
50 Hz signal.
Table 15. Total Active Power Settling Time
Total Active Power Settling Time (sec)
Configuration FS = 99% FS = 99.90%
Integrator On, HPF On,
and LPF2 On
0.85 1.2
Integrator Off, HPF On,
and LPF2 On
0.85 1.2
Integrator Off, HPF On,
and LPF2 Off
0.06 0.66
Tota l Re ac tive Power
Total reactive power includes reactive power on the fundamental
and on the harmonics. The current channel, AI_PCF, is shifted
by 90° at the fundamental and at all harmonics. Then, this signal is
multiplied by the voltage waveform, AV_PCF. Then the result is
low-pass filtered, unless DISRPLPF = 1. Finally the APGAIN is
applied to perform a gain correction and the AVAROS value is
applied to correct the VAR offset. Note that, in most applications,
the total reactive power performance with small inputs is
sufficient with AVAROS at zero.
Figure 57 shows how the total reactive power calculation is
performed.
APGAIN AVAROS
AVAR
LPF2
DISRPLPF
AI_PCF
AV_PCF
ENERGY/
POWER/
CF ACCUMULATION
90 DEGREE
PHASE SHIFT
π
2
14331-049
Figure 57. Total Reactive Power (AVAR) Calculation
The total reactive power at a power factor of 0 has a similar ripple
to the total active power at a power factor of 1 (see Figure 56).
The resulting AVAR signal has an update rate of 4 kSPS and a
bandwidth of 1.6 kHz, as given in Table 1.
Phase B and Phase C have similar datapaths to those described
for AVAR to calculate BVAR and CVAR, with individual gain
and phase coefficients, BPGAIN and BVAROS, and CPGAIN
and CVAROS.
XVAROS has the same scaling as xVAR (see the Total Active
Power section to understand how to calculate this register value).
It is possible to disable total reactive power by setting the
VAR_DIS register. Note that the run register must be set to 0
before changing the VAR_DIS setting and must then be set to 1
again.
Table 16 shows the settling times for total reactive power for a
50 Hz signal.
Table 16. Total Reactive Power Settling Time
Total Reactive Power Settling Time (sec)
Configuration FS = 99% FS = 99.90%
Integrator On, HPF
On, and LPF2 On
0.85 1.19
Integrator Off, HPF
On, and LPF2 On
0.85 1.19
Integrator Off, HPF
On, and LPF2 Off
0.02 0.07
Tota l App arent Power
Apparent power is generated by multiplying the current rms
measurement, xIRMS by the corresponding voltage rms, xVRMS
and then applying a gain correction, APGAIN. The result is stored
in the AVA register. Note that the offset of the total apparent
power calculation is performed by calibrating the AIRMS and
AVRMS measurements, using the AIRMSOS and AVRMSOS
registers (see the Filter-Based Total RMS section for more
information on the rms calculation).
The resulting AVA signal has an update rate of 4 kSPS and a
bandwidth of 1.6 kHz, as given in Table 1.
Phase B and Phase C have similar datapaths to those described
for AVA to calculate BVA and CVA, with individual gain
coefficients, BPGAIN and CPGAIN.
In some applications, if a tamper is detected on the voltage channel
inputs, it is desirable to accumulate the apparent energy assuming
that the voltage were at a nominal level. The ADE9078 offers a
register (VNOM) that can be set to a value to correspond to
240 V rms. If the VNOMx_EN bits in the CONFIG0 register
are set, VNOM is multiplied by xIRMS when calculating xVA.
Table 17 shows the settling times for total apparent power for a
50 Hz signal.
Table 17. Total Apparent Power Settling Time
Configuration
Total Apparent Power Settling Time,
FS = 99% (sec)
Integrator On, HPF On,
and LPF2 On
1.09
Integrator Off, HPF On,
and LPF2 Off
0.96
AIRMSOS
APGAIN
AIRMSOS
AIRMS
AVA
AVRM S
VNOM
LPF2
AI_PCF x
2
2
15
2
15
LPF2
AI_PCF
ENERGY/
POWER/
CF ACCUMULATION
1
x
2
0
14331-050
Figure 58. Total Apparent Power (AVA) Calculation
Table 18‘ Fundamemal Reactive Power Senling Time VAR m- mam:
Data Sheet ADE9078
Rev. 0 | Page 39 of 107
Fundamental Reactive Power
The fundamental reactive power in the ADE9078 is calculated
using a proprietary algorithm that requires initialization of the
network frequency and of the nominal voltage measured in the
voltage channel. The SELFREQ bit in the ACCMODE register
selects whether the system is 50 Hz or 60 Hz. For a 50 Hz system,
clear the SELFREQ bit, and for a 60 Hz system, set the SELFREQ
bit to 1. The SELFREQ selection must be made prior to writing
1 to the run register.
The VLEVEL register indicates the nominal value of the voltage
channel. Calculate VLEVEL according to the following equation:
VLEVEL = X × 1,144,084
where X is the dynamic range that the nominal input signal is at
with respect to full scale.
It is recommended to set the voltage channel input so that the
nominal voltage, for example 240 V rms, corresponds to one half of
the analog input signal range of the ADE9078. The ADE9078
can support ±1 V peak, 0.707 V rms inputs, so it is recommended
to scale the voltage channel inputs to 0.353 V rms. Then, with a
nominal input of 240 V, the input signal is at half of full scale and X
is equal to 2. Write 2,288,168d to the VLEVEL register to configure
this feature.
VLEVEL = 2 × 1,144,084 = 2,288,168
After configuring the SELFREQ and VLEVEL parameters, the
ADE9078 tracks the fundamental line frequency within ±5 Hz
of the 50 Hz or 60 Hz frequency selected in SELFREQ. If a larger
frequency range than ±5 Hz is required in the application, monitor
the line period (xPERIOD) and change the SELFREQ selection
accordingly. Note that the run register must be set to 0 before
changing the SELFREQ setting and must then be set to 1 again.
The fundamental current signal is shifted by 9 and multiplied
by the fundamental voltage signal. This is then gained by
APGAIN and offset correction is applied according to the
AFVAROS register.
APGAIN AFVAROS
AFVAR
AI_PCF
AV_PCF FUNDAMENTAL
VAR
ENERGY/
POWER/CF
ACCUMULATION
14331-051
Figure 59. Fundamental Reactive Power, AFVAR
The fundamental reactive power at a power factor of 0 has a similar
ripple to the total active power at a power factor of 1 (see Figure 56).
xFVAROS has the same scaling as xFVAR (see the Total Active
Power section to understand how to calculate this register value.
Table 18 shows the settling times for fundamental reactive
power for a 50 Hz signal.
Table 18. Fundamental Reactive Power Settling Time
Fundamental Reactive Power
Settling Time (sec)
Configuration FS = 99% FS = 99.90%
Integrator On, HPF On,
and LPF2 On
0.86 1.11
Integrator Off, HPF On,
and LPF2 On
0.86 1.11
Power Factor
The total active power and total apparent power are
accumulated over 1.024 sec. Then the power factor is calculated
on each phase according to the following equation:
sec
1.024
overd
accumulateAVA
sec1.024
over
daccumulate
AWATT
APF =
The sign of the APF calculation follows the sign of AWATT.
To calculate what quadrant the energy is in, look at the sign of
the total or fundamental reactive energy in that phase along
with the sign of the xPF or xWATT value, as indicated in Figure 60.
The quadrants with capacitive power factors are indicated in
dark gray whereas the quadrants with inductive power factor
are indicated in light gray. Note that for most applications, the
watts are received (imported) from the grid and so the active
powe