STM32F745xx, STM32F746xx Datasheet by STMicroelectronics

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‘ ’l hie.ougmenfed @Qfi A176 (10x1 LQFPZOB 28x28 mm) . General—purpose DMA: 16—s‘ream DMA
This is information on a product in full production.
February 2016 DocID027590 Rev 4 1/227
STM32F745xx
STM32F746xx
ARM
®
-based Cortex
®
-M7 32b MCU+FPU, 462DMIPS, up to 1MB Flash/320+16+ 4KB
RAM, USB OTG HS/FS, ethernet, 18 TIMs, 3 ADCs, 25 com itf, cam & LCD
Datasheet - production data
Features
Core: ARM® 32-bit Cortex®-M7 CPU with FPU,
adaptive real-time accelerator (ART
Accelerator™) and L1-cache: 4KB data cache
and 4KB instruction cache, allowing 0-wait
state execution from embedded Flash memory
and external memories, frequency up to
216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz
(Dhrystone 2.1), and DSP instructions.
Memories
Up to 1MB of Flash memory
1024 bytes of OTP memory
SRAM: 320KB (including 64KB of data
TCM RAM for critical real-time data) +
16KB of instruction TCM RAM (for critical
real-time routines) + 4KB of backup SRAM
(available in the lowest power modes)
Flexible external memory controller with up
to 32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND
memories
Dual mode Quad-SPI
LCD parallel interface, 8080/6800 modes
LCD-TFT controller up to XGA resolution with
dedicated Chrom-ART Accelerator™ for
enhanced graphic content creation (DMA2D)
Clock, reset and supply management
1.7 V to 3.6 V application supply and I/Os
POR, PDR, PVD and BOR
Dedicated USB power
4-to-26 MHz crystal oscillator
Internal 16 MHz factory-trimmed RC (1%
accuracy)
32 kHz oscillator for RTC with calibration
Internal 32 kHz RC with calibration
Low-power
Sleep, Stop and Standby modes
–V
BAT supply for RTC, 32×32 bit backup
registers + 4KB backup SRAM
3×12-bit, 2.4 MSPS ADC: up to 24 channels
and 7.2 MSPS in triple interleaved mode
2×12-bit D/A converters
Up to 18 timers: up to thirteen 16-bit (1x low-
power 16-bit timer available in Stop mode) and
two 32-bit timers, each with up to 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input. All 15 timers
running up to 216 MHz. 2x watchdogs, SysTick
timer
General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
Debug mode
SWD & JTAG interfaces
–Cortex
®-M7 Trace Macrocell™
Up to 168 I/O ports with interrupt capability
Up to 164 fast I/Os up to 108 MHz
Up to 166 5 V-tolerant I/Os
Up to 25 communication interfaces
Up to 4× I2C interfaces (SMBus/PMBus)
Up to 4 USARTs/4 UARTs (27 Mbit/s,
ISO7816 interface, LIN, IrDA, modem
control)
Up to 6 SPIs (up to 50 Mbit/s), 3 with
muxed simplex I2S for audio class
accuracy via internal audio PLL or external
clock
2 x SAIs (serial audio interface)
2 × CANs (2.0B active) and SDMMC
interface
SPDIFRX interface
– HDMI-CEC
Advanced connectivity
USB 2.0 full-speed device/host/OTG
controller with on-chip PHY
USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
10/100 Ethernet MAC with dedicated DMA:
supports IEEE 1588v2 hardware, MII/RMII
8- to 14-bit parallel camera interface up to
54 Mbyte/s
True random number generator
CRC calculation unit
RTC: subsecond accuracy, hardware calendar
96-bit unique ID
Table 1. Device summary
Reference Part number
STM32F745xx STM32F745IE, STM32F745VE, STM32F745VG,
STM32F745ZE, STM32F745ZG, STM32F745IG
STM32F746xx
STM32F746BE, STM32F746BG, STM32F746IE,
STM32F746IG, STM32F746NE, STM32F746NG,
STM32F746VE, STM32F746VG, STM32F746ZE,
STM32F746ZG
LQFP100 (14x14 mm)
LQFP144 (20x20 mm)
LQFP176 (24x24 mm)
UFBGA176 (10x10 mm)
&"'!
TFBGA216 (13x13 mm)
LQFP208 (28x28 mm)
WLCSP143
(4.5x5.8 mm)
TFBGA100 (8x8 mm)
www.st.com
Contents STM32F745xx STM32F746xx
2/227 DocID027590 Rev 4
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1 ARM® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 18
2.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6 AXI-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.7 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.8 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.9 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.10 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.11 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 22
2.13 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.14 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.15 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.16 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.17 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.17.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.17.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.18 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.18.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.18.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.18.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 30
2.19 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 30
2.20 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.21 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.22 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.22.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 34
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2.22.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.22.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.22.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.22.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.22.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.22.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.23 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.24 Universal synchronous/asynchronous receiver transmitters (USART) . . 37
2.25 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 38
2.26 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.27 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.28 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.29 Audio and LCD PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.30 SD/SDIO/MMC card host interface (SDMMC) . . . . . . . . . . . . . . . . . . . . . 40
2.31 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 40
2.32 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.33 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 41
2.34 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 41
2.35 High-definition multimedia interface (HDMI) - consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.36 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.37 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.38 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.39 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.40 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.41 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.42 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.43 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
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5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . 101
5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . 101
5.3.5 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . 101
5.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 131
5.3.13 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.3.15 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 137
5.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.3.19 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.3.20 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.3.21 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.3.24 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.3.25 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.3.26 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
5.3.27 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
5.3.28 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
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5
5.3.29 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 191
5.3.30 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 192
5.3.31 SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . 194
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
6.1 LQFP100, 14 x 14 mm low-profile quad flat package information . . . . . 196
6.2 TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array
package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
6.3 WLCSP143, 4.539x 5.849 mm, 0.4 mm pitch wafer level chip
scale package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.4 LQFP144, 20 x 20 mm low-profile quad flat package information . . . . . 205
6.5 LQFP176, 24 x 24 mm low-profile quad flat package information . . . . . 208
6.6 LQFP208, 28 x 28 mm low-profile quad flat package information . . . . . 212
6.7 UFBGA 176+25, 10 x 10 x 0.65 mm ultra thin-pitch ball grid
array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
6.8 TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array
package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
6.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 224
A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
List of tables STM32F745xx STM32F746xx
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List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F745xx and STM32F746xx features and peripheral counts . . . . . . . . . . . . . . . . . . 13
Table 3. Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 27
Table 4. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 5. Voltage regulator modes in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 7. I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 8. USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 9. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 10. STM32F745xx and STM32F746xx pin and ball definition . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 11. FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 12. STM32F745xx and STM32F746xx alternate function mapping . . . . . . . . . . . . . . . . . . . . . 76
Table 13. STM32F745xx and STM32F746xx register boundary addresses. . . . . . . . . . . . . . . . . . . . 90
Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 18. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 100
Table 19. VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 20. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 101
Table 21. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . 101
Table 22. reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 23. Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM RAM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 26. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory or SRAM on AXI (L1-cache disabled), regulator ON . . . . . 106
Table 27. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory on ITCM interface (ART disabled), regulator ON . . . . . . . . 107
Table 28. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 29. Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 109
Table 30. Typical and maximum current consumption in Sleep mode, regulator OFF . . . . . . . . . . . 109
Table 31. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 110
Table 32. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 111
Table 33. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 112
Table 34. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 35. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 36. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 37. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 38. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 39. HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 41. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
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Table 42. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 43. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 44. PLLI2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 45. PLLISAI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 46. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 47. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 48. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 49. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 50. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 51. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 52. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 53. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 54. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 55. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 56. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 57. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 58. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 59. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 60. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 61. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 62. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 63. ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 64. ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 65. ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 66. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 148
Table 67. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 148
Table 68. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 69. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 70. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 71. internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 72. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 73. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 74. Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 75. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 76. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 77. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 78. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 79. USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 80. USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 81. USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 82. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 83. USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 84. Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 85. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 86. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 87. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 171
Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 171
Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 172
Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 173
Table 92. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 93. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 174
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Table 94. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 95. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 176
Table 96. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 97. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 98. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 99. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 100. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 101. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 102. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 103. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 104. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 105. LPSDR SDRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 106. Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 107. Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 108. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 109. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 110. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 195
Table 111. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 195
Table 112. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . . 197
Table 113. TFBGA100, 8 x 8 × 0.8 mm thin fine-pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 114. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 201
Table 115. WLCSP143, 4.539x 5.849 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 116. WLCSP143 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 117. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 118. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 119. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 120. UFBGA 176+25, 10 × 10 × 0.65 mm ultra thin fine-pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 121. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 217
Table 122. TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 123. TFBGA216 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 220
Table 124. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 125. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 126. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 224
Table 127. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
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List of figures
Figure 1. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 2. STM32F745xx and STM32F746xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3. STM32F745xx and STM32F746xx AXI-AHB bus matrix architecture . . . . . . . . . . . . . . . . 19
Figure 4. VDDUSB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 5. VDDUSB connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 25
Figure 7. PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 8. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 9. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 10. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 29
Figure 11. STM32F74xVx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 12. STM32F74xVx TFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 13. STM32F74xZx WLCSP143 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 14. STM32F74xZx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 15. STM32F74xIx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 16. STM32F74xBx LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 17. STM32F74xIx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 18. STM32F74xNx TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 19. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 20. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 21. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 22. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 23. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 24. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 25. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in low drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 26. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in medium low drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 27. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in medium high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 28. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 29. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in high medium drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 30. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 31. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 32. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 33. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 34. HSI deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 35. LSI deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 36. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 37. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 38. FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 39. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 40. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 41. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
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Figure 42. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 43. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 150
Figure 44. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 150
Figure 45. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 46. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 47. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 48. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 49. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 50. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 51. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 52. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 53. USB OTG full speed timings: definition of data signal rise and fall time. . . . . . . . . . . . . . 164
Figure 54. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 55. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 56. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 57. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 58. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 170
Figure 59. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 172
Figure 60. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 61. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 62. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 63. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 64. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 65. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 66. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 67. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 68. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 184
Figure 69. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 185
Figure 70. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 71. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 72. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 73. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 74. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 75. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 76. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 77. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 78. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 79. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 196
Figure 80. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 81. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 82. TFBGA100, 8 × 8 × 0.8 mm thin fine-pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 83. TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 84. TFBGA100, 8 × 8 × 0.8mm thin fine-pitch ball grid array package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 85. WLCSP143, 4.539x 5.849 mm, 0.4 mm pitch wafer level chip scale
package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 86. WLCSP143, 4.539x 5.849 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
DocID027590 Rev 4 11/227
STM32F745xx STM32F746xx List of figures
11
Figure 87. WLCSP143, 0.4 mm pitch wafer level chip scale package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 88. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 205
Figure 89. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 90. LQFP144, 20 x 20mm, 144-pin low-profile quad flat package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 91. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 208
Figure 92. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 93. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 94. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 212
Figure 95. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 96. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 97. UFBGA 176+25, 10 × 10 × 0.65 mm ultra thin fine-pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 98. UFBGA176+25, 10 x 10 x 0.65 mm, ultra fine-pitch ball grid array
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 99. UFBGA 176+25, 10 × 10 × 0.6 mm ultra thin fine-pitch ball grid array
package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 100. TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Figure 101. TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 102. TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array
package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Description STM32F745xx STM32F746xx
12/227 DocID027590 Rev 4
1 Description
The STM32F745xx and STM32F746xx devices are based on the high-performance ARM®
Cortex®-M7 32-bit RISC core operating at up to 216 MHz frequency. The Cortex®-M7 core
features a single floating point unit (SFPU) precision which supports all ARM® single-
precision data-processing instructions and data types. It also implements a full set of DSP
instructions and a memory protection unit (MPU) which enhances the application security.
The STM32F745xx and STM32F746xx devices incorporate high-speed embedded
memories with a Flash memory up to 1 Mbyte, 320 Kbytes of SRAM (including 64 Kbytes of
Data TCM RAM for critical real-time data), 16 Kbytes of instruction TCM RAM (for critical
real-time routines), 4 Kbytes of backup SRAM available in the lowest power modes, and an
extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB
buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal
and external memories access.
All the devices offer three 12-bit ADCs, two DACs, a low-power RTC, thirteen general-
purpose 16-bit timers including two PWM timers for motor control and one low-power timer
available in Stop mode, two general-purpose 32-bit timers, a true random number generator
(RNG). They also feature standard and advanced communication interfaces.
Up to four I2Cs
Six SPIs, three I2Ss in duplex mode. To achieve the audio class accuracy, the I2S
peripherals can be clocked via a dedicated internal audio PLL or via an external clock
to allow synchronization.
Four USARTs plus four UARTs
An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI),
Two CANs
Two SAI serial audio interfaces
An SDMMC host interface
Ethernet and camera interfaces
LCD-TFT display controller
Chrom-ART Accelerator™
SPDIFRX interface
HDMI-CEC
Advanced peripherals include an SDMMC interface, a flexible memory control (FMC)
interface, a Quad-SPI Flash memory interface, a camera interface for CMOS sensors. Refer
to Table 2: STM32F745xx and STM32F746xx features and peripheral counts for the list of
peripherals available on each part number.
The STM32F745xx and STM32F746xx devices operate in the –40 to +105 °C temperature
range from a 1.7 to 3.6 V power supply. A dedicated supply input for USB (OTG_FS and
OTG_HS) is available on all the packages except LQFP100 for a greater power supply
choice.
The supply voltage can drop to 1.7 V with the use of an external power supply supervisor
(refer to Section 2.17.2: Internal reset OFF). A comprehensive set of power-saving mode
allows the design of low-power applications.
The STM32F745xx and STM32F746xx devices offer devices in 8 packages ranging from
100 pins to 216 pins. The set of included peripherals changes with the device chosen.
STM32F745xx STM32F746xx Description
DocID027590 Rev 4 13/227
These features make the STM32F745xx and STM32F746xx microcontrollers suitable for a wide range of applications:
Motor drive and application control,
Medical equipment,
Industrial applications: PLC, inverters, circuit breakers,
Printers, and scanners,
Alarm systems, video intercom, and HVAC,
Home audio appliances,
Mobile applications, Internet of Things,
Wearable devices: smartwatches.
Figure 2 shows the general block diagram of the device family.
Table 2. STM32F745xx and STM32F746xx features and peripheral counts
Peripherals STM32F745Vx STM32F746Vx STM32F745Zx STM32F746Zx STM32F745Ix STM32F746Ix STM32F745Bx STM32F746Bx STM32F745Nx STM32F746Nx
Flash memory in Kbytes 512 1024 512 1024 512 1024 512 1024 512 1024 512 1024 512 1024 512 1024 512 1024 512 1024
SRAM in
Kbytes
System 320(240+16+64)
Instruction 16
Backup 4
FMC memory controller Yes(1)
Ethernet Yes
Timers
General-
purpose 10
Advanced-
control 2
Basic 2
Low-power 1
Random number generator Yes
Description STM32F745xx STM32F746xx
14/227 DocID027590 Rev 4
Communication
interfaces
SPI / I2S 4/3 (simplex)(2) 6/3 (simplex)(2)
I2C 4
USART/
UART 4/4
USB OTG
FS Yes
USB OTG
HS Yes
CAN 2
SAI 2
SPDIFRX 4 inputs
SDMMC Yes
Camera interface Yes
LCD-TFT No Yes No Yes No Yes No Yes No Yes
Chrom-ART Accelerator™
(DMA2D) Yes
GPIOs 82 114 140 168
12-bit ADC
Number of channels
3
16 24
12-bit DAC
Number of channels
Yes
2
Maximum CPU frequency 216 MHz(3)
Operating voltage 1.7 to 3.6 V(4)
Operating temperatures
Ambient temperatures: –40 to +85 °C /–40 to +105 °C
Junction temperature: –40 to + 125 °C
Package LQFP100
TFBGA100
WLCSP143
LQFP144
UFBGA176
LQFP176 LQFP208 TFBGA216
1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select.
2. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
3. 216 MHz maximum frequency for -40°C to + 85°C ambient temperature range (200 MHz maximum frequency for -40°C to + 105°C ambient temperature range).
4. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.17.2: Internal reset OFF).
Table 2. STM32F745xx and STM32F746xx features and peripheral counts (continued)
Peripherals STM32F745Vx STM32F746Vx STM32F745Zx STM32F746Zx STM32F745Ix STM32F746Ix STM32F745Bx STM32F746Bx STM32F745Nx STM32F746Nx
r2; uz u:E USE uek u:& u:% Han u=k uak u an u mm H E u E Hal u an umum “:9 u E u 21 u .3 u3l unn> um? Ho; smzzmsm smurmxx P03 ARAP uswm vwvw m Fms19la A9 are no! wmvahhle PM w m
DocID027590 Rev 4 15/227
STM32F745xx STM32F746xx Description
44
1.1 Full compatibility throughout the family
The STM32F745xx and STM32F746xx devices are fully pin-to-pin, compatible with the
STM32F4xxxx devices, allowing the user to try different peripherals, and reaching higher
performances (higher frequency) for a greater degree of freedom during the development
cycle.
Figure 1 give compatible board designs between the STM32F4xx families.
Figure 1. Compatible board design for LQFP100 package
The STM32F745xx and STM32F746xx LQFP144, LQFP176, LQFP208, TFBGA216,
UFBGA176, WLCSP143 packages are fully pin to pin compatible with STM32F4xxxx
devices.
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Description STM32F745xx STM32F746xx
16/227 DocID027590 Rev 4
Figure 2. STM32F745xx and STM32F746xx block diagram
1. The timers connected to APB2 are clocked from TIMxCLK up to 216 MHz, while the timers connected to APB1 are clocked
from TIMxCLK either up to 108 MHz or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.
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DocID027590 Rev 4 17/227
STM32F745xx STM32F746xx Functional overview
44
2 Functional overview
2.1 ARM® Cortex®-M7 with FPU
The ARM® Cortex®-M7 with FPU processor is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and a low-power consumption, while
delivering an outstanding computational performance and low interrupt latency.
The Cortex®-M7 processor is a highly efficient high-performance featuring:
Six-stage dual-issue pipeline
Dynamic branch prediction
Harvard caches (4 Kbytes of I-cache and 4 Kbytes of D-cache)
64-bit AXI4 interface
64-bit ITCM interface
2x32-bit DTCM interfaces
The processor supports the following memory interfaces:
Tightly Coupled Memory (TCM) interface.
Harvard instruction and data caches and AXI master (AXIM) interface.
Dedicated low-latency AHB-Lite peripheral (AHBP) interface.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU (floating point unit) speeds up the software development by using
metalanguage development tools, while avoiding saturation.
Figure 2 shows the general block diagram of the STM32F745xx and STM32F746xx
devices.
Note: Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core.
2.2 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
Functional overview STM32F745xx STM32F746xx
18/227 DocID027590 Rev 4
2.3 Embedded Flash memory
The STM32F745xx and STM32F746xx devices embed a Flash memory of up to 1 Mbyte
available for storing programs and data.
2.4 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify the data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean of
verifying the Flash memory integrity. The CRC calculation unit helps to compute a signature
of the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
2.5 Embedded SRAM
All the devices features:
System SRAM up to 320 Kbytes:
SRAM1 on AHB bus Matrix: 240 Kbytes
SRAM2 on AHB bus Matrix: 16 Kbytes
DTCM-RAM on TCM interface (Tighly Coupled Memory interface): 64 Kbytes for
critical real-time data.
Instruction RAM (ITCM-RAM) 16 Kbytes:
It is mapped on TCM interface and reserved only for CPU Execution/Instruction
useful for critical real-time routines.
The Data TCM RAM is accessible by the GP-DMAs and peripherals DMAs through specific
AHB slave of the CPU.The TCM RAM instruction is reserved only for CPU. It is accessed at
CPU clock speed with 0-wait states.
4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or VBAT mode.
2.6 AXI-AHB bus matrix
The STM32F745xx and STM32F746xx system architecture is based on 2 sub-systems:
An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol:
3x AXI to 32-bit AHB bridges connected to AHB bus matrix
1x AXI to 64-bit AHB bridge connected to the embedded flash
A multi-AHB Bus-Matrix:
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs,
Ethernet, USB HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM,
FMC, Quad-SPI, AHB and APB peripherals) and ensures a seamless and an
efficient operation even when several high-speed peripherals work
simultaneously.
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DocID027590 Rev 4 19/227
STM32F745xx STM32F746xx Functional overview
44
Figure 3. STM32F745xx and STM32F746xx AXI-AHB bus matrix architecture
1. The above figure has large wires for 64-bits bus and thin wires for 32-bits bus.
2.7 DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
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Functional overview STM32F745xx STM32F746xx
20/227 DocID027590 Rev 4
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals:
SPI and I2S
I2C
USART
General-purpose, basic and advanced-control timers TIMx
DAC
SDMMC
Camera interface (DCMI)
ADC
SAI
SPDIFRX
Quad-SPI
HDMI-CEC
2.8 Flexible memory controller (FMC)
The Flexible memory controller (FMC) includes three memory controllers:
The NOR/PSRAM memory controller
The NAND/memory controller
The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
The main features of the FMC controller are the following:
Interface with static-memory mapped devices including:
Static random access memory (SRAM)
NOR Flash memory/OneNAND Flash memory
PSRAM (4 memory banks)
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
8-,16-,32-bit data bus width
Independent Chip Select control for each memory bank
Independent configuration for each memory bank
Write FIFO
Read FIFO for SDRAM controller
The Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is
HCLK/2.
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
DocID027590 Rev 4 21/227
STM32F745xx STM32F746xx Functional overview
44
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
2.9 Quad-SPI memory interface (QUADSPI)
All devices embed a Quad-SPI memory interface, which is a specialized communication
interface targetting Single, Dual or Quad-SPI Flash memories. It can work in:
Direct mode through registers.
External flash status register polling mode.
Memory mapped mode.
Up to 256 Mbytes external flash are memory mapped, supporting 8, 16 and 32-bit access.
Code execution is supported.
The opcode and the frame format are fully programmable. Communication can be either in
Single Data Rate or Dual Data Rate.
2.10 LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
2 displays layers with dedicated FIFO (64x32-bit)
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
Up to 8 Input color formats selectable per layer
Flexible blending between two layers using alpha value (per pixel or constant)
Flexible programmable parameters for each layer
Color keying (transparency color)
Up to 4 programmable interrupt events.
2.11 Chrom-ART Accelerator™ (DMA2D)
The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
Rectangle filling with a fixed color
Rectangle copy
Rectangle copy with pixel format conversion
Rectangle composition with blending and pixel format conversion.
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
Functional overview STM32F745xx STM32F746xx
22/227 DocID027590 Rev 4
2.12 Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 97 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-
M7 with FPU core.
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
2.13 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 24 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 168 GPIOs can be connected
to the 16 external interrupt lines.
2.14 Clocks and startup
On reset the 16 MHz internal HSI RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can
then select as system clock either the RC oscillator or an external 4-26 MHz clock source.
This clock can be monitored for failure. If a failure is detected, the system automatically
switches back to the internal RC oscillator and a software interrupt is generated (if enabled).
This clock source is input to a PLL thus allowing to increase the frequency up to 216 MHz.
Similarly, full interrupt management of the PLL clock entry is available when necessary (for
example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 216 MHz while the maximum frequency of the high-speed APB domains is
108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz.
The devices embed two dedicated PLL (PLLI2S and PLLSAI) which allow to achieve audio
class performance. In this case, the I2S and SAI master clock can generate all standard
sampling frequencies from 8 kHz to 192 kHz.
DocID027590 Rev 4 23/227
STM32F745xx STM32F746xx Functional overview
44
2.15 Boot modes
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
All Flash address space mapped on ITCM or AXIM interface
All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface
The System memory bootloader
The boot loader is located in system memory. It is used to reprogram the Flash memory
through a serial interface.
2.16 Power supply schemes
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
VDD = 1.7 to 3.6 Vexternal power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, reset blocks,
RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
Note: VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to
Section 2.17.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode
versus device operating mode to identify the packages supporting this option.
VDDUSB can be connected either to VDD or an external independent power supply (3.0
to 3.6V) for USB transceivers (refer to Figure 4 and Figure 5). For example, when
device is powered at 1.8V, an independent power supply 3.3V can be connected to
VDDUSB. When the VDDUSB is connected to a separated power supply, it is independent
from VDD or VDDA but it must be the last supply to be provided and the first to
disappear. The following conditions VDDUSB must be respected:
During power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
During power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
–V
DDSUB rising and falling time rate specifications must be respected (see Table 20
and Table 21)
In operating mode phase, VDDUSB could be lower or higher than VDD:
- If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by
VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX.
- The VDDUSB supply both USB transceiver (USB OTG_HS and USB OTG_FS). If
only one USB transceiver is used in the application, the GPIOs associated to the
other USB transceiver are still supplied by VDDUSB.
- If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by
VDDUSB are operating between VDD_MIN and VDD_MAX.
VDDUSE VDD DDUSB
Functional overview STM32F745xx STM32F746xx
24/227 DocID027590 Rev 4
Figure 4. VDDUSB connected to VDD power supply
Figure 5. VDDUSB connected to external power supply
2.17 Power supply supervisor
2.17.1 Internal reset ON
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other packages, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
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STM32F745xx STM32F746xx Functional overview
44
reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes. The device remains in reset mode when VDD is below a specified threshold,
VPOR/PDR or VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
2.17.2 Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor VDD and should maintain the device in
reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to
VSS. Refer to Figure 6: Power supply supervisor interconnection with internal reset OFF.
Figure 6. Power supply supervisor interconnection with internal reset OFF
The VDD specified threshold, below which the device must be maintained under reset, is
1.7 V (see Figure 7).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
The brownout reset (BOR) circuitry must be disabled
The embedded programmable voltage detector (PVD) is disabled
VBAT functionality is no more available and VBAT pin should be connected to VDD.
All the packages, except for the LQFP100, allow to disable the internal reset through the
PDR_ON signal when connected to VSS.
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26/227 DocID027590 Rev 4
Figure 7. PDR_ON control with internal reset OFF
2.18 Voltage regulator
The regulator has four operating modes:
Regulator ON
Main regulator mode (MR)
Low-power regulator (LPR)
– Power-down
Regulator OFF
2.18.1 Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
MR mode used in Run/sleep modes or in Stop modes
In Run/Sleep mode
The MR mode is used either in the normal mode (default mode) or the over-drive
mode (enabled by software). Different voltages scaling are provided to reach the
best compromise between the maximum frequency and dynamic power
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DocID027590 Rev 4 27/227
STM32F745xx STM32F746xx Functional overview
44
consumption. The over-drive mode allows operating at a higher frequency than
the normal mode for a given voltage scaling.
In Stop modes
The MR can be configured in two ways during Stop mode:
MR operates in normal mode (default mode of MR in Stop mode)
MR operates in under-drive mode (reduced leakage mode).
LPR is used in the Stop modes:
The LP regulator mode is configured by software when entering Stop mode.
Like the MR mode, the LPR can be configured in two ways during Stop mode:
LPR operates in normal mode (default mode when LPR is ON)
LPR operates in under-drive mode (reduced leakage mode).
Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Refer to Table 3 for a summary of voltage regulator modes versus device operating modes.
Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin.
All packages have the regulator ON feature.
2.18.2 Regulator OFF
This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply
externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency.The two 2.2 µF ceramic capacitors should
be replaced by two 100 nF decoupling capacitors.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
Table 3. Voltage regulator configuration mode versus device operating mode(1)
1. ‘-’ means that the corresponding configuration is not available.
Voltage regulator
configuration Run mode Sleep mode Stop mode Standby mode
Normal mode MR MR MR or LPR -
Over-drive
mode(2)
2. The over-drive mode is not available when VDD = 1.7 to 2.1 V.
MR MR - -
Under-drive mode - - MR or LPR -
Power-down mode - - - Yes
Functional overview STM32F745xx STM32F746xx
28/227 DocID027590 Rev 4
In regulator OFF mode, the following features are no more supported:
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
The over-drive and under-drive modes are not available.
The Standby mode is not available.
Figure 8. Regulator OFF
The following conditions must be respected:
VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for
VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1
and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 9).
Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see
Figure 10).
If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a
reset must be asserted on PA0 pin.
Note: The minimum value of V12 depends on the maximum frequency targeted in the application.
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DocID027590 Rev 4 29/227
STM32F745xx STM32F746xx Functional overview
44
Figure 9. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization
1. This figure is valid whatever the internal reset mode (ON or OFF).
Figure 10. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization
1. This figure is valid whatever the internal reset mode (ON or OFF).
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30/227 DocID027590 Rev 4
2.18.3 Regulator ON/OFF and internal reset ON/OFF availability
2.19 Real-time clock (RTC), backup SRAM and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
Two programmable alarms.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
Three anti-tamper detection pins with programmable filter.
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby mode.
The RTC clock sources can be:
A 32.768 kHz external crystal (LSE)
An external resonator or oscillator(LSE)
The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
The high-speed external clock (HSE) divided by 32.
Table 4. Regulator ON/OFF and internal reset ON/OFF availability
Package Regulator ON Regulator OFF Internal reset ON Internal reset OFF
LQFP100
Yes No
Yes No
LQFP144,
LQFP208
Yes
PDR_ON set to
VDD
Yes
PDR_ON set to
VSS
TFBGA100,
LQFP176,
WLCSP143,
UFBGA176,
TFBGA216
Yes
BYPASS_REG set
to VSS
Yes
BYPASS_REG set
to VDD
DocID027590 Rev 4 31/227
STM32F745xx STM32F746xx Functional overview
44
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes.
All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt
and wakeup the device from the low-power modes.
2.20 Low-power modes
The devices support three low-power modes to achieve the best compromise between low-
power consumption, short startup time and available wakeup sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled.
The voltage regulator can be put either in main regulator mode (MR) or in low-power
mode (LPR). Both modes can be configured as follows (see Table 5: Voltage regulator
modes in Stop mode):
Normal mode (default mode when MR or LPR is enabled)
Under-drive mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup and
LPTIM1 asynchronous interrupt).
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising or falling edge on one of the 6 WKUP pins (PA0, PA2, PC1, PC13, PI8, PI11),
or an RTC alarm / wakeup / tamper /time stamp event occurs.
The Standby mode is not supported when the embedded voltage regulator is bypassed
and the 1.2 V domain is controlled by an external power.
Table 5. Voltage regulator modes in Stop mode
Voltage regulator
configuration Main regulator (MR) Low-power regulator (LPR)
Normal mode MR ON LPR ON
Under-drive mode MR in under-drive mode LPR in under-drive mode
Functional overview STM32F745xx STM32F746xx
32/227 DocID027590 Rev 4
2.21 VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when no external battery and an external supercapacitor are
present.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no
more available and VBAT pin should be connected to VDD.
2.22 Timers and watchdogs
The devices include two advanced-control timers, eight general-purpose timers, two basic
timers and two watchdog timers.
All timer counters can be frozen in debug mode.
Table 6 compares the features of the advanced-control, general-purpose and basic timers.
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STM32F745xx STM32F746xx Functional overview
44
Table 6. Timer feature comparison
Timer
type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complem
entary
output
Max
interfac
e clock
(MHz)
Max
timer
clock
(MHz)(1)
Advance
d-control
TIM1,
TIM8 16-bit
Up,
Down,
Up/down
Any
integer
between 1
and 65536
Yes 4 Yes 108 216
General
purpose
TIM2,
TIM5 32-bit
Up,
Down,
Up/down
Any
integer
between 1
and 65536
Yes 4 No 54 108/216
TIM3,
TIM4 16-bit
Up,
Down,
Up/down
Any
integer
between 1
and 65536
Yes 4 No 54 108/216
TIM9 16-bit Up
Any
integer
between 1
and 65536
No 2 No 108 216
TIM10,
TIM11 16-bit Up
Any
integer
between 1
and 65536
No 1 No 108 216
TIM12 16-bit Up
Any
integer
between 1
and 65536
No 2 No 54 108/216
TIM13,
TIM14 16-bit Up
Any
integer
between 1
and 65536
No 1 No 54 108/216
Basic TIM6,
TIM7 16-bit Up
Any
integer
between 1
and 65536
Yes 0 No 54 108/216
1. The maximum timer clock is either 108 or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR
register.
Functional overview STM32F745xx STM32F746xx
34/227 DocID027590 Rev 4
2.22.1 Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
Input capture
Output compare
PWM generation (edge- or center-aligned modes)
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
2.22.2 General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32F74xxx
devices (see Table 6 for differences).
TIM2, TIM3, TIM4, TIM5
The STM32F74xxx include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3,
and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload
up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-
bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent
channels for input capture/output compare, PWM or one-pulse mode output. This gives
up to 16 input capture/output compare/PWMs on the largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9
and TIM12 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers. They can also be used as simple time bases.
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STM32F745xx STM32F746xx Functional overview
44
2.22.3 Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
2.22.4 Low-power timer (LPTIM1)
The low-power timer has an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous / one-shot mode
Selectable software / hardware input trigger
Selectable clock source:
Internal clock source: LSE, LSI, HSI or APB clock
External clock source over LPTIM input (working even with no internal clock source
running, used by the Pulse Counter Application)
Programmable digital glitch filter
Encoder mode
2.22.5 Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
2.22.6 Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
2.22.7 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source.
Functional overview STM32F745xx STM32F746xx
36/227 DocID027590 Rev 4
2.23 Inter-integrated circuit interface (I2C)
The device embeds 4 I2C. Refer to Table 7: I2C implementation for the features
implementation.
The I2C bus interface handles communication between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
I2C-bus specification and user manual rev. 5 compatibility:
Slave and master modes, multimaster capability
Standard-mode (Sm), with a bitrate up to 100 kbit/s
Fast-mode (Fm), with a bitrate up to 400 kbit/s
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
Programmable setup and hold times
Optional clock stretching
System Management Bus (SMBus) specification rev 2.0 compatibility:
Hardware PEC (Packet Error Checking) generation and verification with ACK
control
Address resolution protocol (ARP) support
SMBus alert
Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
Programmable analog and digital noise filters
1-byte buffer with DMA capability
Table 7. I2C implementation
I2C features(1)
1. X: supported
I2C1 I2C2 I2C3 I2C4
Standard-mode (up to 100 kbit/s) X X X X
Fast-mode (up to 400 kbit/s) X X X X
Programmable analog and digital noise filters X X X X
SMBus/PMBus hardware support X X X X
Independent clock X X X X
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STM32F745xx STM32F746xx Functional overview
44
2.24 Universal synchronous/asynchronous receiver transmitters
(USART)
The device embeds USART. Refer to Ta b l e 8: USART implementation for the features
implementation.
The universal synchronous asynchronous receiver transmitter (USART) offers a flexible
means of full-duplex data exchange with external equipment requiring an industry standard
NRZ asynchronous serial data format.
The USART peripheral supports:
Full-duplex asynchronous communications
Configurable oversampling method by 16 or 8 to give flexibility between speed and
clock tolerance
Dual clock domain allowing convenient baud rate programming independent from the
PCLK reprogramming
A common programmable transmit and receive baud rate of up to 27 Mbit/s when
USART clock source is system clock frequency (Max is 216 MHz) and oversampling by
8 is used.
Auto baud rate detection
Programmable data word length (7 or 8 or 9 bits) word length
Programmable data order with MSB-first or LSB-first shifting
Programmable parity (odd, even, no parity)
Configurable stop bits (1 or 1.5 or 2 stop bits)
Synchronous mode and clock output for synchronous communications
Single-wire half-duplex communications
Separate signal polarity control for transmission and reception
Swappable Tx/Rx pin configuration
Hardware flow control for modem and RS-485 transceiver
Multiprocessor communications
LIN master synchronous break send capability and LIN slave break detection capability
IrDA SIR encoder decoder supporting 3/16 bit duration for normal mode
Smartcard mode ( T=0 and T=1 asynchronous protocols for Smartcards as defined in
the ISO/IEC 7816-3 standard )
Support for Modbus communication
The table below summarizes the implementation of all U(S)ARTs instances
Table 8. USART implementation
features(1) USART1/2/3/6 UART4/5/7/8
Data Length 7, 8 and 9 bits
Hardware flow control for modem X X
Continuous communication using DMA X X
Multiprocessor communication X X
Synchronous mode X -
Functional overview STM32F745xx STM32F746xx
38/227 DocID027590 Rev 4
2.25 Serial peripheral interface (SPI)/inter- integrated sound
interfaces (I2S)
The devices feature up to six SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 50 Mbits/s,
SPI2 and SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master
mode frequencies and the frame is configurable from 4 to 16 bits. The SPI interfaces
support NSS pulse mode, TI mode and Hardware CRC calculation. All SPIs can be served
by the DMA controller.
Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in master or slave mode, in simplex communication modes, and can be
configured to operate with a 16-/32-bit resolution as an input or output channel. Audio
sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the
I2S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
All I2Sx can be served by the DMA controller.
2.26 Serial audio interface (SAI)
The devices embed two serial audio interfaces.
The serial audio interface is based on two independent audio subblocks which can operate
as transmitter or receiver with their FIFO. Many audio protocols are supported by each
block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output,
supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both subblocks can be
configured in master or in slave mode.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of
the sampling frequency.
The two sub-blocks can be configured in synchronous mode when full-duplex mode is
required.
Smartcard mode X -
Single-wire half-duplex communication X X
IrDA SIR ENDEC block X X
LIN mode X X
Dual clock domain X X
Receiver timeout interrupt X X
Modbus communication X X
Auto baud rate detection X X
Driver Enable X X
1. X: supported.
Table 8. USART implementation (continued)
features(1) USART1/2/3/6 UART4/5/7/8
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STM32F745xx STM32F746xx Functional overview
44
SAI1 and SAI2 can be served by the DMA controller
2.27 SPDIFRX Receiver Interface (SPDIFRX)
The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main features of the SPDIFRX are the following:
Up to 4 inputs available
Automatic symbol rate detection
Maximum symbol rate: 12.288 MHz
Stereo stream from 32 to 192 kHz supported
Supports Audio IEC-60958 and IEC-61937, consumer applications
Parity bit management
Communication using DMA for audio samples
Communication using DMA for control and user channel information
Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the
manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the
CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF
sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.
2.28 Audio PLL (PLLI2S)
The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows
to achieve error-free I2S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change
without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the
I2S/SAI flow with an external PLL (or Codec output).
Functional overview STM32F745xx STM32F746xx
40/227 DocID027590 Rev 4
2.29 Audio and LCD PLL(PLLSAI)
An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the
PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or
11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.
The PLLSAI is also used to generate the LCD-TFT clock.
2.30 SD/SDIO/MMC card host interface (SDMMC)
An SDMMC host interface is available, that supports MultiMediaCard System Specification
Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory
card specification version 2.0.
The SDMMC card specification version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDMMC/MMC4.2 card at any one time and a
stack of MMC4.1 or previous.
The SDMMC can be served by the DMA controller
2.31 Ethernet MAC interface with dedicated DMA and IEEE 1588
support
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
The devices include the following features:
Support of 10 and 100 Mbit/s rates
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors
Tagged MAC frame support (VLAN support)
Half-duplex (CSMA/CD) and full-duplex operation
MAC control sublayer (control frames) support
32-bit CRC generation and removal
Several address filtering modes for physical and multicast address (multicast and
group addresses)
32-bit status code for each transmitted or received frame
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
Triggers interrupt when system time becomes greater than target time
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STM32F745xx STM32F746xx Functional overview
44
2.32 Controller area network (bxCAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for each CAN.
2.33 Universal serial bus on-the-go full-speed (OTG_FS)
The device embeds an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The major features are:
Combined Rx and Tx FIFO size of 1.28 Kbytes with dynamic FIFO sizing
Support of the session request protocol (SRP) and host negotiation protocol (HNP)
1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints
12 host channels with periodic OUT support
Software configurable to OTG1.3 and OTG2.0 modes of operation
USB 2.0 LPM (Link Power Management) support
Internal FS OTG PHY support
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
2.34 Universal serial bus on-the-go high-speed (OTG_HS)
The device embeds a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral.
The USB OTG HS supports both full-speed and high-speed operations. It integrates the
transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI)
for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an
external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
Functional overview STM32F745xx STM32F746xx
42/227 DocID027590 Rev 4
The major features are:
Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
Support of the session request protocol (SRP) and host negotiation protocol (HNP)
8 bidirectional endpoints
16 host channels with periodic OUT support
Software configurable to OTG1.3 and OTG2.0 modes of operation
USB 2.0 LPM (Link Power Management) support
Internal FS OTG PHY support
External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
Internal USB DMA
HNP/SNP/IP inside (no need for any external resistor)
for OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
2.35 High-definition multimedia interface (HDMI) - consumer
electronics control (CEC)
The device embeds a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wakeup the MCU from Stop mode on data reception.
2.36 Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication can be 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
Supports continuous mode or snapshot (a single frame) mode
Capability to automatically crop the image
2.37 Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
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STM32F745xx STM32F746xx Functional overview
44
2.38 General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 108 MHz.
2.39 Analog-to-digital converters (ADCs)
Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16
external channels, performing conversions in the single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
Simultaneous sample and hold
Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.
2.40 Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the same input channel as VBAT
, ADC1_IN18, which is used to convert the
sensor output voltage into a digital value. When the temperature sensor and VBAT
conversion are enabled at the same time, only VBAT conversion is performed.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
2.41 Digital-to-analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
Functional overview STM32F745xx STM32F746xx
44/227 DocID027590 Rev 4
This dual digital Interface supports the following features:
two DAC converters: one for each output channel
8-bit or 12-bit monotonic output
left or right data alignment in 12-bit mode
synchronized update capability
noise-wave generation
triangular-wave generation
dual DAC channel independent or simultaneous conversions
DMA capability for each channel
external triggers for conversion
input voltage reference VREF+
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.
2.42 Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
2.43 Embedded Trace Macrocell™
The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F74xxx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer that runs the debugger software. TPA
hardware is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
DocID027590 Rev 4 45/227
STM32F745xx STM32F746xx Pinouts and pin description
88
3 Pinouts and pin description
Figure 11. STM32F74xVx LQFP100 pinout
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Pinouts and pin description STM32F745xx STM32F746xx
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Figure 12. STM32F74xVx TFBGA100 ballout
1. The above figure shows the package top view.
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STM32F745xx STM32F746xx Pinouts and pin description
88
Figure 13. STM32F74xZx WLCSP143 ballout
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Pinouts and pin description STM32F745xx STM32F746xx
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Figure 14. STM32F74xZx LQFP144 pinout
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DocID027590 Rev 4 49/227
STM32F745xx STM32F746xx Pinouts and pin description
88
Figure 15. STM32F74xIx LQFP176 pinout
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Pinouts and pin description STM32F745xx STM32F746xx
50/227 DocID027590 Rev 4
Figure 16. STM32F74xBx LQFP208 pinout
1. The above figure shows the package top view.
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DocID027590 Rev 4 51/227
STM32F745xx STM32F746xx Pinouts and pin description
88
Figure 17. STM32F74xIx UFBGA176 ballout
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Pinouts and pin description STM32F745xx STM32F746xx
52/227 DocID027590 Rev 4
Figure 18. STM32F74xNx TFBGA216 ballout
1. The above figure shows the package top view.
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DocID027590 Rev 4 53/227
STM32F745xx STM32F746xx Pinouts and pin description
88
Table 9. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin type
S Supply pin
I Input only pin
I/O Input / output pin
I/O structure
FT 5 V tolerant I/O
TTa 3.3 V tolerant I/O directly connected to ADC
B Dedicated BOOT pin
RST Bidirectional reset pin with weak pull-up resistor
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
functions Functions selected through GPIOx_AFR registers
Additional
functions Functions directly selected/enabled through peripheral registers
Table 10. STM32F745xx and STM32F746xx pin and ball definition
Pin Number
Pin
name
(function
after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
WLCSP143
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
1 A3 D8 1 A2 1 1 A3 PE2 I/O FT -
TRACECLK, SPI4_SCK,
SAI1_MCLK_A,
QUADSPI_BK1_IO2,
ETH_MII_TXD3,
FMC_A23, EVENTOUT
-
2 B3 C10 2 A1 2 2 A2 PE3 I/O FT - TRACED0, SAI1_SD_B,
FMC_A19, EVENTOUT -
3 C3 B11 3 B1 3 3 A1 PE4 I/O FT -
TRACED1, SPI4_NSS,
SAI1_FS_A, FMC_A20,
DCMI_D4, LCD_B0,
EVENTOUT
-
Pinouts and pin description STM32F745xx STM32F746xx
54/227 DocID027590 Rev 4
4 D3 D9 4 B2 4 4 B1 PE5 I/O FT -
TRACED2, TIM9_CH1,
SPI4_MISO,
SAI1_SCK_A, FMC_A21,
DCMI_D6, LCD_G0,
EVENTOUT
-
5 E3 E8 5 B3 5 5 B2 PE6 I/O FT -
TRACED3, TIM1_BKIN2,
TIM9_CH2, SPI4_MOSI,
SAI1_SD_A,
SAI2_MCK_B, FMC_A22,
DCMI_D7, LCD_G1,
EVENTOUT
-
- - - - - - - G6 VSS S - - - -
-- -----F5VDDS-- - -
6B2C116C16 6C1 VBAT S-- - -
- - - - D2 7 7 C2 PI8 I/O FT
(2)
(3) EVENTOUT
RTC_TAMP2/
RTC_TS,WK
UP5
7A2D107D18 8D1 PC13I/OFT
(2)
(3) EVENTOUT
RTC_TAMP1/
RTC_TS/RTC
_OUT,WKUP
4
8A1D118E19 9E1
PC14-
OSC32_I
N(PC14)
I/O FT
(2)
(3) EVENTOUT OSC32_IN
9B1E119F11010F1
PC15-
OSC32_
OUT(PC
15)
I/O FT
(2)
(3) EVENTOUT OSC32_OUT
-- -----G5VDDS-- - -
- - - - D3 11 11 E4 PI9 I/O FT -
CAN1_RX, FMC_D30,
LCD_VSYNC,
EVENTOUT
-
- - - - E3 12 12 D5 PI10 I/O FT -
ETH_MII_RX_ER,
FMC_D31, LCD_HSYNC,
EVENTOUT
-
Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number
Pin
name
(function
after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
WLCSP143
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
DocID027590 Rev 4 55/227
STM32F745xx STM32F746xx Pinouts and pin description
88
- - - - E4 13 13 F3 PI11 I/O FT - OTG_HS_ULPI_DIR,
EVENTOUT WKUP6
- - E7 - F2 14 14 F2 VSS S - - - -
- - E10 - F3 15 15 F4 VDD S - - - -
- - F1110E21616D2 PF0 I/OFT- I2C2_SDA, FMC_A0,
EVENTOUT -
- - E9 11 H3 17 17 E2 PF1 I/O FT - I2C2_SCL, FMC_A1,
EVENTOUT -
- - F1012H21818G2 PF2 I/OFT- I2C2_SMBA, FMC_A2,
EVENTOUT -
- - - - - - 19 E3 PI12 I/O FT - LCD_HSYNC,
EVENTOUT -
- - - - - - 20 G3 PI13 I/O FT - LCD_VSYNC,
EVENTOUT -
- - - - - - 21 H3 PI14 I/O FT - LCD_CLK, EVENTOUT -
- - G11 13 J2 19 22 H2 PF3 I/O FT - FMC_A3, EVENTOUT ADC3_IN9
- - F9 14 J3 20 23 J2 PF4 I/O FT - FMC_A4, EVENTOUT ADC3_IN14
- - F8 15 K3 21 24 K3 PF5 I/O FT - FMC_A5, EVENTOUT ADC3_IN15
10 C2 H7 16 G2 22 25 H6 VSS S - - - -
11D2 - 17G323 26H5 VDD S - - - -
--G1018K22427K2PF6I/OFT-
TIM10_CH1, SPI5_NSS,
SAI1_SD_B, UART7_Rx,
QUADSPI_BK1_IO3,
EVENTOUT
ADC3_IN4
- - F7 19 K1 25 28 K1 PF7 I/O FT -
TIM11_CH1, SPI5_SCK,
SAI1_MCLK_B,
UART7_Tx,
QUADSPI_BK1_IO2,
EVENTOUT
ADC3_IN5
Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number
Pin
name
(function
after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
WLCSP143
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
Pinouts and pin description STM32F745xx STM32F746xx
56/227 DocID027590 Rev 4
- - H1120L32629L3 PF8 I/OFT-
SPI5_MISO,
SAI1_SCK_B,
UART7_RTS,
TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
ADC3_IN6
- - G8 21 L2 27 30 L2 PF9 I/O FT -
SPI5_MOSI, SAI1_FS_B,
UART7_CTS,
TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
ADC3_IN7
- - G9 22 L1 28 31 L1 PF10 I/O FT - DCMI_D11, LCD_DE,
EVENTOUT ADC3_IN8
12C1J1123G129 32G1
PH0-
OSC_IN(
PH0)
I/O FT - EVENTOUT OSC_IN(4)
13 D1 H10 24 H1 30 33 H1
PH1-
OSC_OU
T(PH1)
I/O FT - EVENTOUT OSC_OUT(4)
14 E1 H9 25 J1 31 34 J1 NRST I/O RS
T-- -
15 F1 H8 26 M2 32 35 M2 PC0 I/O FT (4)
SAI2_FS_B,
OTG_HS_ULPI_STP,
FMC_SDNWE, LCD_R5,
EVENTOUT
ADC123_IN1
0
16F2K1127M333 36M3 PC1 I/OFT
(4)
TRACED0,
SPI2_MOSI/I2S2_SD,
SAI1_SD_A, ETH_MDC,
EVENTOUT
ADC123_IN1
1,
RTC_TAMP3,
WKUP3
17E2J1028M434 37M4 PC2 I/OFT
(4)
SPI2_MISO,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2,
FMC_SDNE0,
EVENTOUT
ADC123_IN1
2
Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number
Pin
name
(function
after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
WLCSP143
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
DocID027590 Rev 4 57/227
STM32F745xx STM32F746xx Pinouts and pin description
88
18 F3 J9 29 M5 35 38 L4 PC3 I/O FT (4)
SPI2_MOSI/I2S2_SD,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0,
EVENTOUT
ADC123_IN1
3
- - G7 30 G3 36 39 J5 VDD S - - - -
- - - - - - - J6 VSS S - - - -
19 G1 K10 31 M1 37 40 M1 VSSA S - - - -
- - - - N1 - - N1 VREF- S - - - -
20 - L11 32 P1 38 41 P1 VREF+ S - - - -
21 H1 L10 33 R1 39 42 R1 VDDA S - - - -
22 G2 K9 34 N3 40 43 N3
PA0-
WKUP(P
A0)
I/O FT (5)
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
USART2_CTS,
UART4_TX, SAI2_SD_B,
ETH_MII_CRS,
EVENTOUT
ADC123_IN0,
WKUP1(4)
23 H2 K8 35 N2 41 44 N2 PA1 I/O FT (4)
TIM2_CH2, TIM5_CH2,
USART2_RTS,
UART4_RX,
QUADSPI_BK1_IO3,
SAI2_MCK_B,
ETH_MII_RX_CLK/ETH_
RMII_REF_CLK,
LCD_R2, EVENTOUT
ADC123_IN1
24 J2 L9 36 P2 42 45 P2 PA2 I/O FT (4)
TIM2_CH3, TIM5_CH3,
TIM9_CH1, USART2_TX,
SAI2_SCK_B,
ETH_MDIO, LCD_R1,
EVENTOUT
ADC123_IN2,
WKUP2
- - - - F4 43 46 K4 PH2 I/O FT
LPTIM1_IN2,
QUADSPI_BK2_IO0,
SAI2_SCK_B,
ETH_MII_CRS,
FMC_SDCKE0, LCD_R0,
EVENTOUT
-
Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number
Pin
name
(function
after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
WLCSP143
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
Pinouts and pin description STM32F745xx STM32F746xx
58/227 DocID027590 Rev 4
- - - - G4 44 47 J4 PH3 I/O FT -
QUADSPI_BK2_IO1,
SAI2_MCK_B,
ETH_MII_COL,
FMC_SDNE0, LCD_R1,
EVENTOUT
-
- - - - H4 45 48 H4 PH4 I/O FT -
I2C2_SCL,
OTG_HS_ULPI_NXT,
EVENTOUT
-
- - - - J4 46 49 J3 PH5 I/O FT -
I2C2_SDA, SPI5_NSS,
FMC_SDNWE,
EVENTOUT
-
25 K2 M11 37 R2 47 50 R2 PA3 I/O FT (4)
TIM2_CH4, TIM5_CH4,
TIM9_CH2, USART2_RX,
OTG_HS_ULPI_D0,
ETH_MII_COL, LCD_B5,
EVENTOUT
ADC123_IN3
26 J1 - 38 - - 51 K6 VSS S - - - -
-E6N11-L448-L5
BYPASS
_REG IFT- - -
27 K1 J8 39 K4 49 52 K5 VDD S - - - -
28 G3 M10 40 N4 50 53 N4 PA4 I/O TT
a
(4)
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK,
OTG_HS_SOF,
DCMI_HSYNC,
LCD_VSYNC,
EVENTOUT
ADC12_IN4,
DAC_OUT1
29 H3 M9 41 P4 51 54 P4 PA5 I/O TT
a
(4)
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK/I2S1_CK,
OTG_HS_ULPI_CK,
LCD_R4, EVENTOUT
ADC12_IN5,
DAC_OUT2
30 J3 N10 42 P3 52 55 P3 PA6 I/O FT (4)
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN, SPI1_MISO,
TIM13_CH1,
DCMI_PIXCLK, LCD_G2,
EVENTOUT
ADC12_IN6
Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number
Pin
name
(function
after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
WLCSP143
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
DocID027590 Rev 4 59/227
STM32F745xx STM32F746xx Pinouts and pin description
88
31 K3 L8 43 R3 53 56 R3 PA7 I/O FT (4)
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SD,
TIM14_CH1,
ETH_MII_RX_DV/ETH_R
MII_CRS_DV,
FMC_SDNWE,
EVENTOUT
ADC12_IN7
32 G4 M8 44 N5 54 57 N5 PC4 I/O FT (4)
I2S1_MCK,
SPDIFRX_IN2,
ETH_MII_RXD0/ETH_RM
II_RXD0, FMC_SDNE0,
EVENTOUT
ADC12_IN14
33 H4 N9 45 P5 55 58 P5 PC5 I/O FT (4)
SPDIFRX_IN3,
ETH_MII_RXD1/ETH_RM
II_RXD1, FMC_SDCKE0,
EVENTOUT
ADC12_IN15
- - J7 - - - 59 L7 VDD S - - - -
- - - - - - 60 L6 VSS S - - - -
34 J4 N8 46 R5 56 61 R5 PB0 I/O FT (4)
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N,
UART4_CTS, LCD_R3,
OTG_HS_ULPI_D1,
ETH_MII_RXD2,
EVENTOUT
ADC12_IN8
35 K4 K7 47 R4 57 62 R4 PB1 I/O FT (4)
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N, LCD_R6,
OTG_HS_ULPI_D2,
ETH_MII_RXD3,
EVENTOUT
ADC12_IN9
36 G5 L7 48 M6 58 63 M5 PB2 I/O FT -
SAI1_SD_A,
SPI3_MOSI/I2S3_SD,
QUADSPI_CLK,
EVENTOUT
-
- - - - - - 64 G4 PI15 I/O FT - LCD_R0, EVENTOUT -
- - - - - - 65 R6 PJ0 I/O FT - LCD_R1, EVENTOUT -
- - - - - - 66 R7 PJ1 I/O FT - LCD_R2, EVENTOUT -
Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number
Pin
name
(function
after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
WLCSP143
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
Pinouts and pin description STM32F745xx STM32F746xx
60/227 DocID027590 Rev 4
- - - - - - 67 P7 PJ2 I/O FT - LCD_R3, EVENTOUT -
- - - - - - 68 N8 PJ3 I/O FT - LCD_R4, EVENTOUT -
- - - - - - 69 M9 PJ4 I/O FT - LCD_R5, EVENTOUT -
- - M7 49 R6 59 70 P8 PF11 I/O FT -
SPI5_MOSI, SAI2_SD_B,
FMC_SDNRAS,
DCMI_D12, EVENTOUT
-
- - N7 50 P6 60 71 M6 PF12 I/O FT - FMC_A6, EVENTOUT -
- - - 51M861 72 K7 VSS S - - - -
-- -52N86273L8VDDS-- - -
- - K6 53 N6 63 74 N6 PF13 I/O FT - I2C4_SMBA, FMC_A7,
EVENTOUT -
- - L6 54 R7 64 75 P6 PF14 I/O FT - I2C4_SCL, FMC_A8,
EVENTOUT -
- - M6 55 P7 65 76 M8 PF15 I/O FT - I2C4_SDA, FMC_A9,
EVENTOUT -
- - N6 56 N7 66 77 N7 PG0 I/O FT - FMC_A10, EVENTOUT -
- - K5 57 M7 67 78 M7 PG1 I/O FT - FMC_A11, EVENTOUT -
37 H5 L5 58 R8 68 79 R8 PE7 I/O FT -
TIM1_ETR, UART7_Rx,
QUADSPI_BK2_IO0,
FMC_D4, EVENTOUT
-
38 J5 M5 59 P8 69 80 N9 PE8 I/O FT -
TIM1_CH1N, UART7_Tx,
QUADSPI_BK2_IO1,
FMC_D5, EVENTOUT
-
39 K5 N5 60 P9 70 81 P9 PE9 I/O FT -
TIM1_CH1, UART7_RTS,
QUADSPI_BK2_IO2,
FMC_D6, EVENTOUT
-
- - H3 61 M9 71 82 K8 VSS S - - - -
- - J5 62 N9 72 83 L9 VDD S - - - -
40 G6 J4 63 R9 73 84 R9 PE10 I/O FT -
TIM1_CH2N,
UART7_CTS,
QUADSPI_BK2_IO3,
FMC_D7, EVENTOUT
-
Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number
Pin
name
(function
after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
WLCSP143
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
DocID027590 Rev 4 61/227
STM32F745xx STM32F746xx Pinouts and pin description
88
41 H6 K4 64 P10 74 85 P10 PE11 I/O FT -
TIM1_CH2, SPI4_NSS,
SAI2_SD_B, FMC_D8,
LCD_G3, EVENTOUT
-
42 J6 L4 65 R10 75 86 R10 PE12 I/O FT -
TIM1_CH3N, SPI4_SCK,
SAI2_SCK_B, FMC_D9,
LCD_B4, EVENTOUT
-
43 K6 N4 66 N11 76 87 R12 PE13 I/O FT -
TIM1_CH3, SPI4_MISO,
SAI2_FS_B, FMC_D10,
LCD_DE, EVENTOUT
-
44 G7 M4 67 P11 77 88 P11 PE14 I/O FT -
TIM1_CH4, SPI4_MOSI,
SAI2_MCK_B, FMC_D11,
LCD_CLK, EVENTOUT
-
45 H7 L3 68 R11 78 89 R11 PE15 I/O FT - TIM1_BKIN, FMC_D12,
LCD_R7, EVENTOUT -
46 J7 M3 69 R12 79 90 P12 PB10 I/O FT -
TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
USART3_TX,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER,
LCD_G4, EVENTOUT
-
47 K7 N3 70 R13 80 91 R13 PB11 I/O FT -
TIM2_CH4, I2C2_SDA,
USART3_RX,
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_R
MII_TX_EN, LCD_G5,
EVENTOUT
-
48 F8 N2 71 M10 81 92 L11 VCAP_1 S - - - -
49 - H2 - - - 93 K9 VSS S - - - -
50 - J6 72 N10 82 94 L10 VDD S - - - -
- - - - - - 95 M14 PJ5 I/O FT - LCD_R6, EVENTOUT -
-- --M118396P13PH6I/OFT-
I2C2_SMBA, SPI5_SCK,
TIM12_CH1,
ETH_MII_RXD2,
FMC_SDNE1, DCMI_D8,
EVENTOUT
-
Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number
Pin
name
(function
after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
WLCSP143
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
Pinouts and pin description STM32F745xx STM32F746xx
62/227 DocID027590 Rev 4
-- --N128497N13PH7I/OFT-
I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3,
FMC_SDCKE1,
DCMI_D9, EVENTOUT
-
-- --M128598P14PH8I/OFT-
I2C3_SDA, FMC_D16,
DCMI_HSYNC, LCD_R2,
EVENTOUT
-
-- --M138699N14PH9I/OFT-
I2C3_SMBA,
TIM12_CH2, FMC_D17,
DCMI_D0, LCD_R3,
EVENTOUT
-
- - - - L13 87 100 P15 PH10 I/O FT -
TIM5_CH1, I2C4_SMBA,
FMC_D18, DCMI_D1,
LCD_R4, EVENTOUT
-
- - - - L12 88 101 N15 PH11 I/O FT -
TIM5_CH2, I2C4_SCL,
FMC_D19, DCMI_D2,
LCD_R5, EVENTOUT
-
- - - - K12 89 102 M15 PH12 I/O FT -
TIM5_CH3, I2C4_SDA,
FMC_D20, DCMI_D3,
LCD_R6, EVENTOUT
-
- - - - H12 90 - K10 VSS S - - - -
- - - - J12 91 103 K11 VDD S - - - -
51 K8 M2 73 P12 92 104 L13 PB12 I/O FT -
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
USART3_CK, CAN2_RX,
OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_RM
II_TXD0, OTG_HS_ID,
EVENTOUT
-
52 J8 N1 74 P13 93 105 K14 PB13 I/O FT -
TIM1_CH1N,
SPI2_SCK/I2S2_CK,
USART3_CTS,
CAN2_TX,
OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_RM
II_TXD1, EVENTOUT
OTG_HS_VB
US
Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number
Pin
name
(function
after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
WLCSP143
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
DocID027590 Rev 4 63/227
STM32F745xx STM32F746xx Pinouts and pin description
88
53 H10 K3 75 R14 94 106 R14 PB14 I/O FT -
TIM1_CH2N,
TIM8_CH2N,
SPI2_MISO,
USART3_RTS,
TIM12_CH1,
OTG_HS_DM,
EVENTOUT
-
54 G10 J3 76 R15 95 107 R15 PB15 I/O FT -
RTC_REFIN,
TIM1_CH3N,
TIM8_CH3N,
SPI2_MOSI/I2S2_SD,
TIM12_CH2,
OTG_HS_DP,
EVENTOUT
-
55 K9 L2 77 P15 96 108 L15 PD8 I/O FT -
USART3_TX,
SPDIFRX_IN11,
FMC_D13, EVENTOUT
-
56 J9 M1 78 P14 97 109 L14 PD9 I/O FT - USART3_RX, FMC_D14,
EVENTOUT -
57 H9 H4 79 N15 98 110 K15 PD10 I/O FT - USART3_CK, FMC_D15,
LCD_B3, EVENTOUT -
58 G9 K2 80 N14 99 111 N10 PD11 I/O FT -
I2C4_SMBA,
USART3_CTS,
QUADSPI_BK1_IO0,
SAI2_SD_A,
FMC_A16/FMC_CLE,
EVENTOUT
-
59 K10 H6 81 N13 100 112 M10 PD12 I/O FT -
TIM4_CH1, LPTIM1_IN1,
I2C4_SCL,
USART3_RTS,
QUADSPI_BK1_IO1,
SAI2_FS_A,
FMC_A17/FMC_ALE,
EVENTOUT
-
60 J10 H5 82 M15 101 113 M11 PD13 I/O FT -
TIM4_CH2,
LPTIM1_OUT, I2C4_SDA,
QUADSPI_BK1_IO3,
SAI2_SCK_A, FMC_A18,
EVENTOUT
-
Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number
Pin
name
(function
after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
WLCSP143
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
Pinouts and pin description STM32F745xx STM32F746xx
64/227 DocID027590 Rev 4
- - - 83 - 102 114 J10 VSS S - - - -
- - L1 84 J13 103 115 J11 VDD S - - - -
61 H8 J2 85 M14 104 116 L12 PD14 I/O FT - TIM4_CH3, UART8_CTS,
FMC_D0, EVENTOUT -
62 G8 K1 86 L14 105 117 K13 PD15 I/O FT - TIM4_CH4, UART8_RTS,
FMC_D1, EVENTOUT -
- - - - - - 118 K12 PJ6 I/O FT - LCD_R7, EVENTOUT -
- - - - - - 119 J12 PJ7 I/O FT - LCD_G0, EVENTOUT -
- - - - - - 120 H12 PJ8 I/O FT - LCD_G1, EVENTOUT -
- - - - - - 121 J13 PJ9 I/O FT - LCD_G2, EVENTOUT -
- - - - - - 122 H13 PJ10 I/O FT - LCD_G3, EVENTOUT -
- - - - - - 123 G12 PJ11 I/O FT - LCD_G4, EVENTOUT -
- - - - - - 124 H11 VDD S - - - -
- - - - - - 125 H10 VSS S - - - -
- - - - - - 126 G13 PK0 I/O FT - LCD_G5, EVENTOUT -
- - - - - - 127 F12 PK1 I/O FT - LCD_G6, EVENTOUT -
- - - - - - 128 F13 PK2 I/O FT - LCD_G7, EVENTOUT -
- - J1 87 L15 106 129 M13 PG2 I/O FT - FMC_A12, EVENTOUT -
- - G3 88 K15 107 130 M12 PG3 I/O FT - FMC_A13, EVENTOUT -
- - G5 89 K14 108 131 N12 PG4 I/O FT - FMC_A14/FMC_BA0,
EVENTOUT -
- - G6 90 K13 109 132 N11 PG5 I/O FT - FMC_A15/FMC_BA1,
EVENTOUT -
- - G4 91 J15 110 133 J15 PG6 I/O FT - DCMI_D12, LCD_R7,
EVENTOUT -
- - H1 92 J14 111 134 J14 PG7 I/O FT -
USART6_CK, FMC_INT,
DCMI_D13, LCD_CLK,
EVENTOUT
-
Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number
Pin
name
(function
after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
WLCSP143
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
DocID027590 Rev 4 65/227
STM32F745xx STM32F746xx Pinouts and pin description
88
- - G2 93 H14 112 135 H14 PG8 I/O FT -
SPI6_NSS,
SPDIFRX_IN2,
USART6_RTS,
ETH_PPS_OUT,
FMC_SDCLK,
EVENTOUT
-
- - D2 94 G12 113 136 G10 VSS S - - - -
- F6 G1 95 H13 114 137 G11 VDDUSB S - - - -
63 F10 F2 96 H15 115 138 H15 PC6 I/O FT -
TIM3_CH1, TIM8_CH1,
I2S2_MCK, USART6_TX,
SDMMC1_D6, DCMI_D0,
LCD_HSYNC,
EVENTOUT
-
64 E10 F3 97 G15 116 139 G15 PC7 I/O FT -
TIM3_CH2, TIM8_CH2,
I2S3_MCK, USART6_RX,
SDMMC1_D7, DCMI_D1,
LCD_G6, EVENTOUT
-
65 F9 E4 98 G14 117 140 G14 PC8 I/O FT -
TRACED1, TIM3_CH3,
TIM8_CH3, UART5_RTS,
USART6_CK,
SDMMC1_D0, DCMI_D2,
EVENTOUT
-
66 E9 E3 99 F14 118 141 F14 PC9 I/O FT -
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN, UART5_CTS,
QUADSPI_BK1_IO0,
SDMMC1_D1, DCMI_D3,
EVENTOUT
-
67 D9 F1 100 F15 119 142 F15 PA8 I/O FT -
MCO1, TIM1_CH1,
TIM8_BKIN2, I2C3_SCL,
USART1_CK,
OTG_FS_SOF, LCD_R6,
EVENTOUT
-
68 C9 E2 101 E15 120 143 E15 PA9 I/O FT -
TIM1_CH2, I2C3_SMBA,
SPI2_SCK/I2S2_CK,
USART1_TX, DCMI_D0,
EVENTOUT
OTG_FS_VB
US
Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number
Pin
name
(function
after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
WLCSP143
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
Pinouts and pin description STM32F745xx STM32F746xx
66/227 DocID027590 Rev 4
69 D10 D5 102 D15 121 144 D15 PA10 I/O FT -
TIM1_CH3, USART1_RX,
OTG_FS_ID, DCMI_D1,
EVENTOUT
-
70 C10 D4 103 C15 122 145 C15 PA11 I/O FT -
TIM1_CH4,
USART1_CTS,
CAN1_RX, OTG_FS_DM,
LCD_R4, EVENTOUT
-
71 B10 E1 104 B15 123 146 B15 PA12 I/O FT -
TIM1_ETR,
USART1_RTS,
SAI2_FS_B, CAN1_TX,
OTG_FS_DP, LCD_R5,
EVENTOUT
-
72 A10 D3 105 A15 124 147 A15
PA13(JT
MS-
SWDIO)
I/O FT - JTMS-SWDIO,
EVENTOUT -
73 E7 D1 106 F13 125 148 E11 VCAP_2 S - - - -
74 E5 D2 107 F12 126 149 F10 VSS S - - - -
75 F5 C1 108 G13 127 150 F11 VDD S - - - -
- - - - E12 128 151 E12 PH13 I/O FT -
TIM8_CH1N, CAN1_TX,
FMC_D21, LCD_G2,
EVENTOUT
-
- - - - E13 129 152 E13 PH14 I/O FT -
TIM8_CH2N, FMC_D22,
DCMI_D4, LCD_G3,
EVENTOUT
-
- - - - D13 130 153 D13 PH15 I/O FT -
TIM8_CH3N, FMC_D23,
DCMI_D11, LCD_G4,
EVENTOUT
-
- - - - E14 131 154 E14 PI0 I/O FT -
TIM5_CH4,
SPI2_NSS/I2S2_WS,
FMC_D24, DCMI_D13,
LCD_G5, EVENTOUT
-
- - - - D14 132 155 D14 PI1 I/O FT -
TIM8_BKIN2,
SPI2_SCK/I2S2_CK,
FMC_D25, DCMI_D8,
LCD_G6, EVENTOUT
-
Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number
Pin
name
(function
after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
WLCSP143
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
DocID027590 Rev 4 67/227
STM32F745xx STM32F746xx Pinouts and pin description
88
- - - - C14 133 156 C14 PI2 I/O FT -
TIM8_CH4, SPI2_MISO,
FMC_D26, DCMI_D9,
LCD_G7, EVENTOUT
-
- - - - C13 134 157 C13 PI3 I/O FT -
TIM8_ETR,
SPI2_MOSI/I2S2_SD,
FMC_D27, DCMI_D10,
EVENTOUT
-
- - F5 - D9 135 - F9 VSS S - - - -
- - A1 - C9 136 158 E10 VDD S - - - -
76 A9 B1 109 A14 137 159 A14
PA14(JT
CK-
SWCLK)
I/O FT - JTCK-SWCLK,
EVENTOUT -
77 A8 C2 110 A13 138 160 A13 PA15(JT
DI) I/O FT -
JTDI,
TIM2_CH1/TIM2_ETR,
HDMI-CEC,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
UART4_RTS,
EVENTOUT
-
78 B9 A2 111 B14 139 161 B14 PC10 I/O FT -
SPI3_SCK/I2S3_CK,
USART3_TX,
UART4_TX,
QUADSPI_BK1_IO1,
SDMMC1_D2, DCMI_D8,
LCD_R2, EVENTOUT
-
79 B8 B2 112 B13 140 162 B13 PC11 I/O FT -
SPI3_MISO,
USART3_RX,
UART4_RX,
QUADSPI_BK2_NCS,
SDMMC1_D3, DCMI_D4,
EVENTOUT
-
80 C8 C3 113 A12 141 163 A12 PC12 I/O FT -
TRACED3,
SPI3_MOSI/I2S3_SD,
USART3_CK,
UART5_TX,
SDMMC1_CK, DCMI_D9,
EVENTOUT
-
Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number
Pin
name
(function
after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
WLCSP143
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
Pinouts and pin description STM32F745xx STM32F746xx
68/227 DocID027590 Rev 4
81 D8 B3 114 B12 142 164 B12 PD0 I/O FT - CAN1_RX, FMC_D2,
EVENTOUT -
82 E8 C4 115 C12 143 165 C12 PD1 I/O FT - CAN1_TX, FMC_D3,
EVENTOUT -
83 B7 A3 116 D12 144 166 D12 PD2 I/O FT -
TRACED2, TIM3_ETR,
UART5_RX,
SDMMC1_CMD,
DCMI_D11, EVENTOUT