TMC4361 Datasheet by Trinamic Motion Control GmbH

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MOTION CONTROLLER FOR STEPPER MOTORS INTEGRATED CIRCUITS
TMC4361-LA DATASHEET
Cost-effective S-
ramp motion controller with servo option for stepper motors. Optimized for high
velocities. SPI and Step/Dir interfaces to motor driver and encoder interface for closed loop operation.
APPLICATIONS
Textile, Sewing Machines
Factory Automation
Lab Automation
Medical
Office Automation
Printer and Scanner
CCTV, Security
ATM, Cash recycler
POS
Pumps and Valves
Heliostat Controller
CNC Machines
F
EATURES AND
B
ENEFITS
3.3V or 5V operation
SPI interface for µC with easy-to-use protocol
SPIinterface for SPI motor drivers
Step/Dirinterface forStep/Dir motor drivers
Clock frequency 4.2 MHz up to 32 MHz
Encoder interface: incremental ABN and serial SSI/SPI
2x ref.-switch input
Servo drive option
S-shaped or linear velocity ramps, optimally calculated
On-the-fly change of target motion parameters
Low power operation using clock gating technology
Different current levels related to the motion profile status
Programmable microstep table
Read-out option for all important motion parameters
Compact Size 6x6 mm² QFN40 package
Directly controls TMC23x, TMC24x, and TMC26x motor driver
DESCRIPTION
The TMC4361 is intended for applications
where a fast and jerk-limited motion profile
is desired. This motion controller adds to
any microcontroller with SPI interface. It
supports S-shaped, trapezoid, and rectangle
ramps. With encoder, the TMC4361 allows
for an extremely quick and precise
positioning. Its servo features provide step-
loss protection, energy efficiency, and target
positioning with stepper typical stability.
Standard SPI and STEP/DIR interfaces to the
motor driver simplify communication.
High end features,no software effort and the
small form factor of the TMC4361 enable
miniaturized designs with low external
component count for cost-
effective and
highly competitive solutions.
BLOCK DIAGRAM
TMC4361 DATASHEET (Rev. 1.05 / 2015-FEB-02) Preliminary, Confidential 2
HIGH-END SOLUTION: VELOCITY MEETS PRECISION
The TMC4361 is a miniaturized high performance stepper motor controller with an outstanding cost-
performance ratio. It is designed for high volume as well as for demanding industrial motion control
applications. The TMC4361 is equipped with an SPI™ host interface (SPI is trademark of Motorola) with
easy-to-use protocol and three driver interfaces (SPI, Step/Dir, and PWM) for addressing various stepper
motor driver types.The TMC4361 scores with its unique servo drive features, high integration and a
versatility that covers a wide spectrum of applications, motor sizes, and encoder types.
For a comfortable handling, the chip works with real world units. Extensive support at the chip, board,
and software levels enables rapid design cycles and fast time-to-market with competitive products. High
energy efficiency delivers further cost savings.
S-SHAPED VELOCITY PROFILE
This outstanding ramp profile minimizes jerk. Seven segments of the ramp allow for an optimum
adaption of the velocity profile to the customer specific application requirements. High torque with high
velocities can be reached by calibrating the bows of the ramp in a way that the acceleration value near
VMAX is reduced in parallel to the available motor torque.
v(t)
t
V
MAX
COMPACT DESIGN FOR RELIABLE CLOSED LOOP OPERATION
BENEFIT FROM HIGH VELOCITIES COMBINED WITH EXTREMELY HIGH PRECISION!
Closed loop operation is an optimum choice in case a dynamic and reliable drive without step-loss or
motor stall is desired. The controller IC monitors the encoder values nonstop and uses them for a
sophisticated motor field control.
µC
TMC248
Motor
Driver
MOSFET
Driver
Stage
High level
interface M
TMC4361
Motion
Controller
SPI
Encoder
ABN/SSI
SPI/BiSS
Analog
Inputs A/B
SPI
COMPACT DESIGN FOR RELIABLE OPERATION USING STOP SWITCHES
The TMC4361 offers a left and a right stop switch in hardware as well as a home switch. Further, it
provides two virtual stop switches which can trigger stop slopes in case the related virtual stop
switch microstep position is reached.
ORDER CODES
Order code Description Size
TMC4361-LA
Motion controller with servo and dcStep features, QFN40
6 x 6 mm2
MOTION CONTROLLER FOR STEPPER MOTORS INTEGRATED CIRCUITS
Table of Contents
1 PRINCIPLES OF OPERATION 4
1.1 DRIVE CONCEPTS AND CONTROL MODES 4
1.2 KEY CONCEPTS 5
1.3 OVERVIEW INTERFACES 5
1.4 STEP FREQUENCIES 6
1.5 MOVING THE MOTOR 6
1.6 STATUS FLAGS, EVENTS, AND INTERRUPTS 7
2 PIN ASSIGNMENTS 8
2.1 PACKAGE OUTLINE 8
2.2 SIGNAL DESCRIPTION 8
3 SAMPLE CIRCUITS 10
4 NOTES 11
5 SPI CONTROL INTERFACE 12
5.1 SPI DATAGRAM STRUCTURE 12
5.2 SPI SIGNALS 13
5.3 TIMING 14
6 INPUT FILTERING 15
6.1 INPUT FILTER CONFIGURATION 15
7 STATUS FLAGS & EVENTS 17
7.1 STATUS FLAGS 17
7.2 STATUS EVENTS & SPI STATUS & INTERRUPTS 17
8 RAMP GENERATOR 19
8.1 STEP/DIR OUTPUT CONFIGURATION 19
8.2 RAMP MODES AND TYPES 20
9 REFERENCE SWITCHES 25
9.1 STOPL AND STOPR 25
9.2 VIRTUAL STOP SWITCHES 26
9.3 HOME REFERENCE 27
9.4 CYCLIC MOVEMENT TO XTARGET 28
9.5 TARGET REACHED / POSITION COMPARISON 28
10 RAMP TIMING & SYNCHRONIZATION 29
10.1 START SIGNAL GENERATION 29
10.2 TARGET PIPELINE 33
11 SERIAL DATA OUTPUT 34
11.1 SINE WAVE LOOK-UP TABLE 35
11.2 SPI OUTPUT PARAMETERS 38
11.3 CURRENT DATAGRAMS 39
11.4 TMC MOTOR DRIVER 40
11.5 OTHER DRIVER CHIPS 43
11.6 CURRENT SCALING & RAMP STATUS 44
12 NFREEZE: EMERGENCY-STOP 47
12.1 FREEZE FUNCTION CONFIGURATION 47
13 CONTROLLED PWM OUTPUT 48
13.1 PWM OUTPUT GENERATION 48
14 DECODER UNIT & CLOSED LOOP 49
14.1 GENERAL ENCODER INTERFACE 50
14.2 INCREMENTAL ABN ENCODER 50
14.3 ABSOLUTE ENCODER 52
14.4 CONTROL VIA ENCODER FEEDBACK 56
14.5 ENCODER MISALIGNMENTS 61
15 SERIAL ENCODER OUTPUT UNIT 62
15.1 PROVIDING SSI OUTPUT DATA 62
16 CLK GATING 63
16.1 CLOCK GATING AND WAKE-UP 63
17 REGISTERS AND SWITCHES 65
17.1 GENERAL CONFIGURATION 65
17.2 REFERENCE SWITCH CONFIGURATION 67
17.3 START SWITCH CONFIGURATION 69
17.4 INPUT FILTER CONFIGURATION 70
17.5 SPI-OUT CONFIGURATION 71
17.6 CURRENT CONFIGURATION 73
17.7 CURRENT SCALE VALUES 73
17.8 ENCODER SIGNAL CONFIGURATION 74
17.9 SERIAL ENCODER DATA IN 76
17.10 SERIAL ENCODER DATA OUT 76
17.11 MOTOR DRIVER SETTINGS 76
17.12 EVENT SELECTION REGISTERS 76
17.13 STATUS EVENT REGISTER 77
17.14 STATUS FLAG REGISTER 78
17.15 VARIOUS CONFIGURATION REGISTERS 79
17.16 RAMP GENERATOR REGISTERS 80
17.17 TARGET AND COMPARE REGISTERS 82
17.18 FREEZE REGISTER 83
17.19 CLOCK GATING ENABLE REGISTER 83
17.20 ENCODER REGISTERS 84
17.21 PID AND CLOSED LOOP REGISTERS 85
17.22 MISC REGISTERS 86
17.23 TRANSFER REGISTERS 87
17.24 SINLUT REGISTERS 87
18 ABSOLUTE MAXIMUM RATINGS 88
19 ELECTRICAL CHARACTERISTICS 88
19.1 DC CHARACTERISTICS OPERATING CONDITIONS 88
19.2 POWER DISSIPATION 88
19.3 GENERAL IO TIMING PARAMETERS 89
20 LAYOUT EXAMPLE 90
21 PACKAGE MECHANICAL DATA 92
21.1 DIMENSIONAL DRAWINGS 92
21.2 PACKAGE CODES 93
22 DISCLAIMER 93
23 ESD SENSITIVE DEVICE 93
24 TABLE OF FIGURES 94
25 REVISION HISTORY 95
25.1 DOCUMENT REVISIONS 95
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 4
1 Principles of Operation
SPI
RES
NSCSIN
SCKIN
SDIIN
SDOIN
Host CPU
SPI Interface
Register Block
STOPL
STOPR
v
Decoder Unit
SCLK SCLK A
N
Encoder (differential)
Step/Dir Output
I
DIROUT
STPOUT
NSTDBY_OUT
O
INTR
HOME_REF
Scan Test
I
TEST_MODE
I
SDODRV
SCKDRV
SDIDRV
NSCSDRV
SPI Datagram Generator
Clk-Out
ChopSync Clk
START
SDI SDI B
CLK_EXT
O
IO
I
I
O
O
O
SPI Output
I
I
I
Reference
processing
O
OI
Start / Stop /
Reference Switches
Serial
Encoder
Unit
Ramp
Status
I
I
IO
NSCS NSCLK ANEG
NNEG
External
PosCounter
MasterCLK
SSI
Internal
Pos
External
Pos
IO
or
Pos
Counter
PWM
Unit
Scale
Unit
SCLK NSCLK SDO NSDO
PWMA
(Sine)
PWMB
(Cosine)
Serial encoder
PWM Output
GND(4x) VDD5(3x)
or
or
or or
or
or
IO
I
NRST
VDD1V8(2x)
Target
Register(s)
Timer Unit
CLK_INT
Status flags +
Events à
Interrupt
Control ClkGating
Parameters
from/for all
Units
O
TARGET_REACHED
POR
PulseGen
ClosedLoop Unit
Compare
Internal
(Co)Sine
LUT
Internal
Step
ChopSync
Unit
Actual
Co-/Sine
values
Commutation
angle
Closed
Loop
Scaling
PWM or DAC
encrypted co-/sine
voltage values
StdBy
signal
or
Scaled
current
values
CoverReg
Drv type
FS
DataOut
SSI
SDO NSDI BNEG
DACA
(Sine)
DACB
(Cosine)
DAC Output
or
NFREEZE
Iimmediate freeze
of operation
DAC
Unit
IO
ABN
SSI
or
SPI
or
I
SSI
SPI
ABN
PID
PID_E
Ramp-Generator
S-ramps with 4 bows,
trapezoid, rectangle, ...
Figure 1.1 Basic application block diagram
1.1 Drive Concepts and Control Modes
The TMC4361 motion controller provides four different drive concepts respectivelycontrol modes. Choose
the specific control mode related to the requirements of your application.
CLASSIC STEPPER WITH OPEN LOOP
M
TMC4361 Driver +
MOSFETs
Target
OPEN LOOP WITH ENCODER CHECK
ME
TMC4361
Position Check
Driver +
MOSFETs
Target
OK / Error
ENCODER FOR PRECISION AND POSITION MAINTENANCE
TMC4361
PID controller
ME
DRIVE TRAIN
Mechanical
Transmission
Driver +
MOSFETs
Target
SERVO DRIVE: FEEDBACK CONTROL
ME
FEEDBACK CONTROL
Target
Ready
TMC4361
Closed Loop Unit
Driver +
MOSFETs
Figure 1.2Drive Concepts. M=Motor, E=Encoder
TRINAMIC Motion Control GmbH & Co. KG
Hamburg, Germany
TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 5
1.2 Key Concepts
The TMC4361 realizes real time critical tasks autonomously and guarantees for a robust and reliable drive.
The following features contribute toward greater precision, greater efficiency, higher reliability, higher
velocity, and smoother motion in many stepper motor applications.
Interfacing The TMC4361 offers application specific interfacing via SPI,Step/Dir, and PWM
interface.
Initialization Adapt the TMC4361 to the driver type and configuration and send initial configuration
data to SPI drivers. Configure microstep resolution and waveform.
Positioning The TMC4361 operates motor based on user specified target positions and velocities.
Modify all motion target parameters on-the-fly during motion.
Microstepping Based on internal position counters the TMC4361 performs up to ±231 (micro)steps
completely independent from the microcontroller. Microstep resolutions are
individually programmable. The range goes from full stepping (1 microstep = 1 full
step) and half stepping (2 microsteps per full step) up to 8 bit micro stepping (256
microsteps per full step) for precise positioning and noiseless stepper motor
rotation. With Step/Dir drivers any microstep resolution is possible as supported by
the driver.The internal microstep table can be adapted to specific motor
characteristics to further reduce torque ripple.
Servo Drive The TMC4361 provides closed loop operation for Step/Dir and SPI drivers. Using a
differential or serial encoder, the closed loop unit of the TMC4361 compares the
external position counter values with the internal ones and sends signals for
correction.
chopSync The TMC4361 has an integratedchopSync chopper for very smooth motor
movementwith TMC23x/24x.
Programming Every parameter can be changed at any time. The uniform access to any TMC4361
register simplifies application programming. A read-back option for nearly all internal
registers is available.
Synchronization The TMC4361 provides synchronizing several TMC4361 motion controller chips if it is
desired to drive motors simultaneously. In this case one TMC4361 is the master and
the connected TMC4361 are slaves.
1.3 Overview Interfaces
1.3.1 SPI to CPU
From the software point of view, the TMC4361 provides a set of registers, accessed by a microcontroller
via a serial interface in a uniform way. Each datagram contains address bits, a read-write selection bit,
and data bits to access the registers and the on-chip memory. Each time the microcontroller sends a
datagram to the TMC4361 it simultaneously receives a datagram from the TMC4361. This simplifies the
communication with the TMC4361 and makes programming easy. Most microcontrollers have an SPI
hardware interface, which directly connects to the serial four wire microcontroller interface of the
TMC4361. For microcontrollers without SPIhardware, software doing the serial communication is sufficient
and can easily be implemented. (For further information refer to chapter 5.)
1.3.2 SPI to Driver
The TMC4361 automatically generates the required data-stream for SPI drivers and provides user
configurable microstep waves and motor ramps. The serial interface to the motor driver is configurable
for all TRINAMIC drivers as well as for SPI DACs. Pre-settings for TRINAMIC driver chips are provided. (For
further information refer to chapter 11.)
Third party driver chips can be configured via SPI interface using cover datagrams. During motor
movement the SPI interface remains switched off and the Step/Dir interface isused for driving the motor.
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 6
1.3.3 Step/Dir to Driver
The TMC4361 provides a configurable Step/Dir interface to the driver. The motion controller controls the
motor position by sending pulses on the STEP signal while indicating the direction on the DIR signal.
Programmable step pulse length and step frequencies allow operation at high speed and high microstep
resolution. The driver chip converts these signals into the coil currents which control the position of the
motor. The TMC4361 perfectly fits to the TMC26x smart power Step/Dir driver family. (For further
information refer to chapters 11.4 and 11.5.)
1.3.4 PWM Interface to Driver
The TMC4361 allows for using PWM output values instead of Step/Dir outputs due to disabling the Step/Dir
output and forwarding PWM signals via STPOUT_PWMA and DIROUT_PWMB. The PWM frequency is
calculated with fPWM = fCLK / PWM_FREQ.This mode supports noisefree and smooth microstepping with
TMC23x and TMC24x stepper motor drivers. (For further information refer to chapter 13.)
1.3.5 Encoder Interface
The TMC4361 is equipped with a six pin encoder input interface for incremental ABN encoders (differential
or single ended) or absolute encoders like SSI or SPI encoders. Motor feedback can be analyzed and
closed loop behavior can be reached. All encoder input signals are filtered using anadaptable digital filter.
(For further information refer to chapter 14.)
1.3.6 Reference Switches and Special IOs
The TMC4361 offers a left and a right stop switch in hardware as well as a home switch. Further, it
provides two virtual stop switches which can trigger stop slopes in case the related virtual stop switch
microstep position is reached. (Refer to chapter 9)
The START pin can be used as input or as output:a ramp start can be initialized viaa start input signal.
The other way round, the START pin can be used as output. In this case, multiple drivers can be
synchronized using an internal start signal of a TMC4361 master and forwarding it as start trigger to
further TMC4361 which act as slaves then. (Refer to chapter 10.1.)
The TMC4361 provides a clock output (STDBY_CLK). This output can be used to provide a step-synchronous
chopper or application specific. (Refer to chapter 11.)
1.3.7 Safety Stop
The low-active safety pin NFREEZE can be used to end current operations without any delay. This way, an
emergency-stop can be realized in case of dysfunctions on board level. (Refer to chapter 12.)
1.4 Step Frequencies
All parameter units are real physical units. Therefore, it is necessary to set the CLK_FREQ register to the
appropriate value in [Hz] which is given by the external clock. As operation frequency any value between
4.2 MHz and 32 MHz can be chosen.The maximum motion velocity is restricted by the clock frequency.
Values higher than ½ pulse * fCLK are prohibited because the STPOUT output remains active for one clock
cycle and inactive for one clock cycle afterwards for a Step/Dir driver. The microstep resolution can be
chosen in the range from full steps up to 256 microsteps per full step when using the internal sequencer.
(Refer to chapter 8.2.3.)
1.5 Moving the Motor
Moving the motor is simple:
To move a motor to a new target position, write the target position into the associated register by
sending a datagram to the TMC4361.
To move a motor with a newtarget velocity, write the velocity into the register assigned to the stepper
motor.
1.5.1 Motion Controller Functionality
The ramp generator monitors the motion parameters stored in its registers and calculates velocity profiles.
Based on the actual ramp generator velocity a pulse generator supplies step pulses to the motor driver
and to the internal sequencer.
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 7
1.5.2 Ramp Modes and Types
Two general ramp modes can be chosen (see chapter 8.2):
Velocity mode The target velocity VMAX will be reached using the selected ramp type.
Positioning mode The maximum velocity value is used within the given ramp type as long as the
target position is not exceeded. The stepping direction depends on XACTUAL,
XTARGET, and the current ramp status.
Three ramp types can be selected: rectangle shaped ramps, trapezoidal ramps, and S-shaped ramps. S-
shaped ramps in positioning mode finish exactly at the target position by keeping the actual velocity at
maximum value as long as possible while staying within the motion limits. The slopes to and from
maximum velocity are as fast as possible without exceeding limits.
1.6 Status Flags, Events, and Interrupts
The microcontroller connected to the TMC4361 normally requires status information. Therefore, the
TMC4361 provides 32 status flags and 32 status events. Status events can be configured customer specific
and led through to the interrupt output of the TMC4361. (Refer to chapter 7.)
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 8
2 Pin Assignments
2.1 Package Outline
Figure 2.1Pinning (top view)
Attention: Do not connect pins without assignment!
2.2 Signal Description
Pin Number Type Function
GND 6,15,
25,36 GND Digital ground pin for IOs and digital circuitry
VDD5
5,26,37
VDD
Digital power supply for IOs and digital circuitry (3.3V… 5V)
VDD1V8
16,35
VDD
Connection of internal generated core voltage of 1.8V
NSCSIN 2 I Low active chip select input of the SPI interface to the µC
SCKIN 3 I Serial clock for the SPI interface to the µC
SDIIN 4 I Serial data input of the SPI interface to the µC
SDOIN 7 O Serial data output of the SPI interface to the µC (Z if
NSCSIN=1)
CLK_EXT 38 I Clock input to provide aclock with the frequency fCLK for all
internal operations.
NRST 39 I (PU) Low active reset. If not connected, Power-on-Reset and
internal pull-up resistor will be active.
TEST_MODE 34 I Test mode input. Tie to low for normal operation.
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 9
Pin Number Type Function
STOPL 12 I (PD) Left stop switch. External signal to stop a ramp.
If not connected, an internal pull-down resistor will be active.
HOME_REF 13 I (PD)
Home reference signal input. External signal for reference
search.If not connected,an internal pull-down resistor will be
active.
STOPR 14 I (PD) Right stop switch. External signal to stop a ramp.
If not connected, an internal pull-down resistor will be active.
INTR 33 O Interrupt output
TARGET_REACHED 31 O Target reached output
START 20 IO Start signal input/output
NFREEZE 19 I (PU)
Low active safety pin to immediately freeze output
operations.If not connected, an internal pull-up resistor will
be active.
STDBY_CLK 32 O StandBy signal or internal CLK output or ChopSync output
N 21 I (PD) N signal input of incremental encoder input interface
If not connected, an internal pull-down resistor will be active.
NNEG 22 I (PD) Negated N signal input of incremental encoder input interface
If not connected, an internal pull-down resistor will be active.
B
SDI 10 I (PD)
B signal input of incremental encoder input interface.
Serial data input signal of serial encoder input interface
(SSI/SPI).
If not connected, an internal pull-down resistor will be active.
BNEG
NSDI
SDO_ENC
11 IO
Negated B signal input of incremental encoder input interface.
Negated serial data input signal of SSI encoder input interface
Serial data output of SPI encoder input interface.
A
SCLK 40 IO A signal input of incremental encoder interface.
Serial clock output signal of serial encoder interface (SSI/SPI).
ANEG
NSCLK
NSCS_ENC
1 IO
Negated A signal input of incremental encoder interface.
Negated serial clock output signal of serial encoder interface.
Low active chip select output of SPI encoder input interface.
STPOUT
PWMA
DACA
24 O
Step output.
First PWM signal (Sine).
First DAC output signal (Sine).
DIROUT
PWMB
DACB
23 O
Direction output.
Second PWM signal (Cosine).
Second DAC output signal (Cosine).
NSCSDRV
SDO 30 O Low active chip select output of SPI interface to motor driver.
Serial data output of serial encoder output interface.
SCKDRV
NSDO 29 O Serial clock output of SPI interface to motor driver.
Negated serial data output of serial encoder output interface.
SDODRV
SCLK 27 IO Serial data output of SPI interface to motor driver.
Clock input of serial encoder output interface.
SDIDRV
NSCLK 28 I (PD)
Serial data input of SPI interface to motor driver.
Negated clock input of serial encoder output interface
If not connected, an internal pull-down resistor will be active.
n.c. 8,9,17,18 - Do not connect
PD: if n.c. pull-down
PU: if n.c. pull-up
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 10
3 Sample Circuits
The sample circuits show the connection of external components.
SCKDRV_NSDO
SDODRV_SCLK
SDIDRV_NSCLK
NSCSDRV_SDO
SDIIN
NSCSIN
SCKIN
SDOIN
TMC4361
SPI Control Interface
to Microcontroller
SPI Output Interface
to Motor Driver
STPOUT_PWMA
DIRPOUT_PWMB
Step/Dir Interface
to Motor Driver
HOME STOPL STOPR
A_SCLK
ANEG_NSCLK
B_SDI
BNEG_NSDI
N
NNEG
Encoder Input Interface
for incremental ABN or
serial BiSS/SSI/SPI
Reference Switches
CLK_EXT TEST GND
VDD5
+5 V
START
Start Signal
Input or Output
INTR
Interrupt Output
Ext. Clock
TARGET_REACHED
Target Reached Output
NFREEZE
Emergency Stop Switch
VDD1V8 VDD1V8
100 nF
100 nF 100 nF
STDBY_CLK Standby Clock Output
NRST
Optional Inv. Reset Input
Figure 3.1 How to connect the TMC4361
CHECK YOUR CONNECTIONS!
1. Check, if the STDBY_CLK output provides the pulse which is applied at the CLK_EXT input pin. If
both values fit, POR (power on reset), power supply and clk frequency are ready to be used.
2. The SPI communication to TMC4361 is established if the step frequency at STPOUT_PWMA matches
to the selected value of VMAX (maximum velocity value). This relationship is valid with a clock
frequency of 16MHz. When using another frequency, it is necessary to convert the values
appropriately.
TMC4361
µC
SCK
MOSI
MISO
SS
SCKIN
SDOIN
CLK CLK_EXT
NSCSIN
SDIIN
SDO
CSN
SDI
SCK
TMC248
M
10K
NSCSDRV_SDO
SDODRV_SCLK
SCKDRV_NSDO
SDIDRV_NSCLK
STDBY_CLK
Output for chopSync
OSC
Figure 3.2 TMC4361 with TMC248 stepper driver in SPI mode
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 11
TMC4361
µC
SCK
MOSI
MISO
SS
SCKIN
SDOIN
CLK CLK_EXT
NSCSIN
SDIIN
M
10K
NSCSDRV_SDO
SDODRV_SCLK
SCKDRV_NSDO
SDIDRV_NSCLK
STEP
DIR
CSN
SCK
SDI SDO
TMC26x
STPOUT_PWMA
DIRPOUT_PWMB
Figure 3.3 TMC4361 with TMC26x stepper driver in Step/Dir mode. The SPI interface is used for
configuration.
4 Notes
REGISTER names are italicized with VALUE REGISTER in capital letters and switches with small letters.
PIN names are written with capital letters.
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 12
5 SPI Control Interface
The TMC4361 uses 40 bit SPI™ datagrams for communication with a microcontroller. The bit-serial
interface is synchronous to a bus clock. For every bit sent from the bus master to the bus slave, another
bit is sent simultaneously from the slave to the master. Communication between an SPI master and the
TMC4361 slave always consists of sending one 40-bit command word and receiving one 40-bit status
word. The SPI command rate typically comprises a few commands per complete motor motion.
SPI CONTROL INTERFACE
Pin Name Type Remarks
NSCSIN Input Chip Select of the SPI-µC interface (low active)
SCKIN
Input
Clock of the SPI-µC interface
SDIIN
Input
Data input of the SPI-µC interface
SDOIN
Output
Data output of the SPI-µC interface
5.1 SPI Datagram Structure
Microcontrollers which are equipped with hardware SPI are typically able to communicate using integer
multiples of 8 bit. The NSCSINline of the TMC4361has to be handled in a way, that it stays active (low)
for the complete duration of the datagram transmission.
Each datagram sent to the TMC4361 is composed of an address byte followed by four data bytes. This
allows direct 32 bit data word communication with the register set of the TMC4361. Each register is
accessed via 32 data bits even if it uses less than 32 data bits.
Each register is specified by a one byte address:
- For a read access the most significant bit of the address byte is 0.
- For a write access the most significant bit of the address byte is 1.
Some registers are write only registers, most can be read additionally, and there are also some read only
registers.
5.1.1 Selection of Write / Read (WRITE_notREAD)
The read and write selection is controlled by the MSB of the address byte (bit 39 of the SPI datagram).
This bit is 0 for read access and 1 for write access. So, the bit named W is a WRITE_notREAD control bit.
The active high write bit is the MSB of the address byte. Thus, 0x80 has to be added to the address for
a write access. The SPI interface always delivers data back to the master, independent of the W bit. The
data transferred back is the data read from the address which was transmitted with the previous
datagram, if the previous access was a read access. If the previous access was a write access, then the
data read back mirrors the previously received write data. So, the difference between a read and a write
access is that the read access does not transfer data to the addressed register but it transfers the address
TMC4361 SPI DATAGRAM STRUCTURE
MSB (transmitted first) 40 bit LSB (transmitted last)
39 ... ... 0
8 bit address
8 bit SPI status  32 bit data
39 ... 32
31 ... 0
to TMC4361:
RW + 7 bit address
from TMC4361:
8 bit SPI status
8 bit data 8 bit data 8 bit data 8 bit data
39 / 38 ... 32
31 ... 24
23 ... 16
15 ... 8
7 ... 0
W
38...32 31...28 27...24 23...20 19...16 15...12 11...8 7...4 3...0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 13
only and its 32 data bits are dummies.Further, the following read or write access delivers back data read
from the address transmitted in the preceding read cycle.
A read access request datagram uses dummy write data. Read data is transferred back to the master with
the subsequent read or write access. Hence, reading multiple registers can be done in a pipelined fashion.
Data which will be delivered are latched immediately after the prior data transfer.
Whenever data is read from or written to the TMC4361, the MSBs delivered back contain the SPI
statusSPI_STATUS, which is a number of eight status bits.The selection of these bits will be explained in
chapter 7.2.
Example:
For a read access to the register (XACTUAL) with the address 0x21, the address byte has to be
set to 0x21 in the access preceding the read access. For a write access to the register (VACTUAL),
the address byte has to be set to 0x80 + 0x22 = 0xA2. For read access, the data bit might have
any value, e.g., 0.
action data sent to TMC data received from TMC
read XACTUAL 0x2100000000 0xSS & unused data
read XACTUAL 0x2100000000 0xSS & X_ACTUAL
write VACTUAL:= 0x00ABCDEF 0xA200ABCDEF 0xSS & X_ACTUAL
write VACTUAL:= 0x00123456 0xA200123456 0xSS00ABCDEF
*)SS: is a placeholder for the status bits SPI_STATUS
5.1.2 Data Alignment
All data are right aligned. Some registers represent unsigned (positive) values; some represent integer
values (signed) as two’s complement numbers. Single bits or groups of bits are represented as single
bits respectively as integer groups.
5.2 SPI Signals
The SPI bus on the TMC4361 has four signals:
SCKIN bus clock input
SDIIN serial data input
SDOIN serial data output
NSCSIN chip select input (active low)
The slave is enabled for an SPI transaction by a transition to low level on the chip select input NSCSIN.
Bit transfer is synchronous to the bus clock SCKIN, with the slave latching the data from SDIIN on the
rising edge of SCKIN and driving data to SDOIN following the falling edge. The most significant bit is
sent first. A minimum of 40 SCKIN clock cycles is required for a bus transaction with the TMC4361. If less
than 40 clock cycles are transmitted, the transfer will not be valid, even for a read access. However,
sending only eight clock cycles can be useful to obtain the SPI status because it sends the status
information back first.
If more than 40 clocks are driven, the additional bits shifted into SDIIN are shifted out on SDOIN after a
40-clock delay through an internal shift register. This can be used for daisy chaining multiple chips.
NSCSIN must be low during the whole bus transaction. When NSCSIN goes high, the contents of the
internal shift register are latched into the internal control register and recognized as a command from
the master to the slave. If more than 40 bits are sent, only the last 40 bits received before the rising
edge of NSCSIN are recognized as the command.
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 14
5.3 Timing
The SPI interface is synchronized to the internal system clock, which limits the SPI bus clock SCKIN to
half of the system clock frequency. The signal processing of the SPI inputs are supported with internal
Schmitt Trigger, but not with RC elements. To avoid glitches at the inputs of the SPI interface between
µC and TMC4361, external RC elements have to be provided. Figure 5.1 shows the timing parameters of
an SPI bus transaction and the table below specifies the parameter values.
Figure
5.1 SPI timing
SPI interface timing AC-Characteristics
clock period: tCLK
Parameter Symbol
Conditions Min Typ Max Unit
SCKIN valid before or after
change of NSCSIN
tCC
10 ns
NSCSIN high time tCSH
*) Min time is for
syn
chronous CLK
with SCKIN high
one tCH
before
SCSIN high only
tCLK*) >2tCLK+10 ns
SCKIN low time tCL
*) Min time is for
syn
chronous CLK
only
tCLK*) >tCLK+10 ns
SCKIN high time tCH
*) Min time is for
syn
chronous CLK
only
tCLK*) >tCLK+10 ns
SCKIN frequency using external
clock (Example: fCLK = 16 MHz)
fSCK
assumes
synchronous CLK
f
CLK
/ 2
(8)
MHz
SDIIN setup time before rising
edge of SCKIN
tDU
10 ns
SDIIN hold time after rising edge
of SCKIN tDH 10 ns
Data out valid time after falling
SCKIN clock edge tDO no
capacitive load
on SDOIN tFILT+5 ns
tCLK = 1 / fCLK
NSCSIN
SCKIN
SDIIN
SDOIN
t
CC
t
CC
t
CL
t
CH
bit39 bit38 bit0
bit39 bit38 bit0
t
DO
t
ZC
t
DU
t
DH
t
CH
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6 Input Filtering
Input signals can be noisy due to long cables and circuit paths. To prevent jamming, every input pin
provides a Schmitt Trigger. Additionally, several signalsare passed through a digital filter. Particular
inputpins areseparated into four filtering groups. Each groupcan be programmedindividuallyaccording to
its filter characteristics.
PINS AND REGISTERS: INPUT FILTERING GROUPS
Pin names Type Remarks
A_SCLK
B_SDI
N
ANEG_NSCLK
BNEG_NSDI
NNEG
Inputs
Encoder interface input pins
STOPL
HOME_REF
STOPR
Inputs
Reference input pins
START Input START input pin
SDODRV_SCLK
SDIDRV_NSCLK Inputs Master clock input interface pins for serial encoder
Pin name Register address Remarks
INPUT_FILT_CONF
0x03
RW
Filter configuration for all four input groups
6.1 Input Filter Configuration
Every filtering groupcan be configured separately with regard toinput sample rate and digital filter length.
6.1.1 Input Sample Rate (SR)
fCLK ∙ 1 / 2SR
where SR (extended with the particular name extension) isin [0… 7].
This means that every (2SR)th input bit will be considered for internal processing.
Sample rate configuration
SR value
Sample rate
0
fCLK
1
f
CLK
/ 2
2 fCLK / 4
3
fCLK / 8
4
fCLK / 16
5
fCLK / 32
6
f
CLK
/ 64
7 fCLK / 128
6.1.2 Digital Filter Length (FILT_L)
One bit is sampled within each (2SR)thinput clock cycle. The filter length FILT_L can be set within the range
[0… 7]. The filter lengthFILT_L specifies the number of sampled bits thatmust have the same voltage level
toseta new input bit voltage level.
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 16
Configuration of digital filter length
FILT_L value
Filter length
0 No filtering
1 2 equal bits
2
3 equal bits
3
4 equal bits
4
5 equal bits
5 6 equal bits
6
7 equal bits
7
8 equal bits
6.1.3 Examples
The following three examples depict the input pin filtering of three different input filtering groups. The
voltage levels after passing the Schmitt Trigger are compared to the internal signals which are processed
by the motion controller.
The sample points are depicted as green dashed lines.
REFERENCE INPUT PINS
Here, every second clock cycle is sampled.Two sampled input bits must be equal to be a valid input
voltage.
Figure
6.1 Reference input pins: SR_REF = 1, FILT_L_REF = 1
S
TART INPUT PIN
Every fourth clock cycle
is sampled and the sampled input bit is valid.
CLK
START
internal Start
input signal
Figure
6.2START input pin: SR_S = 2, FILT_L_S = 0
E
NCODER INTERFACE INPUT PINS
Every clock cycle bit
is sampled.Eight sampled input bits must be equal to be a valid input voltage.
Figure
6.3 Encoder interface input pins: SR_ENC_IN = 0, FILT_L_ENC_IN = 7
CLK
HOME
internal
home signal
STOPL
internal left
stop signal
CLK
B_SDI
internal B
input signal
N
internal N
signal
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 17
7 Status Flags & Events
The TMC4361 offers several possibilities for velocity ramps.It combinestarget positioning and velocity
ramps without interventions in between. However, the microcontroller connected to the TMC4361
normally requiresstatus information. Therefore, TMC4361 provides 32 status flags and 32 status events.
Status events can be configured customer specific and lead through using the interrupt output of the
TMC4361. Further, the eight SPI status bits sent witheach SPI datagram can be read out.
PINS AND REGISTERS: STATUS FLAGS AND EVENTS
Pin names Type Remarks
INTR
Output
Interrupt output to indicate status events
Register name
Register address
Remarks
STATUS_FLAGS 0x0F R
32 status flags of the TMC4361 and the connected TMC
motor driver chip
EVENTS
0x0E
R+C
32 events triggered by altered TMC4361 status bits
SPI_STATUS_SELECTION
0x0B
RW
Selection of 8 out of 32 events for SPI status bits
EVENT_CLEAR_CONF 0x0C RW Exceptions for cleared event bits
INTR_CONF
0x0D
RW
Selection of 32 events for INTR output
7.1 Status Flags
Status bits of the STATUS_FLAGS register are specified in the register chapter (see 17).
7.2 Status Events &SPI Status &Interrupts
STATUS FLAGS - STATUS EVENTS
Status eventsare triggered during the transition process of status bits from inactive to active level.Status
bits and status events are associated in different ways:
- Several status eventsare associated with one status bit.
- Some status events show the status transition of one or more status bits out of a status bit group.The
motor driver flags, e.g.,triggeronly one motor driver event MOTOR_EVin case one of the selected
motor driver status flags becomes active.
- In case a flag consists of more than one bit,the number of associated events that can be triggered
corresponds to the valid combinations. The VEL_STATE flag, e.g., has two bit but three associated
velocity state events (00/01/10).Such an eventistriggeredif the associated combination switches from
inactive to active.
- Furthermore, some events have no equivalence in the STATUS_FLAGS register(e.g.,COVER_DONE which
indicates new data from the motor driver chip).
The EVENTS register is automatically cleared after reading the register subsequent to an SPI datagram
request.
To prevent events from being cleared, the EVENT_CLEAR_CONF register can be assigned properly. Just set
the related EVENT_CLEAR_CONF register bit position to 1.
HOW TO AVOID A LACK OF INFORMATION
The recognition of a status event can fail in case it is triggered right before or during the EVENTS register
becomes cleared. By setting the EVENT_CLEAR_CONF register appropriately, this can be avoided. Up to
eight events can be selected for permanent SPI status report.Therefore, select up to eight events by
writing 1 to the specific bit positions of the SPI_STATUS_SELECTIONregister.The bit positionsaresorted
according to the event bit positions in the EVENTS register. In case more than eight events are chosen,
the first eight bits (starting from index 0) are forwarded as SPI_STATUS.
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 18
INTERRUPTS
Similar to the EVENT_CLEAR_CONF register and the SPI_STATUS_SELECTIONregister, events can be selected
using the INTR_CONF register to be forwarded to the INTR output.The active polarity of the INTR output
can be set withintr_pol. The selected events will be ORed to one signal. The INTR output becomes active
as soon as one of the selected events triggers.
Due to the importance of events for interrupt generation and SPI status monitoring, it is recommended
to clear the EVENTS register before starting regular operation.
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8 Ramp Generator
Stepgeneration is one of themain tasks of a steppermotor motion controller. The internal ramp generator
of the TMC4361 provides several ways of step generation in order to form different ramp types to fit for
various applications.
PINS AND REGISTERS: RAMP GENERATOR
Pin names Type Remarks
STPOUT_PWMA Output Step output signal
DIROUT_PWMB Output Direction output signal
Register name
Register address
Remarks
GENERAL_CONF
0x00
RW
Ramp generator affecting bits 1 : 5
STP_LENGTH_ADD
DIR_SETUP_TIME 0x10 RW
Additional step length in clock cycles; 16 bits
Additional time in clock cycles when no steps will occur
after a direction change; 16 bits
RAMPMODE
0x20
RW
Requested ramp type and mode; 3 bits
XACTUAL
0x21
RW
Current internal microstep position;signed; 32 bits
VACTUAL
0x22
R
Current step velocity; 24 bits; signed; no decimals
AACTUAL 0x23 R Current step acceleration; 24 bits; signed; no decimals
VMAX 0x24 RW Maximum permitted or target velocity; signed; 32 bits
=
24+8 (24 bits integer part, 8 bits decimal places)
VSTART 0x25 RW Velocity at ramp start; unsigned; 31 bits=23+8
VSTOP
0x26
RW
Velocity at ramp end; unsigned; 31 bits=23+8
VBREAK 0x27 RW At this velocity value, the ac-
/deceleration will change
during trapezoidal ramps; unsigned; 31 bits=23+8
AMAX 0x28 RW Maximum permitted or target acceleration; unsigned; 24
bits=22+2 (22 bits integer part, 2 bits decimal places)
DMAX 0x29 RW Maximum permitted or target deceleration; unsigned; 24
bits=22+2
ASTART 0x2A RW Acceleration at ramp start or below VBREAK; unsigned; 24
bits=22+2
DFINAL 0x2B RW Deceleration at ramp end or below VBREAK; unsigned; 24
bits=22+2
BOW1 0x2D RW First bow value of a complete velocity ramp; unsigned; 24
bits=24+0 (24 bits integer part, no decimal places)
BOW2 0x2E RW
Second bow value of a complete velocity ramp; unsigned;
24 bits=24+0
BOW3 0x2F RW
Third bow value of a complete velocity ramp; unsigned;
24 bits=24+0
BOW4 0x30 RW
Fourth bow value of a complete velocity ramp; unsigned;
24 bits=24+0
CLK_FREQ
0x31
RW
External clock frequency fCLK; unsigned; 25 bits
XTARGET
0x37
RW
Target position;signed; 32 bits
8.1 Step/Dir Output Configuration
Step/Dir output signals can be configured for the driver circuit:
- For step signals that have to be longer than one clock cycle setSTP_LENGTH_ADD appropriately. Then,
the resulting step length is equal to STP_LENGTH_ADD+1 clock cycles. Thus, the step length can be
chosen within the range 1…216 clock cycles.
- DIROUT does not change the level during the active step pulse signal and for STP_LENGTH_ADD+1
clock cycles after the step signal returns to theinactive level.
- With the register DIR_SETUP_TIME the delay [clock cycles] between DIROUT and STPOUT voltage level
changes can be set. Using this register, no steps are sent via STPOUT for DIR_SETUP_TIME clock cycles
after a level change at DIROUT.
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 20
Note:
- Per default, the step output is high active because a rising edge at STPOUT indicates a step.
- For changing the polarity, setstep_inactive_pol=1. Now,each falling edge indicates a step.
- A step can be generated by toggeling the step output. Therefore, set toggle_step=1.
- pol_dir_out sets the output level for the negative velocity direction.
- pol_dir_out, step_inactive_pol, and toggle_step are part of the general configuration register.
8.2 Ramp Modes and Types
With proper configuration, the internal ramp generator of the TMC4361 is able to generate various ramps
andthe relatedstep outputsfor STPOUT. Note, that there are many possibilities to combine a general ramp
mode (velocity mode, positioning mode) with basicramp types (ramp in hold mode, trapezoidal ramp, S-
shaped ramp). Therefore, select the general ramp mode first and proceed with the ramp type and further
specifications, e.g., setting start and stop velocities or choosing different acceleration/deceleration values
for each ramp phase.
GENERAL RAMP MODES
Two general ramp modes can be chosen with theRAMPMODEregister. Therefore, bit 2 of the Ramp
Generator Register Set(see chapter 17.16) is used:
RAMPMODE(2)=0 Velocity mode. The target velocity VMAX will be reached using the selected ramp
type.
RAMPMODE(2)=1 Positioning mode. VMAX is the maximum velocity value which will be used within
the given ramp type and as long as the target position XTARGET will not be exceeded.
Furthermore, the sign of VMAX is not relevant during positioning. The direction of
the steps depends on XACTUAL, XTARGET, and the current ramp status.
RAMP TYPES
Three basic ramp types are provided. These types differ in the velocity value development during the
drive. For setting the basic ramp type, use the Ramp Generator Register Set bits 1 and 0.
TMC4361 RAMP TYPES
RAMPMODE(1 : 0) Ramp type Function
b’00
Ramp in hold mode
Follow VMAXonly (rectangle velocity shape).
b’01 Trapezoidal ramp
Consideration of acceleration and deceleration values
without adaption of these values.
b’10
S-shaped ramp
Use all ramp values (including bow values).
RAMPMODE(1 : 0)=00
Rectangle shaped ramp type in hold mode. VACTUAL is set immediately to VMAX.
v(t)
t
VMAX
Figure 8.1 Rectangle shaped ramp type
In positioning mode (RAMPMODE(2)=1), VACTUAL is set
instantly to 0 if the target position is reached.
For exact positioning, it is recommended to set
VMAX fCLK • ¼ pulses
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 21
RAMPMODE(1 : 0)=01
Trapezoidal shaped ramp type
v(t)
t
VMAX A
1
A
2
A
3
v(t)
t
VMAX
VBREAK
A
1
A
2
A
3L
A
1L
A
3
Figure 8.2 Trapezoidal shaped ramp type
This trapezoidal ramp type reachesVMAXusing linear ramps whereas the actual acceleration/deceleration
factor AACTUAL depends on the current ramp phase and the velocity which should be reached. The
corresponding sign assignment for different ramp phases is depicted in the following table:
Ramp phase: A1L A1 A2 A3 A3L
v>0: AACTUAL= ASTART AMAX 0 -DMAX -DFINAL
v<0: AACTUAL= -ASTART -AMAX 0 DMAX DFINAL
RAMPMODE(1 : 0)=10
S-shaped ramp types
v(t)
t
VMAX B
1
B
12
B
23
B
34
B
3
B
4
B
2
ASTART=0 DFINAL=0
Figure 8.3 S-shaped ramp without initial and final acceleration/deceleration values
v(t)
t
VMAX
B
1
B
12
B
23
B
34
B
3
B
4
B
2
ASTART>0 DFINAL>0
Figure 8.4 S-shaped ramp type with initial acceleration and final deceleration value for B1 and B4
This ramp type reachesVMAX by means of S-shaped ramps whereas the acceleration/deceleration factor
depends on the current ramp phase and alters every 64 clock cycles during the bow phases B1, B2, B3,
and B4.
Acceleration slope and deceleration slope haveonly one
acceleration/deceleration value each. For this types, set
VBREAK = 0.
The acceleration/deceleration factor alters at VBREAK.
In positioning mode, the ramp finishes exactly at the target
position XTARGET by keeping VACTUAL = VMAX as long as
possible.
The start phase and the end phase of an S-shaped rampcan
be accelerated/decelerated by ASTART and DFINAL.Using
these parameters, the ramp starts with ASTART and it is
ended with DFINAL. DFINAL becomes valid as soon as
AACTUAL reaches the chosen DFINAL value. ASTART and
DFINALcan be set separately.
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 22
Ramp phase: B1 B12 B2 B23 B3 B34 B4
v>0:
AACTUAL=
ASTARTAMAX AMAX AMAX0
0 0-DMAX
-DMAX -DMAX-DFINAL
BOWACTUAL=
BOW1 0 -BOW2 0 -BOW3 0 BOW4
v<0:
AACTUAL=
-ASTART-AMAX
-AMAX -AMAX0
0 0DMAX
DMAX DMAXDFINAL
BOWACTUAL=
-BOW1 0 BOW2 0 BOW3 0 -BOW4
S-SHAPED RAMPS IN POSITIONING MODE
The ramp finishesexactly at the target position by keeping abs(VACTUAL) = VMAX as long as possible.
Furthermore, the slopes to and from VMAXare as fast as possible without exceeding given values. It is
even possible that the phases B12, B23, and B34are left out due to given values. Nevertheless, the S-shaped
ramp style is always performed in positioning mode, if RAMP_MODE(1 : 0) = b’10 is set.The parameter
DFINAL is not considered during positioning mode.
8.2.1 Velocity Start VSTARTand Velocity Stop VSTOP
S-shaped and trapezoidal velocity ramps can be started with an initial velocity value by setting VSTART
higher than zero (see Figure 8.5).Such an S-shaped ramp with VSTART > 0 is a ramp without the first ramp
bow B1. The ramp starts with AACTUAL = AMAX and VACTUAL = VSTART.Logically, the parameter ASTARTis
not considered.
It is also possible to set VSTOP (a final velocity value) which finishes the ramp ifVACTUAL reaches
the VSTOPvalue (see Figure 8.6). This leads to an S-shaped velocity ramp without the bow B4. Hence,
DFINALis not considered.
TRAPEZOIDAL AND S-SHAPED RAMPS USING PARAMETER VSTART
VSTART> 0 and VSTOP = 0
v(t)
t
VMAX
VBREAK
A
1
A
2
A
3L
A
1L
A
3
VSTART
v(t)
t
VMAX B1B12 B23 B34
B3B4
B2
VSTART
Figure 8.5 Trapezoidal and S-shaped ramps using VSTART
TRAPEZOIDAL AND S-SHAPED RAMPS USING PARAMETER VSTOP
VSTART = 0 and VSTOP> 0
v(t)
t
VMAX
VBREAK
A
1
A
2
A
3L
A
1L
A
3
VSTOP
v(t)
t
VMAX B
1
B
12
B
23
B
34
B
3
B
4
B
2
VSTOP
Figure 8.6 Trapezoidal and S-shaped ramps using VSTOP
TRAPEZOIDAL AND S-SHAPED RAMPS USING PARAMETERS VSTART AND VSTOP
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 23
VSTART> 0 and VSTOP> 0
v(t)
t
VMAX
VBREAK
A
1
A
2
A
3L
A
1L
A
3
VSTOP
VSTART
v(t)
t
VMAX B1B12 B23 B34
B3B4
B2
VSTOP
VSTART
Figure 8.7 Trapezoidal and S-shaped ramps using VSTART and VSTOP
S
UGGESTIONS
-
VSTARTand VSTOP are used whenstarting or ending a velocity ramp. If the velocity direction
alters due to register assignments while a velocity ramp is in progress, the velocity values
develop according to the current velocity ramp type without using VSTARTor VSTOP.
- VSTOP is used in positioning modewhen the target position is reached. In velocity mode, VSTOPis
only used whenVACTUAL 0 and the target velocity VMAX is assigned to 0.
- The unsigned values VSTART and VSTOP are valid for both velocity directions.
-
Every register value change is assigned immediately.
8.2.2 Limitations
ATTENTION
-
Ramp parameter value changes in positioning mode during the ramp progress (exceptVMAX and
XTARGET) are allowed but can result in a temporarily overshooting of XTARGET.
- To stop an S-shaped ramp during positioning do not set only VMAX = 0!There are two possibilities
for further settings:
Switch to velocity mode soon after setting VMAX = 0 and when reaching VACTUAL = 0
(VEL_REACHED event triggers) switch back to positioning mode.
The other possibility is to set VMAX = 1. As soon as theVEL_REACHED event triggers, set
VMAX to 0.
- Only valid for trapezoidal ramps: If a register value during a deceleration ramp (e.g. target
position)is altered in a way that an immediate acceleration in the same direction must follow,
the deceleration ramp becomes finished to VACTUAL = 0 first. Afterwards, the acceleration slope
begins regularly. To avoid the unintentional finishing process of the deceleration ramp, set
VMAX < abs(VACTUAL).If VMAX is reached now, set VMAX to the requested first value.
The same procedure has to be usedin velocity mode if VMAXbecomes decreased and increased
again during the deceleration slope.
Very slow deceleration slopes (DMAX (VMAX / 20s)) of trapezoidal ramps can result in an
overdrive of the target position with an immediate subsequent ramp to overh
aul target
mismatch. To avoid this, please use a reasonable value for VSTOP.
- A VACTUAL value which exceeds VMAX can be result of register changes during an S-shaped
ramp. This is, because the bows B1, B2, B3, and B4 are maintained during the ramp progress.
- If the requested conditions for the acceleration slope of an S-shaped ramp (VSTART or ASTART,
BOW1 and BOW2) do not fit toVMAX, the starting acceleration value ASTARTbecomes altered. In
case of misconfiguration at ramp start AMAXor VSTARThave to be decreased in order to reach
XTARGET.
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 24
FASTEST POSSIBLE SLOPE IN POSITIONING MODE
The fastest possible slopes are always performed if the phases B12 and/or B34 are not reached during a
rising and/or falling S-shaped slope. Thus, the ramp maintains the maximum velocity VMAX as long as
possible in positioning mode until the falling slope finishes the ramp to reach XTARGET exactly. The result
is the fastest possible positioning ramp in matters of time.
8.2.3 Internal Ramp Generator Units
All parameter units are real arithmetical units. Therefore, it is necessary to set the CLK_FREQ register to
the appropriate value in [Hz] which is given by the external clock. Any value between 4.2 MHz and 32
MHz can be chosen.
VELOCITY VALUES
VACTUAL is given as a 32 bit signed value with no decimal places. The unsigned velocity values VSTART,
VSTOP, and VBREAK consist of 23 digits and 8 decimal places. VMAXis a signed value with 24 digits and
8 decimal places. Velocity values are given in pulses per second [pps].
The maximum velocity VMAX is restricted by the clock frequency. Values higher than ½ puls * fCLK are
prohibited because of an incorrect STPOUT output if VACTUAL exceeds this limit.
ACCELERATION VALUES
The unsigned values AMAX, DMAX, ASTART, and DFINAL consist of 22 digits and 2 decimal places. AACTUAL
shows a 24 bit non decimal signed value. Acceleration and deceleration units are given in pulses per
second² [pps²].
BOW PARAMETER VALUES
Bow values are unsigned 24 bit values without decimal places. They are given in pulses per second³
[pps³].
The following absolute minimum and maximum values are valid:
Value Classes Velocity Acceleration Bow Clock
Registers VMAX, VSTART,
VSTOP, VBREAK
AMAX, DMAX,
ASTART, DFINAL
BOW1, BOW2,
BOW3, BOW4 CLK_FREQ (fCLK)
Minimum 3.906250 mpps 0.250000 mpps2 1 mpps3 4.194304 MHz
Maximum 8.388607 mpps
½ puls * fCLK 4.194303 mpps2 16.777 mpps3 32MHz
SHORT AND STEEP RAMPS
For short and steep ramps higher acceleration/deceleration and bow values than usual are available by
activating direct_acc_val_en anddirect_bow_val_en (seegenerator configuration register, chapter 17.1). Set
these parameters to 1 to change the units:
direct_acc_val_en=1 The values forAMAX, DMAX,ASTART, DFINAL, and DSTOP (see chapter9) are given
as velocity value change per clock cycle with 24 bit unsigned decimal places(MSB
=2-14).
direct_bow_val_en=1 Bow values aregiven as acceleration value change per clock cycle. The values
BOW1, BOW2, BOW3, and BOW4 are 24 bit unsigned decimal places with the MSB
defined as 2-29.
EXAMPLE
With a clock frequency fCLK=16 MHz the following maximum values are valid:
Value Classes Acceleration (direct_acc_val_en=1) Bow (direct_bow_val_en=1)
Registers AMAX, DMAX, ASTART, DFINAL, DSTOP BOW1, BOW2, BOW3, BOW4
Calculation a[pps²] = (v/clk_cycle) / 237 ∙ fCLK2 bow[pps³] = (∆a/clk_cycle) / 253 ∙ fCLK3
Minimum ~1.86 kpps² ~454.75 kpp
Maximum ~31.25 Gpp ~7.63 Tpps3
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9 Reference Switches
The reference input signals of the TMC4361 can be considered as a safety feature.The TMC4361 provides
differentpossibilitiesfor reference switches and allowsfor appropriate settings for variousapplications.The
TMC4361 offers two switches in hardware (STOPL, STOPR) and two additional virtual stop switches
(VIRT_STOP_LEFT, VIRT_STOP_RIGHT). Additionally, a home reference switch is available.
PINS AND REGISTERS: REFERENCE SWITCHES
Pin names Type Remarks
STOPL
Input
Left reference switch
STOPR Input Right reference switch
HOME_REF Input Home switch
TARGET_REACHED
Output
Reference switch to indicate XACTUAL=XTARGET
Register name
Register address
Remarks
REFERENCE_CONF
0x01
RW
Configuration of interaction with reference pins
HOME_SAFETY_MARGIN
0x1E
RW
Region of uncertainty around X_HOME
DSTOP 0x2C RW
Deceleration value if stop switches STOPL/STOPR or virtual
stops are used with soft stop ramps
.The deceleration
value allows for an automatic linear stop ramp.
POS_COMP
0x32
RW
Free configurable compare position; signed; 32 bits
VIRT_STOP_LEFT 0x33 RW
Virtual left stop that triggers a stop event at
XACTUAL VIRT_STOP_LEFT; signed; 32 bits
VIRT_STOP_RIGHT 0x34 RW
Virtual left stop that triggers a stop event at
XACTUAL VIRT_STOP_RIGHT; signed; 32 bits
X_HOME
0x35
RW
Home reference position; signed; 32 bits
X_LATCH
0x36
RW
Stores XACTUAL at different conditions; signed; 32 bits
9.1 STOPL and STOPR
A left and a right stop switch are provided in hardware in order to stop the drive immediately, if one of
them is triggered. Therefore, pin 12 and pin 14 of the motion controller have to be used. Both switches
have to be enabled first:
- To use STOPL set stop_left_en=1. Now, the current velocity ramp stopsin case STOPL is equal to the
chosen active polarity pol_stop_left and VACTUAL < 0.
- To use STOPR set stop_right_en=1. Now, STOPR stops the ramp in case the STOPR voltage level
matches pol_stop_right and VACTUAL > 0.
The deceleration slope for stopping the ramp is influenced by soft_stop_en:
- Set soft_stop_en=0 for a hard and quick stop.
- Set soft_stop_en=1 to stop the ramp with a linear falling slope. In this case the deceleration factor
is determined by DSTOP.VSTOPis not considered during the stop deceleration slope.
At the same time when a stop switch becomes active, the related status flag will be setand the particular
event will be released. The flag remains set as long as the stop switch remains active. After reaching
VACTUAL=0 due to the slope, further movement in the particular direction is not possible.
Driving on in the direction of areference switch is possible if the following conditions are met:
- The related status event is set back. The reference switch is not active anymore or alternatively, the
related enabling switch (stop_left_en, stop_right_en) is reset to 0 (switched off) to go on driving in
the - prior to that - closed direction.
- Stop eventsare cleared by reading out the EVENTS register. This is done automatically by the motion
controller subsequent to an SPI datagram read request to this register. (There is only one exception
to this if an event is selected for the EVENT_CLEAR_CONF register in order to inhibit the regular
clearing.)
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 26
9.1.1 Configurations
Four different events can be chosen to latch the current internal position XACTUAL in the register X_LATCH.
The following events and reference configurations result in such a transfer with an event indicating the
latching process:
Reference configuration pol_stop_left=0 pol_stop_left=1 pol_stop_right=0 pol_stop_right=1
latch_x_on_inactive_l=1 STOPL=0 1 STOPL=1 0 --- ---
latch_x_on_active_l=1 STOPL=1 0 STOPL=0 1 --- ---
latch_x_on_inactive_r=1 --- --- STOPR=0 1 STOPR = 10
latch_x_on_active_r=1 --- --- STOPR=1 0 STOPR = 01
Setting invert_stop_direction=1 swaps STOPL and STOPR. Thus, all configuration parameters for STOPL
become valid for STOPR and vice versa.
9.2 Virtual Stop Switches
The TMC4361 provides additional virtual limits which trigger stop slopes in case the specific virtual stop
switch microstep position is reached. Virtual stop positions can be setusing VIRTUAL_STOP_LEFT and
VIRTUAL_STOP_RIGHT which are part of the Target and Compare Register (see chapter 17.17).
Virtual stop switches have to be enabled like non-virtual reference switches. Therefore, set
virtual_left_limit_en respectively virtual_right_limit_en to 1. Hitting a virtual limit switch triggers the same
process as hitting STOPL or STOPR.
At the same time when a virtual stop switch becomes active an event becomes released which has to
be cleared in any case before further movement in the particular direction can be performed again.
Driving on in the direction of a virtual switch after a stop event is possible if the following conditions
are met:
- For further movement in negative direction choose a new value for VIRTUAL_STOP_LEFT or set
virtual_left_limit_en=0.
- For further movement in positive direction choose a new value for VIRTUAL_STOP_RIGHT or set
virtual_right_limit_en=0.
The deceleration slope can be chosen with virt_stop_mode:
- Set virt_stop_mode= b’01 for a hard and quick stop.
- Set virt_stop_mode= b’10 to stop the ramp with a linear falling slope. In this case the deceleration
factor is determined by DSTOP.
- Set virt_stop_mode= b’00 to stop the ramp with the currently chosen ramp type.In this case the
actual ramp parameter set DMAX and DFINAL determine the deceleration ramp. Note, that for S-
shaped ramps, BOW3 and BOW4 are valid, too.
Attention
invert_stop_direction has no influence onVIRTUAL_STOP_LEFT resp. VIRTUAL_STOP_RIGHT.
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9.3 HOME Reference
For monitoring, theswitch reference input HOME_REF is provided.
HOMING PROCESS
- Enable the tracking mode with start_home_tracking=1.
- With the next home event XACTUALis latched to X_HOME.
- The switchstart_home_trackingof the REFERENCE_CONF register is automatically reset to 0.
- An error flag is permanently evaluated. This error flag indicates whether the current voltage level of
the HOME_REF reference input is valid in respect to X_HOME and the chosen home_event.
Nine different home events are possible. Besides home_event = b’0000 which uses the N signal of an
incremental ABN encoder, the following home events can be used. Therefore, configure the four
home_event bits which are part of the reference switch configuration register (see chapter 17.2)
home_event Description
X_HOME
(direction: negative/positive)
b’0011 HOME_REF =
0 indicates negative direction in
reference to X_HOME
b’1100 HOME_REF =
0 indicates positive direction in
reference to X_HOME
b’0110
HOME_REF =
1
indicates home
position
X_HOME in center
b’0010 X_HOME at the left side
b’0100 X_HOME at the right side
b’1001
HOME_REF =
0
indicates home
position
X_HOME in center
b’1011 X_HOME at the right side
b’1101 X_HOME at the left side
DEFINING AN UNCERTAINTY AREA AROUND X_HOME
Use the register HOME_SAFETY_MARGIN for defining an uncertainty area around X_HOME. Then, homing
uncertainties related to the special application environment are considered for the further process. There
will be no error flag generated if two conditions are met:
XACTUAL = X_HOME - HOME_SAFETY_MARGIN and XACTUAL = X_HOME + HOME_SAFETY_MARGIN
The followingexamples (see Figure 9.1.) show the pointsat which - dependent on the chosen home_ event
-an error flag is generated.
It is recommended to set theHOME_SAFETY_MARGINbigger than the periodduring which the HOME_REF
level is active for the home_events b’0110, b’0010, b’0100, b’1001, b’1011, and b’1101.This is necessary to
avoid wrongHOME_ERROR_Flags.
After homing with the N channel (home_event = b’0000) for a precise assignment of X_HOME the correct
home_eventhas to be assigned in order to activate the generation of HOME_ERROR_Flags.Note that
home_event = b’0000 results in HOME_ERROR_Flag=0 permanently.
Attention
If the homing process is based on the n event (home_event = b’0000),latch_enc_on_nhas to be set as well
as clr_latch_cont_on_n or clr_latch_once_on_n.Refer to chapter 14.2.1 for further information about the
switches.
HOME_REF
0
1
HOME_REF
0
1
HOME_REF 0
1
HOME_REF 0
1
HOME_REF 0
1
HOME_REF 0
1
HOME_REF
0
1
HOME_REF 0
1
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 28
Figure
9.1HOME_REF monitoring and HOME_ERROR_FLAG
The two examples above illustrate HOME_REF monitoring and generation of the HOME_ERROR_Flag for
home_event = b’0011 (*), b’1100 (**), b’0110 (***), b’0010 (***), b’0100 (***), b’1001 (****), b’1011 (****), and
b’1101 (****).
HOMING WITH STOPL AND STOPR
STOPL and STOPR inputs can also be used as HOME_REF inputs.Thereforesetthe REFERENCE_CONF register
bits stop_left_is_home=1 respectivelystop_right_is_home=1. This leads to a stop of the current ramp only
after STOPL or STOPR is switching to active state and the home uncertainty region is crossed. The home
uncertainty region is given by X_HOME and HOME_SAFETY_MARGIN.
9.4 Cyclic Movement toXTARGET
Usually, reaching XTARGETin positioning mode finishes a velocity ramp. To repeat the current ramp with
its specified parameters steadily set clr_pos_at_targetto 1. Until velocity mode is chosen or
clr_pos_at_target is set to 0, XACTUAL will be reset to 0 if XTARGET is reached (XACTUAL = XTARGET).
Normally,the falling slope to stop the ramp is performed within each ramp cycle.
TRIGGERING FURTHER RAMPSIDENTICAL TO THE FIRST ONE (POSITIONING MODE ONLY)
- Set clr_pos_at_target=1
- SetXTARGET.
- Now, XACTUAL is set to 0 automatically if XTARGET is reached.
- Another velocity ramp for reachingXTARGETbecomes active now.
9.5 Target Reached / Position Comparison
The TARGET_REACHEDpin 31forwards the TARGET_REACHED_Flag. Thus, if XACTUAL = XTARGET,
TARGET_REACHED is active. The polarity can be configured via invert_pol_target_reached switch of the
GENERAL_CONF register. The output pin can also be used to indicate the status of the
POS_COMP_REACHED_Flag which is generated if the POS_COMP register value is equal to XACTUAL or
ENC_POS.
OVERVIEW: SETTINGS FOR POSITION COMPARISON
- Choose a POS_COMP value. The position compare register provides 32 bits.
- Choose a compare parameter by settingpos_comp_source.
Set pos_comp_source=1 for ENC_POS.
Set pos_comp_source=0 for XACTUAL.
Theposition compare process is permanently active.Thestored POS_COMPposition is compared
withXACTUAL respectively ENC_POS automatically. If POS_COMP = XACTUAL the status flag
POS_COMP_REACHED_F becomes set and the POS_COMP_REACHED event becomes released, provided
that switching to active state is done first.
- Additional, the output TARGET_REACHEDcan be used to reportthe state of position comparison
instead of the target reached status. Therefore, set pos_comp_output = b’11.
HOME_ERROR_Flag ***
HOME_REF
X_HOME
HOME_SAFETY_MARGIN
HOME_ERROR_Flag *
HOME_ERROR_Flag **
HOME_ERROR_Flag ****
X_HOME
HOME_SAFETY_MARGIN
HOME_ERROR_Flag ***
HOME_REF
HOME_ERROR_Flag *
HOME_ERROR_Flag **
HOME_ERROR_Flag ****
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10 Ramp Timing &Synchronization
The TMC4361 provides various possibilities for ramp timing. Usually, every external register change via an
SPI input is assigned immediately to the internal registers. With a proper start configuration of the
TMC4361, rampsequences without any intervening in between can be programmed. Various possibilities
result from choosing different target positions, which can be predefined and successively activated,
combined with the opportunity of a cyclic pipeline. Therefore, it is necessary to understand ramp start
configurations, triggers, and consequences.
PINS AND REGISTERS: SYNCHRONIZATION
Pin names Type Remarks
START Input and
Output
External start input to get a start signal or
external start output to indicate an internal start event.
Register name Register address Remarks
START_CONF 0x02 RW The configuration register of the synchronization unit
START_OUT_ADD
0x11
RW
Additional active output length of external start signal
START_DELAY
0x13
RW
Delay time between start trigger and signal
X_PIPE0… 7
0x38…0x3F
RW
Target positions pipeline
10.1 Start Signal Generation
A ramp can be initiated using an internal or an external start trigger for the start signal generation. Note
that a start trigger is not the start signal itself but the transition slope to the active start state. Now, for
ramp start configuration consider the following steps:
1. Choose internal or external start trigger(s).
2. Adjust the timing of the start signal after a start trigger has been recognized.
3. Enable start signal processing.
10.1.1 Starting a Ramp via an Internal Start Trigger
There are different triggers available for an internal start signal. These triggers are assigned by the
trigger_events switches (bits 58) of the START_CONF register. Every bit of trigger_event can be selected
separately. Thus, more than one signal can trigger a start event.
trigger_events(8 : 5)
Description
b’xxx0 Set bit 5 to 0 for internal start trigger only. The START pin as output
. (If bit 5 is
set to 1, an external trigger is chosen and the START pin is used as input)
b’xx1x TARGET_REACHED event is assigned as start signal for timer
b’x1xx
VELOCITY_REACHED event is assigned as start signal for timer
b’1xxx
POSCOMP_REACHED event is assigned as start signal for timer
10.1.2 Starting a Ramp via an External Start Trigger
Set Start_en(0) = 1 to use external start signals. Further, there is one specific bit that has to be set for
using an external trigger:
trigger_events(8 : 5)
Description
b’xxx1
Set bit 5 to 1 for an external start trigger. Use the START pin as input now.
DEFINING THE ACTIVE VOLTAGE LEVEL OF THE START PIN
The active voltage level of the START pin is defined by pol_start_signal.
EXAMPLES
1. Setpol_start_signal=0 and trigger_events(0)=start_en(0)=1
Now, the voltage level transition from high to low triggers a start signal.The signal is further processed
by the synchronization unit.
2. Set pol_start_signal = 1 and trigger_events(0) = 0
Now, start is used as output forwarding internal start signals with a high active level.
External start signalshave to be filtered. The filter length must exceed START_OUT_ADD clock cycles!
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10.1.3 start_enSettings
To enable a start signal for a ramp it is necessary to set start_en which is part of the START_CONF register.
By setting start_en, the impact of generated start signals on the internal rampis specified.
A start signal can be used in different ways:
start_en(2 : 0)
Description
b’000
No start signal will be generated or processed further.
b’xx1
XTARGET is altered only after a start signal.
b’x1x VMAX is altered only after a start signal.
b’1xx
RAMPMODEcan be changed after a start signal.
10.1.4 Adjustments Related to Start Signal Timing and Prioritizing
Every start switch can be enabled and disabled separately. In case an enable switch is set low, the
particular register is changed immediately if the register is assigned by an SPI datagram. Using enable
switches allows for setting specific points in time for altering register values. Thus, the assignment of
SPI requests to the registers XTARGET, VMAX and RAMP_MODEcan be uncoupled from the SPI transfer
itself. The assignment can be combined with trigger events which are related to the internal start signal
generation.
START_DELAYsetting a delay time for the start signal after a trigger
For delaying an immediate ramp start set START_DELAY (31 : 0) to a reasonable value. Then, the chosen
START_DELAY value defines the time interval between the recognition of the chosen start trigger(s) and
the internal start signal generation. For switching off a chosen start delay time setstart_en = b’000.
immediate_start_inprioritizing the external START signal
For prioritizing the external START signal opposed to all other triggers set immediate_start_in = 1. Thus,
an external START is executed immediately after its recognition independently from a given START_DELAY
time, an active timer, or other triggers.
Synchronizing Several Motion Controllers
Due to the fact that the start pin can be assigned as input or output synchronization between several
motion controllers is feasible. Besides the setup of several TMC4361 as slaves and one master µC which
can initiate velocity ramps of the slave devices concurrently, it is possible to use the internal start signal
of a TMC4361 as external trigger for other motion controllers. Assigning the start pin as output, one
master TMC4361can forward its internal start signal (e.g. due to a target reached event) to trigger register
changes for other motion controllers which act as slaves under this condition. Therefore,
START_OUT_ADDcan be set appropriately to prolong the active start signal because otherwise the start
signal activated at the start pin as output only lasts for one clock cycle.
The active polarity of the external start signal can be configured by pol_start_signal. It is valid for both
configurations of the start pin (input or output).
If an external start trigger is not used and the START pin is also not used for communication with an
external device, connect it to GND and select pol_start_signal = 1. Alternatively, connect START toVIO supply
and set pol_start_signal=0. Additionally, choose the value 7 for FILT_L_S and SR_S.
10.1.5 Examples for Ramp Timing
The following three examples depict SPI datagrams, internal and external signal levels, corresponding
velocity ramps, and additional explanations. SPI data is transferred internally at the end of each datagram.
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 31
EXAMPLE 1
Parameter
Setting
Description
RAMPMODE b’101 The velocity value change is executed immediately. The new XTARGET
value is assigned after TARGET_REACHED has been set and START_DELAY
has been expired. A new ramp does not start at the end because there is
no new XTARGET value assigned. START is used as output. The internal
start signal is forwarded with a step length of (START_OUT_ADD+1) clock
cycles. This way, external devices can be synchronized.
start_en
b’001
trigger_events
b’0010
START_DELAY
>0
START_OUT_ADD
>0
pol_start_signal 1
SPI
XTARGET
=2000
VMAX
=2000
v(t)
2000
1000
TARGET_REACHED
VMAX_REACHED
internal start signal
START
internal start timer
t
START_DELAY START_DELAY
START_OUT_ADD START_OUT_ADD
trigger event trigger event
XACTUAL=1800 XACTUAL=2000
Figure 10.1Start example 1
EXAMPLE 2
Parameter
Setting
Description
RAMPMODE
b’001
The velocity value and ramp mode value change will be executed after
the first start signal. Because of the new ramp mode positioning mode
and S-shaped ramps are activated and the ramp stops at target position.
Due to a further target request, the ramp starts again. The active START
output signal lasts only one clock cycle.
start_en b’111
trigger_events
b’0110
START_DELAY
>0
START_OUT_ADD
0
pol_start_signal
0
SPI
v(t)
2000
1000
TARGET_REACHED
VMAX_REACHED
internal start signal
START
internal start timer
t
START_DELAY
trigger event
RAMPMODE
=110
VMAX
=1000
XTARGET
=2000
XTARGET
=2000
trigger event trigger event
VMAX
=2250
START_DELAY
XACTUAL=2000
Figure 10.2Start example 2
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EXAMPLE 3
For this example start signal triggers have been prioritized due to the use of start timing via a
START_DELAY setting and due to the setting immediate_start_in=1.
Parameter
Setting
Description
RAMPMODE b’000 When XACTUAL = POSCOMP the start timer is activated and the external
start signal in between is ignored.
The second start event is triggered due to the external start signal. The
POSCOMP_REACHED event is ignored.
The third start timer process is disrupted by the external START signal
which is forced to be executed immediately due to the setting
immediate_start_in = 1.
start_en
b’010
trigger_events
b’1001
immediate_start_in
0
START_DELAY
>0
pol_start_signal 1
SPI
VMAX
= -1000
v(t)
1000
POSCOMP_REACHED
internal start signal
START
internal start timer
t
START_DELAY
trigger event
XACTUAL=POSCOMP
-1000
VMAX
=1000
START_DELAY
trigger event
VMAX
=250
VMAX
= -250
immediate_start_in
=1
ignored trigger event due
to ongoing start timer
trigger event trigger event
XACTUAL=POSCOMP
ignored trigger event due
to ongoing start timer
Figure 10.3 Startexample 3
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10.2 Target Pipeline
The TMC4361 provides a target pipeline for sequencing subordinatetargets during the drive. This way, a
complex target structure can be easily arranged.
PROCEED AS FOLLOWS:
- Set x_pipeline_en=1.
- Set start_en(0)=1.
- Now, the value in X_PIPE0 becomes transferred to XTARGET at the next internal start signal.
- The complete target pipeline X_PIPE0X_PIPE7becomes shifted forward step by step following the
condition X_PIPEn = X_PIPEn+1.
This flexible target pipeline provides up to eight additional target positions which become transferred at
the next specific start signal. The actually valid target position is written back to X_PIPEx, where x is equal
to the bit position of x_pipe_rewrite_reg. More precisely, if x_pipe_rewrite_reg = b’00010000,
X_PIPE4 = XACTUAL at the next internal start signal. If x_pipe_rewrite_reg = b’00000000, XTARGET will not
written back to any X_PIPEn register. If multiple bits are set, XTARGET will written back to each of the
selected X_PIPEn registers.
37
38
39 X_PIPE1
3A X_PIPE2
3BX_PIPE3
3C X_PIPE4
3D X_PIPE5
3E X_PIPE6
3FX_PIPE7
XTARGET
X_PIPE0
x_pipe_rewrite_reg(0)='1'
XX XXXX
Register
address
Register name
Caption
x_pipeline_en=1
x_pipeline_en=1
x_pipe_rewrite_reg0
x_pipe_rewrite_reg(1)='1'
x_pipe_rewrite_reg(2)='1'
x_pipe_rewrite_reg(3)='1'
x_pipe_rewrite_reg(4)='1'
x_pipe_rewrite_reg(5)='1'
x_pipe_rewrite_reg(6)='1'
x_pipe_rewrite_reg(7)='1'
Figure 10.4 Flexible target pipeline
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11 Serial Data Output
The TMC4361 provides an SPI interface for initialization and configuration of the motor driver (additional
to the Step/Dir output) before and during motor motion. Furthermore, it is possible to control TRINIAMIC
stepper drivers during SPI motor drive.The SPI interface is used for principal tasks:
- Two current values of the integrated sine wave look-up table can be transferred at a time to the
driver chip in order to energize the motor coils. This is done within each SPI datagram. A series of
current values is transferred to move the motor. Values of the MSLUT (microstep sine wave look-up
table) are adjusted using velocity ramp dependent scale values. This way, maximum amplitude
current values are aligned to the requirements of certain velocity slopes.
- The TMC4361 integrates an adjustable cover register for configuration purposes. This way, TRINIAMIC
motor driver chips and third parties chips can be adjusted with only little effort.
PINS AND REGISTERS: SPI TO MOTOR DRIVER
Pin names Type Remarks
NSCSDRV_SDO
Output
Chip select output to motor driver, low active
SCKDRV_NSDO Output Serial clock output to motor driver
SDODRV_SCLK
InOut as Output
Serial data output to motor driver
SDIDRV_NSCLK
Input
Serial data input from motor driver
STDBY_CLK
Output
Clock output, standby output, or ChopSync clockoutput
Register name
Register address
Remarks
GENERAL_CONF 0x00 RW Bit14 : 13, bit19, bit20
REFERENCE_CONF
0x01
RW
Bit26, bit27
SPIOUT_CONF
0x04
RW
Configuration register for SPI output communication
CURRENT_CONF
0x05
RW
Current scaling configuration
SCALE_VALUES 0x06 RW Current scaling values
STEP_CONF 0x0A RW Microsteps/fullstep,fullstep/revolution, and
motor status bit event selection
STDBY_DELAY 0x15 RW Delay time after standby mode is valid
FREEWHEEL_DELAY
0x16
RW
Delay time after freewheeling is valid
VDRV_SCALE_LIMIT
0x17
RW
Velocity setting for changing the drive scale value
UP_SCALE_DELAY
0x18
RW
Increment delay to a higher scaling value; 24 bit
HOLD_SCALE_DELAY
0x19
RW
Decrement delay to the hold scaling value; 24 bit
DRV_SCALE_DELAY 0x1A RW Decrement delay to the drive scaling value
BOOST_TIME 0x1B RW Delay time after ramp start when boost scaling is valid
DAC_ADDR 0x1D RW
SPI addresses/commands which areput in frontof
the DAC
values: Coil A: DAC_ADDR (bit 15 : 0)
Coil B: DAC_ADDR (bit 31 : 16)
CHOPSYNC_DIV 0x1F RW Chopper clock divider (bit 11 : 0)
FS_VEL 0x60 W Velocity at which fullstep drive will be enabled
COVER_LOW
0x6C
W
Lower 32 bit of the cover register (µC to motor driver)
COVER_HIGH
0x6D
W
Upper 32 bit of the cover register (µC to motor driver)
COVER_DRV_LOW
0x6E
R
Lower 32 bit of the cover register (motor driver to µC)
COVER_DRV_HIGH 0x6F R Upper 32 bit of the cover register (motor driver to µC)
MSLUT[0…7] 0x70…77
W Difference values between two consecutive MSLUT values
MSLUTSEL
0x78
W
Definition of segments within each MSLUT quarter wave
Register name
Register address
Remarks
MSCNT
0x79
R
Current microstep position of the MSLUT
CURRENTA
CURRENTB 0x7A R Actual current values of the MSLUT:
SIN (coil A) and SIN90_120 (coilB); each 9 bit
CURRENTA_SPI
CURRENTB_SPI
0x7B R
Actual scaled current values of the MSLUT:
SIN (coil A) and SIN90_120 (coilB); each 9 bit
SCALE_PARAM
0x7C
R
Actual scaling parameter; 8 bit
START_SIN
START_SIN90_120
DAC_OFFSET
0x7E RW
Sine start value of the MSLUT (bit 7 : 0)
Cosine start value of the MSLUT (bit 23 : 16)
Offset value for DAC output values (bit 31 : 24)
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 35
Note
For a good start with a TRINAMIC motor driver, setup SPIOUT_CONF register properly. Thus, the TMC4361
offers presets for current transfer and automatic configuration routines if the correct driver is selected.
Status bits of TMC motor drivers are transmitted to the status register of the motion controller.
11.1 Sine Wave Look-up Table
TMC4361 provides a programmable look-up table for storing the microstep current wave. As a default, the
tables are pre-programmed with a sine wave, which is a good starting point for most stepper motors.
Reprogramming the table to a motor specific wave allows drastically improved microstepping especially
with low-cost motors. In order to minimize required memory and the amount of data to be programmed,
only a quarter of the wave becomes stored. The internal microstep table maps the microstep wave from
0° to 90°. It becomes symmetrically extended to 360°. When reading out the table the 10-bit microstep
counter MSCNT addresses the fully extended wave table. The table is stored in an incremental fashion,
using each one bit per entry. Therefore only 256 bits (ofs00 to ofs255) are required to store the quarter
wave. These bits are mapped to eight 32 bit registers.
Each ofs bit controls the addition of an inclination Wx or Wx+1 when advancing one step in the table. As
the wave can have a higher inclination than 1, the base inclinations Wx can be programmed to -1, 0, 1,
or 2 using up to four flexible programmable segments within the quarter wave. This way, even a negative
inclination can be realized. The four inclination segments are controlled by the position registers X1 to
X3.
When modifying the wave, care must be taken to ensure a smooth and symmetrical zero transition when
the quarter wave becomes expanded to a full wave. The maximum resulting swing of the wave should
be adjusted to a range of -248 to 248, in order to give the best possible resolution while leaving headroom
for the hysteresis based chopper to add an offset.
MSCNT
y
256
256
248
-248
512 768 0
0X1 X3X2
W0: +2/+3
W1: +1/+2
W2: +0/+1
W3: -1/+0
LUT stores
entries 0 to 255
255
START_SIN
START_SIN90_120
Figure 11.1 LUT programming example
When the microstep sequencer advances within the table, it calculates the actual current values for the
motor coils with each microstep and stores them to the registers CURRENTA and CURRENTB. However the
incremental coding requires an absolute initialization, especially when the microstep table becomes
modified. Therefore, CURRENTA and CURRENTB become initialized whenever MSCNT passes zero.
TWO REGISTERS CONTROL THE STARTING VALUES OF THE TABLES:
- As the starting value at zero is not necessarily 0 (it might be 1 or 2), it can be programmed into the
starting point register START_SIN.
- In the same way, the start of the second wave for the second motor coil needs to be stored in
START_SIN90_120. This register stores the resulting table entry for a phase shift of 90° for 2-phase
stepper motors.
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 36
11.1.1 Programming the Incremental Microstep Table
For understanding the background of the incremental coding of the microstep table, it is good to have
an idea of the characteristics of the microstep wave.
A MICROSTEP TABLE FOR A TWO PHASE MOTOR HAS CERTAIN CHARACTERISTICS:
1. It is in principle a reverse characteristic of the motor pole behavior.
2. It is a smoothened wave to provide a smooth motor behavior. There are no jumps within the
wave.
3. The phase shift between both phases is exactly 90°, because this is the optimum angle of the
poles within the motor.
4. The zero transition is at 0°. The curve is symmetrical within each quadrant (like a sine wave).
5. The slope of the wave is normally positive, but due to torque variations it can also be (slightly)
negative.
6. But it must not be strictly monotonic as the example in the previous chapter shows.
Considering these facts, it becomes clear that the wave table can be compressed. The incremental coding
used in the TMC4361 uses a format which reduces the required information per entry of the 8 bit by 256
entry wave table to slightly more than a single bit.
INCREMENTAL ENCODING
The principle of incremental encoding just stores the difference between the actual and the next table
entry. To have an absolute start value, the first entry is directly stored (START_SIN). For the ease of use,
also the first entry of the shifted table for the second motor phase is stored (START_SIN_90_120).
The TMC4361 provides four inclination segments (0, 1, 2, and 3) with the base inclinations (W0, W1, W2,
and W3) and the segment borders (0, X1, X2, X3, and 255).
Inclination segment Base inclination Segments
0
W0
0… X1
1 W1 X1… X2
2 W2 X2… X3
3
W3
X3… 255
Table 11.1 Inclination segments of TMC4361
EXPLANATORY NOTES AND EXAMPLES
Using a single bit per table entry allows any inclination between 0 and 1. E.g., a 0-bit can mean do not
add anything and a 1-bit can mean add one. This allows describing a digital slope of 0° (all bits zero) to
45° (all bits one).
It becomes clear, that higher inclinations are necessary. However, the inclination will not drastically
change from point to point. Therefore, the wave can be divided into up to four segments with different
base inclinations.
Using a base inclination of one, a 0-bit means add one and a 1-bit means add two. This way, a slope
between 45° (all bits zero) and 77.5° is yielded (all bits one).
The base inclinations can be set between -1 (falling slope) and +2. This way, slopes between -45° and
78.75° can be described.
The default sine wave table in TRINAMIC drivers uses one segment with a base inclination of 1 and one
segment with a base inclination of 0.
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 37
y
256
0
+2/+3
+1/+2
+0/+1
-1/+0
255
X1 X2 X3
Segment upper limits
Segment lower limits
0
Segment
inclination W
Figure 11.2 Wave showing segments with all possible base inclinations (highest inclination first)
EXAMPLE
CONSIDER THE GIVEN CONDITIONS:
The microstep table for the standard sine wave begins with the eight entries (0 to 7) {0, 1, 3, 4, 6,
7, 9, 10 …} etc.
The maximum inclination in this area is 2 (1+2=3).
The minimum inclination in these eight entries is 1.
The start value is 0.
Advancing in the table, the first time the inclination becomes lower than +1 is from position 153 to
position 154. Both entries are identical.
The calculated value for position 256 (start of cosine wave) is 247.
THEREFORE, THE FOLLOWING SETTINGS NEED TO BE MADE:
- Set a starting value START_SIN=0 matching sine wave entry 0.
- Set a base inclination range of W0: +1 / +2 (W0=%10), valid from 0 to X1.
- Calculate the differences between each two entries: {+1, +2, +1, +2, +1, +2, +1,…}
- Set the microstep table entries ofsxx to 0 for the lower value (+1), 1 for the higher value (+2).
Thus, the first seven microstep table entries ofs00 to ofs06 are: {0, 1, 0, 1, 0, 1, 0 …}
- Latest at position 153, the inclination must be lowered. Use the next inclination range 1 with
W1: +0 / +1 (W1=%01). Therefore, X1 becomes set to 153 in order to switch to the next inclination
range. Thus, starting from position 153, an offset ofsxx of 0 means add nothing, 1 means add
+1.
- START_SIN90_120 becomes equal to the value at position 256, i.e. 247.
- As the wave does not more have segments with different inclinations, the remaining inclination
ranges W2 and W3 shall be set to the same value as W1, and X2 and X3 can be set to 255. This
way, only two inclination segments are effective.
OVERVIEW OF EXAMPLE
Microstep number 0 1 2 3 4 5 6 7 153 154
Desired table entry
0 1 3 4 6 7 9 10 200 200
Difference to next entry
1
2
1
2
1
2
1
0
Required segment inclination
+1
+1
+1
+1
+1
+1
+1
+0
Offs bit entry
0
1
0
1
0
1
0
0
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 38
11.2 SPI Output Parameters
The TMC4361 provides SPI output parameters to adjust a proper communication with the motor driver.
Set serial_enc_out_enable=0 to enable the SPI output communication. The TMC4361 generates the
necessary SPI output clock frequency and forwards it to the SCKDRV_NSDO output pin. The low phase of
the serial clock is set with SPI_OUT_LOW_TIME, whereas SPI_OUT_HIGH_TIME sets the high phase.
Additionally, an SPI_OUT_BLOCK_TIME can be set for a minimum time period where no new datagram
will be sent after the last SPI output datagram. During this inactive phase SCKDRV_NSDO stays high. All
three SPI output parameters are part of the SPIOUT_CONF register. They are 4 bit values and represent a
number of clock cycles.
PINS WHICH ARE ALSO AFFECTED BY SPI OUTPUT COMMUNICATION
NSCSDRV_SDO low active chip select signal
SDODRV_SCLK used as output to transfer the datagram to the motor driver
SDIDRV_NSCLK receives the response from the motor driver. The response is sampled duringthe data
transfer to the motor driver.
MINIMUM AND MAXIMUM TIME PERIOD
Theminimum time period for all three parameters is 1/fCLK. If an SPI output parameter is set to 0 it
becomes altered to 2 clock cycles internally. A maximum time period of 15/fCLK can be set for all three
parameters.
Thus, SPI clock frequency fSPI_CLKcovers the following range: fCLK/30 fSPI_CLK fCLK/2. The timing of the SPI
output communication is illustrated in Figure 11.3.
NSCSDRV_SCLK
SCKDRV_NSDO
SDODRV_SCLK
SDIDRV_NSCLK
bit
CDL-1
bit
CDL-2
bit
0
bit39 bit38 bit0
spi_out_low_time / fCLK
spi_out_block_time / fCLK
spi_out_high_time / fCLK
sample points
Figure 11.3 SPI output datagram timing (CDL cover_data_length)
COVER_DONE
At the end of a successful data transmission, the event COVER_DONE becomes set. This indicates that the
cover register data have been sent to the motor driver and that received responses have been stored in
the registers COVER_DRV_HIGH and COVER_DRV_LOW. COVER_DRV-HIGH and COVER_DRV-LOW form the
cover response register.
The event COVER_DONE becomes also set after a successful current datagram transmission.
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 39
64 BIT SPI COVER REGISTERS FOR COMMUNICATION BETWEEN µC AND DRIVER
The 64 bit SPI cover register is separated into two 32 bit registers (COVER_HIGH and COVER_LOW). Using
the cover register, an additional SPI communication channel between microcontroller and motor driver
is not needed. The total length of the cover register can be set by COVER_DATA_LENGTH. If this parameter
is set higher than 64, the cover register data length is still 64 bits at its maximum. The LSB (last significant
bit) of the whole cover register is located at COVER_LOW(0). Thus, if less than 33 bits are required for SPI
communication, only COVER_LOWrespectively a part of it becomes transmitted (in accordance
toCOVER_DATA_LENGTH). The cover register and the datagram structure are illustrated in Figure 11.4.
Every SPI communication starts with the most significant bit (MSB):
- MSBisCOVER_LOW(COVER_DATA_LENGTH - 1) if COVER_DATA_LENGTH < 33.
- MSB isCOVER_HIGH(COVER_DATA_LENGTH - 33) if COVER_DATA_LENGTH 33.
Note
Similar to COVER_LOW and COVER_HIGH, the motor driver response is divided in the registers
COVER_DRV_LOW and COVER_DRV_HIGH. The composition of the response cover register and the
positioning of the MSB follow the same structure.
bit
63
bit
62
bit
33
bit
32
...
bit
31
bit
30
bit
1
bit
0
...
bit
31
bit
30
bit
1
bit
0
...
COVER_HIGH
COVER_LOW
Cover register bit
31
bit
30
bit
1
bit
0
...
MSB if CDL=63 MSB if CDL=30
(COVER_HIGH not
required)
Figure 11.4 Cover data register composition (CDL cover_data_length)
11.3 Current Datagrams
TMC4361 uses the introduced internal microstep look-up table (MSLUT) for providing current data for the
motor driver. With every step initialized by the ramp generator the MSCNT value becomes increased or
decreased, dependent on the ramp direction. The MSCNT register contains the current microstep position
of the sine value. Accordingly, the current values CURRENTA and CURRENTB are altered.
In case the output configuration of the TMC4361 allows for automatic current transfer an updated current
value leads to a new datagram transfer. This way, the motor driver always receives the latest data. The
length for current datagrams becomes automatically set and the TMC4361 converts new values into the
selected datagram format, usually divided in amplitude and polarity bit for TMC motor drivers.
Note that the TMC23x and TMC24x only forward new current data if the upper five bits of one of the two
9 bit current values have changed. This is because TMC23x and TMC24x current data consist of four bit
current values and one polarity bit for each coil. Further on, TMC23x and TMC24x current datagrams
forward mixed decay bits. These bits can be set with mixed_decay which is part of the SPIOUT_CONF
register. Please refer to the TMC23x/TMC24x datasheets to get more information about setting mixed decay
bits correctly.
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 40
11.4 TMC Motor Driver
For connecting a TMC stepper motor driver proceed as follows:
The TMC4361 is able to set the cover register length automatically.Therefore, set COVER_DATA_LENGTH = 0.
Now, the cover register length is set according to the chosen spi_output_format setting.
spi_output_formatis the essential parameter for choosing predefined SPI default settings for theparticular
TMC motor driver.
COVER_DATA_LENGTH and spi_output_format are part of the SPIOUT_CONF register.
TMC STEPPER MOTOR DRIVER AND SETTINGS
TMC motor driver spi_output_format
3 : 0
Automatic current
datagram transfer
Cover register length
COVER_DATA_LENGH=0
TMC23x b’1000 12
TMC24x b’1001 12
TMC26x/389
SPI output for conf. only
b’1010
b’1011
-
20
20
TMC21xx
SPI output for conf. only
b’1101
b’1100
-
40
40
11.4.1 Switching from µSteps to Fullsteps
TMC4361 provides switching to fullstep mode if the absolute velocity value VACTUAL exceeds the
parameter FS_VEL, which is the minimum fullstep velocity. In case, e.g., the Step/Dir output is used,
switching from microsteps to fullstepscan lead to a step rate which is 256 times lower than before,
assumed that the highest microstep resolution is set. To indicate this microstep resolution change to the
microcontroller, the event FS_ACTIVE becomes released and thus the microcontroller can adapt the motor
driver configuration properly.
For enabling fullstep drive set fs_en=1.
TMC260, TMC261, TMC262, TMC2660, TMC389: AUTOMATIC SWITCHOVER TO FULLSTEPS
These advanced motor driver chips offer two interfaces for communication with the motion controller:
SPI and Step/Dir. The TMC4361 provides related data for both interfaces concurrently. Decreasing the
microstep resolution during a velocity ramp has to be done very carefully. For the ease of use, the
TMC4361 provides configuring TMC motor drivers automatically.
SPI OUTPUT USED FOR CONFIGURATION AND CURRENT DATAGRAMS
For this configuration set spi_output_format = b’1010.
Now, current values become switched to fullstep values if |VACTUAL| > FS_VEL, the internal microstep
position of the TMC4361 suits, and fs_en = 1 has been set before. Consistently, a switchback from fullsteps
to microsteps becomes executed if |VACTUAL| < FS_VEL.
STEP/DIR INTERFACE USED FOR MOVING THE MOTOR /SPI OUTPUT ONLY USED FOR CONFIGURATION
For this configuration set spi_output_format = b’1011, fs_en = 1, and fs_sdout = 0. Note that fs_sdout is
only to be used if a motor driver does not provide switching between fullsteps and microsteps
automatically.
A continuous polling for SPI datagrams is necessary to get status data from the drivers. Therefore, set
disable_polling = 0. By setting POLL_BLOCK_MULT properly, the time between two consecutive polling
datagrams becomes extended to (POLL_BLOCK_TIME + 1)• SPI_OUT_BLOCK_TIME / fCLK. A high fullstep
frequency requires a short SPI datagram polling time.
Beware the fullstep switch for the TMC26x and TMC389 requires a correct assignment of the read selection
bits in the driver registers. If these bits are not set to 00 the transition to fullsteps cannot not be executed
due to the fact that the TMC4361 does not receive any microstep data from the driver. If fullstep drive is
requested and |VACTUAL| > FS_VEL, the motor driver is polled to recognize the correct point in time to
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 41
switch to full steps. This moment becomes reached when the microstep position of the motor driver
equals a fullstep position. The same operation is carried out if fullstep drive has to be switched back to
microstep drive.
TMC21XX: MANUAL SWITCHOVER TO FULLSTEPS
These powerful motor driver chips offers two interfaces for communication with the motion controller:
SPI and Step/Dir. Therefore, the TMC4361 provides related data for both.
SPI OUTPUT USED FOR CONFIGURATION AND CURRENT DATAGRAMS
For this configuration set spi_output_format = b’1101.
Now, current values become switched to fullstep values if |VACTUAL| > FS_VEL, the internal microstep
position of the TMC4361 suits, and fs_en = 1 has been set first. Consistently, a switchback from fullsteps
to microsteps becomes executed in case |VACTUAL| < FS_VEL.
STEP/DIR INTERFACE USED FOR MOVING THE MOTOR /SPI OUTPUT ONLY USED FOR CONFIGURATION
Note that automatic switching from microsteps to fullsteps and back is not supported for TMC21xx drivers.
For switching the microstep resolution manually to fullsteps, check if the motor position fits and set
spi_output_format = b’1100, fs_en = 1, fs_sdout = 1, and disable_polling = 1 afterwards. A point in time
for switching over between microsteps and fullsteps is reached as soon as the microstep position suits
to a fullstep position.
Another possibility is to change the microstep resolution using the STEP_CONF register.
TMC23X AND TMC24X: AUTOMATIC SWITCHOVER TO FULLSTEPS
Setspi_output_format = b’1000for TMC23x or spi_output_format = b’1001 for TMC24x motor drivers.Now,
current values become switched to fullstep values if |VACTUAL| > FS_VEL, the internal microstep position
of the TMC4361 suits, and fs_en = 1 has been set before. Consistently, a switchback from fullsteps to
microsteps becomes executed in case |VACTUAL| < FS_VEL.
CHANGING THE MICROSTEP RESOLUTION
By altering the microstep resolution from 256 (MSTEP_PER_FS = b’0000) to a lower value, an internal step
results in more than one MSLUT step. If, e.g., the microstep resolution is set to 64 (MSTEP_PER_FS = b‘0010),
the MSCNT becomes in-/decreased by 4 for one internal step. Accordingly, the passage through the MSLUT
skips three current values for each internal step to match the new microstep resolution.
11.4.2 How to Use the Current Scale Parameter via SPI Output
Further automatic driver configuration for spi_output_format = b’1100 and spi_output_format = b’1011 can
be used by setting scale_val_transfer_en = 1. Using this feature, the current scale parameter SCALE_PARAM
is sent via SPI output to the motor driver. Pre-settings (made before via cover datagrams)become
considered if the particular registers become overwritten with the new scaling value or with the new
microstep resolution. The configuration of automatic scaling will be explained in chapter 11.6.
11.4.3 Configuration for the TMC389 3-Phase Stepper Driver
If a TMC389 is connected to the SPI output and a microstep resolution of 256 is set, a three phase stepper
output for coil B can be generated. Therefore, set three_phase_stepper_en = 1. Now, the CURRENTB and
CURRENTB_SPI values are shifted for 120° (instead of 90° for 2-phase stepper motors).
11.4.4 ChopSync™Configuration for TMC23x/TMC24x Stepper Drivers
- Set stdby_clk_pin_assignment = b’10 to forward the internal clock to the STDBY_CLK output pin.
- Connect the clock signal to the OSC input of the stepper driver. (This input is used as PWM clock
input.) Now, the chopSync feature can be used for a fast and smooth drive.
- The clock frequency of the PWM is assigned by setting CHOPSYNC_DIV. The internal clock of TMC4361
is divided by this parameter to assign the PWM frequency fOSC = fCLK / CHOPSYNC_DIV with
96 CHOPSYNC_DIV 818.
- If stdby_clk_pin_assignment = b’11 is set the internal clock is forwarded via STDBY_CLK and the
chopSyncfeature is not available.
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 42
11.4.5 Motor Driver Status Bits and Stall Detection
When a TMC motor driver receives a current datagram (transmitted via the SPI output of the TMC4361)
status data is sent back to the TMC4361 controller immediately. These responses from the driver are
stored in the cover response register which consists of COVER_DRV_LOW and if
necessaryCOVER_DRV_HIGH. Additionally, motor driver status bits are forwarded to the STATUS register.
Refer to chapter 17 for detailed information about status bits of TMC motor driver chips.
EVENTS AND INTERRUPTS BASED ON MOTOR DRIVER STATUS BITS
- The STEP_CONF(23 : 16) register can be set in a way that selected motor driver status bits release an
event if a status bit becomes active.
- For generating an interrupt the motor driver event EVENTS(31) can be configured as interrupt source.
STALL DETECTION HANDLING
- TMC motor driver chips always return the stall detection status to the TMC4361 motion controller in
response to every received SPI datagram. In most cases, one bit indicates that a motor stall occurred.
- If stop_on_stall = 1 is set, an active stall status is handled as a stop event with a hard stop.
- The subsequently releasedstop_on_stall event immediately stops the currently valid velocity ramp.
- For starting a new velocity ramp setdrv_after_stall = 1. Now, the stop_on_stall event becomes reset.
- The drv_after_stall switch has to be set back manually.
TMC26XX, TMC21XX, AND TMC389
Motor driver status bits as response from current datagramsare received automatically if
disable_polling = 0 during step direction mode. One stall detection status bit is returned to the
microcontroller inresponse to every received SPI datagram.
TMC24X STALLGUARD CHARACTERISTICS
The TMC24x forwards stallGuard values (=LD2&LD1&LD0) instead of one stallGuard status bit. These bits
represent an unsigned value between 0 and 7. The lower the value the higher is the mechanical load. By
setting STALL_LOAD_LIMIT properly, a stall is indicated when (LD2&LD1&LD0) STALL_LOAD_LIMIT which
results in a hard stop if stop_on_stall = 1.
Setstall_flag_instead_of_uv_en = 1 toreplace the undervoltage status bit in the STATUS register with the
stall status of TMC24x drivers.
A standby datagram is sent to the TMC24x stepper driver if stdby_on_stall_for_24x = 1 and a stop_on_stall
event occurs. This datagram sets current values to 0 which results in a power down of the TMC24x motor
driver.
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 43
11.5 Other Driver Chips
The TMC4361 provides also configuration data for driver chips of other companies via the cover registers.
Please note that the COVER_DATA_LENGTH has to be set properly. Furthermore, it is possible to support
automatic current data transfer. The following format settings can be chosen:
Output formats spi_output_format Automatic current
datagram transfer
Automatic cover register length
(if COVER_DATA_LENGH=0)
SPI output off b’0000 - 1
Signed current data b’0101
1
Unsigned scaling factor b’0100 - 1
DAC scaling factor b’0110 - 1
DAC absolute values b’0010 / b’0011
1
DAC adapted values b’0001
1
COMMENTS ON THE TABLE
- spi_output_format = b’0000 switches off the SPI output.
- spi_output_format = b’0101 leads to a transfer of both signed current values one after the other in
an 18 bit datagram.
- With spi_output_format = b’0100, the 8 bit scaling factor is transmitted if it has been altered. This
scaling data could also be transmitted for a DAC by setting spi_output_format = b’0110, assumed
that the SPI capabilities of the DAC fit.
- spi_output_format = b’0010 converts the current values for the SPI capable DAC into absolute values.
The current phases of both coils are forwarded via the STPOUT (coilA) and DIROUT (coilB) outputs. A
phase bit polarity of 0 indicates a positive value.
- spi_output_format = b’0011 converts the current values for the SPI capable DAC into absolute values.
The current phases of both coils are forwarded via the STPOUT (coilA) and DIROUT (coilB) outputs. A
phase bit polarity of 0 indicates a negative value.
- With spi_output_format = b’0001 the currents are mapped to an unsigned value. Therefore, a value
of 256 is added to the signed current values. Thus, the current value 0 results in a 9 bit value of
b’10000000 whereas the minimum value of -256 is exported as b’000000000 and the maximum value
of 255 as b’111111111.
- Additionallyfs_sdout can be set to 1 in case switching from microsteps to fullsteps and back is
desired.
DAC VALUE OFFSET AND LENGTH OF DATAGRAM
- An offset can be added for the values of both coils by setting DAC_OFFSET to compensate for a
shifted base line, except in case spi_output_format = b’0001.
- Usually, SPI transfers require an address or a command in front of a transmitted value. The length
of the prefixed command or address can be assigned by setting DAC_CMD_LENGTH.
- The bit stream which constitutes the command or address can be stored in the DAC_ADDR register
with 16 bits for both coils separately.Due to the transfer of only one value per datagram, two
datagrams are sent in a row: first the coilA command and value are sent and afterwards the coilB
command and value.If the cover register length comprises more bits than the combination of
command and value, zeros are added at the end.This is because the cover register length determines
the length of the datagram for DAC values. Note that the command bits consist of the least significant
bits of DAC_ADDR if the command length is less than 16 bit.
CHANGING SPI OUTPUT TRANSFER CONDITIONS
Sometimes, other SPI output transfer conditions are required. Therefore, further configuration is possible:
- By setting sck_low_before_csn = 1, SCKDRV_NSDO is tied low before NSCSDRV_SDO.(Per default
setting, SCKDRV_NSDO is tied high.)
- Further on, TMC drivers sample the master data with the rising edge of the master clock. Thus,
TMC4361 shifts the output data at SDODRV_SCLK with the falling edge of SCKDRV_NSDO. In case the
data is sampled with the falling edge of the master clock at the driver’s side, the data at
SDODRV_SCLK has to be shifted with the rising edge of SCKDRV_NSDO.Therefore,
setnew_out_bit_at_rise = 1
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Current value calculation for SP1 outgul:
TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 44
11.6 Current Scaling & Ramp Status
Variouspossibilities have been implemented to adapt the actual current values of the internal microstep
look-up table MSLUT to the current ramp status.
Multiplication Actual current values are multiplied with the MULT_SCALE parameter, which
is deduced from the SCALE_PARAMregister:
MULT_SCALE = (actual_SCALE_VAL + 1) / 256
with 0 < MULT_SCALE 1 and actual = {HOLD, BOOST, DRV1, DRV2}.
The actual MULT_SCALE parameter is provided via the SCALE_PARAM
register value which is calculated by the following expression:
SCALE_PARAM = MULT_SCALE 256 - 1.
Current value calculation for SPI output:
CURRENTA_SPI = CURRENTA MULT_SCALECURRENTB_SPI = CURRENTB MU
LT_SCALE
Eight bit scale parameters The actual values CURRENTA and CURRENTBcan be scaled down with bit
scale parameters. The names of these parameters end with_SCALE_VAL.
They are part of the SCALE_VALUES register.
Scale parameters are available for boost current (BOOST_SCALE_VAL), hold current (HOLD_SCALE_VAL), and
drive current (DRV1_SCALE_VAL and DRV2_SCALE_VAL). These parameters can be assigned
independently.Several different scaling types are provided:
For scaling the current values during standstill two settings are available:
STANDBY SCALING
- Set HOLD_CURRENT_SCALE_EN = 1.
- TheSTDBY_DELAY timeris started as soon asVACTUAL reaches 0.
- In casethe standby timer expires and VACTUAL is still 0, standby mode is valid and currents are
scaled down usingHOLD_SCALE_VAL now.
- In caseSTDBY_DELAY is set to 0 standby mode isvalid immediately after reaching VACTUAL=0.
Note: if stdby_clk_pin_assignment(1) = 0, the STDBY_CLK output pin forwards the standby signal with
active polarity which is equal to the setting stdby_clk_pin_assignment(0).
SCALINGFOR FREEWHEELING
- For freewheeling set freewheling_en = 1.
- As soon as standby mode is reached, theFREEWHEEL_DELAY timeris started.It expires while standby
mode remains active.
- When FREEWHEEL_DELAY is elapsed,freewheeling modebecomes enabled and thus all current values
are altered to 0.
- In case FREEWHEEL_DELAY is set to 0, freewheeling mode becomes valid immediately after reaching
standby mode.
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 45
It is also possible to manipulate standard current values during the ramp:
BOOST SCALING AT RAMP START
- Setboost_current_after_start_en = 1for scaling current values with BOOST_SCALE_VAL.
- Boost scaling at ramp start begins with the onset of a velocity ramp, assumed that VACTUAL has
been set to 0 before.
- At the ramp start the BOOST_TIME(value represents a number of clock cycles) becomes initialized.
When this timer expires, boost scaling after start is finished.
BOOST SCALING ON ACCELERATION RAMPS
- If RAMP_STATE = b’01 and boost_current_on_acc_en = 1 are set, actual current values are scaled with
BOOST_SCALE_VAL.
- RAMP_STATE = b’01 is always valid when the absolute velocity value increases.
BOOST SCALING ON DECELERATION RAMPS
- If RAMP_STATE = b’10 and boost_current_on_dec_en = 1 are set, the actual current values are scaled
with BOOST_SCALE_VAL.
- RAMP_STATE = b’10 is always valid when the absolute velocity value decreases.
DRIVE SCALING
- If drive_current_scale_en is set to 1, current values are scaled with DRV1_SCALE_VAL, assumed that
no other scaling mode is active at that moment.
- In casesec_drive_current_scale_en = 1 is chosen additionally, DRV1_SCALE_VALis only used if the
condition VACTUAL VDRV_SCALE_LIMITis met.
- If sec_drive_current_scale_en = 1,drive_current_scale_en = 1, and VACTUAL > VDRV_SCALE_LIMIT are
valid, current values are scaled with DRV2_SCALE_VAL, assumed that no other scaling mode is active.
Setup of scaling values for Step/Dir operation with TMC21xx, TMX26xx, or TMC389
Scaling values are transmitted directly to the driver in case Step/Dir output modeand
scale_val_transfer_en = 1 is valid. Please note that the maximum scale value is 31 due to the fact that
scale values are stored as 5 bit numbers. Thus, only the last 5 bits of the eight bit scaling registers are
transferred in Step/Dir output mode. Furthermore, MULT_SCALE is calculated at the driver devices using
the following equation: MULT_SCALE = (actual_SCALE_VAL + 1) / 32
Controlling the transition process from one scale mode to another
The transition from one scale value to the nextcan be configured and has not to be abruptly. Three
parameters are available for controlling the progression:
UP_SCALE_DELAY
Set the period of clock cycles during which a current scale value is increased by one step towards the
higher target scale value with UP_SCALE_DELAY.
HOLD_SCALE_DELAY
Set the period of clock cycles during which a current scale value is decreased by one step towards the
lower target scale value HOLD_SCALE_VAL with HOLD_SCALE_DELAY.
DRV_SCALE_DELAY
DRV_SCALE_DELAY is the time period that is required to decrease the actual scale value towards a scale
value which is smaller than the current one.
Setting any of these parameters to 0 will result in an immediate transition to the next scale value for
the introduced conditions.
The following two examples illustratehow scaling modes are to be used.
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; ?/ r 7‘ WI f W 7
TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 46
EXAMPLE 1
Standby scaling, freewheeling, boost scaling at start, boost scaling on deceleration ramps, and drive
scaling I are enabled.Current scale parameters (SCALE_PARAM) are shown as well as their related scale
timers in clock cycles. The timers are used to finish boost scaling after start and to start standby scaling
and freewheeling. The three depicted delay values are calculated as follow:
tDN_SCALE = (BOOST_SCALE_VAL - DRV1_SCALE_VAL) DRV_SCALE_DELAY
tUP_SCALE = (BOOST_SCALE_VAL - DRV1_SCALE_VAL) UP_SCALE_DELAY
tHOLD_SCALE = (DRV1_SCALE_VAL - HOLD_SCALE_VAL) HOLD_SCALE_DELAY
Figure 11.5Scaling: example 1
EXAMPLE 2
Boost scaling on acceleration ramps and both drive scaling modes are enabled. As long as
VACTUAL < VDRV_SCALE_LIMIT, drive scaling I is active. Both drive scaling modes are usedfor the
deceleration ramp due to boost_current_on_dec = 0. When VACTUAL reaches 0, the RAMP_STATUS switches
to acceleration ramp and boost scaling becomesenableda second time.
Figure 11.6 Scaling: example 2
v(t)
t
t
SCALE_PARAM
Boost scaling
Drv1 scaling
StdBy scaling
Freewheeling
t
scale timer [clk cycles]
BOOST_SCALE_VAL
DRV1_SCALE_VAL
HOLD_SCALE_VAL
STDBY_DELAY
FREEWHEEL_DELAY
BOOST_TIME
tDN_SCALE tUP_SCALE tDN_SCALE
tHOLD_SCALE
v(t)
t
t
SCALE_PARAM
VDRV_SCALE_LIMIT
-VDRV_SCALE_LIMIT
Boost scaling
Drv1 scaling
Drv2 scaling
BOOST_SCALE_VAL
DRV1_SCALE_VAL
DRV2_SCALE_VAL
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 47
12 NFREEZE: Emergency-Stop
In case of dysfunctions at board level, some applications requirean additional strategy to end current
operations without any delay. Therefore, the TMC4361 provides thelow active safety pin NFREEZE.
PINS AND REGISTERS: FREEZE FUNCTIONALITY
Pin names Type Remarks
NFREEZE
Input
External enable pin; low active
Register name
Register address
Remarks
DFREEZE
0x4E
(23 : 0)
RW
Deceleration value in the case of an active FREEZE event
IFREEZE
0x4E
(31 : 24)
RW
Current scaling value in the case of an active FREEZE
event
NFREEZE is low active. An active NFREEZE input transition from high to low level stops the current ramp
immediately in a user configured way. At the momentwhen NFREEZE switches to low, an event (FREEZED)
is triggered at EVENTS(10). FREEZED remains active until the reset of the TMC4361.
Due to an input filter of three consecutive sample points it is necessary to tie NFREEZE low for at least
three clock cycles.
12.1 Freeze Function Configuration
Two parameters (DFREEZE and IFREEZE) are necessary forusing the TMC4361 freeze function. They are
integratedin the freezeregisterwhichcan be written only once after an active reset, assumed that there
has been no ramp started before. Thus, the freeze parameters should be set directly in the beginning of
operation. Note that the chosen values cannot be altered until the next active reset.
These restrictions are necessary to protect the TMC4361freeze configuration from incorrect SPI data sent
from the microcontroller in case of error.
Note
The polarity of the NFREEZE input cannot be assigned.
The freeze register canalways be read out.
During freeze state ramp register values can be read out.
CONFIGURING DFREEZE FOR AN AUTOMATIC RAMP STOP
- Set DFREEZE = 0 for a hard stop.
- Set DFREEZE 0 for a linear deceleration ramp.
Due to the independence of DFREEZEfrom internal register values like direct_acc_val_en or the given clock
frequency CLK_FREQ(which can be altered by erroneous SPI signals) the deceleration value DFREEZE is
always given as velocity value change per clock cycle. Therefore, the DFREEZE value is calculated as
follows:
d_freeze[pps²] = DFREEZE / 237 ∙ fCLK2
This leads to the same behavior of the motor as a direct_acc_val_en = 1 setting during normal operation.
CONFIGURING THE IFREEZE CURRENT SCALING VALUE
IFREEZEis a current scaling value which becomes valid in caseNFREEZE has beentied to low and the related
event (FREEZED) has been released.In caseIFREEZE is set to 0, the last scaling value before the emergency
eventis assigned permanently. The scale value IFREEZEthen manipulates the current value in the same
way as explained in chapter 11.6.
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TMC4361 DATASHEET (Rev. 1.05 / 2015-MAR-02) Preliminary, Confidential 48
13 Controlled PWM Output
The TMC4361 allows for using PWM output values instead of Step/Dir outputs.
PINS AND REGISTERS: PWM OUTPUT
Pin names Type Remarks
STPOUT_PWMA
Output
PWM output for coilA
DIROUT_PWMB
Output
PWM output for coilB
Register name Register address Remarks
GENERAL_CONF 0x00 RW Bit21: pwm_out_en
PWM_AMPL 0x06 RW Second assignment to SCALE_VALUES(15 : 0):
PWM amplitude at VACTUAL = 0
PWM_VMAX 0x17 RW Second assignment to VDRV_SCALE_LIMIT
:velocity at
which the PWM scale parameter reaches 1 (max)
PWM_FREQ 0x1F RW # of clock cycles which forms one PWM period
13.1 PWM Output Generation
For generating a PWM output, setpwm_out_en = 1. Now, the Step/Dir output is disabled and PWM signals
are forwarded via STPOUT_PWMA and DIROUT_PWMB. The PWM frequency is calculated as follows:
fPWM = fCLK / PWM_FREQ.
The duty cycle for both coils is indicated by a high output level. For higher velocity a higher duty cycle
is required. Therefore, the TMC4361 alters a PWM scale parameter (PWM_SCALE) as a function of the
current velocity:
- IfVACTUAL = 0, PWM_SCALE = (PWM_AMPL + 1) / 217.
- With increasing velocity, the scale parameter raises linear to a maximum of PWM_SCALE = 0.5 at
VACTUAL = PWM_VMAX.
- The minimum duty cycle is calculated withDUTY_MIN = (0.5PWM_SCALE).
- The maximum duty cycle is calculated with DUTY_MAX = (0.5 + PWM_SCALE).
The current duty cycle for both coils is calculated using the microstep loop-up table MSLUT. In this case
the MSLUT describes a voltage (co-)sine curve whose amplitudes become transferred to the PWM phases.
The values are scaled related to minimum and maximum duty cycles.
In the following illustration, the calculation of minimum/maximum PWM duty cycles with
PWM_AMPL = 32767 is pointed outat the left side. Resulting duty cycles for different positions in the sine
voltage curve are depicted at the right side. Calculated delays of minimum/maximum duty cycles are also
shown.
Figure 13.1 Calculation of PWM duty cycles
PWM_SCALE
VACTUAL
PWM_VMAX
(PWM_AMPL+1)
2^17
0.5
t
DUTY_CYCLE
PWM_VMAX
PWM_FREQ
f
CLK
t
DUTY_MAX
=(0.5+PWM_SCALE)•PWM_FREQ/f
CLK
t
DUTY_MIN
=(0.5–PWM_SCALE)•PWM_FREQ/f
CLK
VACTUAL