MP6003 Datasheet by Monolithic Power Systems Inc.

a! n 0‘ 5v ' VW 13 L L {:IVOUT uu 9‘ l m H cs :: 90 ‘ ‘ 8 GND GND 1:} can sw g : VL mm 30 V‘N 36V EN 1:} 2 m vm 7 ? if.“ 3 Fa vcc 5 Q 70 VWTEV R2 ‘ W" R" 5 2m % 60 vw=sov R5 E C3 - ‘BGK u. C2 P! Lu 41 so. R4 R7 40 3' 5k 00 05 10 15 20 25 LOAD CURRENT ( A)
MP6003
Monolithic Flyback/SEPIC
DC-DC Converter
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The Future of Analog IC Technology
DESCRIPTION
The MP6003 is a monolithic flyback DC-DC
converter which includes a 150V power switch
and is capable of delivering up to 15W output
power. It can also be used for SEPIC boost and
Flyback and Forward applications.
The MP6003 uses the fixed-frequency peak
current mode primary controller architecture. It
has an internal soft-start, auto-retry, and
incorporates over current, short circuit, and
over-voltage protection. The MP6003 can also
skip cycles to maintain zero load regulation.
It has a direct optocoupler interface which
bypasses the internal error amplifier when an
isolated output is desired.
The MP6003 is ideal for telecom applications,
and is available in a compact, thermally
enhanced SOIC8 package with an exposed pad.
FEATURES
• Integrated 0.9 150V Power Switch
• Cycle-by-Cycle Current Limiting
• Programmable Switching Frequency
• Duty Cycle Limiting with Line Feed Forward
• Integrated 100V Startup Circuit
• Internal Slope Compensation
• Disable Function
• Built-in Soft-Start
• Line Under Voltage Lockout
• Line Over Voltage Protection
• Auto-Restart for Opened/Shorted Output
• Zero Load Regulation
• Thermal Shutdown
APPLICATIONS
• Telecom Equipment
• VoIP Phones, Power over Ethernet (PoE)
• Distributed Power Conversion
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks o
f
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
3333 O. CECE l'l'll‘E'
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ORDERING INFORMATION
Part Number* Package Top Marking Free Air Temperature (TA)
MP6003DN SOIC8E MP6003 -40°C to +85°C
* For Tape & Reel, add suffix –Z (eg. MP6003DN–Z).
For RoHS compliant packaging, add suffix –LF (eg. MP6003DN–LF–Z)
PACKAGE REFERENCE
GND
LINE
FB
COMP
SW
VIN
VCC
RT
1
2
3
4
8
7
6
5
TOP VIEW
ABSOLUTE MAXIMUM RATINGS (1)
VSW ..............................................-0.5V to +180V
VIN ..............................................-0.3V to +120V
All Other Pins...............................-0.3V to +6.5V
Continuous Power Dissipation… (TA = +25°C) (2)
……………………………………………......2.5W
Junction Temperature...............................150°C
Lead Temperature ....................................260°C
Storage Temperature............... -65°C to +150°C
Recommended Operating Conditions (3)
Supply Voltage VCC ...........................4.5 V to 6V
Output Voltage VSW .....................-0.5V to +150V
Input Voltage VIN .........................+10V to +100V
Maximum Junction Temp. (TJ) ................+125°C
Thermal Resistance (4) θJA θJC
SOIC8E .................................. 50 ...... 10... °C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance JA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/JA. Exceeding the maximum allowable powe
r
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7 4-layer board.
l'l'll‘E’
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ELECTRICAL CHARACTERISTICS
VCC = 5.0V, VLINE = 1.8V, RT = 10k, TA = +25°C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Quiescent Supply Current ICC 1.2V < VLINE < 3.2V, VFB = 1.3V 1.0 1.5 mA
Line OV Threshold Voltage VCC = 5.0V 2.85 3 3.15 V
Line OV Hysteresis VCC = 5.0V 300 mV
Line UV Threshold Voltage VCC = 5.0V 1.16 1.21 1.26 V
Line UV Hysteresis VCC = 5.0V 100 mV
VCC Upper Threshold Voltage 5.7 6.0 6.3 V
VCC Lower Threshold Voltage 4.30 4.50 4.70 V
VCC Over Voltage Threshold
Voltage 6.3 6.6 6.9 V
Feedback Voltage VFB 1.16 1.21 1.26 V
Feedback Input Current IFB V
FB = 1.2V 50 nA
Error Amplifier Gain Bandwidth (5) GBW 1 MHz
Error Amplifier DC Gain (5) A
V 60 dB
Comp Output Source Current IOH V
FB = 1.0V, VCOMP = 0.5V 6.5 mA
Comp Output Sink Current IOL V
FB = 1.4V, VCOMP = 2.5V 3.3 mA
Switch-On Resistance RON V
SW = 0.1V 0.9
Switch Leakage Current ILK V
SW = 180V 1 µA
Minimum Oscillating Frequency FMIN RT = 100k 60 kHz
Maximum Oscillating Frequency FMAX RT = 10k 550 kHz
Thermal Shutdown (5) 150 °C
Thermal Shutdown Hysteresis (5) 30
°C
Current Limit (5) I
LIM 550 700 mA
Startup Current Ist V
IN = 20V, VCC = 4.0V 6.5 mA
Note:
5) Guaranteed by design, not production tested.
ll'lPS' EFFICiENCV (n/n) EFFiCIENCV ("/a) Load Efficiency Load Regulation Line Regulation 90 ‘ 0 m o 05 VIN:36V A 006 A 004 so u i 005 .,\= 003 f; 5 004 C2> 002 70 V|N=75V E 0 02 E 0 01 i (59 000 3 000 60 V‘N:5°V g 70 02 8 70 m 2 -0 04 E 70 02 z 50 , 9 ,0 05 3 -0 03 -0 09 70 GA 40 ,0 m 70 05 0.0 o 5 10 15 2 0 2.5 0 0 0.5 1.0 1.5 20 2.5 36 44 52 60 as 76 LOAD CURRENT ( At LOAD CURRENT ( A) iNPUT VOLTAGET ( V) Line Efficiency VFB vs. Temperature Switch Frequency vs. Temperature 90 1 30 7o ‘oUT=1-5A IOUT=1.DA E n 1 25 i as 50 3 > U 3 70 ‘oUT:0 5A E 122 5 62 g S \_ 50 x 118 g 58 0 I g e 50 a MA E 54 u; w u. 40 1 10 50 as 44 52 60 as 76 .45 40 20 50 so 110 140 .40 710 20 50 50 110 140 iNPUT VOLTAGET(V) AMBIENT TEMPERATURE(°C) AMBTENT TEMPERATURE ( DC) Power Ramp Up Power Ramp Down Short Output Protection iOUT: 0.54 a u / v.ND ZUV/dw ‘ ViN zuv/mv ,__.___. vS . szu SUV/div ' SUV/div vow __ vow X m vow I —— SVldIv 5V/dw 5V/dw IOUT. —— ‘OUT ‘OUTi . 0 541m W“ V ZDms/dlv W“ 20ms/dw. 1ms/dlv
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TYPICAL PERFORMANCE CHARACTERISTICS
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 36V, VOUT = 5V, IOUT = 1A, TA = 25ºC, unless otherwise noted.
VEN ZV/dwv sw seV/dw Vour 5v/aw ‘om wow 20V/dw sz 50V/dw Vour svlaw ‘our «New PS' Enable Start Up Enable Start Down Short Output Recovery IOU-[=1 5A wow-=1 5A ‘our = 0 5A fl I: u VEN 2v/aw ” . ' “ V w sevfii‘c H V V ‘1 , svfiiw “ svfifivI R burr—— “121%; k D.5A/d|v 4 2ms/dw Amps/div «ms/aw Steady State Steady State Steady State \OUT=1.5A V‘N : 75v 3 I] H MHHHH Zofldiv D 4 mW/div g seV/&VW—~-——“'“—— A A; _A AA VOUT VOUI “ 5V/dlv ” r j- —— 5v/aw ” ‘OUI ‘ 2mm ‘4 ; u , W m , musldw Aug/aw Ays/dw
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 36V, VOUT = 5V, IOUT = 1A, TA = 25ºC, unless otherwise noted.
l'l'll‘E'
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PIN FUNCTIONS
Pin # Name Description
1 GND Ground. Power return and reference node.
2 LINE UV/OV Set Point. Short to ground to turn the controller off.
3 FB
Regulation Feedback Input. Inverting input of the error amplifier. The non-inverting is internally
connected to 1.2V
4 COMP Error Amplifier Output.
5 RT
Oscillator Resistor and Synchronous Clock Pin. Connect an external resistor to GND for
oscillator frequency setting. It can be used as a synchronous input from external oscillator clock.
6 VCC Supply Bias Voltage. A capacitor no less than 1uF is recommended to connect between GND.
7 VIN High Voltage Startup Circuit Supply.
8 SW
Output Switching Node. High voltage power N-Channel MOSFET drain output. The internal
start bias current is supplied from this pin.
l'I'II‘E' J fi'J] fl: ta L_l YYI TTT |—_I |_l |—_I |_l
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OPERATION
The MP6003 uses programmable fixed-
frequency, peak current-mode PWM with a
single-ended primary architecture to regulate
the output voltage. The MP6003 incorporates
features such as protection circuitry and an
integrated high voltage power switch into a
small 8-pin SOIC. This product targets high
performance, cost effective DC-DC converter
applications.
--
+
--
+
--
--
+
+
1.2V EA
1.0V
1.2V
3.0V
OVLO
6.5V
4.5V
UVLO
ERROR
AMPLIFIER
PWM
COMPARATOR
CURRENT LIMIT
COMPARATOR
CURRENT SENSE
SLOPE
COMP
CLOCK
--
+
--
+
--
+
Σ
THERMAL
MONITOR
SOFT-START
CURRENT LIMIT
OSC LEB
5
3
4
2
RT
FB
COMP
LINE
REGULATOR
IBIAS
REF
6
8
1
VCC
SW
GND
STARTUP
CONTROL
LOGIC
7
VIN
Figure 1—Functional Block Diagram
l'I'II‘E' n‘ -— 3 4* / 1—D—
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High Voltage Startup
The MP6003 features a 100V startup circuit,
see Figure 1. When power is applied, the
capacitor at the VCC pin is charged through the
VIN pin. When the voltage at the VCC pin
crosses 6.0V without fault, the controller is
enabled. The VCC pin is then disconnected
from the VIN pin and VCC voltage is discharged
via the operating current. When VCC drops to
4.5V, the VCC pin is reconnected to the VIN pin
and VCC will be recharged. The voltage at the
VCC pin repeats this ramp cycle between 4.5V
and 6.0V. VIN needs to be higher than 10V in
order to keep high voltage startup circuit
working properly. This can be guaranteed by
setting input UVLO ≥10V. It is also
recommended that the capacitor at VCC pin be
no less than 1uF to achieve stable operation.
The VCC pin can be powered with a voltage
higher than 4.5V from an auxiliary winding to
reduce the power dissipated in the internal
start-up circuit. The VCC pin is internally
clamped at 8V.
Under-Voltage and Over-Voltage Detection
The MP6003 includes a line monitor circuit.
Two external resistors form a voltage divider
from the input voltage to GND; its tap connects
to the LINE pin. The controller is operational
when the voltage at the UV/OV pin is between
1.2V and 3V. When the voltage at the UV/OV
pin goes out of this operating range, the
controller is disabled and goes into standby
mode. The LINE pin can also be used as a
remote enable. Grounding the UV/OV pin will
disable the controller.
Error Amplifier
The MP6003 includes an error amplifier with its
non-inverting input connected to internal 1.2V
reference voltage. The regulated voltage is fed
back through a resistor network or an
optocoupler to the FB pin. Figure 2 shows some
common error amplifier configurations.
--
+
1.2V
FB
C2
C3R3
COMP
VCC
C1
PRIMARY
WINDING
R1
R2
D1
EA
34
6
--
+
1.2V
FB COMP
VCC
C2
R2
R3
(a) Using Primary winding to provide feedback
(b) Feedback is from Secondary (Common Collector)
EA
34
6
Figure 2—Error Amplifier Configurations
Synchronize Programmable Oscillator
The MP6003 oscillating frequency is set by an
external resistor from the RT pin to ground. The
value of RT can be calculated from:
S
f
550kHz
10kRT ×=
The MP6003 can be synchronized to an
external clock pulse. The frequency of the clock
pulse must be higher than the internal oscillator
frequency. The clock pulse width should be
within 50ns to 150ns. The external clock can be
coupled to the RT pin with a 100pF capacitor
and a peak level greater than 3.5V.
Duty Cycle Limiting with Line Feed Forward
The MP6003 has a DMAX (maximum duty cycle)
limit at 67.5% when the LINE pin voltage is
equal to 1.3V. As VLINE increases, DMAX reduces.
Maximum duty cycle can be calculated by:
%100
VV7.2
V7.2
D
LINE
MAX ×
⎥
⎦
⎤
⎢
⎣
⎡
+
=
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Limiting the duty cycle at high line voltage
protects against magnetic saturation and
minimizes the output sensitivity to line
transients.
Auto-Restart
When VCC is biased from an auxiliary winding
and an open loop condition occurs, the voltage
at the VCC pin increases to 6.5V. When VCC
crosses the threshold voltage, the auto-restart
circuit turns off the power switch and puts the
controller in standby mode. When VCC drops to
4.5V, the startup switch turns on to charge VCC
up again. When VCC crosses 6.0V, the switch
turns off and the standby current discharges
VCC back to 4.5V. After repeating the ramp
cycles between the two threshold voltages 15
times, the auto-restart circuit is disabled and the
controller begins soft-start.
l'l'll‘E' 1. Transformer Turns Ratio
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APPLICATION INFORMATION
Switching Frequency
The frequency (fS), has big effects on the
selection of the transformer (Tr), the output cap,
(C2), and the input cap, (C1). The higher the
frequency, the smaller the sizes for Tr, C2, and
C1. However, a higher frequency also leads to
higher AC power losses in the power switch,
control circuitry, transformer, and in the external
interconnection. The general rule states that
lower the output power, higher the optimum
switching frequency. For low current (<10A)
applications, fS is usually 200kHz to 300kHz if
synchronous rectifiers are used and 300KHz to
500kHz if Schottky rectifiers are used.
Fundamental Equations
The transformer turns ratio N is defined as:
S
P
N
N
N=
Where NP and NS are the number of turns of the
primary and secondary side windings,
respectively.
The output voltage VO is estimated to be:
N
V
D1
D
VIN
O×
−
=
Where D is the duty cycle.
The steady-state drain to source voltage of the
primary power switch when it is off is estimated
as:
OINDS VNVV ×+=
The steady-state reverse voltage of the
Schottky diode D2 is estimated as:
N
V
VV IN
O2D +=
The output current is calculated as:
)D1(II DO −×=
Where ID is the average current through
Schottky diode when it is conducting.
The input current is calculated as:
DII SIN ×=
Where IS is the average current through the
primary power switch when it is conducting.
Transformer (Coupled Inductor) Design
1. Transformer Turns Ratio
The transformer turns ratio determines the duty
cycle range, selection of the rectifier (D2),
primary side peak current, primary snubber loss,
and the current as well as voltage stresses on
the power switch (S). It also has effects on the
selection of C1 and C2. A higher transformer
turns ratio (N) means the following:
• Higher Duty Cycle
• Higher voltage stress on S (VDS), but
lower voltage stress on D2 (VD2).
• Lower primary side RMS current (IS(RMS)),
but higher secondary side RMS current
(ID2(RMS)).
• Use of a smaller input capacitor but
bigger output capacitor.
• Lower primary side peak current (IS(PEAK))
and lower primary snubber loss.
• Lower main switch (S) turn-on loss
For a 5V power supply design, with
VIN=36V~75V, below table shows the voltage
stresses of the power switch (S) and the
rectifier (D2).
Table 1—Main Switch (S) and Rectifier (D2)
Voltage Stress vs. Transformer Turns Ratio
N DMAX VDS
(V) VDS/0.9
(V) VD2
(V) VD2/0.9
(V)
4 0.36 119 132 38 42
5 0.41 125 139 32 36
6 0.45 131 146 28 31
7 0.49 138 153 25 28
8 0.53 144 160 23 26
9 0.56 150 167 21 24
10 0.58 156 174 20 22
11 0.60 163 181 19 21
Note:
The voltage spike due to the leakage inductance of the
transformer and device’s voltage rating/derating factors were
considered. See power switch selection and snubber design for
more information.
l'I'II‘E' 2. Ri Ie Factor of the Ma netizin Current E 5. Right Half Plane Zero AIM i 3. Core Selection 4. Winding Selection
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2. Ripple Factor of the Magnetizing Current
The conduction loss in S, D2, the transformer,
the snubber, and in the ESR of the input/output
capacitors will increase as the ripple of the
magnetizing current increases. The ripple factor
(Kr) is defined as the ratio of the peak-to-peak
ripple current vs. the average current as shown
in Figure 3.
M
M
rI
I
KΔ
=
Where IM can be derived either from input or
output current;
)D1(N
I
D
I
I0IN
M−×
==
I
M
I
M
I
D2
/N
T
S
DT
S
0
Figure 3—Magnetic Current of Flyback
Transformer (Reflected to Primary Side)
The input/output ripple voltage will also
increase with a high ripple factor, which makes
the filter bigger and more expensive. On the
other hand, it can help to minimize the turn-on
loss of S and reverse-recovery loss due to D2.
With nominal input voltage, Kr can be selected
at 60%~120% for most DC-DC converters.
The primary side (or magnetizing) inductance
can be determined by:
Mr
SIN
FIK
TDV
L×
××
=
3. Core Selection
Pick a core based on experience or through a
catalog (Refer to http://www.ferroxcube.com).
Select an ER, EQ, PQ, or RM core to minimize
the transformer’s leakage inductance.
4. Winding Selection
Solid wire, Litz wire, PCB winding, Flex PCB
winding or any combination thereof can be used
as transformer winding. For low current
applications, solid wire is the most cost effective
choice. Consider using several wires in parallel
and interleaving the winding structure for better
performance of the transformer.
The number of primary turns can be determined
by:
EMAX
PF
PAB
IL
N×
×
=
Where BMAX is the allowed maximum flux
density (usually below 300mT) and AE is the
effective area of the core.
The air gap can be estimated by:
F
E
2
o
L
AN
Gap ××μ
=
5. Right Half Plane Zero
A Flyback converter operating in continuous
mode has a right half plane (RHP) zero. In the
frequency domain, this RHP zero adds not only
a phase lag to the control characteristics but
also increases the gain of the circuit. Typical
rule of thumb states that the highest usable
loop crossover frequency is limited to one third
the value of the RHP zero. The expression for
the location of the RHP zero in a continuous
mode flyback is given by:
2
F
2
LOADRHPZ N
DL2
)D1(
Rf ×
××π
−
×=
Where RLOAD is the load resistance, LF is the
magnetizing inductance on transformer primary
side, and N is the transformer’s turn ratio.
Reducing the primary inductance increases the
RHP zero frequency which results in higher
crossover frequencies.
l'I'II‘E'
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Duty Cycle Range
The duty cycle range is determined once N is
selected. In general, the optimum operating
duty cycle should be smaller for high input/low
output than low input/high output applications.
Except for high output voltage or wide input
range applications, the maximum D usually
does not exceed 60%.
Voltage Stress of the Internal Power Switch
& External Schottky Diode
For the internal power switch, the voltage stress
is given by:
POINDS VNVVV +×+=
Where VP is a function of LLK (leakage
inductrance), fS, R, C, CDS, VIN, IO, etc. Please
refer to Figure 4. The lower the LLK and Io, the
lower the Vp. Smaller R can reduce Vp, but
power loss will increase. See Snubber Design
for details.
Typically VP can be selected as 20~40% of
(VIN+NVO).
--
+
--
+
C2
ID2
LLK
IS
C
R
D
VDS
VDS
VCVP
VIN
0
VC
C1
S
TrD2
Figure 4—Key Operation Waveform
For the rectifier, D2, the voltage stress is given
by:
2PD
IN
O2D V
N
V
VV ++=
Use of a R-C or R-C-D type snubber circuit for
D2 is recommended.
2PD
V can be selected as 40~100% of
(VO+VIN/N), thus:
)NVV(KV 0)MAX(INs)MAX(DS +×
=
Where KS=1.2~1.4, and
)
N
V
V(KV )MAX(IN
02D)MAX(2D +⋅=
Where KD2=1.4~2.
For example,
V23)8V75V5(6.1V
V144)V58V75(25.1V
V5V,6.1K,25.1K,8N,V75V
2D
DS
O2DS)MAX(IN
=÷+×=
=×+×=
=====
So
the power switch rating should be higher than
144V, and the rated voltage for the
synchronous rectifier or Schottky diode should
be higher than 23V.
Snubber Design (Passive)
Snubber for Power Switch
Figure 5 shows four different ways to clamp the
voltage on the power device. RCD type of
snubber circuit is widely used in many
applications.
S
(A) (B)
(C) (D)
D
Z
R
D
R
D
C
D
C
D
D
Z
S
S S
Figure 5—Snubber Designs
l'I'II‘E' RCD T e of Snubber Desi n Procedure:
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RCD Type of Snubber Design Procedure:
1. Setting VP
Higher VP means higher voltage stress on the
power switch, but lower power loss. Usually, VP
can be set as 20%~40% of (VIN+ NxVO).
V
DS
V
P
V
IN
N x V
O
0
V
C
Figure 6—Voltage Waveform of Primary
Power Switch Shown in Figure 5(C)
2. Estimated RCD snubber loss is given by:
)
V
VN
1(PP
P
O
LKLOSS_RCD
×
+×=
Where:
C
2
PLKLK fIL
2
1
P××=
PLK is the energy stored in the leakage
inductance (LLK), which carries the peak current
at the power switch turn-off.
3. Calculate values of the RD and CD of RCD
snubber by:
LOSS_RCD
2
P
DP
V
R=
S
DD f
1
CR >>×
Input Capacitor
The input capacitors (C1) are chosen based
upon the AC voltage ripple on the input
capacitors, RMS current ratings, and voltage
rating of the input capacitors.
For a given AC ripple voltage, VIN_PP, C1 can
be derived from:
PP_IN
SIN
V
T)D1(I
1C Δ
×−×
=
VIN_PP may affect the C1 voltage rating and
converter stability. C1 RMS current has to be
considered:
D
)D1(
II IN1C_RMS
−
×=
C1 has to have enough RMS current rating.
Output Filter
The simplest filter is an output capacitor (C2),
whose capacitance is determined by the output
ripple requirement.
The current waveform in the output capacitor is
mostly in rectangular shape. The full load
current is drawn from the capacitors during the
primary switch on time. The worse case for the
output ripple occurs under low line and full load
conditions. The ripple voltage can be estimated
by:
S
OCPP0 f2C
D
IV ×
×=Δ −−
ESR also needs to be specified for the output
capacitors. This is due to the step change in D2
current results in a ripple voltage that is
proportional to the ESR. Assuming that the D2
current waveform is in rectangular shape, the
ESR requirement is then obtained by given the
output ripple voltage.
)D1(
ESRI
VO
R_PPO ESR −
×
=Δ −
The total ripple voltage can be estimated by:
ESR_PPOCPPOPPO VVV −−−− Δ+
Δ
=
Δ
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MP6003 – MONOLITHIC FLYBACK/SEPIC DC-DC CONVERTER
MP6003 Rev. 1.01 www.MonolithicPower.com 14
1/26/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
Control Design
Generally, some of power supplies require the
galvanic isolation between a relatively high
input voltage and low output voltages. The most
widely used devices to transfer signals across
the isolation boundary are pulse transformers
and optocouplers.
--
+
--
+
S
Tr
D
d
R6
R3
Rb
R4
R1
R2
R5
C1
V
REF
V
CC
R
LOAD
R
ESR
C
O
V
O
TL431
V
IN
--
+
Figure 7—Simplified Circuit of Isolated
Power Supply with Optocoupler Feedback
The MP6003 uses current mode control to
achieve easy compensation and fast transient
response. A type II compensation network
which has two poles and one zero is needed to
stabilize the system. The practical
compensation parameters are provided in the
EVQ6003DN datasheet.
Boost Controller Application Design
Example 2
The MP6003 can be used as a boost controller
as shown in Figure 8.
MP6003
GND
COMP
FB
LINE
8
5
6
7
1
4
3
2
SW
RT
VCC
VIN
V
IN
R6
63.4kΩ
R2
200kΩ
C4
10μF
16V
C2
1μF
200V
C3
10nF
L1
22μF/2.5A
D1
200V/1A
180V
20mA
R5
1.5kΩ
R4
10kΩ
R1
60.4Ω
R3
10kΩ
C1
10μF
25V
Figure 8—High Voltage LED Boost
Controller Circuit
Design Example
This design example shows an flyback topology
for industrial application. It has wide input
voltage rang from 36V to 80V and 5V output.
1
2
3
4
3
1
2
Figure 9—Reference Design Circuit for Flyback Application
l'l'll‘E' 0.139 4.3a FHDNT VIEW *Wfi :Hflflfii _ II"_ ._ wim— HECDMMENDED LAND FATIERN 112441.15) FHEM BO'I'I'OM VIEW / \ / l I E i 100750.19 / T_(_) " SIDE VIEW 1+— ,£,,,,,, , 1—5, 0W, o.n1e(o DETAIL "A" NOTE:
MP6003 – MONOLITHIC FLYBACK/SEPIC DC-DC CONVERTER
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP6003 Rev. 1.01 www.MonolithicPower.com 15
1/26/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
PACKAGE INFORMATION
SOIC8E
SEE DETAIL "A"
0.0075(0.19)
0.0098(0.25)
0.050(1.27)
BSC
0.013(0.33)
0.020(0.51)
SEATING PLANE
0.000(0.00)
0.006(0.15)
0.051(1.30)
0.067(1.70)
TOP VIEW
FRONT VIEW
SIDE VIEW
BOTTOM VIEW
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION BA.
6) DRAWING IS NOT TO SCALE.
0.089(2.26)
0.101(2.56)
0.124(3.15)
0.136(3.45)
RECOMMENDED LAND PATTERN
0.213(5.40)
0.063(1.60)
0.050(1.27)
0.024(0.61)
0.103(2.62)
0.138(3.51)
0.150(3.80)
0.157(4.00)
PIN 1 ID
0.189(4.80)
0.197(5.00)
0.228(5.80)
0.244(6.20)
14
85
0.016(0.41)
0.050(1.27)
0o-8o
DETAIL "A"
0.010(0.25)
0.020(0.50) x 45o
0.010(0.25) BSC
GAUGE PLANE