TPD2E2U06-Q1 Datasheet by Texas Instruments

V'.‘ TEXAS INSTRUMENTS X
TPD2E2U06-Q1
1 2
3
USB 2.0
Connector
Vbus
D+
D-
GND
USB 2.0
Transceiver
Power
Supply
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD2E2U06-Q1
SLLSEJ9D –DECEMBER 2014–REVISED MAY 2016
TPD2E2U06-Q1 Automotive Dual-Channel High-Speed ESD Protection Device
1
1 Features
1• AEC-Q101 Qualified
• IEC 61000-4-2 Level 4 ESD Protection
– ±25-kV (Contact Discharge)
– ±30-kV (Air-gap Discharge)
• ISO 10605 (330 pF, 330 Ω) ESD Protection
– ±20-kV (Contact Discharge)
– ±25-kV (Air-gap Discharge)
• IO Capacitance 1.5-pF (Typical)
• DC Breakdown Voltage 6.5 V (Minimum)
• Ultra-Low Leakage Current 10-nA (Maximum)
• Low ESD Clamping Voltage
• Industrial Temperature Range: –40°C to +125°C
• Small Easy-to-Route DBZ and DCK Packages
2 Applications
• End Equipment
– Head Units
– Rear Seat Entertainment
– Telematics
– Navigation Modules
– Media Interfaces
• Interfaces
– USB 2.0
– Ethernet
– Antenna
– LVDS
– I2C
3 Description
The TPD2E2U06-Q1 is a Transient Voltage
Suppressor (TVS) Electrostatic Discharge (ESD)
protection diode array with low capacitance. This
dual-channel ESD protection diode is rated to
dissipate ESD strikes above the maximum level
specified in the IEC 61000-4-2 international standard.
The 1.5-pF line capacitance of the TPD2E2U06-Q1
makes it ideal for protecting interfaces such as USB
2.0, Ethernet, LVDS, Antenna, and I2C.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPD2E2U06-Q1 SOT23 (3) 2.92 mm × 1.30 mm
TPD2E2U06-Q1 SC70 (3) 2.00 mm × 1.25 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
l TEXAS INSTRUMENTS
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings—AEC Specification............................. 4
6.3 ESD Ratings—IEC Specification .............................. 4
6.4 ESD Ratings—ISO Specification .............................. 4
6.5 Recommended Operating Conditions....................... 4
6.6 Thermal Information.................................................. 4
6.7 Electrical Characteristics........................................... 5
6.8 Typical Characteristics.............................................. 6
7 Detailed Description.............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 9
8 Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
9 Power Supply Recommendations...................... 12
10 Layout................................................................... 12
10.1 Layout Guidelines ................................................. 12
10.2 Layout Example .................................................... 12
11 Device and Documentation Support ................. 13
11.1 Documentation Support ....................................... 13
11.2 Community Resources.......................................... 13
11.3 Trademarks........................................................... 13
11.4 Electrostatic Discharge Caution............................ 13
11.5 Glossary................................................................ 13
12 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (March 2016) to Revision D Page
• Updated Features ,Applications and Description .................................................................................................................. 1
• Updated ESD Ratings—AEC Specification table .................................................................................................................. 1
Changes from Revision B (December 2014) to Revision C Page
• Added DCK package.............................................................................................................................................................. 1
• Added DCK thermal data in Thermal Information table.......................................................................................................... 1
Changes from Revision A (December 2014) to Revision B Page
• Added temperature specification to VBR TEST CONDITIONS. ............................................................................................. 5
Changes from Original (December 2014) to Revision A Page
• Initial release of full document. .............................................................................................................................................. 1
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IO1
IO2
1
2
GND
3
IO1
IO2
1
2
GND
3
3
TPD2E2U06-Q1
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5 Pin Configuration and Functions
DBZ Package
3-Pin SOT23
Top View
DCK Package
3-Pin SC70
Top View
Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 IO1 I/O The IO1 and IO2 pins are an ESD protected channel. Connect these pins to the data
line as close to the connector as possible.
2 IO2 I/O
3 GND G The GND (ground) pin is connected to ground.
l TEXAS INSTRUMENTS
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Measured at 25°C.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
IPP Peak pulse current (tp= 8/20 μs) 5.5(2) A
PPP Peak pulse power (tp= 8/20 μs) 75(2) W
TJJunction temperature –40 125 °C
Tstg Storage temperature –65 150 °C
(1) AAEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.2 ESD Ratings—AEC Specification
VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±10000 V
Charged device model (CDM), per AEC Q100-011 ±1000
6.3 ESD Ratings—IEC Specification
VALUE UNIT
V(ESD) Electrostatic discharge IEC 61000-4-2 Contact discharge ±25000 V
Air-gap discharge ±30000
6.4 ESD Ratings—ISO Specification
VALUE UNIT
V(ESD) Electrostatic discharge ISO 10605 (330 pF, 330 Ω)Contact discharge ±20000 V
Air-gap discharge ±25000
6.5 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIO Input pin voltage 0 5.5 V
TAOperating free air temperature –40 125 ℃
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 Thermal Information
THERMAL METRIC(1)
TPD2E2U06-Q1
UNITDBZ (SOT23) DCK (SC70)
3 PINS 3 PINS
RθJA Junction-to-ambient thermal resistance 439.5 308.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 194.9 170.7 °C/W
RθJB Junction-to-board thermal resistance 173.9 89.2 °C/W
ψJT Junction-to-top characterization parameter 53.7 34.2 °C/W
ψJB Junction-to-board characterization parameter 172 88.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
l TEXAS INSTRUMENTS
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(1) Transmission Line Pulse with 10-ns rise time, 100-ns width.
(2) Measured at 25°C.
(3) Extraction of RDYN Using least squares fit of TLP characteristics between I = 20 A and I = 30 A.
6.7 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRWM Reverse stand-off voltage IIO < 10 µA 5.5 V
VCLAMP IO to GND IPP = 1 A, TLP(1)(2) 9.7 V
IPP = 5 A, TLP(1)(2) 12.4
VCLAMP GND to IO IPP = 1 A, TLP(1)(2) 1.9 V
IPP = 5 A, TLP(1)(2) 4
RDYN Dynamic resistance IO to GND(3)(2) 0.6 Ω
GND to IO(3)(2) 0.4
CLLine capacitance f = 1 MHz, VBIAS = 2.5 V(2) 1.5 1.9 pF
CCROSS Channel-to-channel input
capacitance Pin 3 = 0 V, f = 1 MHz, VBIAS = 2.5 V, between
channel pins(2) 0.02 0.03 pF
∆CL Variation of channel input
capacitance Pin 3 = 0 V, f = 1 MHz, VBIAS = 2.5 V,
Pin 1 to GND – Pin 2 to GND(2) 0.03 0.1 pF
VBR Break-down voltage IIO = 1 mA(2) 6.5 8.5 V
ILEAK Leakage current VIO = 2.5 V 1 10 nA
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0
100
200
300
400
500
±40 ±15 10 35 60 85 110 135
Current (pA)
Temperature (ƒC)
-0.001
-0.0005
0
0.0005
0.001
±2 ±1 0 1 2 3 4 5 6 7 8 9 10
Current (A)
Voltage (V)
C005
±15
0
15
30
45
60
75
90
105
120
0 25 50 75 100 125 150 175 200
Voltage (V)
Time (ns)
C003
±120
±105
±90
±75
±60
±45
±30
±15
0
15
0 25 50 75 100 125 150 175 200
Voltage (V)
Time (ns)
C004
0
5
10
15
20
25
30
0 5 10 15 20 25 30 35 40 45 50
Current (A)
Voltage (V)
C001
0
5
10
15
20
25
30
0 5 10 15 20 25 30 35 40 45 50
Current (A)
Voltage (V)
C002
6
TPD2E2U06-Q1
SLLSEJ9D –DECEMBER 2014–REVISED MAY 2016
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6.8 Typical Characteristics
Measured at TA= 25°C unless otherwise specified
Figure 1. TLP, Data to GND Figure 2. TLP, GND to Data
Figure 3. IEC 61000-4-2 Clamping Voltage, 8-kV Contact Figure 4. IEC 61000-4-2 Clamping Voltage, –8-kV Contact
Figure 5. IV Curve, TA= 25°C Figure 6. ILEAK vs Temperature, VIN = 2.5 V
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±18
±15
±12
±9
±6
±3
0
1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10
Insertion Loss (dB)
Frequency (Hz)
C009
0
10
20
30
40
50
60
70
80
90
0
1
2
3
4
5
6
7
-20 -10 0 10 20 30 40 50
Power (W)
Current (A)
Time (µs)
Current
Power
C008
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
0 1 2 3 4 5
Capacitance (pF)
Voltage (V)
C007
7
TPD2E2U06-Q1
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Typical Characteristics (continued)
Measured at TA= 25°C unless otherwise specified
Figure 7. Capacitance Across VBIAS
f = 1 MHz Figure 8. Surge Curve (tp= 8/20 μs)
IO TO GND
Figure 9. Insertion Loss
l TEXAS INSTRUMENTS Copyngmmme. Texas \nslrumems \ncarpma‘eu
IO1 IO2
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7 Detailed Description
7.1 Overview
The TPD2E2U06-Q1 device is a TVS ESD protection diode array with low capacitance. It is rated to dissipate
ESD strikes above the maximum level specified in the IEC 61000-4-2 international standard. The 1.5-pF line
capacitance makes it ideal for protecting interfaces such as USB 2.0, LVDS, Antenna, and I2C.
7.2 Functional Block Diagram
7.3 Feature Description
The TPD2E2U06-Q1 device is a TVS ESD protection diode array with low capacitance. It is rated to dissipate
ESD strikes above the maximum level specified in the IEC 61000-4-2 international standard. The 1.5-pF line
capacitance makes it ideal for protecting interfaces such as USB 2.0, LVDS, Antenna, and I2C.
7.3.1 AEC-Q101 Qualified
This device is qualified to AEC-Q101 standards. It passes HBM H3B (±8 kV) and CDM C5 (±1 kV) ESD ratings
and is qualified to operate from –40°C to +125°C.
7.3.2 IEC 61000-4-2 Level 4
The I/O pins can withstand ESD events up to ±25-kV contact and ±30-kV air. An ESD-surge clamp diverts the
current to ground.
7.3.3 IO Capacitance
The capacitance between each I/O pin to ground is 1.5 pF. These capacitances support data rates in excess of
1.5 Gbps.
7.3.4 DC Breakdown Voltage
The DC breakdown voltage of each I/O pin is a minimum of 6.5 V. This ensures that sensitive equipment is
protected from surges above the reverse standoff voltage of 5.5 V.
7.3.5 Ultra-Low Leakage Current
The I/O pins feature an ultra-low leakage current of 10 nA (Maximum) with a bias of 2.5 V.
7.3.6 Low ESD Clamping Voltage
The I/O pins feature an ESD clamp that is capable of clamping the voltage to 9.7 V (IPP = 1 A).
7.3.7 Industrial Temperature Range
This device is designed to operate from –40°C to +125°C.
l TEXAS INSTRUMENTS
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Feature Description (continued)
7.3.8 Small Easy-to-Route Packages
The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers
flow-through routing, requiring minimal modification to an existing layout.
7.4 Device Functional Modes
The TPD2E2U06-Q1 device is a passive integrated circuit that triggers when voltages are above VBR or below
the lower diodes Vf(–0.6 V). During ESD events, voltages as high as ±30 kV (air) can be directed to ground via
the internal diode network. When the voltages on the protected line fall below the trigger levels of the
TPD2E2U06-Q1 (usually within 10s of nano-seconds) the device reverts to passive.
l TEXAS INSTRUMENTS
TPD2E2U06-Q1
1 2
3
USB 2.0
Connector
Vbus
D+
D-
GND
USB 2.0
Transceiver
Power
Supply
Copyright © 2016, Texas Instruments Incorporated
10
TPD2E2U06-Q1
SLLSEJ9D –DECEMBER 2014–REVISED MAY 2016
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPD2E2U06-Q1 device is a diode type TVS which is typically used to provide a path to ground for
dissipating ESD events on hi-speed signal lines between a human interface connector and a system. As the
current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the
voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe
level for the protected IC.
8.2 Typical Application
Figure 10. Typical USB Application Diagram
8.2.1 Design Requirements
For this design example, one TPD2E2U06-Q1 device will be used in a USB 2.0 application. This will provide
complete port protection.
Given the USB 2.0 application, the parameters listed in Table 1 are known.
Table 1. Design Parameters
DESIGN PARAMETER VALUE
Signal range on pins 1 or 2 0 V to 3.3 V
Operating frequency 240 MHz
l TEXAS INSTRUMENTS
±9
±8
±7
±6
±5
±4
±3
±2
±1
0
1
1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10
Insertion Loss (dB)
Frequency (Hz)
C010
11
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8.2.2 Detailed Design Procedure
8.2.2.1 Signal Range
The TPD2E2U06-Q1 device has 2 identical protection channels for signal lines. The symmetry of the device
provides flexibility when selecting which of the 2 I/O channels will protect which signal lines. Any I/O will support
a signal range of 0 to 5.5 V.
8.2.2.2 Operating Frequency
The TPD2E2U06-Q1 device has a capacitance of 1.5 pF (typical), supporting USB 2.0 data rates.
8.2.3 Application Curve
Figure 11. Insertion Loss Graph
l TEXAS INSTRUMENTS
GND
= VIA to GND
IO2
IO1
12
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9 Power Supply Recommendations
This device is a passive ESD protection device and there is no need to power it. Make sure that the maximum
voltage specifications for each line are not violated.
10 Layout
10.1 Layout Guidelines
• The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
This application is typical of a differential data pair application, such as USB 2.0.
Figure 12. Routing with DBZ Package
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
•Reading and Understanding an ESD Protection Datasheet,SLLA305
•ESD Layout Guide,SLVA680
•TPD2E2U06QEVM User's Guide,SLVUAC6
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I TEXAS INSTRUMENTS Sample: Sample:
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPD2E2U06QDBZRQ1 ACTIVE SOT-23 DBZ 3 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 22U6Q
TPD2E2U06QDCKRQ1 ACTIVE SC70 DCK 3 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 11X
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
OTHER QUALIFIED VERSIONS OF TPD2E2U06-Q1 :
•Catalog: TPD2E2U06
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«m» Reel Diame|er AD Dimension deswgned to accommodate the componem wwdlh E0 Dimension desxgned to accommodate the componenl \ength KO Dimenslun deswgned to accommodate the componem thickness 7 w OveraH wwdm loe earner cape i p1 Pitch between successwe cavuy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O Sprockemoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPD2E2U06QDBZRQ1 SOT-23 DBZ 3 3000 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TPD2E2U06QDCKRQ1 SC70 DCK 3 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPD2E2U06QDBZRQ1 SOT-23 DBZ 3 3000 213.0 191.0 35.0
TPD2E2U06QDCKRQ1 SC70 DCK 3 3000 180.0 180.0 18.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Apr-2020
Pack Materials-Page 2
GENERIC PACKAGE VIEW D32 3 SOT-23 - 1.12 mm max heigm SMALL OUTLINE TRANSISTOR Images above are jusl a represenlalion of the package family, aclual package may vary Refel lo the product dala sheel for package details. I TEXAS INSTRI IMFNTS
4203227/C
I-III
www.ti.com
PACKAGE OUTLINE
C
TYP
0.20
0.08
0.25
2.64
2.10 1.12 MAX
TYP
0.10
0.01
3X 0.5
0.3
TYP
0.6
0.2
1.9
0.95
TYP-80
A
3.04
2.80
B
1.4
1.2
(0.95)
SOT-23 - 1.12 mm max heightDBZ0003A
SMALL OUTLINE TRANSISTOR
4214838/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-236, except minimum foot length.
0.2 C A B
1
3
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
3X (1.3)
3X (0.6)
(2.1)
2X (0.95)
(R0.05) TYP
4214838/C 04/2017
SOT-23 - 1.12 mm max heightDBZ0003A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
SCALE:15X
PKG
1
3
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
www.ti.com
EXAMPLE STENCIL DESIGN
(2.1)
2X(0.95)
3X (1.3)
3X (0.6)
(R0.05) TYP
SOT-23 - 1.12 mm max heightDBZ0003A
SMALL OUTLINE TRANSISTOR
4214838/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
SYMM
PKG
1
3
2
.l. w-Q
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.15
2.4
1.8
0.65
1.1 MAX
0.1
0.0 TYP
3X 0.30
0.15
0.46
0.26 TYP
8
0 TYP
1.3
A
2.15
1.85
B
1.4
1.1
(0.9)
SOT-SC70 - 1.1 max heightDCK0003A
SMALL OUTLINE TRANSISTOR SC70
4220745/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
0.1 C A B
1
3
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 5.600
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
3X (0.95)
3X (0.4)
(2.2)
(1.3)
(0.65)
(R0.05) TYP
4220745/C 06/2021
SOT-SC70 - 1.1 max heightDCK0003A
SMALL OUTLINE TRANSISTOR SC70
NOTES: (continued)
3. Publication IPC-7351 may have alternate designs.
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
PKG
1
3
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.2)
(1.3)
(0.65)
3X (0.95)
3X (0.4)
(R0.05) TYP
SOT-SC70 - 1.1 max heightDCK0003A
SMALL OUTLINE TRANSISTOR SC70
4220745/C 06/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
6. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
SYMM
PKG
1
3
2
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