SIHB28N60EF-GE3 Datasheet by Vishay Siliconix

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SiHB28N60EF
www.vishay.com Vishay Siliconix
S21-0115-Rev. D, 15-Feb-2021 1Document Number: 91601
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
EF Series Power MOSFET with Fast Body Diode
FEATURES
Fast body diode MOSFET using E series
technology
Reduced trr, Qrr, and IRRM
Low figure-of-merit (FOM): Ron x Qg
Low input capacitance (Ciss)
Low switching losses due to reduced Qrr
Ultra low gate charge (Qg)
Avalanche energy rated (UIS)
Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Telecommunications
- Server and telecom power supplies
• Lighting
- High intensity discharge (HID)
- Light emitting diodes (LEDs)
Consumer and computing
- ATX power supplies
• Industrial
- Welding
- Battery chargers
Renewable energy
- Solar (PV inverters)
Switch mode power suppliers (SMPS)
Applications using the following topologies
- LLC
- Phase shifted bridge (ZVS)
- 3-level inverter
- AC/DC bridge
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature
b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 Ω, IAS = 7 A
c. 1.6 mm from case
d. ISD ID, dI/dt = 900 A/μs, starting TJ = 25 °C
PRODUCT SUMMARY
VDS (V) 650
RDS(on) max. (Ω) at VGS = 10 V 0.123
Qg typ. (nC) 33
ID (A) 28
Configuration Single
N-Channel MOSFET
G
D
S
GD
S
D
2
PAK (TO-263)
ORDERING INFORMATION
Package D2PAK (TO-263)
Lead (Pb)-free and Halogen-free
SIHB28N60EF-GE3
SIHB28N60EF-T1-GE3
SIHB28N60EF-T5-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-source voltage VDS 600 V
Gate-source voltage VGS ± 30
Continuous drain current (TJ = 150 °C) VGS at 10 V TC = 25 °C ID
28
ATC = 100 °C 18
Pulsed drain current a IDM 75
Linear derating factor 2W/°C
Single pulse avalanche energy b EAS 691 mJ
Maximum power dissipation PD250 W
Operating junction and storage temperature range TJ, Tstg -55 to +150 °C
Drain-source voltage slope TJ = 125 °C dV/dt 70 V/ns
Reverse diode dV/dt d 50
Soldering recommendations (peak temperature) c for 10 s 300 °C
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SiHB28N60EF
www.vishay.com Vishay Siliconix
S21-0115-Rev. D, 15-Feb-2021 2Document Number: 91601
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDS
b. Coss(tr) is a fixed capacitance that gives the charging time as Coss while VDS is rising from 0 % to 80 % VDS
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum junction-to-ambient RthJA -62
°C/W
Maximum junction-to-case (drain) RthJC -0.5
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-source breakdown voltage VDS VGS = 0 V, ID = 250 μA 600 - - V
VDS temperature coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.76 - V/°C
Gate-source threshold voltage (N) VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V
Gate-source leakage IGSS VGS = ± 20 V - - ± 100 nA
VGS = ± 30 V - - ± 1 μA
Zero gate voltage drain current IDSS
VDS = 480 V, VGS = 0 V - - 1 μA
VDS = 480 V, VGS = 0 V, TJ = 125 °C - - 2 mA
Drain-source on-state resistance RDS(on) V
GS = 10 V ID = 14 A - 0.107 0.123 Ω
Forward transconductance gfs VDS = 30 V, ID = 14 A - 9.7 - S
Dynamic
Input capacitance Ciss VGS = 0 V,
VDS = 100 V,
f = 1 MHz
- 2714 -
pF
Output capacitance Coss - 123 -
Reverse transfer capacitance Crss -6-
Effective output capacitance, energy
related a Co(er)
VGS = 0 V, VDS = 0 V to 480 V
-98-
Effective output capacitance, time
related b Co(tr) - 356 -
Total gate charge Qg
VGS = 10 V ID = 14 A, VDS = 480 V
- 80 120
nC Gate-source charge Qgs -17-
Gate-drain charge Qgd -33-
Turn-on delay time td(on)
VDD = 480 V, ID = 14 A
Rg = 9.1 Ω, VGS = 10 V
-2448
ns
Rise time tr -4080
Turn-off delay time td(off) - 82 123
Fall time tf -3978
Gate input resistance Rg f = 1 MHz, open drain 0.2 0.5 1.0 Ω
Drain-Source Body Diode Characteristics
Continuous source-drain diode current IS
MOSFET symbol
showing the
integral reverse
p - n junction diode
--28
A
Pulsed diode forward current ISM --70
Diode forward voltage VSD TJ = 25 °C, IS = 11 A, VGS = 0 V - 0.9 1.2 V
Reverse recovery time trr TJ = 25 °C, IF = IS = 14 A,
dI/dt = 100 A/μs, VR = 400 V
- 142 284 ns
Reverse recovery charge Qrr - 0.97 1.94 μC
Reverse recovery current IRRM - 13.2 - A
S
D
G
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SiHB28N60EF
www.vishay.com Vishay Siliconix
S21-0115-Rev. D, 15-Feb-2021 3Document Number: 91601
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics
Fig. 2 - Typical Output Characteristics
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Coss and Eoss vs. VDS
0
20
40
60
80
0 5 10 15 20 25 30
ID, Drain-to-Source Current (A)
VDS, Drain-to-Source Voltage (V)
TJ = 25 °C
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9 V
8 V
7 V
6 V
BOTTOM 5 V
0
15
30
45
0 5 10 15 20 25 30
ID, Drain-to-Source Current (A)
VDS, Drain-to-Source Voltage (V)
TJ = 150 °C
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9 V
8 V
7 V
6 V
BOTTOM 5 V
0
20
40
60
80
0 5 10 15 20 25
ID, Drain-to-Source Current (A)
VGS, Gate-to-Source Voltage (V)
TJ = 150 °C
TJ = 25 °C
VDS = 28 V
0
0.5
1.0
1.5
2.0
2.5
3.0
-60 -40 -20 0 20 40 60 80 100 120 140 160
RDS(on), Drain-to-Source On-Resistance
(Normalized)
TJ, Junction Temperature (°C)
ID = 14 A
VGS = 10 V
1
10
100
1000
10 000
0 100 200 300 400 500 600
C, Capacitance (pF)
VDS, Drain-to-Source Voltage (V)
Ciss
Coss
Crss
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds shorted
Crss = Cgd
Coss = Cds + Cgd
0
2
4
6
8
10
12
14
16
18
50
500
5000
0 100 200 300 400 500 600
Eoss (μJ)
Coss (pF)
VDS
Coss Eoss
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SiHB28N60EF
www.vishay.com Vishay Siliconix
S21-0115-Rev. D, 15-Feb-2021 4Document Number: 91601
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 - Typical Source-Drain Diode Forward Voltage
Fig. 9 - Maximum Safe Operating Area
Note
a. VGS > minimum VGS at which RDS(on) is specified
Fig. 10 - Maximum Drain Current vs. Case Temperature
Fig. 11 - Typical Drain-to-Source Voltage vs. Temperature
0
4
8
12
16
20
24
0 40 80 120 160
VGS, Gate-to-Source Voltage (V)
Qg, Total Gate Charge (nC)
VDS = 480 V
VDS = 300 V
VDS = 120 V
0.1
1
10
100
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
ISD, Reverse Drain Current (A)
VSD, Source-Drain Voltage (V)
TJ = 150 °C
TJ = 25 °C
VGS = 0 V
0.01
0.1
1
10
100
1101001000
ID, Drain Current (A)
VDS, Drain-to-Source Voltage (V)
Limited by RDS(on)*
1 ms
IDM Limited
TC= 25 °C
TJ= 150 °C
Single PulseBVDSS Limited
10 ms
100 μs
Operation in this Area
Limited by RDS(on)
0
6
12
18
24
30
25 50 75 100 125 150
ID, Drain Current (A)
TC, Case Temperature (°C)
575
600
625
650
675
700
725
750
-60 -40 -20 0 20 40 60 80 100 120 140 160
VDS, Drain-to-Source Breakdown Voltage (V)
TJ, Junction Temperature (°C)
ID = 250 μA
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SiHB28N60EF
www.vishay.com Vishay Siliconix
S21-0115-Rev. D, 15-Feb-2021 5Document Number: 91601
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
Fig. 13 - Switching Time Test Circuit
Fig. 14 - Switching Time Waveforms
Fig. 15 - Unclamped Inductive Test Circuit
Fig. 16 - Unclamped Inductive Waveforms
Fig. 17 - Basic Gate Charge Waveform
Fig. 18 - Gate Charge Test Circuit
0.01
0.1
1
0.0001 0.001 0.01 0.1 1
Normalized Effective Transient
Thermal Impedance
Pulse Time (s)
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
Single Pulse
VDS
90 %
10 %
VGS
td(on) trtd(off) tf
R
G
I
AS
0.01 Ω
t
p
D.U.T
L
V
DS
+
-V
DD
10 V
Vary t
p
to obtain
required I
AS
IAS
VDS
VDD
VDS
tp
QGS QGD
QG
V
G
Charge
10 V
D.U.T.
3 mA
VGS
VDS
IGID
0.3 µF
0.2 µF
50 kΩ
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
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SiHB28N60EF
www.vishay.com Vishay Siliconix
S21-0115-Rev. D, 15-Feb-2021 6Document Number: 91601
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 19 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91601.
P.W. Period
dI/dt
Diode recovery
dV/dt
Ripple 5 %
Body diode forward drop
Re-applied
voltage
Reverse
recovery
current
Body diode forward
current
VGS = 10 Va
ISD
Driver gate drive
D.U.T. lSD waveform
D.U.T. VDS waveform
Inductor current
D = P.W.
Period
+
-
+
+
+
-
-
-
Peak Diode Recovery dV/dt Test Circuit
VDD
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
D.U.T. Circuit layout considerations
Low stray inductance
Ground plane
Low leakage inductance
current transformer
Rg
Note
a. VGS = 5 V for logic level devices
VDD
‘IIIII' VISHAY.. fl 1—‘. teeeeeeeeeeeeeeeeeef : Delall‘” \ /. U 4.7 +&. V IA T 4A 3 l L 4 El lj SewanE~EandC~C 4 Notes 1. DlmenSlonlng and lolerancmg per ASME V14.5M71994 2. Dlmenslons are shown m rnllllmelers (unenes), a. Dlmensmn D and E as nol Include mald llash. Mold llasn sna outmosl extremes ol lne plasllc body al datum A. .Tnennal PAD contour opllonal wlmln almenslon E, LL [)1 a . Dlmenslon m and CI apply la base melal only. . Dalum A and a m be aelermlnea at damm plane H. . omllne conmrms lo JEDEC oufllne m TorzsaAB. \Ammb Documenl Number, 91364 Revlsmrl. TSVSepVOE
Document Number: 91364 www.vishay.com
Revision: 15-Sep-08 1
Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
5
4
13
L1
L2
D
BB
E
H
B
A
Detail A
A
A
c
c2
A
2 x e
2 x b2
2 x b
0.010 A B
MM ± 0.004 B
M
Base
metal
Plating b1, b3
(b, b2)
c1
(c)
Section B - B and C - C
Scale: none
Lead tip
4
34
(Datum A)
2CC
BB
5
5
View A - A
E1
D1
E
4
4
B
H
Seating plane
Gauge
plane
0° to 8°
Detail “A”
Rotated 90° CW
scale 8:1
L3 A1
L4
L
MILLIMETERS INCHES MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.
A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 -
A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420
b 0.51 0.99 0.020 0.039 E1 6.22 - 0.245 -
b1 0.51 0.89 0.020 0.035 e 2.54 BSC 0.100 BSC
b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625
b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110
c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066
c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070
c2 1.14 1.65 0.045 0.065 L3 0.25 BSC 0.010 BSC
D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.188 0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
_ VISHAYQ o 420 {mass} n 635 He ‘29) 0135 (a 429) o 200 (5 080) Recommended Mwmum Pads Dmensmns m Inchesxmm) Dncumem Number “Amos 73397
AN826
Vishay Siliconix
Document Number: 73397
11-Apr-05
www.vishay.com
1
RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead
0.635
(16.129)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.420
(10.668)
0.355
(9.017)
0.145
(3.683)
0.135
(3.429)
0.200
(5.080)
0.050
(1.257)
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