HV853 Datasheet by Microchip Technology

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Supertex inc. 5 upertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
HV853
Features
No external components required when using an
external EL clock frequency
Audible noise reduction with improved EMI
EL frequency can be set by an external resistor
DC to AC converter
Drives up to 5.3nF (approx. 1.5in2 lamp) load
Output voltage regulation
Enable function
EL Lamp dimming
Available in 10-Lead DFN and 8-Lead MSOP
packages
Applications
Cellular phone keypad
Watches
Small handheld wireless devices
MP3 Players
General Description
The Supertex HV853 is a high voltage, low noise EL
(electroluminescent) lamp driver. It is the low noise version of
the HV852 with improved EMI performance, operating over an
input voltage range of 3.2V to 5.0V. It is designed to drive EL
lamps of up to 1.5in2, with capacitive values up to 5.3nF. The
HV853 converts a low voltage DC input to a high voltage AC
output across an EL lamp. A nominal regulated output voltage
of ±80V is applied to the EL lamp. It uses a charge pump
scheme to boost the input voltage eliminating the need for an
external inductor, diode, and high voltage capacitor commonly
found in conventional topologies.
The charge pump circuit discharges its energy into an EL lamp
through a high voltage H-bridge. Once the voltage reaches
its regulated limit, it is turned off to conserve power. The EL
lamp is then discharged to ground and the H-bridge changes
state to allow the charge pump to charge the EL lamp in the
opposite direction.
The EL lamp frequency can be set either by an external
resistor REL or by applying an external clock where the clock
frequency is divided by 128 to set the EL lamp frequency.
Typical Application Circuits
High Voltage, Low Noise,
Inductorless EL Lamp Driver
EL Lamp Frequency set by REL
+
-
VDD = ON
GND = OFF
VDD CDD
VDD
GND
EL
LAMP
VDD
+
-GND
CLKEN
VA
VB
CLKIN
EN
REL
VDD
GND
CLKEN
VA
VB
CLKIN
EN
REL
VDD EL
LAMP
VDD CDD
REL
VDD = ON
GND = OFF
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
HV853MG HV853MG
EL Lamp Frequency set by External Clock
Absolute Maximum Ratings H853 YWLL Top Markmg H853 LLLL WWII—IN LILILILI Supertex inc.
2
HV853
1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
Ordering Information
DEVICE
Package Options
10-Lead DFN
3.00x3.00mm body
0.80mm height (max)
0.50mm pitch
8-Lead MSOP
3.00x3.00mm body
1.10mm height (max)
0.65mm pitch
HV853 HV853K7-G HV853MG-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter Value
VDD, supply voltage -0.5V to 6.5V
Storage temperature -65°C to +150°C
Power dissipation (10-Lead DFN) 1.6W
Power dissipation (8-Lead MSOP) 300mW
Sym Parameter Min Typ Max Units Conditions
IDDQ Quiescent current - - 150 nA EN = 0V
VA or VBPeak output voltage 68 80 92 V No load
VA-VBPeak to peak output voltage 136 160 184 V
IDD Operating current - 15 30 mA See Figure 1
VDD = 3.5V
REL = 1.5MΩ
Load = 3.3nF + 1.0kΩ
VA or VBPeak output voltage 68 80 92 V
VA-VBPeak to peak output voltage 136 160 184 V
fEL EL lamp frequency 240 280 320 Hz
Electrical Characteristics
(Over recommended operating conditions unless otherwise specified, TA = 25ºC)
Absolute Maximum Ratings are those values beyond which damage to
the device may occur. Functional operation under these conditions is not
implied. Continuous operation of the device at the absolute rating level
may affect device reliability. All voltages are referenced to device ground.
Pin Configurations
Product Marking
8-Lead MSOP(MG)
10-Lead DFN (K7)
H853
YWLL
Y = Last Digit of Year Sealed
W = Code for Week Sealed
L = Lot Number
= “Green” Packaging
L = Lot Number
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
H853
LLLL
YYWW
Top Marking
Bottom Marking
1
2
3
4
8
7
6
5
8-Lead MSOP (MG)
(top view)
GND
VA
VB
CLKEN
VDD
REL
EN
CLKIN
10-Lead DFN (K7)
(top View)
1
2
3
GND
VA
VB
CLKEN
VDD
REL
EN
CLKIN
4
5
8
7
6
9
10
GND
NC
Recommended Operating Conditions
Sym Parameter Min Typ Max Units Conditions
VDD Input voltage 3.2 - 5.0 V ---
fEL EL lamp frequency 50 - 500 Hz ---
Cload EL lamp capacitance 0 - 5.3 nF ---
TAOperating temperature -25 - +85 OC ---
Note:
Pads are at the bottom of the package.
Center heat slug should be connected to
GND or left floating.
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3
HV853
1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
Functional Block Diagram
Feedback
VDD
MOSFET
Full Bridge
REL
VDD
VA
VB
EN
GND
CLKIN
CLKEN
VDD
VSENSE High
Voltage
Level
Trans-
lators
EL
Oscillator
Capacitor
Charge
Pump Circuit
Typical Output Waveform
trout Output voltage rise time - 450 - µs 1.0in2 lamp
0V to 90% of final value
tfout Output voltage fall time 150 - - µs 90% to 10% of final value
Logic Inputs
VIL Input logic low voltage 0 - 0.5 V ---
VIH Input logic high voltage 2.0 - VDD V ---
IIL Input logic low current - - 1.0 µA ---
IIH Input logic high current - - 1.0 µA ---
ENrise Enable input rise time (for delay turn off) 0.01 - 10 ms Using external R-C circuit,
see Figure 2
ENfall Enable input fall time (for delay turn off) 10µ - 5.0 s
Cin Logic input capacitance - - 10 pF ---
Sym Parameter Min Typ Max Units Conditions
Electrical Characteristics (cont.)
(Over recommended operating conditions unless otherwise specified, TA = 25ºC)
Supertex inc.
4
HV853
1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
Figure 2: Push Button Turn on with Delay Turn off
Figure 3: Independent Programmable Output Frequency (fEL)
Note: fEL = fCLK/128
Figure 1: Typical Application
+
-
C
EL
Lamp
VDD
CDD
Push Button
Turn On
REL
R
RC time constant
will set Turn OFF
Delay time
GND
VA
VB
EN
REL
VDD
CLKEN
CLKIN
1
2
3
4
8
7
6
5
HV853MG
+
-
VDD
VDD = ON
GND = OFF
VDD CDD
fCLK
EL
Lamp
GND
CLKEN
VA
VB
CLKIN
EN
REL
VDD
HV853MG
1
2
3
4
8
7
6
5
VDD
GND
EL
Lamp
VDD = ON
GND = OFF
CDD
VDD
+
-
REL
GND
VA
VB
EN
REL
VDD
CLKEN
CLKIN
1
2
3
4
8
7
6
5
HV853MG
Load REL
(MΩ)
VDD
(V)
IDD
(mA)
VA-VB
(V)
fEL
(Hz)
3.3nF + 1.0kΩ 1.5
3.2 13.1 158
294
3.5 12.9 158
3.8 12.7 158
4.2 12.5 158
5.0 12.3 158
Typical Performance
(The following was the observed performance when driving a 1.0in2 green lamp)
mm: a Pin Descriptions: 10-Lead DFN (K7) I 8-Lead MSOP (MG) Supertex inc.
5
HV853
1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
Pin Descriptions: 10-Lead DFN (K7) / 8-Lead MSOP (MG)
K7 MG Pin
Name Description
Pin #
1 1 VDD Input supply voltage pin.
2 2 REL
An external resistor to VDD will set the EL lamp frequency. The EL frequency is inversely
proportional to the REL resistor value. A 1.5MΩ resistor would provide a nominal lamp fre-
quency of 280Hz
fEL = (1.5MΩ)(280Hz) / (REL)
When using an external clock to set the EL lamp frequency, the REL pin should be con-
nected to ground.
3 3 EN Enable input pin. Logic high will turn the device on. An external R-C circuit can be added for
a delayed turn off.
4 4 CLKIN
Logic input pin. An external logic clock applied to this pin can be used to set the EL lamp
frequency (see Figure 3). The EL lamp frequency is the external clock frequency divided by
128. This is useful for applications requiring the EL lamp to be synchronized to a system
clock. Connect to ground when not in use.
5 - NC No connect.
6 5 CLKEN Logic input pin. Logic high will cause the EL lamp frequency to be set by the CLKIN input.
Logic low will cause the EL lamp frequency to be set by the external REL resistor.
7,8 6 GND IC ground pin.
9 7 VB EL lamp driver output pin. The EL lamp is connected across VA and VB terminals.
10 8 VA EL lamp driver output pin. The EL lamp is connected across VA and VB terminals.
EL Lamp Dimming Using PWM
EL lamp dimming can be achieved by applying a PWM signal to the ENABLE pin. This is done by pulse skipping the out-
put pulses. The PWM frequency should be kept below the EL frequency but above 50Hz to avoid flickering.
Figure 4: PWM Dimming Circuit
EL Lamp
CDD
VDD
+
-
REL
8
7
6
5
VDD
VB
REL
GND
VA
1
2
3
4
EN
CLKIN CLKEN
HV853MG
VDD
GND
PWM
Signal
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6
HV853
1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
10-Lead DFN Package Outline (K7)
3.00x3.00mm body, 0.80mm height (max), 0.50mm pitch
Symbol A A1 A3 b D D2 E E2 e L L1 θ
Dimension
(mm)
MIN 0.70 0.00
0.20
REF
0.18 2.85* 2.20 2.85* 1.40
0.50
BSC
0.30 0.00* 0O
NOM 0.75 0.02 0.25 3.00 - 3.00 - 0.40 - -
MAX 0.80 0.05 0.30 3.15* 2.70 3.15* 1.75 0.50 0.15 14O
JEDEC Registration MO-229, Variation WEED-5, Issue C, Aug. 2003.
* This dimension is not specified in the original JEDEC drawing. The value listed is for reference only.
Drawings not to scale.
Supertex Doc.#: DSPD-10DFNK73X3P050, Version C101008.
Seating
Plane
θ
Top View
Side View
Bottom View
A
A1
D
E
D2
e
b
E2
A3
L
L1
View B
View B
Note 1
(Index Area
D/2 x E/2)
Note 3
Note 2
Note 1
(Index Area
D/2 x E/2)
10
1
10
1
Notes:
A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
The inner tip of the lead may be either rounded or square.
1.
2.
3.
FIFIFIFI \ / + / \ TopVhw J H H H7 Li—F + SMthw Supertex inc.
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an
adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the
replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com.
©2008 All rights reserved. Unauthorized use or reproduction is prohibited.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
7
HV853
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV853
B110308
1
8
Seating
Plane
Gauge
Plane
θ
L
L1
L2
E
E1
D
eb
AA2
A1
Seating
Plane
A
A
Top View
Side View View A-A
View B
View B
θ1 (x4)
Note 1
(Index Area
D/2 x E1/2)
Symbol A A1 A2 b D E E1 e L L1 L2 θ θ1
Dimension
(mm)
MIN 0.75* 0.00 0.75 0.22 2.80* 4.65* 2.80*
0.65
BSC
0.40
0.95
REF
0.25
BSC
0O5O
NOM - - 0.85 - 3.00 4.90 3.00 0.60 - -
MAX 1.10 0.15 0.95 0.38 3.20* 5.15* 3.20* 0.80 8O15O
JEDEC Registration MO-187, Variation AA, Issue E, Dec. 2004.
* This dimension is not specified in the original JEDEC drawing. The value listed is for reference only.
Drawings are not to scale.
Supertex Doc. #: DSPD-8MSOPMG, Version G101008.
Note:
A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
1.
8-Lead MSOP Package Outline (MG)
3.00x3.00mm body, 1.10mm height (max), 0.65mm pitch

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